2 * ARM AdvSIMD / SVE Vector Helpers
4 * Copyright (c) 2020 Linaro
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef TARGET_ARM_VEC_INTERNALS_H
21 #define TARGET_ARM_VEC_INTERNALS_H
24 * Note that vector data is stored in host-endian 64-bit chunks,
25 * so addressing units smaller than that needs a host-endian fixup.
27 * The H<N> macros are used when indexing an array of elements of size N.
29 * The H1_<N> macros are used when performing byte arithmetic and then
30 * casting the final pointer to a type of size N.
32 #ifdef HOST_WORDS_BIGENDIAN
33 #define H1(x) ((x) ^ 7)
34 #define H1_2(x) ((x) ^ 6)
35 #define H1_4(x) ((x) ^ 4)
36 #define H2(x) ((x) ^ 3)
37 #define H4(x) ((x) ^ 1)
47 static inline void clear_tail(void *vd
, uintptr_t opr_sz
, uintptr_t max_sz
)
49 uint64_t *d
= vd
+ opr_sz
;
52 for (i
= opr_sz
; i
< max_sz
; i
+= 8) {
57 static inline int32_t do_sqrshl_bhs(int32_t src
, int32_t shift
, int bits
,
58 bool round
, uint32_t *sat
)
61 /* Rounding the sign bit always produces 0. */
66 } else if (shift
< 0) {
69 return (src
>> 1) + (src
& 1);
72 } else if (shift
< bits
) {
73 int32_t val
= src
<< shift
;
75 if (!sat
|| val
>> shift
== src
) {
79 int32_t extval
= sextract32(val
, 0, bits
);
80 if (!sat
|| val
== extval
) {
84 } else if (!sat
|| src
== 0) {
89 return (1u << (bits
- 1)) - (src
>= 0);
92 static inline uint32_t do_uqrshl_bhs(uint32_t src
, int32_t shift
, int bits
,
93 bool round
, uint32_t *sat
)
95 if (shift
<= -(bits
+ round
)) {
97 } else if (shift
< 0) {
100 return (src
>> 1) + (src
& 1);
102 return src
>> -shift
;
103 } else if (shift
< bits
) {
104 uint32_t val
= src
<< shift
;
106 if (!sat
|| val
>> shift
== src
) {
110 uint32_t extval
= extract32(val
, 0, bits
);
111 if (!sat
|| val
== extval
) {
115 } else if (!sat
|| src
== 0) {
120 return MAKE_64BIT_MASK(0, bits
);
123 static inline int32_t do_suqrshl_bhs(int32_t src
, int32_t shift
, int bits
,
124 bool round
, uint32_t *sat
)
126 if (sat
&& src
< 0) {
130 return do_uqrshl_bhs(src
, shift
, bits
, round
, sat
);
133 static inline int64_t do_sqrshl_d(int64_t src
, int64_t shift
,
134 bool round
, uint32_t *sat
)
137 /* Rounding the sign bit always produces 0. */
142 } else if (shift
< 0) {
145 return (src
>> 1) + (src
& 1);
147 return src
>> -shift
;
148 } else if (shift
< 64) {
149 int64_t val
= src
<< shift
;
150 if (!sat
|| val
>> shift
== src
) {
153 } else if (!sat
|| src
== 0) {
158 return src
< 0 ? INT64_MIN
: INT64_MAX
;
161 static inline uint64_t do_uqrshl_d(uint64_t src
, int64_t shift
,
162 bool round
, uint32_t *sat
)
164 if (shift
<= -(64 + round
)) {
166 } else if (shift
< 0) {
169 return (src
>> 1) + (src
& 1);
171 return src
>> -shift
;
172 } else if (shift
< 64) {
173 uint64_t val
= src
<< shift
;
174 if (!sat
|| val
>> shift
== src
) {
177 } else if (!sat
|| src
== 0) {
185 static inline int64_t do_suqrshl_d(int64_t src
, int64_t shift
,
186 bool round
, uint32_t *sat
)
188 if (sat
&& src
< 0) {
192 return do_uqrshl_d(src
, shift
, round
, sat
);
195 int8_t do_sqrdmlah_b(int8_t, int8_t, int8_t, bool, bool);
196 int16_t do_sqrdmlah_h(int16_t, int16_t, int16_t, bool, bool, uint32_t *);
197 int32_t do_sqrdmlah_s(int32_t, int32_t, int32_t, bool, bool, uint32_t *);
198 int64_t do_sqrdmlah_d(int64_t, int64_t, int64_t, bool, bool);
200 #endif /* TARGET_ARM_VEC_INTERNALS_H */