hw/timer/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007, 2017 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/timer/m48t59.h"
  28 #include "qemu/timer.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/sysbus.h"
  31 #include "exec/address-spaces.h"
  32 #include "qemu/bcd.h"
  33
  34 #include "m48t59-internal.h"
  35
  36 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
  37 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
  38     OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
  39 #define M48TXX_SYS_BUS_CLASS(klass) \
  40     OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
  41 #define M48TXX_SYS_BUS(obj) \
  42     OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
  43
  44 /*
  45  * Chipset docs:
  46  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  47  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  48  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  49  */
  50
  51 typedef struct M48txxSysBusState {
  52     SysBusDevice parent_obj;
  53     M48t59State state;
  54     MemoryRegion io;
  55 } M48txxSysBusState;
  56
  57 typedef struct M48txxSysBusDeviceClass {
  58     SysBusDeviceClass parent_class;
  59     M48txxInfo info;
  60 } M48txxSysBusDeviceClass;
  61
  62 static M48txxInfo m48txx_sysbus_info[] = {
  63     {
  64         .bus_name = "sysbus-m48t02",
  65         .model = 2,
  66         .size = 0x800,
  67     },{
  68         .bus_name = "sysbus-m48t08",
  69         .model = 8,
  70         .size = 0x2000,
  71     },{
  72         .bus_name = "sysbus-m48t59",
  73         .model = 59,
  74         .size = 0x2000,
  75     }
  76 };
  77
  78
  79 /* Fake timer functions */
  80
  81 /* Alarm management */
  82 static void alarm_cb (void *opaque)
  83 {
  84     struct tm tm;
  85     uint64_t next_time;
  86     M48t59State *NVRAM = opaque;
  87
  88     qemu_set_irq(NVRAM->IRQ, 1);
  89     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
  90         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
  91         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
  92         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
  93         /* Repeat once a month */
  94         qemu_get_timedate(&tm, NVRAM->time_offset);
  95         tm.tm_mon++;
  96         if (tm.tm_mon == 13) {
  97             tm.tm_mon = 1;
  98             tm.tm_year++;
  99         }
 100         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 101     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 102                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 103                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 104                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 105         /* Repeat once a day */
 106         next_time = 24 * 60 * 60;
 107     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 108                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 109                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 110                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 111         /* Repeat once an hour */
 112         next_time = 60 * 60;
 113     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 114                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 115                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 116                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 117         /* Repeat once a minute */
 118         next_time = 60;
 119     } else {
 120         /* Repeat once a second */
 121         next_time = 1;
 122     }
 123     timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
 124                     next_time * 1000);
 125     qemu_set_irq(NVRAM->IRQ, 0);
 126 }
 127
 128 static void set_alarm(M48t59State *NVRAM)
 129 {
 130     int diff;
 131     if (NVRAM->alrm_timer != NULL) {
 132         timer_del(NVRAM->alrm_timer);
 133         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 134         if (diff > 0)
 135             timer_mod(NVRAM->alrm_timer, diff * 1000);
 136     }
 137 }
 138
 139 /* RTC management helpers */
 140 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 141 {
 142     qemu_get_timedate(tm, NVRAM->time_offset);
 143 }
 144
 145 static void set_time(M48t59State *NVRAM, struct tm *tm)
 146 {
 147     NVRAM->time_offset = qemu_timedate_diff(tm);
 148     set_alarm(NVRAM);
 149 }
 150
 151 /* Watchdog management */
 152 static void watchdog_cb (void *opaque)
 153 {
 154     M48t59State *NVRAM = opaque;
 155
 156     NVRAM->buffer[0x1FF0] |= 0x80;
 157     if (NVRAM->buffer[0x1FF7] & 0x80) {
 158         NVRAM->buffer[0x1FF7] = 0x00;
 159         NVRAM->buffer[0x1FFC] &= ~0x40;
 160         /* May it be a hw CPU Reset instead ? */
 161         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 162     } else {
 163         qemu_set_irq(NVRAM->IRQ, 1);
 164         qemu_set_irq(NVRAM->IRQ, 0);
 165     }
 166 }
 167
 168 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 169 {
 170     uint64_t interval; /* in 1/16 seconds */
 171
 172     NVRAM->buffer[0x1FF0] &= ~0x80;
 173     if (NVRAM->wd_timer != NULL) {
 174         timer_del(NVRAM->wd_timer);
 175         if (value != 0) {
 176             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 177             timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 178                            ((interval * 1000) >> 4));
 179         }
 180     }
 181 }
 182
 183 /* Direct access to NVRAM */
 184 void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
 185 {
 186     struct tm tm;
 187     int tmp;
 188
 189     if (addr > 0x1FF8 && addr < 0x2000)
 190         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 191
 192     /* check for NVRAM access */
 193     if ((NVRAM->model == 2 && addr < 0x7f8) ||
 194         (NVRAM->model == 8 && addr < 0x1ff8) ||
 195         (NVRAM->model == 59 && addr < 0x1ff0)) {
 196         goto do_write;
 197     }
 198
 199     /* TOD access */
 200     switch (addr) {
 201     case 0x1FF0:
 202         /* flags register : read-only */
 203         break;
 204     case 0x1FF1:
 205         /* unused */
 206         break;
 207     case 0x1FF2:
 208         /* alarm seconds */
 209         tmp = from_bcd(val & 0x7F);
 210         if (tmp >= 0 && tmp <= 59) {
 211             NVRAM->alarm.tm_sec = tmp;
 212             NVRAM->buffer[0x1FF2] = val;
 213             set_alarm(NVRAM);
 214         }
 215         break;
 216     case 0x1FF3:
 217         /* alarm minutes */
 218         tmp = from_bcd(val & 0x7F);
 219         if (tmp >= 0 && tmp <= 59) {
 220             NVRAM->alarm.tm_min = tmp;
 221             NVRAM->buffer[0x1FF3] = val;
 222             set_alarm(NVRAM);
 223         }
 224         break;
 225     case 0x1FF4:
 226         /* alarm hours */
 227         tmp = from_bcd(val & 0x3F);
 228         if (tmp >= 0 && tmp <= 23) {
 229             NVRAM->alarm.tm_hour = tmp;
 230             NVRAM->buffer[0x1FF4] = val;
 231             set_alarm(NVRAM);
 232         }
 233         break;
 234     case 0x1FF5:
 235         /* alarm date */
 236         tmp = from_bcd(val & 0x3F);
 237         if (tmp != 0) {
 238             NVRAM->alarm.tm_mday = tmp;
 239             NVRAM->buffer[0x1FF5] = val;
 240             set_alarm(NVRAM);
 241         }
 242         break;
 243     case 0x1FF6:
 244         /* interrupts */
 245         NVRAM->buffer[0x1FF6] = val;
 246         break;
 247     case 0x1FF7:
 248         /* watchdog */
 249         NVRAM->buffer[0x1FF7] = val;
 250         set_up_watchdog(NVRAM, val);
 251         break;
 252     case 0x1FF8:
 253     case 0x07F8:
 254         /* control */
 255        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 256         break;
 257     case 0x1FF9:
 258     case 0x07F9:
 259         /* seconds (BCD) */
 260         tmp = from_bcd(val & 0x7F);
 261         if (tmp >= 0 && tmp <= 59) {
 262             get_time(NVRAM, &tm);
 263             tm.tm_sec = tmp;
 264             set_time(NVRAM, &tm);
 265         }
 266         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 267             if (val & 0x80) {
 268                 NVRAM->stop_time = time(NULL);
 269             } else {
 270                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 271                 NVRAM->stop_time = 0;
 272             }
 273         }
 274         NVRAM->buffer[addr] = val & 0x80;
 275         break;
 276     case 0x1FFA:
 277     case 0x07FA:
 278         /* minutes (BCD) */
 279         tmp = from_bcd(val & 0x7F);
 280         if (tmp >= 0 && tmp <= 59) {
 281             get_time(NVRAM, &tm);
 282             tm.tm_min = tmp;
 283             set_time(NVRAM, &tm);
 284         }
 285         break;
 286     case 0x1FFB:
 287     case 0x07FB:
 288         /* hours (BCD) */
 289         tmp = from_bcd(val & 0x3F);
 290         if (tmp >= 0 && tmp <= 23) {
 291             get_time(NVRAM, &tm);
 292             tm.tm_hour = tmp;
 293             set_time(NVRAM, &tm);
 294         }
 295         break;
 296     case 0x1FFC:
 297     case 0x07FC:
 298         /* day of the week / century */
 299         tmp = from_bcd(val & 0x07);
 300         get_time(NVRAM, &tm);
 301         tm.tm_wday = tmp;
 302         set_time(NVRAM, &tm);
 303         NVRAM->buffer[addr] = val & 0x40;
 304         break;
 305     case 0x1FFD:
 306     case 0x07FD:
 307         /* date (BCD) */
 308        tmp = from_bcd(val & 0x3F);
 309         if (tmp != 0) {
 310             get_time(NVRAM, &tm);
 311             tm.tm_mday = tmp;
 312             set_time(NVRAM, &tm);
 313         }
 314         break;
 315     case 0x1FFE:
 316     case 0x07FE:
 317         /* month */
 318         tmp = from_bcd(val & 0x1F);
 319         if (tmp >= 1 && tmp <= 12) {
 320             get_time(NVRAM, &tm);
 321             tm.tm_mon = tmp - 1;
 322             set_time(NVRAM, &tm);
 323         }
 324         break;
 325     case 0x1FFF:
 326     case 0x07FF:
 327         /* year */
 328         tmp = from_bcd(val);
 329         if (tmp >= 0 && tmp <= 99) {
 330             get_time(NVRAM, &tm);
 331             tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
 332             set_time(NVRAM, &tm);
 333         }
 334         break;
 335     default:
 336         /* Check lock registers state */
 337         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 338             break;
 339         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 340             break;
 341     do_write:
 342         if (addr < NVRAM->size) {
 343             NVRAM->buffer[addr] = val & 0xFF;
 344         }
 345         break;
 346     }
 347 }
 348
 349 uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
 350 {
 351     struct tm tm;
 352     uint32_t retval = 0xFF;
 353
 354     /* check for NVRAM access */
 355     if ((NVRAM->model == 2 && addr < 0x078f) ||
 356         (NVRAM->model == 8 && addr < 0x1ff8) ||
 357         (NVRAM->model == 59 && addr < 0x1ff0)) {
 358         goto do_read;
 359     }
 360
 361     /* TOD access */
 362     switch (addr) {
 363     case 0x1FF0:
 364         /* flags register */
 365         goto do_read;
 366     case 0x1FF1:
 367         /* unused */
 368         retval = 0;
 369         break;
 370     case 0x1FF2:
 371         /* alarm seconds */
 372         goto do_read;
 373     case 0x1FF3:
 374         /* alarm minutes */
 375         goto do_read;
 376     case 0x1FF4:
 377         /* alarm hours */
 378         goto do_read;
 379     case 0x1FF5:
 380         /* alarm date */
 381         goto do_read;
 382     case 0x1FF6:
 383         /* interrupts */
 384         goto do_read;
 385     case 0x1FF7:
 386         /* A read resets the watchdog */
 387         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 388         goto do_read;
 389     case 0x1FF8:
 390     case 0x07F8:
 391         /* control */
 392         goto do_read;
 393     case 0x1FF9:
 394     case 0x07F9:
 395         /* seconds (BCD) */
 396         get_time(NVRAM, &tm);
 397         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 398         break;
 399     case 0x1FFA:
 400     case 0x07FA:
 401         /* minutes (BCD) */
 402         get_time(NVRAM, &tm);
 403         retval = to_bcd(tm.tm_min);
 404         break;
 405     case 0x1FFB:
 406     case 0x07FB:
 407         /* hours (BCD) */
 408         get_time(NVRAM, &tm);
 409         retval = to_bcd(tm.tm_hour);
 410         break;
 411     case 0x1FFC:
 412     case 0x07FC:
 413         /* day of the week / century */
 414         get_time(NVRAM, &tm);
 415         retval = NVRAM->buffer[addr] | tm.tm_wday;
 416         break;
 417     case 0x1FFD:
 418     case 0x07FD:
 419         /* date */
 420         get_time(NVRAM, &tm);
 421         retval = to_bcd(tm.tm_mday);
 422         break;
 423     case 0x1FFE:
 424     case 0x07FE:
 425         /* month */
 426         get_time(NVRAM, &tm);
 427         retval = to_bcd(tm.tm_mon + 1);
 428         break;
 429     case 0x1FFF:
 430     case 0x07FF:
 431         /* year */
 432         get_time(NVRAM, &tm);
 433         retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
 434         break;
 435     default:
 436         /* Check lock registers state */
 437         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 438             break;
 439         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 440             break;
 441     do_read:
 442         if (addr < NVRAM->size) {
 443             retval = NVRAM->buffer[addr];
 444         }
 445         break;
 446     }
 447     if (addr > 0x1FF9 && addr < 0x2000)
 448        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 449
 450     return retval;
 451 }
 452
 453 /* IO access to NVRAM */
 454 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
 455                          unsigned size)
 456 {
 457     M48t59State *NVRAM = opaque;
 458
 459     NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 460     switch (addr) {
 461     case 0:
 462         NVRAM->addr &= ~0x00FF;
 463         NVRAM->addr |= val;
 464         break;
 465     case 1:
 466         NVRAM->addr &= ~0xFF00;
 467         NVRAM->addr |= val << 8;
 468         break;
 469     case 3:
 470         m48t59_write(NVRAM, NVRAM->addr, val);
 471         NVRAM->addr = 0x0000;
 472         break;
 473     default:
 474         break;
 475     }
 476 }
 477
 478 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
 479 {
 480     M48t59State *NVRAM = opaque;
 481     uint32_t retval;
 482
 483     switch (addr) {
 484     case 3:
 485         retval = m48t59_read(NVRAM, NVRAM->addr);
 486         break;
 487     default:
 488         retval = -1;
 489         break;
 490     }
 491     NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 492
 493     return retval;
 494 }
 495
 496 static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
 497 {
 498     M48t59State *NVRAM = opaque;
 499
 500     m48t59_write(NVRAM, addr, value & 0xff);
 501 }
 502
 503 static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
 504 {
 505     M48t59State *NVRAM = opaque;
 506
 507     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
 508     m48t59_write(NVRAM, addr + 1, value & 0xff);
 509 }
 510
 511 static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
 512 {
 513     M48t59State *NVRAM = opaque;
 514
 515     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
 516     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
 517     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
 518     m48t59_write(NVRAM, addr + 3, value & 0xff);
 519 }
 520
 521 static uint32_t nvram_readb (void *opaque, hwaddr addr)
 522 {
 523     M48t59State *NVRAM = opaque;
 524
 525     return m48t59_read(NVRAM, addr);
 526 }
 527
 528 static uint32_t nvram_readw (void *opaque, hwaddr addr)
 529 {
 530     M48t59State *NVRAM = opaque;
 531     uint32_t retval;
 532
 533     retval = m48t59_read(NVRAM, addr) << 8;
 534     retval |= m48t59_read(NVRAM, addr + 1);
 535     return retval;
 536 }
 537
 538 static uint32_t nvram_readl (void *opaque, hwaddr addr)
 539 {
 540     M48t59State *NVRAM = opaque;
 541     uint32_t retval;
 542
 543     retval = m48t59_read(NVRAM, addr) << 24;
 544     retval |= m48t59_read(NVRAM, addr + 1) << 16;
 545     retval |= m48t59_read(NVRAM, addr + 2) << 8;
 546     retval |= m48t59_read(NVRAM, addr + 3);
 547     return retval;
 548 }
 549
 550 static const MemoryRegionOps nvram_ops = {
 551     .old_mmio = {
 552         .read = { nvram_readb, nvram_readw, nvram_readl, },
 553         .write = { nvram_writeb, nvram_writew, nvram_writel, },
 554     },
 555     .endianness = DEVICE_NATIVE_ENDIAN,
 556 };
 557
 558 static const VMStateDescription vmstate_m48t59 = {
 559     .name = "m48t59",
 560     .version_id = 1,
 561     .minimum_version_id = 1,
 562     .fields = (VMStateField[]) {
 563         VMSTATE_UINT8(lock, M48t59State),
 564         VMSTATE_UINT16(addr, M48t59State),
 565         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, size),
 566         VMSTATE_END_OF_LIST()
 567     }
 568 };
 569
 570 void m48t59_reset_common(M48t59State *NVRAM)
 571 {
 572     NVRAM->addr = 0;
 573     NVRAM->lock = 0;
 574     if (NVRAM->alrm_timer != NULL)
 575         timer_del(NVRAM->alrm_timer);
 576
 577     if (NVRAM->wd_timer != NULL)
 578         timer_del(NVRAM->wd_timer);
 579 }
 580
 581 static void m48t59_reset_sysbus(DeviceState *d)
 582 {
 583     M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
 584     M48t59State *NVRAM = &sys->state;
 585
 586     m48t59_reset_common(NVRAM);
 587 }
 588
 589 const MemoryRegionOps m48t59_io_ops = {
 590     .read = NVRAM_readb,
 591     .write = NVRAM_writeb,
 592     .impl = {
 593         .min_access_size = 1,
 594         .max_access_size = 1,
 595     },
 596     .endianness = DEVICE_LITTLE_ENDIAN,
 597 };
 598
 599 /* Initialisation routine */
 600 Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
 601                    uint32_t io_base, uint16_t size, int base_year,
 602                    int model)
 603 {
 604     DeviceState *dev;
 605     SysBusDevice *s;
 606     int i;
 607
 608     for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
 609         if (m48txx_sysbus_info[i].size != size ||
 610             m48txx_sysbus_info[i].model != model) {
 611             continue;
 612         }
 613
 614         dev = qdev_create(NULL, m48txx_sysbus_info[i].bus_name);
 615         qdev_prop_set_int32(dev, "base-year", base_year);
 616         qdev_init_nofail(dev);
 617         s = SYS_BUS_DEVICE(dev);
 618         sysbus_connect_irq(s, 0, IRQ);
 619         if (io_base != 0) {
 620             memory_region_add_subregion(get_system_io(), io_base,
 621                                         sysbus_mmio_get_region(s, 1));
 622         }
 623         if (mem_base != 0) {
 624             sysbus_mmio_map(s, 0, mem_base);
 625         }
 626
 627         return NVRAM(s);
 628     }
 629
 630     assert(false);
 631     return NULL;
 632 }
 633
 634 void m48t59_realize_common(M48t59State *s, Error **errp)
 635 {
 636     s->buffer = g_malloc0(s->size);
 637     if (s->model == 59) {
 638         s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
 639         s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
 640     }
 641     qemu_get_timedate(&s->alarm, 0);
 642 }
 643
 644 static void m48t59_init1(Object *obj)
 645 {
 646     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(obj);
 647     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 648     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 649     M48t59State *s = &d->state;
 650
 651     s->model = u->info.model;
 652     s->size = u->info.size;
 653     sysbus_init_irq(dev, &s->IRQ);
 654
 655     memory_region_init_io(&s->iomem, obj, &nvram_ops, s, "m48t59.nvram",
 656                           s->size);
 657     memory_region_init_io(&d->io, obj, &m48t59_io_ops, s, "m48t59", 4);
 658 }
 659
 660 static void m48t59_realize(DeviceState *dev, Error **errp)
 661 {
 662     M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
 663     M48t59State *s = &d->state;
 664     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 665
 666     sysbus_init_mmio(sbd, &s->iomem);
 667     sysbus_init_mmio(sbd, &d->io);
 668     m48t59_realize_common(s, errp);
 669 }
 670
 671 static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
 672 {
 673     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 674     return m48t59_read(&d->state, addr);
 675 }
 676
 677 static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
 678 {
 679     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 680     m48t59_write(&d->state, addr, val);
 681 }
 682
 683 static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
 684 {
 685     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 686     m48t59_toggle_lock(&d->state, lock);
 687 }
 688
 689 static Property m48t59_sysbus_properties[] = {
 690     DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
 691     DEFINE_PROP_END_OF_LIST(),
 692 };
 693
 694 static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
 695 {
 696     DeviceClass *dc = DEVICE_CLASS(klass);
 697     NvramClass *nc = NVRAM_CLASS(klass);
 698
 699     dc->realize = m48t59_realize;
 700     dc->reset = m48t59_reset_sysbus;
 701     dc->props = m48t59_sysbus_properties;
 702     dc->vmsd = &vmstate_m48t59;
 703     nc->read = m48txx_sysbus_read;
 704     nc->write = m48txx_sysbus_write;
 705     nc->toggle_lock = m48txx_sysbus_toggle_lock;
 706 }
 707
 708 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
 709 {
 710     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
 711     M48txxInfo *info = data;
 712
 713     u->info = *info;
 714 }
 715
 716 static const TypeInfo nvram_info = {
 717     .name = TYPE_NVRAM,
 718     .parent = TYPE_INTERFACE,
 719     .class_size = sizeof(NvramClass),
 720 };
 721
 722 static const TypeInfo m48txx_sysbus_type_info = {
 723     .name = TYPE_M48TXX_SYS_BUS,
 724     .parent = TYPE_SYS_BUS_DEVICE,
 725     .instance_size = sizeof(M48txxSysBusState),
 726     .instance_init = m48t59_init1,
 727     .abstract = true,
 728     .class_init = m48txx_sysbus_class_init,
 729     .interfaces = (InterfaceInfo[]) {
 730         { TYPE_NVRAM },
 731         { }
 732     }
 733 };
 734
 735 static void m48t59_register_types(void)
 736 {
 737     TypeInfo sysbus_type_info = {
 738         .parent = TYPE_M48TXX_SYS_BUS,
 739         .class_size = sizeof(M48txxSysBusDeviceClass),
 740         .class_init = m48txx_sysbus_concrete_class_init,
 741     };
 742     int i;
 743
 744     type_register_static(&nvram_info);
 745     type_register_static(&m48txx_sysbus_type_info);
 746
 747     for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
 748         sysbus_type_info.name = m48txx_sysbus_info[i].bus_name;
 749         sysbus_type_info.class_data = &m48txx_sysbus_info[i];
 750         type_register(&sysbus_type_info);
 751     }
 752 }
 753
 754 type_init(m48t59_register_types)