hw/timer/a9gtimer.c

   1 /*
   2  * Global peripheral timer block for ARM A9MP
   3  *
   4  * (C) 2013 Xilinx Inc.
   5  *
   6  * Written by François LEGAL
   7  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "hw/timer/a9gtimer.h"
  25 #include "qemu/timer.h"
  26 #include "qemu/bitops.h"
  27 #include "qemu/log.h"
  28
  29 #ifndef A9_GTIMER_ERR_DEBUG
  30 #define A9_GTIMER_ERR_DEBUG 0
  31 #endif
  32
  33 #define DB_PRINT_L(level, ...) do { \
  34     if (A9_GTIMER_ERR_DEBUG > (level)) { \
  35         fprintf(stderr,  ": %s: ", __func__); \
  36         fprintf(stderr, ## __VA_ARGS__); \
  37     } \
  38 } while (0);
  39
  40 #define DB_PRINT(...) DB_PRINT_L(0, ## __VA_ARGS__)
  41
  42 static inline int a9_gtimer_get_current_cpu(A9GTimerState *s)
  43 {
  44     if (current_cpu->cpu_index >= s->num_cpu) {
  45         hw_error("a9gtimer: num-cpu %d but this cpu is %d!\n",
  46                  s->num_cpu, current_cpu->cpu_index);
  47     }
  48     return current_cpu->cpu_index;
  49 }
  50
  51 static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s)
  52 {
  53     uint64_t prescale = extract32(s->control, R_CONTROL_PRESCALER_SHIFT,
  54                                   R_CONTROL_PRESCALER_LEN);
  55
  56     return (prescale + 1) * 10;
  57 }
  58
  59 static A9GTimerUpdate a9_gtimer_get_update(A9GTimerState *s)
  60 {
  61     A9GTimerUpdate ret;
  62
  63     ret.now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  64     ret.new = s->ref_counter +
  65               (ret.now - s->cpu_ref_time) / a9_gtimer_get_conv(s);
  66     return ret;
  67 }
  68
  69 static void a9_gtimer_update(A9GTimerState *s, bool sync)
  70 {
  71
  72     A9GTimerUpdate update = a9_gtimer_get_update(s);
  73     int i;
  74     int64_t next_cdiff = 0;
  75
  76     for (i = 0; i < s->num_cpu; ++i) {
  77         A9GTimerPerCPU *gtb = &s->per_cpu[i];
  78         int64_t cdiff = 0;
  79
  80         if ((s->control & R_CONTROL_TIMER_ENABLE) &&
  81                 (gtb->control & R_CONTROL_COMP_ENABLE)) {
  82             /* R2p0+, where the compare function is >= */
  83             while (gtb->compare < update.new) {
  84                 DB_PRINT("Compare event happened for CPU %d\n", i);
  85                 gtb->status = 1;
  86                 if (gtb->control & R_CONTROL_AUTO_INCREMENT) {
  87                     DB_PRINT("Auto incrementing timer compare by %" PRId32 "\n",
  88                              gtb->inc);
  89                     gtb->compare += gtb->inc;
  90                 } else {
  91                     break;
  92                 }
  93             }
  94             cdiff = (int64_t)gtb->compare - (int64_t)update.new + 1;
  95             if (cdiff > 0 && (cdiff < next_cdiff || !next_cdiff)) {
  96                 next_cdiff = cdiff;
  97             }
  98         }
  99
 100         qemu_set_irq(gtb->irq,
 101                      gtb->status && (gtb->control & R_CONTROL_IRQ_ENABLE));
 102     }
 103
 104     timer_del(s->timer);
 105     if (next_cdiff) {
 106         DB_PRINT("scheduling qemu_timer to fire again in %"
 107                  PRIx64 " cycles\n", next_cdiff);
 108         timer_mod(s->timer, update.now + next_cdiff * a9_gtimer_get_conv(s));
 109     }
 110
 111     if (s->control & R_CONTROL_TIMER_ENABLE) {
 112         s->counter = update.new;
 113     }
 114
 115     if (sync) {
 116         s->cpu_ref_time = update.now;
 117         s->ref_counter = s->counter;
 118     }
 119 }
 120
 121 static void a9_gtimer_update_no_sync(void *opaque)
 122 {
 123     A9GTimerState *s = A9_GTIMER(opaque);
 124
 125     a9_gtimer_update(s, false);
 126 }
 127
 128 static uint64_t a9_gtimer_read(void *opaque, hwaddr addr, unsigned size)
 129 {
 130     A9GTimerPerCPU *gtb = (A9GTimerPerCPU *)opaque;
 131     A9GTimerState *s = gtb->parent;
 132     A9GTimerUpdate update;
 133     uint64_t ret = 0;
 134     int shift = 0;
 135
 136     switch (addr) {
 137     case R_COUNTER_HI:
 138         shift = 32;
 139         /* fallthrough */
 140     case R_COUNTER_LO:
 141         update = a9_gtimer_get_update(s);
 142         ret = extract64(update.new, shift, 32);
 143         break;
 144     case R_CONTROL:
 145         ret = s->control | gtb->control;
 146         break;
 147     case R_INTERRUPT_STATUS:
 148         ret = gtb->status;
 149         break;
 150     case R_COMPARATOR_HI:
 151         shift = 32;
 152         /* fallthrough */
 153     case R_COMPARATOR_LO:
 154         ret = extract64(gtb->compare, shift, 32);
 155         break;
 156     case R_AUTO_INCREMENT:
 157         ret =  gtb->inc;
 158         break;
 159     default:
 160         qemu_log_mask(LOG_GUEST_ERROR, "bad a9gtimer register: %x\n",
 161                       (unsigned)addr);
 162         return 0;
 163     }
 164
 165     DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, ret);
 166     return ret;
 167 }
 168
 169 static void a9_gtimer_write(void *opaque, hwaddr addr, uint64_t value,
 170                             unsigned size)
 171 {
 172     A9GTimerPerCPU *gtb = (A9GTimerPerCPU *)opaque;
 173     A9GTimerState *s = gtb->parent;
 174     int shift = 0;
 175
 176     DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, value);
 177
 178     switch (addr) {
 179     case R_COUNTER_HI:
 180         shift = 32;
 181         /* fallthrough */
 182     case R_COUNTER_LO:
 183         /*
 184          * Keep it simple - ARM docco explicitly says to disable timer before
 185          * modding it, so dont bother trying to do all the difficult on the fly
 186          * timer modifications - (if they even work in real hardware??).
 187          */
 188         if (s->control & R_CONTROL_TIMER_ENABLE) {
 189             qemu_log_mask(LOG_GUEST_ERROR, "Cannot mod running ARM gtimer\n");
 190             return;
 191         }
 192         s->counter = deposit64(s->counter, shift, 32, value);
 193         return;
 194     case R_CONTROL:
 195         a9_gtimer_update(s, (value ^ s->control) & R_CONTROL_NEEDS_SYNC);
 196         gtb->control = value & R_CONTROL_BANKED;
 197         s->control = value & ~R_CONTROL_BANKED;
 198         break;
 199     case R_INTERRUPT_STATUS:
 200         a9_gtimer_update(s, false);
 201         gtb->status &= ~value;
 202         break;
 203     case R_COMPARATOR_HI:
 204         shift = 32;
 205         /* fallthrough */
 206     case R_COMPARATOR_LO:
 207         a9_gtimer_update(s, false);
 208         gtb->compare = deposit64(gtb->compare, shift, 32, value);
 209         break;
 210     case R_AUTO_INCREMENT:
 211         gtb->inc = value;
 212         return;
 213     default:
 214         return;
 215     }
 216
 217     a9_gtimer_update(s, false);
 218 }
 219
 220 /* Wrapper functions to implement the "read global timer for
 221  * the current CPU" memory regions.
 222  */
 223 static uint64_t a9_gtimer_this_read(void *opaque, hwaddr addr,
 224                                     unsigned size)
 225 {
 226     A9GTimerState *s = A9_GTIMER(opaque);
 227     int id = a9_gtimer_get_current_cpu(s);
 228
 229     /* no \n so concatenates with message from read fn */
 230     DB_PRINT("CPU:%d:", id);
 231
 232     return a9_gtimer_read(&s->per_cpu[id], addr, size);
 233 }
 234
 235 static void a9_gtimer_this_write(void *opaque, hwaddr addr,
 236                                  uint64_t value, unsigned size)
 237 {
 238     A9GTimerState *s = A9_GTIMER(opaque);
 239     int id = a9_gtimer_get_current_cpu(s);
 240
 241     /* no \n so concatenates with message from write fn */
 242     DB_PRINT("CPU:%d:", id);
 243
 244     a9_gtimer_write(&s->per_cpu[id], addr, value, size);
 245 }
 246
 247 static const MemoryRegionOps a9_gtimer_this_ops = {
 248     .read = a9_gtimer_this_read,
 249     .write = a9_gtimer_this_write,
 250     .valid = {
 251         .min_access_size = 4,
 252         .max_access_size = 4,
 253     },
 254     .endianness = DEVICE_NATIVE_ENDIAN,
 255 };
 256
 257 static const MemoryRegionOps a9_gtimer_ops = {
 258     .read = a9_gtimer_read,
 259     .write = a9_gtimer_write,
 260     .valid = {
 261         .min_access_size = 4,
 262         .max_access_size = 4,
 263     },
 264     .endianness = DEVICE_NATIVE_ENDIAN,
 265 };
 266
 267 static void a9_gtimer_reset(DeviceState *dev)
 268 {
 269     A9GTimerState *s = A9_GTIMER(dev);
 270     int i;
 271
 272     s->counter = 0;
 273     s->control = 0;
 274
 275     for (i = 0; i < s->num_cpu; i++) {
 276         A9GTimerPerCPU *gtb = &s->per_cpu[i];
 277
 278         gtb->control = 0;
 279         gtb->status = 0;
 280         gtb->compare = 0;
 281         gtb->inc = 0;
 282     }
 283     a9_gtimer_update(s, false);
 284 }
 285
 286 static void a9_gtimer_realize(DeviceState *dev, Error **errp)
 287 {
 288     A9GTimerState *s = A9_GTIMER(dev);
 289     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 290     int i;
 291
 292     if (s->num_cpu < 1 || s->num_cpu > A9_GTIMER_MAX_CPUS) {
 293         error_setg(errp, "%s: num-cpu must be between 1 and %d",
 294                    __func__, A9_GTIMER_MAX_CPUS);
 295         return;
 296     }
 297
 298     memory_region_init_io(&s->iomem, OBJECT(dev), &a9_gtimer_this_ops, s,
 299                           "a9gtimer shared", 0x20);
 300     sysbus_init_mmio(sbd, &s->iomem);
 301     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, a9_gtimer_update_no_sync, s);
 302
 303     for (i = 0; i < s->num_cpu; i++) {
 304         A9GTimerPerCPU *gtb = &s->per_cpu[i];
 305
 306         gtb->parent = s;
 307         sysbus_init_irq(sbd, &gtb->irq);
 308         memory_region_init_io(&gtb->iomem, OBJECT(dev), &a9_gtimer_ops, gtb,
 309                               "a9gtimer per cpu", 0x20);
 310         sysbus_init_mmio(sbd, &gtb->iomem);
 311     }
 312 }
 313
 314 static const VMStateDescription vmstate_a9_gtimer_per_cpu = {
 315     .name = "arm.cortex-a9-global-timer.percpu",
 316     .version_id = 1,
 317     .minimum_version_id = 1,
 318     .fields = (VMStateField[]) {
 319         VMSTATE_UINT32(control, A9GTimerPerCPU),
 320         VMSTATE_UINT64(compare, A9GTimerPerCPU),
 321         VMSTATE_UINT32(status, A9GTimerPerCPU),
 322         VMSTATE_UINT32(inc, A9GTimerPerCPU),
 323         VMSTATE_END_OF_LIST()
 324     }
 325 };
 326
 327 static const VMStateDescription vmstate_a9_gtimer = {
 328     .name = "arm.cortex-a9-global-timer",
 329     .version_id = 1,
 330     .minimum_version_id = 1,
 331     .fields = (VMStateField[]) {
 332         VMSTATE_TIMER_PTR(timer, A9GTimerState),
 333         VMSTATE_UINT64(counter, A9GTimerState),
 334         VMSTATE_UINT64(ref_counter, A9GTimerState),
 335         VMSTATE_UINT64(cpu_ref_time, A9GTimerState),
 336         VMSTATE_STRUCT_VARRAY_UINT32(per_cpu, A9GTimerState, num_cpu,
 337                                      1, vmstate_a9_gtimer_per_cpu,
 338                                      A9GTimerPerCPU),
 339         VMSTATE_END_OF_LIST()
 340     }
 341 };
 342
 343 static Property a9_gtimer_properties[] = {
 344     DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0),
 345     DEFINE_PROP_END_OF_LIST()
 346 };
 347
 348 static void a9_gtimer_class_init(ObjectClass *klass, void *data)
 349 {
 350     DeviceClass *dc = DEVICE_CLASS(klass);
 351
 352     dc->realize = a9_gtimer_realize;
 353     dc->vmsd = &vmstate_a9_gtimer;
 354     dc->reset = a9_gtimer_reset;
 355     dc->props = a9_gtimer_properties;
 356 }
 357
 358 static const TypeInfo a9_gtimer_info = {
 359     .name          = TYPE_A9_GTIMER,
 360     .parent        = TYPE_SYS_BUS_DEVICE,
 361     .instance_size = sizeof(A9GTimerState),
 362     .class_init    = a9_gtimer_class_init,
 363 };
 364
 365 static void a9_gtimer_register_types(void)
 366 {
 367     type_register_static(&a9_gtimer_info);
 368 }
 369
 370 type_init(a9_gtimer_register_types)