hw/prep_pci.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "prep_pci.h"
  29
  30 typedef PCIHostState PREPPCIState;
  31
  32 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
  33 {
  34     int i;
  35
  36     for(i = 0; i < 11; i++) {
  37         if ((addr & (1 << (11 + i))) != 0)
  38             break;
  39     }
  40     return (addr & 0x7ff) |  (i << 11);
  41 }
  42
  43 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
  44 {
  45     PREPPCIState *s = opaque;
  46     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
  47 }
  48
  49 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
  50 {
  51     PREPPCIState *s = opaque;
  52     val = bswap16(val);
  53     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
  54 }
  55
  56 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
  57 {
  58     PREPPCIState *s = opaque;
  59     val = bswap32(val);
  60     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
  61 }
  62
  63 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
  64 {
  65     PREPPCIState *s = opaque;
  66     uint32_t val;
  67     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
  68     return val;
  69 }
  70
  71 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
  72 {
  73     PREPPCIState *s = opaque;
  74     uint32_t val;
  75     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
  76     val = bswap16(val);
  77     return val;
  78 }
  79
  80 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
  81 {
  82     PREPPCIState *s = opaque;
  83     uint32_t val;
  84     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
  85     val = bswap32(val);
  86     return val;
  87 }
  88
  89 static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = {
  90     &PPC_PCIIO_writeb,
  91     &PPC_PCIIO_writew,
  92     &PPC_PCIIO_writel,
  93 };
  94
  95 static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
  96     &PPC_PCIIO_readb,
  97     &PPC_PCIIO_readw,
  98     &PPC_PCIIO_readl,
  99 };
 100
 101 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
 102 {
 103     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 104 }
 105
 106 static void prep_set_irq(void *opaque, int irq_num, int level)
 107 {
 108     qemu_irq *pic = opaque;
 109
 110     qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
 111 }
 112
 113 PCIBus *pci_prep_init(qemu_irq *pic,
 114                       MemoryRegion *address_space_mem,
 115                       MemoryRegion *address_space_io)
 116 {
 117     PREPPCIState *s;
 118     PCIDevice *d;
 119     int PPC_io_memory;
 120
 121     s = g_malloc0(sizeof(PREPPCIState));
 122     s->bus = pci_register_bus(NULL, "pci",
 123                               prep_set_irq, prep_map_irq, pic,
 124                               address_space_mem,
 125                               address_space_io,
 126                               0, 4);
 127
 128     memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
 129                           "pci-conf-idx", 1);
 130     memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
 131     sysbus_init_ioports(&s->busdev, 0xcf8, 1);
 132
 133     memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s,
 134                           "pci-conf-data", 1);
 135     memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
 136     sysbus_init_ioports(&s->busdev, 0xcfc, 1);
 137
 138     PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
 139                                            PPC_PCIIO_write, s,
 140                                            DEVICE_NATIVE_ENDIAN);
 141     cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
 142
 143     /* PCI host bridge */
 144     d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
 145                             sizeof(PCIDevice), 0, NULL, NULL);
 146     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 147     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
 148     d->config[0x08] = 0x00; // revision
 149     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 150     d->config[0x0C] = 0x08; // cache_line_size
 151     d->config[0x0D] = 0x10; // latency_timer
 152     d->config[0x34] = 0x00; // capabilities_pointer
 153
 154     return s->bus;
 155 }