2 * Arm SSE (Subsystems for Embedded): IoTKit
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
14 #include "qemu/module.h"
15 #include "qemu/bitops.h"
16 #include "qapi/error.h"
18 #include "hw/sysbus.h"
19 #include "migration/vmstate.h"
20 #include "hw/registerfields.h"
21 #include "hw/arm/armsse.h"
22 #include "hw/arm/boot.h"
24 #include "hw/qdev-clock.h"
26 /* Format of the System Information block SYS_CONFIG register */
27 typedef enum SysConfigFormat
{
38 SysConfigFormat sys_config_format
;
47 static Property iotkit_properties
[] = {
48 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
50 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
51 DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE
, mainclk_frq
, 0),
52 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
53 DEFINE_PROP_UINT32("init-svtor", ARMSSE
, init_svtor
, 0x10000000),
54 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE
, cpu_fpu
[0], true),
55 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE
, cpu_dsp
[0], true),
56 DEFINE_PROP_END_OF_LIST()
59 static Property armsse_properties
[] = {
60 DEFINE_PROP_LINK("memory", ARMSSE
, board_memory
, TYPE_MEMORY_REGION
,
62 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE
, exp_numirq
, 64),
63 DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE
, mainclk_frq
, 0),
64 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE
, sram_addr_width
, 15),
65 DEFINE_PROP_UINT32("init-svtor", ARMSSE
, init_svtor
, 0x10000000),
66 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE
, cpu_fpu
[0], false),
67 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE
, cpu_dsp
[0], false),
68 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE
, cpu_fpu
[1], true),
69 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE
, cpu_dsp
[1], true),
70 DEFINE_PROP_END_OF_LIST()
73 static const ARMSSEInfo armsse_variants
[] = {
78 .sys_version
= 0x41743,
80 .sys_config_format
= IoTKitFormat
,
83 .has_cachectrl
= false,
84 .has_cpusecctrl
= false,
86 .props
= iotkit_properties
,
92 .sys_version
= 0x22041743,
94 .sys_config_format
= SSE200Format
,
97 .has_cachectrl
= true,
98 .has_cpusecctrl
= true,
100 .props
= armsse_properties
,
104 static uint32_t armsse_sys_config_value(ARMSSE
*s
, const ARMSSEInfo
*info
)
106 /* Return the SYS_CONFIG value for this SSE */
109 switch (info
->sys_config_format
) {
112 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
113 sys_config
= deposit32(sys_config
, 4, 4, s
->sram_addr_width
- 12);
117 sys_config
= deposit32(sys_config
, 0, 4, info
->sram_banks
);
118 sys_config
= deposit32(sys_config
, 4, 5, s
->sram_addr_width
);
119 sys_config
= deposit32(sys_config
, 24, 4, 2);
120 if (info
->num_cpus
> 1) {
121 sys_config
= deposit32(sys_config
, 10, 1, 1);
122 sys_config
= deposit32(sys_config
, 20, 4, info
->sram_banks
- 1);
123 sys_config
= deposit32(sys_config
, 28, 4, 2);
127 g_assert_not_reached();
132 /* Clock frequency in HZ of the 32KHz "slow clock" */
133 #define S32KCLK (32 * 1000)
135 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */
136 static bool irq_is_common
[32] = {
138 /* 6, 7: per-CPU MHU interrupts */
140 /* 13: per-CPU icache interrupt */
146 /* 28, 29: per-CPU CTI interrupts */
147 /* 30, 31: reserved */
151 * Create an alias region in @container of @size bytes starting at @base
152 * which mirrors the memory starting at @orig.
154 static void make_alias(ARMSSE
*s
, MemoryRegion
*mr
, MemoryRegion
*container
,
155 const char *name
, hwaddr base
, hwaddr size
, hwaddr orig
)
157 memory_region_init_alias(mr
, NULL
, name
, container
, orig
, size
);
158 /* The alias is even lower priority than unimplemented_device regions */
159 memory_region_add_subregion_overlap(container
, base
, mr
, -1500);
162 static void irq_status_forwarder(void *opaque
, int n
, int level
)
164 qemu_irq destirq
= opaque
;
166 qemu_set_irq(destirq
, level
);
169 static void nsccfg_handler(void *opaque
, int n
, int level
)
171 ARMSSE
*s
= ARM_SSE(opaque
);
176 static void armsse_forward_ppc(ARMSSE
*s
, const char *ppcname
, int ppcnum
)
178 /* Each of the 4 AHB and 4 APB PPCs that might be present in a
179 * system using the ARMSSE has a collection of control lines which
180 * are provided by the security controller and which we want to
181 * expose as control lines on the ARMSSE device itself, so the
182 * code using the ARMSSE can wire them up to the PPCs.
184 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[ppcnum
];
185 DeviceState
*armssedev
= DEVICE(s
);
186 DeviceState
*dev_secctl
= DEVICE(&s
->secctl
);
187 DeviceState
*dev_splitter
= DEVICE(splitter
);
190 name
= g_strdup_printf("%s_nonsec", ppcname
);
191 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
193 name
= g_strdup_printf("%s_ap", ppcname
);
194 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
196 name
= g_strdup_printf("%s_irq_enable", ppcname
);
197 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
199 name
= g_strdup_printf("%s_irq_clear", ppcname
);
200 qdev_pass_gpios(dev_secctl
, armssedev
, name
);
203 /* irq_status is a little more tricky, because we need to
204 * split it so we can send it both to the security controller
205 * and to our OR gate for the NVIC interrupt line.
206 * Connect up the splitter's outputs, and create a GPIO input
207 * which will pass the line state to the input splitter.
209 name
= g_strdup_printf("%s_irq_status", ppcname
);
210 qdev_connect_gpio_out(dev_splitter
, 0,
211 qdev_get_gpio_in_named(dev_secctl
,
213 qdev_connect_gpio_out(dev_splitter
, 1,
214 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), ppcnum
));
215 s
->irq_status_in
[ppcnum
] = qdev_get_gpio_in(dev_splitter
, 0);
216 qdev_init_gpio_in_named_with_opaque(armssedev
, irq_status_forwarder
,
217 s
->irq_status_in
[ppcnum
], name
, 1);
221 static void armsse_forward_sec_resp_cfg(ARMSSE
*s
)
223 /* Forward the 3rd output from the splitter device as a
224 * named GPIO output of the armsse object.
226 DeviceState
*dev
= DEVICE(s
);
227 DeviceState
*dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
229 qdev_init_gpio_out_named(dev
, &s
->sec_resp_cfg
, "sec_resp_cfg", 1);
230 s
->sec_resp_cfg_in
= qemu_allocate_irq(irq_status_forwarder
,
232 qdev_connect_gpio_out(dev_splitter
, 2, s
->sec_resp_cfg_in
);
235 static void armsse_mainclk_update(void *opaque
)
237 ARMSSE
*s
= ARM_SSE(opaque
);
239 * Set system_clock_scale from our Clock input; this is what
240 * controls the tick rate of the CPU SysTick timer.
242 system_clock_scale
= clock_ticks_to_ns(s
->mainclk
, 1);
245 static void armsse_init(Object
*obj
)
247 ARMSSE
*s
= ARM_SSE(obj
);
248 ARMSSEClass
*asc
= ARM_SSE_GET_CLASS(obj
);
249 const ARMSSEInfo
*info
= asc
->info
;
252 assert(info
->sram_banks
<= MAX_SRAM_BANKS
);
253 assert(info
->num_cpus
<= SSE_MAX_CPUS
);
255 s
->mainclk
= qdev_init_clock_in(DEVICE(s
), "MAINCLK",
256 armsse_mainclk_update
, s
);
257 s
->s32kclk
= qdev_init_clock_in(DEVICE(s
), "S32KCLK", NULL
, NULL
);
259 memory_region_init(&s
->container
, obj
, "armsse-container", UINT64_MAX
);
261 for (i
= 0; i
< info
->num_cpus
; i
++) {
263 * We put each CPU in its own cluster as they are logically
264 * distinct and may be configured differently.
268 name
= g_strdup_printf("cluster%d", i
);
269 object_initialize_child(obj
, name
, &s
->cluster
[i
], TYPE_CPU_CLUSTER
);
270 qdev_prop_set_uint32(DEVICE(&s
->cluster
[i
]), "cluster-id", i
);
273 name
= g_strdup_printf("armv7m%d", i
);
274 object_initialize_child(OBJECT(&s
->cluster
[i
]), name
, &s
->armv7m
[i
],
276 qdev_prop_set_string(DEVICE(&s
->armv7m
[i
]), "cpu-type",
277 ARM_CPU_TYPE_NAME("cortex-m33"));
279 name
= g_strdup_printf("arm-sse-cpu-container%d", i
);
280 memory_region_init(&s
->cpu_container
[i
], obj
, name
, UINT64_MAX
);
283 name
= g_strdup_printf("arm-sse-container-alias%d", i
);
284 memory_region_init_alias(&s
->container_alias
[i
- 1], obj
,
285 name
, &s
->container
, 0, UINT64_MAX
);
290 object_initialize_child(obj
, "secctl", &s
->secctl
, TYPE_IOTKIT_SECCTL
);
291 object_initialize_child(obj
, "apb-ppc0", &s
->apb_ppc0
, TYPE_TZ_PPC
);
292 object_initialize_child(obj
, "apb-ppc1", &s
->apb_ppc1
, TYPE_TZ_PPC
);
293 for (i
= 0; i
< info
->sram_banks
; i
++) {
294 char *name
= g_strdup_printf("mpc%d", i
);
295 object_initialize_child(obj
, name
, &s
->mpc
[i
], TYPE_TZ_MPC
);
298 object_initialize_child(obj
, "mpc-irq-orgate", &s
->mpc_irq_orgate
,
301 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
302 char *name
= g_strdup_printf("mpc-irq-splitter-%d", i
);
303 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
305 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
308 object_initialize_child(obj
, "timer0", &s
->timer0
, TYPE_CMSDK_APB_TIMER
);
309 object_initialize_child(obj
, "timer1", &s
->timer1
, TYPE_CMSDK_APB_TIMER
);
310 object_initialize_child(obj
, "s32ktimer", &s
->s32ktimer
,
311 TYPE_CMSDK_APB_TIMER
);
312 object_initialize_child(obj
, "dualtimer", &s
->dualtimer
,
313 TYPE_CMSDK_APB_DUALTIMER
);
314 object_initialize_child(obj
, "s32kwatchdog", &s
->s32kwatchdog
,
315 TYPE_CMSDK_APB_WATCHDOG
);
316 object_initialize_child(obj
, "nswatchdog", &s
->nswatchdog
,
317 TYPE_CMSDK_APB_WATCHDOG
);
318 object_initialize_child(obj
, "swatchdog", &s
->swatchdog
,
319 TYPE_CMSDK_APB_WATCHDOG
);
320 object_initialize_child(obj
, "armsse-sysctl", &s
->sysctl
,
322 object_initialize_child(obj
, "armsse-sysinfo", &s
->sysinfo
,
323 TYPE_IOTKIT_SYSINFO
);
324 if (info
->has_mhus
) {
325 object_initialize_child(obj
, "mhu0", &s
->mhu
[0], TYPE_ARMSSE_MHU
);
326 object_initialize_child(obj
, "mhu1", &s
->mhu
[1], TYPE_ARMSSE_MHU
);
328 if (info
->has_ppus
) {
329 for (i
= 0; i
< info
->num_cpus
; i
++) {
330 char *name
= g_strdup_printf("CPU%dCORE_PPU", i
);
331 int ppuidx
= CPU0CORE_PPU
+ i
;
333 object_initialize_child(obj
, name
, &s
->ppu
[ppuidx
],
334 TYPE_UNIMPLEMENTED_DEVICE
);
337 object_initialize_child(obj
, "DBG_PPU", &s
->ppu
[DBG_PPU
],
338 TYPE_UNIMPLEMENTED_DEVICE
);
339 for (i
= 0; i
< info
->sram_banks
; i
++) {
340 char *name
= g_strdup_printf("RAM%d_PPU", i
);
341 int ppuidx
= RAM0_PPU
+ i
;
343 object_initialize_child(obj
, name
, &s
->ppu
[ppuidx
],
344 TYPE_UNIMPLEMENTED_DEVICE
);
348 if (info
->has_cachectrl
) {
349 for (i
= 0; i
< info
->num_cpus
; i
++) {
350 char *name
= g_strdup_printf("cachectrl%d", i
);
352 object_initialize_child(obj
, name
, &s
->cachectrl
[i
],
353 TYPE_UNIMPLEMENTED_DEVICE
);
357 if (info
->has_cpusecctrl
) {
358 for (i
= 0; i
< info
->num_cpus
; i
++) {
359 char *name
= g_strdup_printf("cpusecctrl%d", i
);
361 object_initialize_child(obj
, name
, &s
->cpusecctrl
[i
],
362 TYPE_UNIMPLEMENTED_DEVICE
);
366 if (info
->has_cpuid
) {
367 for (i
= 0; i
< info
->num_cpus
; i
++) {
368 char *name
= g_strdup_printf("cpuid%d", i
);
370 object_initialize_child(obj
, name
, &s
->cpuid
[i
],
375 object_initialize_child(obj
, "nmi-orgate", &s
->nmi_orgate
, TYPE_OR_IRQ
);
376 object_initialize_child(obj
, "ppc-irq-orgate", &s
->ppc_irq_orgate
,
378 object_initialize_child(obj
, "sec-resp-splitter", &s
->sec_resp_splitter
,
380 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
381 char *name
= g_strdup_printf("ppc-irq-splitter-%d", i
);
382 SplitIRQ
*splitter
= &s
->ppc_irq_splitter
[i
];
384 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
387 if (info
->num_cpus
> 1) {
388 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
389 if (irq_is_common
[i
]) {
390 char *name
= g_strdup_printf("cpu-irq-splitter%d", i
);
391 SplitIRQ
*splitter
= &s
->cpu_irq_splitter
[i
];
393 object_initialize_child(obj
, name
, splitter
, TYPE_SPLIT_IRQ
);
400 static void armsse_exp_irq(void *opaque
, int n
, int level
)
402 qemu_irq
*irqarray
= opaque
;
404 qemu_set_irq(irqarray
[n
], level
);
407 static void armsse_mpcexp_status(void *opaque
, int n
, int level
)
409 ARMSSE
*s
= ARM_SSE(opaque
);
410 qemu_set_irq(s
->mpcexp_status_in
[n
], level
);
413 static qemu_irq
armsse_get_common_irq_in(ARMSSE
*s
, int irqno
)
416 * Return a qemu_irq which can be used to signal IRQ n to
417 * all CPUs in the SSE.
419 ARMSSEClass
*asc
= ARM_SSE_GET_CLASS(s
);
420 const ARMSSEInfo
*info
= asc
->info
;
422 assert(irq_is_common
[irqno
]);
424 if (info
->num_cpus
== 1) {
425 /* Only one CPU -- just connect directly to it */
426 return qdev_get_gpio_in(DEVICE(&s
->armv7m
[0]), irqno
);
428 /* Connect to the splitter which feeds all CPUs */
429 return qdev_get_gpio_in(DEVICE(&s
->cpu_irq_splitter
[irqno
]), 0);
433 static void map_ppu(ARMSSE
*s
, int ppuidx
, const char *name
, hwaddr addr
)
435 /* Map a PPU unimplemented device stub */
436 DeviceState
*dev
= DEVICE(&s
->ppu
[ppuidx
]);
438 qdev_prop_set_string(dev
, "name", name
);
439 qdev_prop_set_uint64(dev
, "size", 0x1000);
440 sysbus_realize(SYS_BUS_DEVICE(dev
), &error_fatal
);
441 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ppu
[ppuidx
]), 0, addr
);
444 static void armsse_realize(DeviceState
*dev
, Error
**errp
)
446 ARMSSE
*s
= ARM_SSE(dev
);
447 ARMSSEClass
*asc
= ARM_SSE_GET_CLASS(dev
);
448 const ARMSSEInfo
*info
= asc
->info
;
452 SysBusDevice
*sbd_apb_ppc0
;
453 SysBusDevice
*sbd_secctl
;
454 DeviceState
*dev_apb_ppc0
;
455 DeviceState
*dev_apb_ppc1
;
456 DeviceState
*dev_secctl
;
457 DeviceState
*dev_splitter
;
458 uint32_t addr_width_max
;
460 if (!s
->board_memory
) {
461 error_setg(errp
, "memory property was not set");
465 if (!clock_has_source(s
->mainclk
)) {
466 error_setg(errp
, "MAINCLK clock was not connected");
468 if (!clock_has_source(s
->s32kclk
)) {
469 error_setg(errp
, "S32KCLK clock was not connected");
472 assert(info
->num_cpus
<= SSE_MAX_CPUS
);
474 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
475 assert(is_power_of_2(info
->sram_banks
));
476 addr_width_max
= 24 - ctz32(info
->sram_banks
);
477 if (s
->sram_addr_width
< 1 || s
->sram_addr_width
> addr_width_max
) {
478 error_setg(errp
, "SRAM_ADDR_WIDTH must be between 1 and %d",
483 /* Handling of which devices should be available only to secure
484 * code is usually done differently for M profile than for A profile.
485 * Instead of putting some devices only into the secure address space,
486 * devices exist in both address spaces but with hard-wired security
487 * permissions that will cause the CPU to fault for non-secure accesses.
489 * The ARMSSE has an IDAU (Implementation Defined Access Unit),
490 * which specifies hard-wired security permissions for different
491 * areas of the physical address space. For the ARMSSE IDAU, the
492 * top 4 bits of the physical address are the IDAU region ID, and
493 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
494 * region, otherwise it is an S region.
496 * The various devices and RAMs are generally all mapped twice,
497 * once into a region that the IDAU defines as secure and once
498 * into a non-secure region. They sit behind either a Memory
499 * Protection Controller (for RAM) or a Peripheral Protection
500 * Controller (for devices), which allow a more fine grained
501 * configuration of whether non-secure accesses are permitted.
503 * (The other place that guest software can configure security
504 * permissions is in the architected SAU (Security Attribution
505 * Unit), which is entirely inside the CPU. The IDAU can upgrade
506 * the security attributes for a region to more restrictive than
507 * the SAU specifies, but cannot downgrade them.)
509 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff
510 * 0x20000000..0x2007ffff 32KB FPGA block RAM
511 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
512 * 0x40000000..0x4000ffff base peripheral region 1
513 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
514 * 0x40020000..0x4002ffff system control element peripherals
515 * 0x40080000..0x400fffff base peripheral region 2
516 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
519 memory_region_add_subregion_overlap(&s
->container
, 0, s
->board_memory
, -2);
521 for (i
= 0; i
< info
->num_cpus
; i
++) {
522 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[i
]);
523 Object
*cpuobj
= OBJECT(&s
->armv7m
[i
]);
527 qdev_prop_set_uint32(cpudev
, "num-irq", s
->exp_numirq
+ 32);
529 * In real hardware the initial Secure VTOR is set from the INITSVTOR*
530 * registers in the IoT Kit System Control Register block. In QEMU
531 * we set the initial value here, and also the reset value of the
532 * sysctl register, from this object's QOM init-svtor property.
533 * If the guest changes the INITSVTOR* registers at runtime then the
534 * code in iotkit-sysctl.c will update the CPU init-svtor property
535 * (which will then take effect on the next CPU warm-reset).
537 * Note that typically a board using the SSE-200 will have a system
538 * control processor whose boot firmware initializes the INITSVTOR*
539 * registers before powering up the CPUs. QEMU doesn't emulate
540 * the control processor, so instead we behave in the way that the
541 * firmware does: the initial value should be set by the board code
542 * (using the init-svtor property on the ARMSSE object) to match
543 * whatever its firmware does.
545 qdev_prop_set_uint32(cpudev
, "init-svtor", s
->init_svtor
);
547 * CPUs start powered down if the corresponding bit in the CPUWAIT
548 * register is 1. In real hardware the CPUWAIT register reset value is
549 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
550 * CPUWAIT1_RST parameters), but since all the boards we care about
551 * start CPU0 and leave CPU1 powered off, we hard-code that in
552 * info->cpuwait_rst for now. We can add QOM properties for this
553 * later if necessary.
555 if (extract32(info
->cpuwait_rst
, i
, 1)) {
556 if (!object_property_set_bool(cpuobj
, "start-powered-off", true,
561 if (!s
->cpu_fpu
[i
]) {
562 if (!object_property_set_bool(cpuobj
, "vfp", false, errp
)) {
566 if (!s
->cpu_dsp
[i
]) {
567 if (!object_property_set_bool(cpuobj
, "dsp", false, errp
)) {
573 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
574 &s
->container_alias
[i
- 1], -1);
576 memory_region_add_subregion_overlap(&s
->cpu_container
[i
], 0,
579 object_property_set_link(cpuobj
, "memory",
580 OBJECT(&s
->cpu_container
[i
]), &error_abort
);
581 object_property_set_link(cpuobj
, "idau", OBJECT(s
), &error_abort
);
582 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj
), errp
)) {
586 * The cluster must be realized after the armv7m container, as
587 * the container's CPU object is only created on realize, and the
588 * CPU must exist and have been parented into the cluster before
589 * the cluster is realized.
591 if (!qdev_realize(DEVICE(&s
->cluster
[i
]), NULL
, errp
)) {
595 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
596 s
->exp_irqs
[i
] = g_new(qemu_irq
, s
->exp_numirq
);
597 for (j
= 0; j
< s
->exp_numirq
; j
++) {
598 s
->exp_irqs
[i
][j
] = qdev_get_gpio_in(cpudev
, j
+ 32);
601 gpioname
= g_strdup("EXP_IRQ");
603 gpioname
= g_strdup_printf("EXP_CPU%d_IRQ", i
);
605 qdev_init_gpio_in_named_with_opaque(dev
, armsse_exp_irq
,
607 gpioname
, s
->exp_numirq
);
611 /* Wire up the splitters that connect common IRQs to all CPUs */
612 if (info
->num_cpus
> 1) {
613 for (i
= 0; i
< ARRAY_SIZE(s
->cpu_irq_splitter
); i
++) {
614 if (irq_is_common
[i
]) {
615 Object
*splitter
= OBJECT(&s
->cpu_irq_splitter
[i
]);
616 DeviceState
*devs
= DEVICE(splitter
);
619 if (!object_property_set_int(splitter
, "num-lines",
620 info
->num_cpus
, errp
)) {
623 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
626 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
627 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
629 qdev_connect_gpio_out(devs
, cpunum
,
630 qdev_get_gpio_in(cpudev
, i
));
636 /* Set up the big aliases first */
637 make_alias(s
, &s
->alias1
, &s
->container
, "alias 1",
638 0x10000000, 0x10000000, 0x00000000);
639 make_alias(s
, &s
->alias2
, &s
->container
,
640 "alias 2", 0x30000000, 0x10000000, 0x20000000);
641 /* The 0x50000000..0x5fffffff region is not a pure alias: it has
642 * a few extra devices that only appear there (generally the
643 * control interfaces for the protection controllers).
644 * We implement this by mapping those devices over the top of this
645 * alias MR at a higher priority. Some of the devices in this range
646 * are per-CPU, so we must put this alias in the per-cpu containers.
648 for (i
= 0; i
< info
->num_cpus
; i
++) {
649 make_alias(s
, &s
->alias3
[i
], &s
->cpu_container
[i
],
650 "alias 3", 0x50000000, 0x10000000, 0x40000000);
653 /* Security controller */
654 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->secctl
), errp
)) {
657 sbd_secctl
= SYS_BUS_DEVICE(&s
->secctl
);
658 dev_secctl
= DEVICE(&s
->secctl
);
659 sysbus_mmio_map(sbd_secctl
, 0, 0x50080000);
660 sysbus_mmio_map(sbd_secctl
, 1, 0x40080000);
662 s
->nsc_cfg_in
= qemu_allocate_irq(nsccfg_handler
, s
, 1);
663 qdev_connect_gpio_out_named(dev_secctl
, "nsc_cfg", 0, s
->nsc_cfg_in
);
665 /* The sec_resp_cfg output from the security controller must be split into
666 * multiple lines, one for each of the PPCs within the ARMSSE and one
667 * that will be an output from the ARMSSE to the system.
669 if (!object_property_set_int(OBJECT(&s
->sec_resp_splitter
),
670 "num-lines", 3, errp
)) {
673 if (!qdev_realize(DEVICE(&s
->sec_resp_splitter
), NULL
, errp
)) {
676 dev_splitter
= DEVICE(&s
->sec_resp_splitter
);
677 qdev_connect_gpio_out_named(dev_secctl
, "sec_resp_cfg", 0,
678 qdev_get_gpio_in(dev_splitter
, 0));
680 /* Each SRAM bank lives behind its own Memory Protection Controller */
681 for (i
= 0; i
< info
->sram_banks
; i
++) {
682 char *ramname
= g_strdup_printf("armsse.sram%d", i
);
683 SysBusDevice
*sbd_mpc
;
684 uint32_t sram_bank_size
= 1 << s
->sram_addr_width
;
686 memory_region_init_ram(&s
->sram
[i
], NULL
, ramname
,
687 sram_bank_size
, &err
);
690 error_propagate(errp
, err
);
693 object_property_set_link(OBJECT(&s
->mpc
[i
]), "downstream",
694 OBJECT(&s
->sram
[i
]), &error_abort
);
695 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->mpc
[i
]), errp
)) {
698 /* Map the upstream end of the MPC into the right place... */
699 sbd_mpc
= SYS_BUS_DEVICE(&s
->mpc
[i
]);
700 memory_region_add_subregion(&s
->container
,
701 0x20000000 + i
* sram_bank_size
,
702 sysbus_mmio_get_region(sbd_mpc
, 1));
703 /* ...and its register interface */
704 memory_region_add_subregion(&s
->container
, 0x50083000 + i
* 0x1000,
705 sysbus_mmio_get_region(sbd_mpc
, 0));
708 /* We must OR together lines from the MPC splitters to go to the NVIC */
709 if (!object_property_set_int(OBJECT(&s
->mpc_irq_orgate
), "num-lines",
710 IOTS_NUM_EXP_MPC
+ info
->sram_banks
,
714 if (!qdev_realize(DEVICE(&s
->mpc_irq_orgate
), NULL
, errp
)) {
717 qdev_connect_gpio_out(DEVICE(&s
->mpc_irq_orgate
), 0,
718 armsse_get_common_irq_in(s
, 9));
720 /* Devices behind APB PPC0:
723 * 0x40002000: dual timer
724 * 0x40003000: MHU0 (SSE-200 only)
725 * 0x40004000: MHU1 (SSE-200 only)
726 * We must configure and realize each downstream device and connect
727 * it to the appropriate PPC port; then we can realize the PPC and
728 * map its upstream ends to the right place in the container.
730 qdev_prop_set_uint32(DEVICE(&s
->timer0
), "pclk-frq", s
->mainclk_frq
);
731 qdev_connect_clock_in(DEVICE(&s
->timer0
), "pclk", s
->mainclk
);
732 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timer0
), errp
)) {
735 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer0
), 0,
736 armsse_get_common_irq_in(s
, 3));
737 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer0
), 0);
738 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[0]", OBJECT(mr
),
741 qdev_prop_set_uint32(DEVICE(&s
->timer1
), "pclk-frq", s
->mainclk_frq
);
742 qdev_connect_clock_in(DEVICE(&s
->timer1
), "pclk", s
->mainclk
);
743 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timer1
), errp
)) {
746 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timer1
), 0,
747 armsse_get_common_irq_in(s
, 4));
748 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->timer1
), 0);
749 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[1]", OBJECT(mr
),
752 qdev_prop_set_uint32(DEVICE(&s
->dualtimer
), "pclk-frq", s
->mainclk_frq
);
753 qdev_connect_clock_in(DEVICE(&s
->dualtimer
), "TIMCLK", s
->mainclk
);
754 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->dualtimer
), errp
)) {
757 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->dualtimer
), 0,
758 armsse_get_common_irq_in(s
, 5));
759 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->dualtimer
), 0);
760 object_property_set_link(OBJECT(&s
->apb_ppc0
), "port[2]", OBJECT(mr
),
763 if (info
->has_mhus
) {
765 * An SSE-200 with only one CPU should have only one MHU created,
766 * with the region where the second MHU usually is being RAZ/WI.
767 * We don't implement that SSE-200 config; if we want to support
768 * it then this code needs to be enhanced to handle creating the
769 * RAZ/WI region instead of the second MHU.
771 assert(info
->num_cpus
== ARRAY_SIZE(s
->mhu
));
773 for (i
= 0; i
< ARRAY_SIZE(s
->mhu
); i
++) {
776 SysBusDevice
*mhu_sbd
= SYS_BUS_DEVICE(&s
->mhu
[i
]);
778 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->mhu
[i
]), errp
)) {
781 port
= g_strdup_printf("port[%d]", i
+ 3);
782 mr
= sysbus_mmio_get_region(mhu_sbd
, 0);
783 object_property_set_link(OBJECT(&s
->apb_ppc0
), port
, OBJECT(mr
),
788 * Each MHU has an irq line for each CPU:
789 * MHU 0 irq line 0 -> CPU 0 IRQ 6
790 * MHU 0 irq line 1 -> CPU 1 IRQ 6
791 * MHU 1 irq line 0 -> CPU 0 IRQ 7
792 * MHU 1 irq line 1 -> CPU 1 IRQ 7
794 for (cpunum
= 0; cpunum
< info
->num_cpus
; cpunum
++) {
795 DeviceState
*cpudev
= DEVICE(&s
->armv7m
[cpunum
]);
797 sysbus_connect_irq(mhu_sbd
, cpunum
,
798 qdev_get_gpio_in(cpudev
, 6 + i
));
803 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->apb_ppc0
), errp
)) {
807 sbd_apb_ppc0
= SYS_BUS_DEVICE(&s
->apb_ppc0
);
808 dev_apb_ppc0
= DEVICE(&s
->apb_ppc0
);
810 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 0);
811 memory_region_add_subregion(&s
->container
, 0x40000000, mr
);
812 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 1);
813 memory_region_add_subregion(&s
->container
, 0x40001000, mr
);
814 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 2);
815 memory_region_add_subregion(&s
->container
, 0x40002000, mr
);
816 if (info
->has_mhus
) {
817 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 3);
818 memory_region_add_subregion(&s
->container
, 0x40003000, mr
);
819 mr
= sysbus_mmio_get_region(sbd_apb_ppc0
, 4);
820 memory_region_add_subregion(&s
->container
, 0x40004000, mr
);
822 for (i
= 0; i
< IOTS_APB_PPC0_NUM_PORTS
; i
++) {
823 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_nonsec", i
,
824 qdev_get_gpio_in_named(dev_apb_ppc0
,
826 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_ap", i
,
827 qdev_get_gpio_in_named(dev_apb_ppc0
,
830 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_enable", 0,
831 qdev_get_gpio_in_named(dev_apb_ppc0
,
833 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc0_irq_clear", 0,
834 qdev_get_gpio_in_named(dev_apb_ppc0
,
836 qdev_connect_gpio_out(dev_splitter
, 0,
837 qdev_get_gpio_in_named(dev_apb_ppc0
,
840 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external
841 * ones) are sent individually to the security controller, and also
842 * ORed together to give a single combined PPC interrupt to the NVIC.
844 if (!object_property_set_int(OBJECT(&s
->ppc_irq_orgate
),
845 "num-lines", NUM_PPCS
, errp
)) {
848 if (!qdev_realize(DEVICE(&s
->ppc_irq_orgate
), NULL
, errp
)) {
851 qdev_connect_gpio_out(DEVICE(&s
->ppc_irq_orgate
), 0,
852 armsse_get_common_irq_in(s
, 10));
855 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
856 * private per-CPU region (all these devices are SSE-200 only):
857 * 0x50010000: L1 icache control registers
858 * 0x50011000: CPUSECCTRL (CPU local security control registers)
859 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
861 if (info
->has_cachectrl
) {
862 for (i
= 0; i
< info
->num_cpus
; i
++) {
863 char *name
= g_strdup_printf("cachectrl%d", i
);
866 qdev_prop_set_string(DEVICE(&s
->cachectrl
[i
]), "name", name
);
868 qdev_prop_set_uint64(DEVICE(&s
->cachectrl
[i
]), "size", 0x1000);
869 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cachectrl
[i
]), errp
)) {
873 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cachectrl
[i
]), 0);
874 memory_region_add_subregion(&s
->cpu_container
[i
], 0x50010000, mr
);
877 if (info
->has_cpusecctrl
) {
878 for (i
= 0; i
< info
->num_cpus
; i
++) {
879 char *name
= g_strdup_printf("CPUSECCTRL%d", i
);
882 qdev_prop_set_string(DEVICE(&s
->cpusecctrl
[i
]), "name", name
);
884 qdev_prop_set_uint64(DEVICE(&s
->cpusecctrl
[i
]), "size", 0x1000);
885 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cpusecctrl
[i
]), errp
)) {
889 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cpusecctrl
[i
]), 0);
890 memory_region_add_subregion(&s
->cpu_container
[i
], 0x50011000, mr
);
893 if (info
->has_cpuid
) {
894 for (i
= 0; i
< info
->num_cpus
; i
++) {
897 qdev_prop_set_uint32(DEVICE(&s
->cpuid
[i
]), "CPUID", i
);
898 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->cpuid
[i
]), errp
)) {
902 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->cpuid
[i
]), 0);
903 memory_region_add_subregion(&s
->cpu_container
[i
], 0x4001F000, mr
);
907 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
908 /* Devices behind APB PPC1:
909 * 0x4002f000: S32K timer
911 qdev_prop_set_uint32(DEVICE(&s
->s32ktimer
), "pclk-frq", S32KCLK
);
912 qdev_connect_clock_in(DEVICE(&s
->s32ktimer
), "pclk", s
->s32kclk
);
913 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->s32ktimer
), errp
)) {
916 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32ktimer
), 0,
917 armsse_get_common_irq_in(s
, 2));
918 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->s32ktimer
), 0);
919 object_property_set_link(OBJECT(&s
->apb_ppc1
), "port[0]", OBJECT(mr
),
922 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->apb_ppc1
), errp
)) {
925 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->apb_ppc1
), 0);
926 memory_region_add_subregion(&s
->container
, 0x4002f000, mr
);
928 dev_apb_ppc1
= DEVICE(&s
->apb_ppc1
);
929 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_nonsec", 0,
930 qdev_get_gpio_in_named(dev_apb_ppc1
,
932 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_ap", 0,
933 qdev_get_gpio_in_named(dev_apb_ppc1
,
935 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_enable", 0,
936 qdev_get_gpio_in_named(dev_apb_ppc1
,
938 qdev_connect_gpio_out_named(dev_secctl
, "apb_ppc1_irq_clear", 0,
939 qdev_get_gpio_in_named(dev_apb_ppc1
,
941 qdev_connect_gpio_out(dev_splitter
, 1,
942 qdev_get_gpio_in_named(dev_apb_ppc1
,
945 if (!object_property_set_int(OBJECT(&s
->sysinfo
), "SYS_VERSION",
946 info
->sys_version
, errp
)) {
949 if (!object_property_set_int(OBJECT(&s
->sysinfo
), "SYS_CONFIG",
950 armsse_sys_config_value(s
, info
), errp
)) {
953 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sysinfo
), errp
)) {
956 /* System information registers */
957 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysinfo
), 0, 0x40020000);
958 /* System control registers */
959 object_property_set_int(OBJECT(&s
->sysctl
), "SYS_VERSION",
960 info
->sys_version
, &error_abort
);
961 object_property_set_int(OBJECT(&s
->sysctl
), "CPUWAIT_RST",
962 info
->cpuwait_rst
, &error_abort
);
963 object_property_set_int(OBJECT(&s
->sysctl
), "INITSVTOR0_RST",
964 s
->init_svtor
, &error_abort
);
965 object_property_set_int(OBJECT(&s
->sysctl
), "INITSVTOR1_RST",
966 s
->init_svtor
, &error_abort
);
967 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sysctl
), errp
)) {
970 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sysctl
), 0, 0x50021000);
972 if (info
->has_ppus
) {
973 /* CPUnCORE_PPU for each CPU */
974 for (i
= 0; i
< info
->num_cpus
; i
++) {
975 char *name
= g_strdup_printf("CPU%dCORE_PPU", i
);
977 map_ppu(s
, CPU0CORE_PPU
+ i
, name
, 0x50023000 + i
* 0x2000);
979 * We don't support CPU debug so don't create the
980 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000.
984 map_ppu(s
, DBG_PPU
, "DBG_PPU", 0x50029000);
986 for (i
= 0; i
< info
->sram_banks
; i
++) {
987 char *name
= g_strdup_printf("RAM%d_PPU", i
);
989 map_ppu(s
, RAM0_PPU
+ i
, name
, 0x5002a000 + i
* 0x1000);
994 /* This OR gate wires together outputs from the secure watchdogs to NMI */
995 if (!object_property_set_int(OBJECT(&s
->nmi_orgate
), "num-lines", 2,
999 if (!qdev_realize(DEVICE(&s
->nmi_orgate
), NULL
, errp
)) {
1002 qdev_connect_gpio_out(DEVICE(&s
->nmi_orgate
), 0,
1003 qdev_get_gpio_in_named(DEVICE(&s
->armv7m
), "NMI", 0));
1005 qdev_prop_set_uint32(DEVICE(&s
->s32kwatchdog
), "wdogclk-frq", S32KCLK
);
1006 qdev_connect_clock_in(DEVICE(&s
->s32kwatchdog
), "WDOGCLK", s
->s32kclk
);
1007 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->s32kwatchdog
), errp
)) {
1010 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0,
1011 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 0));
1012 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->s32kwatchdog
), 0, 0x5002e000);
1014 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
1016 qdev_prop_set_uint32(DEVICE(&s
->nswatchdog
), "wdogclk-frq", s
->mainclk_frq
);
1017 qdev_connect_clock_in(DEVICE(&s
->nswatchdog
), "WDOGCLK", s
->mainclk
);
1018 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->nswatchdog
), errp
)) {
1021 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->nswatchdog
), 0,
1022 armsse_get_common_irq_in(s
, 1));
1023 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->nswatchdog
), 0, 0x40081000);
1025 qdev_prop_set_uint32(DEVICE(&s
->swatchdog
), "wdogclk-frq", s
->mainclk_frq
);
1026 qdev_connect_clock_in(DEVICE(&s
->swatchdog
), "WDOGCLK", s
->mainclk
);
1027 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->swatchdog
), errp
)) {
1030 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->swatchdog
), 0,
1031 qdev_get_gpio_in(DEVICE(&s
->nmi_orgate
), 1));
1032 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->swatchdog
), 0, 0x50081000);
1034 for (i
= 0; i
< ARRAY_SIZE(s
->ppc_irq_splitter
); i
++) {
1035 Object
*splitter
= OBJECT(&s
->ppc_irq_splitter
[i
]);
1037 if (!object_property_set_int(splitter
, "num-lines", 2, errp
)) {
1040 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
1045 for (i
= 0; i
< IOTS_NUM_AHB_EXP_PPC
; i
++) {
1046 char *ppcname
= g_strdup_printf("ahb_ppcexp%d", i
);
1048 armsse_forward_ppc(s
, ppcname
, i
);
1052 for (i
= 0; i
< IOTS_NUM_APB_EXP_PPC
; i
++) {
1053 char *ppcname
= g_strdup_printf("apb_ppcexp%d", i
);
1055 armsse_forward_ppc(s
, ppcname
, i
+ IOTS_NUM_AHB_EXP_PPC
);
1059 for (i
= NUM_EXTERNAL_PPCS
; i
< NUM_PPCS
; i
++) {
1060 /* Wire up IRQ splitter for internal PPCs */
1061 DeviceState
*devs
= DEVICE(&s
->ppc_irq_splitter
[i
]);
1062 char *gpioname
= g_strdup_printf("apb_ppc%d_irq_status",
1063 i
- NUM_EXTERNAL_PPCS
);
1064 TZPPC
*ppc
= (i
== NUM_EXTERNAL_PPCS
) ? &s
->apb_ppc0
: &s
->apb_ppc1
;
1066 qdev_connect_gpio_out(devs
, 0,
1067 qdev_get_gpio_in_named(dev_secctl
, gpioname
, 0));
1068 qdev_connect_gpio_out(devs
, 1,
1069 qdev_get_gpio_in(DEVICE(&s
->ppc_irq_orgate
), i
));
1070 qdev_connect_gpio_out_named(DEVICE(ppc
), "irq", 0,
1071 qdev_get_gpio_in(devs
, 0));
1075 /* Wire up the splitters for the MPC IRQs */
1076 for (i
= 0; i
< IOTS_NUM_EXP_MPC
+ info
->sram_banks
; i
++) {
1077 SplitIRQ
*splitter
= &s
->mpc_irq_splitter
[i
];
1078 DeviceState
*dev_splitter
= DEVICE(splitter
);
1080 if (!object_property_set_int(OBJECT(splitter
), "num-lines", 2,
1084 if (!qdev_realize(DEVICE(splitter
), NULL
, errp
)) {
1088 if (i
< IOTS_NUM_EXP_MPC
) {
1089 /* Splitter input is from GPIO input line */
1090 s
->mpcexp_status_in
[i
] = qdev_get_gpio_in(dev_splitter
, 0);
1091 qdev_connect_gpio_out(dev_splitter
, 0,
1092 qdev_get_gpio_in_named(dev_secctl
,
1093 "mpcexp_status", i
));
1095 /* Splitter input is from our own MPC */
1096 qdev_connect_gpio_out_named(DEVICE(&s
->mpc
[i
- IOTS_NUM_EXP_MPC
]),
1098 qdev_get_gpio_in(dev_splitter
, 0));
1099 qdev_connect_gpio_out(dev_splitter
, 0,
1100 qdev_get_gpio_in_named(dev_secctl
,
1102 i
- IOTS_NUM_EXP_MPC
));
1105 qdev_connect_gpio_out(dev_splitter
, 1,
1106 qdev_get_gpio_in(DEVICE(&s
->mpc_irq_orgate
), i
));
1108 /* Create GPIO inputs which will pass the line state for our
1109 * mpcexp_irq inputs to the correct splitter devices.
1111 qdev_init_gpio_in_named(dev
, armsse_mpcexp_status
, "mpcexp_status",
1114 armsse_forward_sec_resp_cfg(s
);
1116 /* Forward the MSC related signals */
1117 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_status");
1118 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_clear");
1119 qdev_pass_gpios(dev_secctl
, dev
, "mscexp_ns");
1120 qdev_connect_gpio_out_named(dev_secctl
, "msc_irq", 0,
1121 armsse_get_common_irq_in(s
, 11));
1124 * Expose our container region to the board model; this corresponds
1125 * to the AHB Slave Expansion ports which allow bus master devices
1126 * (eg DMA controllers) in the board model to make transactions into
1127 * devices in the ARMSSE.
1129 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->container
);
1131 /* Set initial system_clock_scale from MAINCLK */
1132 armsse_mainclk_update(s
);
1135 static void armsse_idau_check(IDAUInterface
*ii
, uint32_t address
,
1136 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
1139 * For ARMSSE systems the IDAU responses are simple logical functions
1140 * of the address bits. The NSC attribute is guest-adjustable via the
1141 * NSCCFG register in the security controller.
1143 ARMSSE
*s
= ARM_SSE(ii
);
1144 int region
= extract32(address
, 28, 4);
1146 *ns
= !(region
& 1);
1147 *nsc
= (region
== 1 && (s
->nsccfg
& 1)) || (region
== 3 && (s
->nsccfg
& 2));
1148 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
1149 *exempt
= (address
& 0xeff00000) == 0xe0000000;
1153 static const VMStateDescription armsse_vmstate
= {
1156 .minimum_version_id
= 2,
1157 .fields
= (VMStateField
[]) {
1158 VMSTATE_CLOCK(mainclk
, ARMSSE
),
1159 VMSTATE_CLOCK(s32kclk
, ARMSSE
),
1160 VMSTATE_UINT32(nsccfg
, ARMSSE
),
1161 VMSTATE_END_OF_LIST()
1165 static void armsse_reset(DeviceState
*dev
)
1167 ARMSSE
*s
= ARM_SSE(dev
);
1172 static void armsse_class_init(ObjectClass
*klass
, void *data
)
1174 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1175 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(klass
);
1176 ARMSSEClass
*asc
= ARM_SSE_CLASS(klass
);
1177 const ARMSSEInfo
*info
= data
;
1179 dc
->realize
= armsse_realize
;
1180 dc
->vmsd
= &armsse_vmstate
;
1181 device_class_set_props(dc
, info
->props
);
1182 dc
->reset
= armsse_reset
;
1183 iic
->check
= armsse_idau_check
;
1187 static const TypeInfo armsse_info
= {
1188 .name
= TYPE_ARM_SSE
,
1189 .parent
= TYPE_SYS_BUS_DEVICE
,
1190 .instance_size
= sizeof(ARMSSE
),
1191 .class_size
= sizeof(ARMSSEClass
),
1192 .instance_init
= armsse_init
,
1194 .interfaces
= (InterfaceInfo
[]) {
1195 { TYPE_IDAU_INTERFACE
},
1200 static void armsse_register_types(void)
1204 type_register_static(&armsse_info
);
1206 for (i
= 0; i
< ARRAY_SIZE(armsse_variants
); i
++) {
1208 .name
= armsse_variants
[i
].name
,
1209 .parent
= TYPE_ARM_SSE
,
1210 .class_init
= armsse_class_init
,
1211 .class_data
= (void *)&armsse_variants
[i
],
1217 type_init(armsse_register_types
);