2 * Xilinx Zynq cadence TTC model
4 * Copyright (c) 2011 Xilinx Inc.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
6 * Copyright (c) 2012 PetaLogix Pty Ltd.
7 * Written By Haibing Ma
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "hw/sysbus.h"
21 #include "qemu/module.h"
22 #include "qemu/timer.h"
24 #ifdef CADENCE_TTC_ERR_DEBUG
25 #define DB_PRINT(...) do { \
26 fprintf(stderr, ": %s: ", __func__); \
27 fprintf(stderr, ## __VA_ARGS__); \
33 #define COUNTER_INTR_IV 0x00000001
34 #define COUNTER_INTR_M1 0x00000002
35 #define COUNTER_INTR_M2 0x00000004
36 #define COUNTER_INTR_M3 0x00000008
37 #define COUNTER_INTR_OV 0x00000010
38 #define COUNTER_INTR_EV 0x00000020
40 #define COUNTER_CTRL_DIS 0x00000001
41 #define COUNTER_CTRL_INT 0x00000002
42 #define COUNTER_CTRL_DEC 0x00000004
43 #define COUNTER_CTRL_MATCH 0x00000008
44 #define COUNTER_CTRL_RST 0x00000010
46 #define CLOCK_CTRL_PS_EN 0x00000001
47 #define CLOCK_CTRL_PS_V 0x0000001e
56 uint16_t reg_interval
;
57 uint16_t reg_match
[3];
60 uint32_t reg_event_ctrl
;
64 unsigned int cpu_time_valid
;
69 #define TYPE_CADENCE_TTC "cadence_ttc"
70 #define CADENCE_TTC(obj) \
71 OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC)
73 typedef struct CadenceTTCState
{
74 SysBusDevice parent_obj
;
77 CadenceTimerState timer
[3];
80 static void cadence_timer_update(CadenceTimerState
*s
)
82 qemu_set_irq(s
->irq
, !!(s
->reg_intr
& s
->reg_intr_en
));
85 static CadenceTimerState
*cadence_timer_from_addr(void *opaque
,
89 CadenceTTCState
*s
= (CadenceTTCState
*)opaque
;
91 index
= (offset
>> 2) % 3;
93 return &s
->timer
[index
];
96 static uint64_t cadence_timer_get_ns(CadenceTimerState
*s
, uint64_t timer_steps
)
98 /* timer_steps has max value of 0x100000000. double check it
99 * (or overflow can happen below) */
100 assert(timer_steps
<= 1ULL << 32);
102 uint64_t r
= timer_steps
* 1000000000ULL;
103 if (s
->reg_clock
& CLOCK_CTRL_PS_EN
) {
104 r
>>= 16 - (((s
->reg_clock
& CLOCK_CTRL_PS_V
) >> 1) + 1);
108 r
/= (uint64_t)s
->freq
;
112 static uint64_t cadence_timer_get_steps(CadenceTimerState
*s
, uint64_t ns
)
114 uint64_t to_divide
= 1000000000ULL;
117 /* for very large intervals (> 8s) do some division first to stop
118 * overflow (costs some prescision) */
119 while (r
>= 8ULL << 30 && to_divide
> 1) {
124 /* keep early-dividing as needed */
125 while (r
>= 8ULL << 30 && to_divide
> 1) {
129 r
*= (uint64_t)s
->freq
;
130 if (s
->reg_clock
& CLOCK_CTRL_PS_EN
) {
131 r
/= 1 << (((s
->reg_clock
& CLOCK_CTRL_PS_V
) >> 1) + 1);
138 /* determine if x is in between a and b, exclusive of a, inclusive of b */
140 static inline int64_t is_between(int64_t x
, int64_t a
, int64_t b
)
143 return x
> a
&& x
<= b
;
145 return x
< a
&& x
>= b
;
148 static void cadence_timer_run(CadenceTimerState
*s
)
151 int64_t event_interval
, next_value
;
153 assert(s
->cpu_time_valid
); /* cadence_timer_sync must be called first */
155 if (s
->reg_count
& COUNTER_CTRL_DIS
) {
156 s
->cpu_time_valid
= 0;
160 { /* figure out what's going to happen next (rollover or match) */
161 int64_t interval
= (uint64_t)((s
->reg_count
& COUNTER_CTRL_INT
) ?
162 (int64_t)s
->reg_interval
+ 1 : 0x10000ULL
) << 16;
163 next_value
= (s
->reg_count
& COUNTER_CTRL_DEC
) ? -1ULL : interval
;
164 for (i
= 0; i
< 3; ++i
) {
165 int64_t cand
= (uint64_t)s
->reg_match
[i
] << 16;
166 if (is_between(cand
, (uint64_t)s
->reg_value
, next_value
)) {
171 DB_PRINT("next timer event value: %09llx\n",
172 (unsigned long long)next_value
);
174 event_interval
= next_value
- (int64_t)s
->reg_value
;
175 event_interval
= (event_interval
< 0) ? -event_interval
: event_interval
;
177 timer_mod(s
->timer
, s
->cpu_time
+
178 cadence_timer_get_ns(s
, event_interval
));
181 static void cadence_timer_sync(CadenceTimerState
*s
)
185 int64_t interval
= ((s
->reg_count
& COUNTER_CTRL_INT
) ?
186 (int64_t)s
->reg_interval
+ 1 : 0x10000ULL
) << 16;
187 uint64_t old_time
= s
->cpu_time
;
189 s
->cpu_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
190 DB_PRINT("cpu time: %lld ns\n", (long long)old_time
);
192 if (!s
->cpu_time_valid
|| old_time
== s
->cpu_time
) {
193 s
->cpu_time_valid
= 1;
197 r
= (int64_t)cadence_timer_get_steps(s
, s
->cpu_time
- old_time
);
198 x
= (int64_t)s
->reg_value
+ ((s
->reg_count
& COUNTER_CTRL_DEC
) ? -r
: r
);
200 for (i
= 0; i
< 3; ++i
) {
201 int64_t m
= (int64_t)s
->reg_match
[i
] << 16;
205 /* check to see if match event has occurred. check m +/- interval
206 * to account for match events in wrap around cases */
207 if (is_between(m
, s
->reg_value
, x
) ||
208 is_between(m
+ interval
, s
->reg_value
, x
) ||
209 is_between(m
- interval
, s
->reg_value
, x
)) {
210 s
->reg_intr
|= (2 << i
);
213 if ((x
< 0) || (x
>= interval
)) {
214 s
->reg_intr
|= (s
->reg_count
& COUNTER_CTRL_INT
) ?
215 COUNTER_INTR_IV
: COUNTER_INTR_OV
;
220 s
->reg_value
= (uint32_t)(x
% interval
);
221 cadence_timer_update(s
);
224 static void cadence_timer_tick(void *opaque
)
226 CadenceTimerState
*s
= opaque
;
229 cadence_timer_sync(s
);
230 cadence_timer_run(s
);
233 static uint32_t cadence_ttc_read_imp(void *opaque
, hwaddr offset
)
235 CadenceTimerState
*s
= cadence_timer_from_addr(opaque
, offset
);
238 cadence_timer_sync(s
);
239 cadence_timer_run(s
);
242 case 0x00: /* clock control */
247 case 0x0c: /* counter control */
252 case 0x18: /* counter value */
255 return (uint16_t)(s
->reg_value
>> 16);
257 case 0x24: /* reg_interval counter */
260 return s
->reg_interval
;
262 case 0x30: /* match 1 counter */
265 return s
->reg_match
[0];
267 case 0x3c: /* match 2 counter */
270 return s
->reg_match
[1];
272 case 0x48: /* match 3 counter */
275 return s
->reg_match
[2];
277 case 0x54: /* interrupt register */
280 /* cleared after read */
283 cadence_timer_update(s
);
286 case 0x60: /* interrupt enable */
289 return s
->reg_intr_en
;
294 return s
->reg_event_ctrl
;
306 static uint64_t cadence_ttc_read(void *opaque
, hwaddr offset
,
309 uint32_t ret
= cadence_ttc_read_imp(opaque
, offset
);
311 DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset
, (unsigned)ret
);
315 static void cadence_ttc_write(void *opaque
, hwaddr offset
,
316 uint64_t value
, unsigned size
)
318 CadenceTimerState
*s
= cadence_timer_from_addr(opaque
, offset
);
320 DB_PRINT("addr: %08x data %08x\n", (unsigned)offset
, (unsigned)value
);
322 cadence_timer_sync(s
);
325 case 0x00: /* clock control */
328 s
->reg_clock
= value
& 0x3F;
331 case 0x0c: /* counter control */
334 if (value
& COUNTER_CTRL_RST
) {
337 s
->reg_count
= value
& 0x3f & ~COUNTER_CTRL_RST
;
340 case 0x24: /* interval register */
343 s
->reg_interval
= value
& 0xffff;
346 case 0x30: /* match register */
349 s
->reg_match
[0] = value
& 0xffff;
352 case 0x3c: /* match register */
355 s
->reg_match
[1] = value
& 0xffff;
358 case 0x48: /* match register */
361 s
->reg_match
[2] = value
& 0xffff;
364 case 0x54: /* interrupt register */
369 case 0x60: /* interrupt enable */
372 s
->reg_intr_en
= value
& 0x3f;
375 case 0x6c: /* event control */
378 s
->reg_event_ctrl
= value
& 0x07;
385 cadence_timer_run(s
);
386 cadence_timer_update(s
);
389 static const MemoryRegionOps cadence_ttc_ops
= {
390 .read
= cadence_ttc_read
,
391 .write
= cadence_ttc_write
,
392 .endianness
= DEVICE_NATIVE_ENDIAN
,
395 static void cadence_timer_reset(CadenceTimerState
*s
)
400 static void cadence_timer_init(uint32_t freq
, CadenceTimerState
*s
)
402 memset(s
, 0, sizeof(CadenceTimerState
));
405 cadence_timer_reset(s
);
407 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cadence_timer_tick
, s
);
410 static void cadence_ttc_init(Object
*obj
)
412 CadenceTTCState
*s
= CADENCE_TTC(obj
);
415 for (i
= 0; i
< 3; ++i
) {
416 cadence_timer_init(133000000, &s
->timer
[i
]);
417 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->timer
[i
].irq
);
420 memory_region_init_io(&s
->iomem
, obj
, &cadence_ttc_ops
, s
,
422 sysbus_init_mmio(SYS_BUS_DEVICE(obj
), &s
->iomem
);
425 static int cadence_timer_pre_save(void *opaque
)
427 cadence_timer_sync((CadenceTimerState
*)opaque
);
432 static int cadence_timer_post_load(void *opaque
, int version_id
)
434 CadenceTimerState
*s
= opaque
;
436 s
->cpu_time_valid
= 0;
437 cadence_timer_sync(s
);
438 cadence_timer_run(s
);
439 cadence_timer_update(s
);
443 static const VMStateDescription vmstate_cadence_timer
= {
444 .name
= "cadence_timer",
446 .minimum_version_id
= 1,
447 .pre_save
= cadence_timer_pre_save
,
448 .post_load
= cadence_timer_post_load
,
449 .fields
= (VMStateField
[]) {
450 VMSTATE_UINT32(reg_clock
, CadenceTimerState
),
451 VMSTATE_UINT32(reg_count
, CadenceTimerState
),
452 VMSTATE_UINT32(reg_value
, CadenceTimerState
),
453 VMSTATE_UINT16(reg_interval
, CadenceTimerState
),
454 VMSTATE_UINT16_ARRAY(reg_match
, CadenceTimerState
, 3),
455 VMSTATE_UINT32(reg_intr
, CadenceTimerState
),
456 VMSTATE_UINT32(reg_intr_en
, CadenceTimerState
),
457 VMSTATE_UINT32(reg_event_ctrl
, CadenceTimerState
),
458 VMSTATE_UINT32(reg_event
, CadenceTimerState
),
459 VMSTATE_END_OF_LIST()
463 static const VMStateDescription vmstate_cadence_ttc
= {
464 .name
= "cadence_TTC",
466 .minimum_version_id
= 1,
467 .fields
= (VMStateField
[]) {
468 VMSTATE_STRUCT_ARRAY(timer
, CadenceTTCState
, 3, 0,
469 vmstate_cadence_timer
,
471 VMSTATE_END_OF_LIST()
475 static void cadence_ttc_class_init(ObjectClass
*klass
, void *data
)
477 DeviceClass
*dc
= DEVICE_CLASS(klass
);
479 dc
->vmsd
= &vmstate_cadence_ttc
;
482 static const TypeInfo cadence_ttc_info
= {
483 .name
= TYPE_CADENCE_TTC
,
484 .parent
= TYPE_SYS_BUS_DEVICE
,
485 .instance_size
= sizeof(CadenceTTCState
),
486 .instance_init
= cadence_ttc_init
,
487 .class_init
= cadence_ttc_class_init
,
490 static void cadence_ttc_register_types(void)
492 type_register_static(&cadence_ttc_info
);
495 type_init(cadence_ttc_register_types
)