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libcacard: remove unnecessary EOL from debug prints
[qemu/ar7.git] / hw / arm / pxa2xx.c
blobe0cd847b95063fd86473af0ead5e3da3bc77d193
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "hw/sysbus.h"
11 #include "hw/arm/pxa.h"
12 #include "sysemu/sysemu.h"
13 #include "hw/char/serial.h"
14 #include "hw/i2c/i2c.h"
15 #include "hw/ssi.h"
16 #include "sysemu/char.h"
17 #include "sysemu/blockdev.h"
18
19 static struct {
20 hwaddr io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 hwaddr io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
92 unsigned size)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
111 uint64_t value, unsigned size)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 /* Clear the write-one-to-clear bits... */
118 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
119 /* ...and set the plain r/w bits */
120 s->pm_regs[addr >> 2] &= ~0x15;
121 s->pm_regs[addr >> 2] |= value & 0x15;
122 break;
123
124 case PSSR: /* Read-clean registers */
125 case RCSR:
126 case PKSR:
127 s->pm_regs[addr >> 2] &= ~value;
128 break;
129
130 default: /* Read-write registers */
131 if (!(addr & 3)) {
132 s->pm_regs[addr >> 2] = value;
133 break;
134 }
135
136 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
137 break;
138 }
139 }
140
141 static const MemoryRegionOps pxa2xx_pm_ops = {
142 .read = pxa2xx_pm_read,
143 .write = pxa2xx_pm_write,
144 .endianness = DEVICE_NATIVE_ENDIAN,
145 };
146
147 static const VMStateDescription vmstate_pxa2xx_pm = {
148 .name = "pxa2xx_pm",
149 .version_id = 0,
150 .minimum_version_id = 0,
151 .minimum_version_id_old = 0,
152 .fields = (VMStateField[]) {
153 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
154 VMSTATE_END_OF_LIST()
155 }
156 };
157
158 #define CCCR 0x00 /* Core Clock Configuration register */
159 #define CKEN 0x04 /* Clock Enable register */
160 #define OSCC 0x08 /* Oscillator Configuration register */
161 #define CCSR 0x0c /* Core Clock Status register */
162
163 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
164 unsigned size)
165 {
166 PXA2xxState *s = (PXA2xxState *) opaque;
167
168 switch (addr) {
169 case CCCR:
170 case CKEN:
171 case OSCC:
172 return s->cm_regs[addr >> 2];
173
174 case CCSR:
175 return s->cm_regs[CCCR >> 2] | (3 << 28);
176
177 default:
178 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
179 break;
180 }
181 return 0;
182 }
183
184 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
185 uint64_t value, unsigned size)
186 {
187 PXA2xxState *s = (PXA2xxState *) opaque;
188
189 switch (addr) {
190 case CCCR:
191 case CKEN:
192 s->cm_regs[addr >> 2] = value;
193 break;
194
195 case OSCC:
196 s->cm_regs[addr >> 2] &= ~0x6c;
197 s->cm_regs[addr >> 2] |= value & 0x6e;
198 if ((value >> 1) & 1) /* OON */
199 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
200 break;
201
202 default:
203 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
204 break;
205 }
206 }
207
208 static const MemoryRegionOps pxa2xx_cm_ops = {
209 .read = pxa2xx_cm_read,
210 .write = pxa2xx_cm_write,
211 .endianness = DEVICE_NATIVE_ENDIAN,
212 };
213
214 static const VMStateDescription vmstate_pxa2xx_cm = {
215 .name = "pxa2xx_cm",
216 .version_id = 0,
217 .minimum_version_id = 0,
218 .minimum_version_id_old = 0,
219 .fields = (VMStateField[]) {
220 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
221 VMSTATE_UINT32(clkcfg, PXA2xxState),
222 VMSTATE_UINT32(pmnc, PXA2xxState),
223 VMSTATE_END_OF_LIST()
224 }
225 };
226
227 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
228 {
229 PXA2xxState *s = (PXA2xxState *)ri->opaque;
230 return s->clkcfg;
231 }
232
233 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
234 uint64_t value)
235 {
236 PXA2xxState *s = (PXA2xxState *)ri->opaque;
237 s->clkcfg = value & 0xf;
238 if (value & 2) {
239 printf("%s: CPU frequency change attempt\n", __func__);
240 }
241 }
242
243 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
244 uint64_t value)
245 {
246 PXA2xxState *s = (PXA2xxState *)ri->opaque;
247 static const char *pwrmode[8] = {
248 "Normal", "Idle", "Deep-idle", "Standby",
249 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
250 };
251
252 if (value & 8) {
253 printf("%s: CPU voltage change attempt\n", __func__);
254 }
255 switch (value & 7) {
256 case 0:
257 /* Do nothing */
258 break;
259
260 case 1:
261 /* Idle */
262 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
263 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
264 break;
265 }
266 /* Fall through. */
267
268 case 2:
269 /* Deep-Idle */
270 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
271 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
272 goto message;
273
274 case 3:
275 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
276 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
277 s->cpu->env.cp15.c1_sys = 0;
278 s->cpu->env.cp15.c1_coproc = 0;
279 s->cpu->env.cp15.ttbr0_el1 = 0;
280 s->cpu->env.cp15.c3 = 0;
281 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
282 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
283
284 /*
285 * The scratch-pad register is almost universally used
286 * for storing the return address on suspend. For the
287 * lack of a resuming bootloader, perform a jump
288 * directly to that address.
289 */
290 memset(s->cpu->env.regs, 0, 4 * 15);
291 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
292
293 #if 0
294 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
295 cpu_physical_memory_write(0, &buffer, 4);
296 buffer = s->pm_regs[PSPR >> 2];
297 cpu_physical_memory_write(8, &buffer, 4);
298 #endif
299
300 /* Suspend */
301 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
302
303 goto message;
304
305 default:
306 message:
307 printf("%s: machine entered %s mode\n", __func__,
308 pwrmode[value & 7]);
309 }
310 }
311
312 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
313 {
314 PXA2xxState *s = (PXA2xxState *)ri->opaque;
315 return s->pmnc;
316 }
317
318 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
319 uint64_t value)
320 {
321 PXA2xxState *s = (PXA2xxState *)ri->opaque;
322 s->pmnc = value;
323 }
324
325 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
326 {
327 PXA2xxState *s = (PXA2xxState *)ri->opaque;
328 if (s->pmnc & 1) {
329 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
330 } else {
331 return 0;
332 }
333 }
334
335 static const ARMCPRegInfo pxa_cp_reginfo[] = {
336 /* cp14 crm==1: perf registers */
337 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
338 .access = PL1_RW,
339 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
340 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
341 .access = PL1_RW,
342 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
343 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
344 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
345 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
346 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
347 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
348 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
349 /* cp14 crm==2: performance count registers */
350 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
351 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
352 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
353 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
354 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
355 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
356 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
357 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
358 /* cp14 crn==6: CLKCFG */
359 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
360 .access = PL1_RW,
361 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
362 /* cp14 crn==7: PWRMODE */
363 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
364 .access = PL1_RW,
365 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
366 REGINFO_SENTINEL
367 };
368
369 static void pxa2xx_setup_cp14(PXA2xxState *s)
370 {
371 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
372 }
373
374 #define MDCNFG 0x00 /* SDRAM Configuration register */
375 #define MDREFR 0x04 /* SDRAM Refresh Control register */
376 #define MSC0 0x08 /* Static Memory Control register 0 */
377 #define MSC1 0x0c /* Static Memory Control register 1 */
378 #define MSC2 0x10 /* Static Memory Control register 2 */
379 #define MECR 0x14 /* Expansion Memory Bus Config register */
380 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
381 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
382 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
383 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
384 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
385 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
386 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
387 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
388 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
389 #define ARB_CNTL 0x48 /* Arbiter Control register */
390 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
391 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
392 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
393 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
394 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
395 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
396 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
397
398 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
399 unsigned size)
400 {
401 PXA2xxState *s = (PXA2xxState *) opaque;
402
403 switch (addr) {
404 case MDCNFG ... SA1110:
405 if ((addr & 3) == 0)
406 return s->mm_regs[addr >> 2];
407
408 default:
409 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
410 break;
411 }
412 return 0;
413 }
414
415 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
416 uint64_t value, unsigned size)
417 {
418 PXA2xxState *s = (PXA2xxState *) opaque;
419
420 switch (addr) {
421 case MDCNFG ... SA1110:
422 if ((addr & 3) == 0) {
423 s->mm_regs[addr >> 2] = value;
424 break;
425 }
426
427 default:
428 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
429 break;
430 }
431 }
432
433 static const MemoryRegionOps pxa2xx_mm_ops = {
434 .read = pxa2xx_mm_read,
435 .write = pxa2xx_mm_write,
436 .endianness = DEVICE_NATIVE_ENDIAN,
437 };
438
439 static const VMStateDescription vmstate_pxa2xx_mm = {
440 .name = "pxa2xx_mm",
441 .version_id = 0,
442 .minimum_version_id = 0,
443 .minimum_version_id_old = 0,
444 .fields = (VMStateField[]) {
445 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
446 VMSTATE_END_OF_LIST()
447 }
448 };
449
450 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
451 #define PXA2XX_SSP(obj) \
452 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
453
454 /* Synchronous Serial Ports */
455 typedef struct {
456 /*< private >*/
457 SysBusDevice parent_obj;
458 /*< public >*/
459
460 MemoryRegion iomem;
461 qemu_irq irq;
462 int enable;
463 SSIBus *bus;
464
465 uint32_t sscr[2];
466 uint32_t sspsp;
467 uint32_t ssto;
468 uint32_t ssitr;
469 uint32_t sssr;
470 uint8_t sstsa;
471 uint8_t ssrsa;
472 uint8_t ssacd;
473
474 uint32_t rx_fifo[16];
475 int rx_level;
476 int rx_start;
477 } PXA2xxSSPState;
478
479 #define SSCR0 0x00 /* SSP Control register 0 */
480 #define SSCR1 0x04 /* SSP Control register 1 */
481 #define SSSR 0x08 /* SSP Status register */
482 #define SSITR 0x0c /* SSP Interrupt Test register */
483 #define SSDR 0x10 /* SSP Data register */
484 #define SSTO 0x28 /* SSP Time-Out register */
485 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
486 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
487 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
488 #define SSTSS 0x38 /* SSP Time Slot Status register */
489 #define SSACD 0x3c /* SSP Audio Clock Divider register */
490
491 /* Bitfields for above registers */
492 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
493 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
494 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
495 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
496 #define SSCR0_SSE (1 << 7)
497 #define SSCR0_RIM (1 << 22)
498 #define SSCR0_TIM (1 << 23)
499 #define SSCR0_MOD (1U << 31)
500 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
501 #define SSCR1_RIE (1 << 0)
502 #define SSCR1_TIE (1 << 1)
503 #define SSCR1_LBM (1 << 2)
504 #define SSCR1_MWDS (1 << 5)
505 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
506 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
507 #define SSCR1_EFWR (1 << 14)
508 #define SSCR1_PINTE (1 << 18)
509 #define SSCR1_TINTE (1 << 19)
510 #define SSCR1_RSRE (1 << 20)
511 #define SSCR1_TSRE (1 << 21)
512 #define SSCR1_EBCEI (1 << 29)
513 #define SSITR_INT (7 << 5)
514 #define SSSR_TNF (1 << 2)
515 #define SSSR_RNE (1 << 3)
516 #define SSSR_TFS (1 << 5)
517 #define SSSR_RFS (1 << 6)
518 #define SSSR_ROR (1 << 7)
519 #define SSSR_PINT (1 << 18)
520 #define SSSR_TINT (1 << 19)
521 #define SSSR_EOC (1 << 20)
522 #define SSSR_TUR (1 << 21)
523 #define SSSR_BCE (1 << 23)
524 #define SSSR_RW 0x00bc0080
525
526 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
527 {
528 int level = 0;
529
530 level |= s->ssitr & SSITR_INT;
531 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
532 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
533 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
534 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
535 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
536 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
537 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
538 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
539 qemu_set_irq(s->irq, !!level);
540 }
541
542 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
543 {
544 s->sssr &= ~(0xf << 12); /* Clear RFL */
545 s->sssr &= ~(0xf << 8); /* Clear TFL */
546 s->sssr &= ~SSSR_TFS;
547 s->sssr &= ~SSSR_TNF;
548 if (s->enable) {
549 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
550 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
551 s->sssr |= SSSR_RFS;
552 else
553 s->sssr &= ~SSSR_RFS;
554 if (s->rx_level)
555 s->sssr |= SSSR_RNE;
556 else
557 s->sssr &= ~SSSR_RNE;
558 /* TX FIFO is never filled, so it is always in underrun
559 condition if SSP is enabled */
560 s->sssr |= SSSR_TFS;
561 s->sssr |= SSSR_TNF;
562 }
563
564 pxa2xx_ssp_int_update(s);
565 }
566
567 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
568 unsigned size)
569 {
570 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
571 uint32_t retval;
572
573 switch (addr) {
574 case SSCR0:
575 return s->sscr[0];
576 case SSCR1:
577 return s->sscr[1];
578 case SSPSP:
579 return s->sspsp;
580 case SSTO:
581 return s->ssto;
582 case SSITR:
583 return s->ssitr;
584 case SSSR:
585 return s->sssr | s->ssitr;
586 case SSDR:
587 if (!s->enable)
588 return 0xffffffff;
589 if (s->rx_level < 1) {
590 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
591 return 0xffffffff;
592 }
593 s->rx_level --;
594 retval = s->rx_fifo[s->rx_start ++];
595 s->rx_start &= 0xf;
596 pxa2xx_ssp_fifo_update(s);
597 return retval;
598 case SSTSA:
599 return s->sstsa;
600 case SSRSA:
601 return s->ssrsa;
602 case SSTSS:
603 return 0;
604 case SSACD:
605 return s->ssacd;
606 default:
607 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
608 break;
609 }
610 return 0;
611 }
612
613 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
614 uint64_t value64, unsigned size)
615 {
616 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
617 uint32_t value = value64;
618
619 switch (addr) {
620 case SSCR0:
621 s->sscr[0] = value & 0xc7ffffff;
622 s->enable = value & SSCR0_SSE;
623 if (value & SSCR0_MOD)
624 printf("%s: Attempt to use network mode\n", __FUNCTION__);
625 if (s->enable && SSCR0_DSS(value) < 4)
626 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
627 SSCR0_DSS(value));
628 if (!(value & SSCR0_SSE)) {
629 s->sssr = 0;
630 s->ssitr = 0;
631 s->rx_level = 0;
632 }
633 pxa2xx_ssp_fifo_update(s);
634 break;
635
636 case SSCR1:
637 s->sscr[1] = value;
638 if (value & (SSCR1_LBM | SSCR1_EFWR))
639 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
640 pxa2xx_ssp_fifo_update(s);
641 break;
642
643 case SSPSP:
644 s->sspsp = value;
645 break;
646
647 case SSTO:
648 s->ssto = value;
649 break;
650
651 case SSITR:
652 s->ssitr = value & SSITR_INT;
653 pxa2xx_ssp_int_update(s);
654 break;
655
656 case SSSR:
657 s->sssr &= ~(value & SSSR_RW);
658 pxa2xx_ssp_int_update(s);
659 break;
660
661 case SSDR:
662 if (SSCR0_UWIRE(s->sscr[0])) {
663 if (s->sscr[1] & SSCR1_MWDS)
664 value &= 0xffff;
665 else
666 value &= 0xff;
667 } else
668 /* Note how 32bits overflow does no harm here */
669 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
670
671 /* Data goes from here to the Tx FIFO and is shifted out from
672 * there directly to the slave, no need to buffer it.
673 */
674 if (s->enable) {
675 uint32_t readval;
676 readval = ssi_transfer(s->bus, value);
677 if (s->rx_level < 0x10) {
678 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
679 } else {
680 s->sssr |= SSSR_ROR;
681 }
682 }
683 pxa2xx_ssp_fifo_update(s);
684 break;
685
686 case SSTSA:
687 s->sstsa = value;
688 break;
689
690 case SSRSA:
691 s->ssrsa = value;
692 break;
693
694 case SSACD:
695 s->ssacd = value;
696 break;
697
698 default:
699 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
700 break;
701 }
702 }
703
704 static const MemoryRegionOps pxa2xx_ssp_ops = {
705 .read = pxa2xx_ssp_read,
706 .write = pxa2xx_ssp_write,
707 .endianness = DEVICE_NATIVE_ENDIAN,
708 };
709
710 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
711 {
712 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
713 int i;
714
715 qemu_put_be32(f, s->enable);
716
717 qemu_put_be32s(f, &s->sscr[0]);
718 qemu_put_be32s(f, &s->sscr[1]);
719 qemu_put_be32s(f, &s->sspsp);
720 qemu_put_be32s(f, &s->ssto);
721 qemu_put_be32s(f, &s->ssitr);
722 qemu_put_be32s(f, &s->sssr);
723 qemu_put_8s(f, &s->sstsa);
724 qemu_put_8s(f, &s->ssrsa);
725 qemu_put_8s(f, &s->ssacd);
726
727 qemu_put_byte(f, s->rx_level);
728 for (i = 0; i < s->rx_level; i ++)
729 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
730 }
731
732 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
733 {
734 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
735 int i, v;
736
737 s->enable = qemu_get_be32(f);
738
739 qemu_get_be32s(f, &s->sscr[0]);
740 qemu_get_be32s(f, &s->sscr[1]);
741 qemu_get_be32s(f, &s->sspsp);
742 qemu_get_be32s(f, &s->ssto);
743 qemu_get_be32s(f, &s->ssitr);
744 qemu_get_be32s(f, &s->sssr);
745 qemu_get_8s(f, &s->sstsa);
746 qemu_get_8s(f, &s->ssrsa);
747 qemu_get_8s(f, &s->ssacd);
748
749 v = qemu_get_byte(f);
750 if (v < 0 || v > ARRAY_SIZE(s->rx_fifo)) {
751 return -EINVAL;
752 }
753 s->rx_level = v;
754 s->rx_start = 0;
755 for (i = 0; i < s->rx_level; i ++)
756 s->rx_fifo[i] = qemu_get_byte(f);
757
758 return 0;
759 }
760
761 static int pxa2xx_ssp_init(SysBusDevice *sbd)
762 {
763 DeviceState *dev = DEVICE(sbd);
764 PXA2xxSSPState *s = PXA2XX_SSP(dev);
765
766 sysbus_init_irq(sbd, &s->irq);
767
768 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_ssp_ops, s,
769 "pxa2xx-ssp", 0x1000);
770 sysbus_init_mmio(sbd, &s->iomem);
771 register_savevm(dev, "pxa2xx_ssp", -1, 0,
772 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
773
774 s->bus = ssi_create_bus(dev, "ssi");
775 return 0;
776 }
777
778 /* Real-Time Clock */
779 #define RCNR 0x00 /* RTC Counter register */
780 #define RTAR 0x04 /* RTC Alarm register */
781 #define RTSR 0x08 /* RTC Status register */
782 #define RTTR 0x0c /* RTC Timer Trim register */
783 #define RDCR 0x10 /* RTC Day Counter register */
784 #define RYCR 0x14 /* RTC Year Counter register */
785 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
786 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
787 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
788 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
789 #define SWCR 0x28 /* RTC Stopwatch Counter register */
790 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
791 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
792 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
793 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
794
795 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
796 #define PXA2XX_RTC(obj) \
797 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
798
799 typedef struct {
800 /*< private >*/
801 SysBusDevice parent_obj;
802 /*< public >*/
803
804 MemoryRegion iomem;
805 uint32_t rttr;
806 uint32_t rtsr;
807 uint32_t rtar;
808 uint32_t rdar1;
809 uint32_t rdar2;
810 uint32_t ryar1;
811 uint32_t ryar2;
812 uint32_t swar1;
813 uint32_t swar2;
814 uint32_t piar;
815 uint32_t last_rcnr;
816 uint32_t last_rdcr;
817 uint32_t last_rycr;
818 uint32_t last_swcr;
819 uint32_t last_rtcpicr;
820 int64_t last_hz;
821 int64_t last_sw;
822 int64_t last_pi;
823 QEMUTimer *rtc_hz;
824 QEMUTimer *rtc_rdal1;
825 QEMUTimer *rtc_rdal2;
826 QEMUTimer *rtc_swal1;
827 QEMUTimer *rtc_swal2;
828 QEMUTimer *rtc_pi;
829 qemu_irq rtc_irq;
830 } PXA2xxRTCState;
831
832 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
833 {
834 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
835 }
836
837 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
838 {
839 int64_t rt = qemu_clock_get_ms(rtc_clock);
840 s->last_rcnr += ((rt - s->last_hz) << 15) /
841 (1000 * ((s->rttr & 0xffff) + 1));
842 s->last_rdcr += ((rt - s->last_hz) << 15) /
843 (1000 * ((s->rttr & 0xffff) + 1));
844 s->last_hz = rt;
845 }
846
847 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
848 {
849 int64_t rt = qemu_clock_get_ms(rtc_clock);
850 if (s->rtsr & (1 << 12))
851 s->last_swcr += (rt - s->last_sw) / 10;
852 s->last_sw = rt;
853 }
854
855 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
856 {
857 int64_t rt = qemu_clock_get_ms(rtc_clock);
858 if (s->rtsr & (1 << 15))
859 s->last_swcr += rt - s->last_pi;
860 s->last_pi = rt;
861 }
862
863 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
864 uint32_t rtsr)
865 {
866 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
867 timer_mod(s->rtc_hz, s->last_hz +
868 (((s->rtar - s->last_rcnr) * 1000 *
869 ((s->rttr & 0xffff) + 1)) >> 15));
870 else
871 timer_del(s->rtc_hz);
872
873 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
874 timer_mod(s->rtc_rdal1, s->last_hz +
875 (((s->rdar1 - s->last_rdcr) * 1000 *
876 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
877 else
878 timer_del(s->rtc_rdal1);
879
880 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
881 timer_mod(s->rtc_rdal2, s->last_hz +
882 (((s->rdar2 - s->last_rdcr) * 1000 *
883 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
884 else
885 timer_del(s->rtc_rdal2);
886
887 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
888 timer_mod(s->rtc_swal1, s->last_sw +
889 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
890 else
891 timer_del(s->rtc_swal1);
892
893 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
894 timer_mod(s->rtc_swal2, s->last_sw +
895 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
896 else
897 timer_del(s->rtc_swal2);
898
899 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
900 timer_mod(s->rtc_pi, s->last_pi +
901 (s->piar & 0xffff) - s->last_rtcpicr);
902 else
903 timer_del(s->rtc_pi);
904 }
905
906 static inline void pxa2xx_rtc_hz_tick(void *opaque)
907 {
908 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
909 s->rtsr |= (1 << 0);
910 pxa2xx_rtc_alarm_update(s, s->rtsr);
911 pxa2xx_rtc_int_update(s);
912 }
913
914 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
915 {
916 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
917 s->rtsr |= (1 << 4);
918 pxa2xx_rtc_alarm_update(s, s->rtsr);
919 pxa2xx_rtc_int_update(s);
920 }
921
922 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
923 {
924 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
925 s->rtsr |= (1 << 6);
926 pxa2xx_rtc_alarm_update(s, s->rtsr);
927 pxa2xx_rtc_int_update(s);
928 }
929
930 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
931 {
932 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
933 s->rtsr |= (1 << 8);
934 pxa2xx_rtc_alarm_update(s, s->rtsr);
935 pxa2xx_rtc_int_update(s);
936 }
937
938 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
939 {
940 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
941 s->rtsr |= (1 << 10);
942 pxa2xx_rtc_alarm_update(s, s->rtsr);
943 pxa2xx_rtc_int_update(s);
944 }
945
946 static inline void pxa2xx_rtc_pi_tick(void *opaque)
947 {
948 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
949 s->rtsr |= (1 << 13);
950 pxa2xx_rtc_piupdate(s);
951 s->last_rtcpicr = 0;
952 pxa2xx_rtc_alarm_update(s, s->rtsr);
953 pxa2xx_rtc_int_update(s);
954 }
955
956 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
957 unsigned size)
958 {
959 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
960
961 switch (addr) {
962 case RTTR:
963 return s->rttr;
964 case RTSR:
965 return s->rtsr;
966 case RTAR:
967 return s->rtar;
968 case RDAR1:
969 return s->rdar1;
970 case RDAR2:
971 return s->rdar2;
972 case RYAR1:
973 return s->ryar1;
974 case RYAR2:
975 return s->ryar2;
976 case SWAR1:
977 return s->swar1;
978 case SWAR2:
979 return s->swar2;
980 case PIAR:
981 return s->piar;
982 case RCNR:
983 return s->last_rcnr +
984 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
985 (1000 * ((s->rttr & 0xffff) + 1));
986 case RDCR:
987 return s->last_rdcr +
988 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
989 (1000 * ((s->rttr & 0xffff) + 1));
990 case RYCR:
991 return s->last_rycr;
992 case SWCR:
993 if (s->rtsr & (1 << 12))
994 return s->last_swcr +
995 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
996 else
997 return s->last_swcr;
998 default:
999 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1000 break;
1001 }
1002 return 0;
1003 }
1004
1005 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
1006 uint64_t value64, unsigned size)
1007 {
1008 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1009 uint32_t value = value64;
1010
1011 switch (addr) {
1012 case RTTR:
1013 if (!(s->rttr & (1U << 31))) {
1014 pxa2xx_rtc_hzupdate(s);
1015 s->rttr = value;
1016 pxa2xx_rtc_alarm_update(s, s->rtsr);
1017 }
1018 break;
1019
1020 case RTSR:
1021 if ((s->rtsr ^ value) & (1 << 15))
1022 pxa2xx_rtc_piupdate(s);
1023
1024 if ((s->rtsr ^ value) & (1 << 12))
1025 pxa2xx_rtc_swupdate(s);
1026
1027 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1028 pxa2xx_rtc_alarm_update(s, value);
1029
1030 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1031 pxa2xx_rtc_int_update(s);
1032 break;
1033
1034 case RTAR:
1035 s->rtar = value;
1036 pxa2xx_rtc_alarm_update(s, s->rtsr);
1037 break;
1038
1039 case RDAR1:
1040 s->rdar1 = value;
1041 pxa2xx_rtc_alarm_update(s, s->rtsr);
1042 break;
1043
1044 case RDAR2:
1045 s->rdar2 = value;
1046 pxa2xx_rtc_alarm_update(s, s->rtsr);
1047 break;
1048
1049 case RYAR1:
1050 s->ryar1 = value;
1051 pxa2xx_rtc_alarm_update(s, s->rtsr);
1052 break;
1053
1054 case RYAR2:
1055 s->ryar2 = value;
1056 pxa2xx_rtc_alarm_update(s, s->rtsr);
1057 break;
1058
1059 case SWAR1:
1060 pxa2xx_rtc_swupdate(s);
1061 s->swar1 = value;
1062 s->last_swcr = 0;
1063 pxa2xx_rtc_alarm_update(s, s->rtsr);
1064 break;
1065
1066 case SWAR2:
1067 s->swar2 = value;
1068 pxa2xx_rtc_alarm_update(s, s->rtsr);
1069 break;
1070
1071 case PIAR:
1072 s->piar = value;
1073 pxa2xx_rtc_alarm_update(s, s->rtsr);
1074 break;
1075
1076 case RCNR:
1077 pxa2xx_rtc_hzupdate(s);
1078 s->last_rcnr = value;
1079 pxa2xx_rtc_alarm_update(s, s->rtsr);
1080 break;
1081
1082 case RDCR:
1083 pxa2xx_rtc_hzupdate(s);
1084 s->last_rdcr = value;
1085 pxa2xx_rtc_alarm_update(s, s->rtsr);
1086 break;
1087
1088 case RYCR:
1089 s->last_rycr = value;
1090 break;
1091
1092 case SWCR:
1093 pxa2xx_rtc_swupdate(s);
1094 s->last_swcr = value;
1095 pxa2xx_rtc_alarm_update(s, s->rtsr);
1096 break;
1097
1098 case RTCPICR:
1099 pxa2xx_rtc_piupdate(s);
1100 s->last_rtcpicr = value & 0xffff;
1101 pxa2xx_rtc_alarm_update(s, s->rtsr);
1102 break;
1103
1104 default:
1105 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1106 }
1107 }
1108
1109 static const MemoryRegionOps pxa2xx_rtc_ops = {
1110 .read = pxa2xx_rtc_read,
1111 .write = pxa2xx_rtc_write,
1112 .endianness = DEVICE_NATIVE_ENDIAN,
1113 };
1114
1115 static int pxa2xx_rtc_init(SysBusDevice *dev)
1116 {
1117 PXA2xxRTCState *s = PXA2XX_RTC(dev);
1118 struct tm tm;
1119 int wom;
1120
1121 s->rttr = 0x7fff;
1122 s->rtsr = 0;
1123
1124 qemu_get_timedate(&tm, 0);
1125 wom = ((tm.tm_mday - 1) / 7) + 1;
1126
1127 s->last_rcnr = (uint32_t) mktimegm(&tm);
1128 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1129 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1130 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1131 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1132 s->last_swcr = (tm.tm_hour << 19) |
1133 (tm.tm_min << 13) | (tm.tm_sec << 7);
1134 s->last_rtcpicr = 0;
1135 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1136
1137 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
1138 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1139 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1140 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1141 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1142 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
1143
1144 sysbus_init_irq(dev, &s->rtc_irq);
1145
1146 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_rtc_ops, s,
1147 "pxa2xx-rtc", 0x10000);
1148 sysbus_init_mmio(dev, &s->iomem);
1149
1150 return 0;
1151 }
1152
1153 static void pxa2xx_rtc_pre_save(void *opaque)
1154 {
1155 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1156
1157 pxa2xx_rtc_hzupdate(s);
1158 pxa2xx_rtc_piupdate(s);
1159 pxa2xx_rtc_swupdate(s);
1160 }
1161
1162 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1163 {
1164 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1165
1166 pxa2xx_rtc_alarm_update(s, s->rtsr);
1167
1168 return 0;
1169 }
1170
1171 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1172 .name = "pxa2xx_rtc",
1173 .version_id = 0,
1174 .minimum_version_id = 0,
1175 .minimum_version_id_old = 0,
1176 .pre_save = pxa2xx_rtc_pre_save,
1177 .post_load = pxa2xx_rtc_post_load,
1178 .fields = (VMStateField[]) {
1179 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1180 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1181 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1182 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1183 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1184 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1185 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1186 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1187 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1188 VMSTATE_UINT32(piar, PXA2xxRTCState),
1189 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1190 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1191 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1192 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1193 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1194 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1195 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1196 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1197 VMSTATE_END_OF_LIST(),
1198 },
1199 };
1200
1201 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1202 {
1203 DeviceClass *dc = DEVICE_CLASS(klass);
1204 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1205
1206 k->init = pxa2xx_rtc_init;
1207 dc->desc = "PXA2xx RTC Controller";
1208 dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1209 }
1210
1211 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1212 .name = TYPE_PXA2XX_RTC,
1213 .parent = TYPE_SYS_BUS_DEVICE,
1214 .instance_size = sizeof(PXA2xxRTCState),
1215 .class_init = pxa2xx_rtc_sysbus_class_init,
1216 };
1217
1218 /* I2C Interface */
1219
1220 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1221 #define PXA2XX_I2C_SLAVE(obj) \
1222 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1223
1224 typedef struct PXA2xxI2CSlaveState {
1225 I2CSlave parent_obj;
1226
1227 PXA2xxI2CState *host;
1228 } PXA2xxI2CSlaveState;
1229
1230 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1231 #define PXA2XX_I2C(obj) \
1232 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1233
1234 struct PXA2xxI2CState {
1235 /*< private >*/
1236 SysBusDevice parent_obj;
1237 /*< public >*/
1238
1239 MemoryRegion iomem;
1240 PXA2xxI2CSlaveState *slave;
1241 I2CBus *bus;
1242 qemu_irq irq;
1243 uint32_t offset;
1244 uint32_t region_size;
1245
1246 uint16_t control;
1247 uint16_t status;
1248 uint8_t ibmr;
1249 uint8_t data;
1250 };
1251
1252 #define IBMR 0x80 /* I2C Bus Monitor register */
1253 #define IDBR 0x88 /* I2C Data Buffer register */
1254 #define ICR 0x90 /* I2C Control register */
1255 #define ISR 0x98 /* I2C Status register */
1256 #define ISAR 0xa0 /* I2C Slave Address register */
1257
1258 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1259 {
1260 uint16_t level = 0;
1261 level |= s->status & s->control & (1 << 10); /* BED */
1262 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1263 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1264 level |= s->status & (1 << 9); /* SAD */
1265 qemu_set_irq(s->irq, !!level);
1266 }
1267
1268 /* These are only stubs now. */
1269 static void pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1270 {
1271 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1272 PXA2xxI2CState *s = slave->host;
1273
1274 switch (event) {
1275 case I2C_START_SEND:
1276 s->status |= (1 << 9); /* set SAD */
1277 s->status &= ~(1 << 0); /* clear RWM */
1278 break;
1279 case I2C_START_RECV:
1280 s->status |= (1 << 9); /* set SAD */
1281 s->status |= 1 << 0; /* set RWM */
1282 break;
1283 case I2C_FINISH:
1284 s->status |= (1 << 4); /* set SSD */
1285 break;
1286 case I2C_NACK:
1287 s->status |= 1 << 1; /* set ACKNAK */
1288 break;
1289 }
1290 pxa2xx_i2c_update(s);
1291 }
1292
1293 static int pxa2xx_i2c_rx(I2CSlave *i2c)
1294 {
1295 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1296 PXA2xxI2CState *s = slave->host;
1297
1298 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1299 return 0;
1300 }
1301
1302 if (s->status & (1 << 0)) { /* RWM */
1303 s->status |= 1 << 6; /* set ITE */
1304 }
1305 pxa2xx_i2c_update(s);
1306
1307 return s->data;
1308 }
1309
1310 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1311 {
1312 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1313 PXA2xxI2CState *s = slave->host;
1314
1315 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1316 return 1;
1317 }
1318
1319 if (!(s->status & (1 << 0))) { /* RWM */
1320 s->status |= 1 << 7; /* set IRF */
1321 s->data = data;
1322 }
1323 pxa2xx_i2c_update(s);
1324
1325 return 1;
1326 }
1327
1328 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1329 unsigned size)
1330 {
1331 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1332 I2CSlave *slave;
1333
1334 addr -= s->offset;
1335 switch (addr) {
1336 case ICR:
1337 return s->control;
1338 case ISR:
1339 return s->status | (i2c_bus_busy(s->bus) << 2);
1340 case ISAR:
1341 slave = I2C_SLAVE(s->slave);
1342 return slave->address;
1343 case IDBR:
1344 return s->data;
1345 case IBMR:
1346 if (s->status & (1 << 2))
1347 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1348 else
1349 s->ibmr = 0;
1350 return s->ibmr;
1351 default:
1352 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1353 break;
1354 }
1355 return 0;
1356 }
1357
1358 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1359 uint64_t value64, unsigned size)
1360 {
1361 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1362 uint32_t value = value64;
1363 int ack;
1364
1365 addr -= s->offset;
1366 switch (addr) {
1367 case ICR:
1368 s->control = value & 0xfff7;
1369 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1370 /* TODO: slave mode */
1371 if (value & (1 << 0)) { /* START condition */
1372 if (s->data & 1)
1373 s->status |= 1 << 0; /* set RWM */
1374 else
1375 s->status &= ~(1 << 0); /* clear RWM */
1376 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1377 } else {
1378 if (s->status & (1 << 0)) { /* RWM */
1379 s->data = i2c_recv(s->bus);
1380 if (value & (1 << 2)) /* ACKNAK */
1381 i2c_nack(s->bus);
1382 ack = 1;
1383 } else
1384 ack = !i2c_send(s->bus, s->data);
1385 }
1386
1387 if (value & (1 << 1)) /* STOP condition */
1388 i2c_end_transfer(s->bus);
1389
1390 if (ack) {
1391 if (value & (1 << 0)) /* START condition */
1392 s->status |= 1 << 6; /* set ITE */
1393 else
1394 if (s->status & (1 << 0)) /* RWM */
1395 s->status |= 1 << 7; /* set IRF */
1396 else
1397 s->status |= 1 << 6; /* set ITE */
1398 s->status &= ~(1 << 1); /* clear ACKNAK */
1399 } else {
1400 s->status |= 1 << 6; /* set ITE */
1401 s->status |= 1 << 10; /* set BED */
1402 s->status |= 1 << 1; /* set ACKNAK */
1403 }
1404 }
1405 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1406 if (value & (1 << 4)) /* MA */
1407 i2c_end_transfer(s->bus);
1408 pxa2xx_i2c_update(s);
1409 break;
1410
1411 case ISR:
1412 s->status &= ~(value & 0x07f0);
1413 pxa2xx_i2c_update(s);
1414 break;
1415
1416 case ISAR:
1417 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f);
1418 break;
1419
1420 case IDBR:
1421 s->data = value & 0xff;
1422 break;
1423
1424 default:
1425 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1426 }
1427 }
1428
1429 static const MemoryRegionOps pxa2xx_i2c_ops = {
1430 .read = pxa2xx_i2c_read,
1431 .write = pxa2xx_i2c_write,
1432 .endianness = DEVICE_NATIVE_ENDIAN,
1433 };
1434
1435 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1436 .name = "pxa2xx_i2c_slave",
1437 .version_id = 1,
1438 .minimum_version_id = 1,
1439 .minimum_version_id_old = 1,
1440 .fields = (VMStateField []) {
1441 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
1442 VMSTATE_END_OF_LIST()
1443 }
1444 };
1445
1446 static const VMStateDescription vmstate_pxa2xx_i2c = {
1447 .name = "pxa2xx_i2c",
1448 .version_id = 1,
1449 .minimum_version_id = 1,
1450 .minimum_version_id_old = 1,
1451 .fields = (VMStateField []) {
1452 VMSTATE_UINT16(control, PXA2xxI2CState),
1453 VMSTATE_UINT16(status, PXA2xxI2CState),
1454 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1455 VMSTATE_UINT8(data, PXA2xxI2CState),
1456 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1457 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1458 VMSTATE_END_OF_LIST()
1459 }
1460 };
1461
1462 static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
1463 {
1464 /* Nothing to do. */
1465 return 0;
1466 }
1467
1468 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1469 {
1470 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1471
1472 k->init = pxa2xx_i2c_slave_init;
1473 k->event = pxa2xx_i2c_event;
1474 k->recv = pxa2xx_i2c_rx;
1475 k->send = pxa2xx_i2c_tx;
1476 }
1477
1478 static const TypeInfo pxa2xx_i2c_slave_info = {
1479 .name = TYPE_PXA2XX_I2C_SLAVE,
1480 .parent = TYPE_I2C_SLAVE,
1481 .instance_size = sizeof(PXA2xxI2CSlaveState),
1482 .class_init = pxa2xx_i2c_slave_class_init,
1483 };
1484
1485 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1486 qemu_irq irq, uint32_t region_size)
1487 {
1488 DeviceState *dev;
1489 SysBusDevice *i2c_dev;
1490 PXA2xxI2CState *s;
1491 I2CBus *i2cbus;
1492
1493 dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
1494 qdev_prop_set_uint32(dev, "size", region_size + 1);
1495 qdev_prop_set_uint32(dev, "offset", base & region_size);
1496 qdev_init_nofail(dev);
1497
1498 i2c_dev = SYS_BUS_DEVICE(dev);
1499 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1500 sysbus_connect_irq(i2c_dev, 0, irq);
1501
1502 s = PXA2XX_I2C(i2c_dev);
1503 /* FIXME: Should the slave device really be on a separate bus? */
1504 i2cbus = i2c_init_bus(dev, "dummy");
1505 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0);
1506 s->slave = PXA2XX_I2C_SLAVE(dev);
1507 s->slave->host = s;
1508
1509 return s;
1510 }
1511
1512 static int pxa2xx_i2c_initfn(SysBusDevice *sbd)
1513 {
1514 DeviceState *dev = DEVICE(sbd);
1515 PXA2xxI2CState *s = PXA2XX_I2C(dev);
1516
1517 s->bus = i2c_init_bus(dev, "i2c");
1518
1519 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_i2c_ops, s,
1520 "pxa2xx-i2c", s->region_size);
1521 sysbus_init_mmio(sbd, &s->iomem);
1522 sysbus_init_irq(sbd, &s->irq);
1523
1524 return 0;
1525 }
1526
1527 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1528 {
1529 return s->bus;
1530 }
1531
1532 static Property pxa2xx_i2c_properties[] = {
1533 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1534 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1535 DEFINE_PROP_END_OF_LIST(),
1536 };
1537
1538 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1539 {
1540 DeviceClass *dc = DEVICE_CLASS(klass);
1541 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1542
1543 k->init = pxa2xx_i2c_initfn;
1544 dc->desc = "PXA2xx I2C Bus Controller";
1545 dc->vmsd = &vmstate_pxa2xx_i2c;
1546 dc->props = pxa2xx_i2c_properties;
1547 }
1548
1549 static const TypeInfo pxa2xx_i2c_info = {
1550 .name = TYPE_PXA2XX_I2C,
1551 .parent = TYPE_SYS_BUS_DEVICE,
1552 .instance_size = sizeof(PXA2xxI2CState),
1553 .class_init = pxa2xx_i2c_class_init,
1554 };
1555
1556 /* PXA Inter-IC Sound Controller */
1557 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1558 {
1559 i2s->rx_len = 0;
1560 i2s->tx_len = 0;
1561 i2s->fifo_len = 0;
1562 i2s->clk = 0x1a;
1563 i2s->control[0] = 0x00;
1564 i2s->control[1] = 0x00;
1565 i2s->status = 0x00;
1566 i2s->mask = 0x00;
1567 }
1568
1569 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1570 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1571 #define SACR_DREC(val) (val & (1 << 3))
1572 #define SACR_DPRL(val) (val & (1 << 4))
1573
1574 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1575 {
1576 int rfs, tfs;
1577 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1578 !SACR_DREC(i2s->control[1]);
1579 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1580 i2s->enable && !SACR_DPRL(i2s->control[1]);
1581
1582 qemu_set_irq(i2s->rx_dma, rfs);
1583 qemu_set_irq(i2s->tx_dma, tfs);
1584
1585 i2s->status &= 0xe0;
1586 if (i2s->fifo_len < 16 || !i2s->enable)
1587 i2s->status |= 1 << 0; /* TNF */
1588 if (i2s->rx_len)
1589 i2s->status |= 1 << 1; /* RNE */
1590 if (i2s->enable)
1591 i2s->status |= 1 << 2; /* BSY */
1592 if (tfs)
1593 i2s->status |= 1 << 3; /* TFS */
1594 if (rfs)
1595 i2s->status |= 1 << 4; /* RFS */
1596 if (!(i2s->tx_len && i2s->enable))
1597 i2s->status |= i2s->fifo_len << 8; /* TFL */
1598 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1599
1600 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1601 }
1602
1603 #define SACR0 0x00 /* Serial Audio Global Control register */
1604 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1605 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1606 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1607 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1608 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1609 #define SADR 0x80 /* Serial Audio Data register */
1610
1611 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1612 unsigned size)
1613 {
1614 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1615
1616 switch (addr) {
1617 case SACR0:
1618 return s->control[0];
1619 case SACR1:
1620 return s->control[1];
1621 case SASR0:
1622 return s->status;
1623 case SAIMR:
1624 return s->mask;
1625 case SAICR:
1626 return 0;
1627 case SADIV:
1628 return s->clk;
1629 case SADR:
1630 if (s->rx_len > 0) {
1631 s->rx_len --;
1632 pxa2xx_i2s_update(s);
1633 return s->codec_in(s->opaque);
1634 }
1635 return 0;
1636 default:
1637 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1638 break;
1639 }
1640 return 0;
1641 }
1642
1643 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1644 uint64_t value, unsigned size)
1645 {
1646 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1647 uint32_t *sample;
1648
1649 switch (addr) {
1650 case SACR0:
1651 if (value & (1 << 3)) /* RST */
1652 pxa2xx_i2s_reset(s);
1653 s->control[0] = value & 0xff3d;
1654 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1655 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1656 s->codec_out(s->opaque, *sample);
1657 s->status &= ~(1 << 7); /* I2SOFF */
1658 }
1659 if (value & (1 << 4)) /* EFWR */
1660 printf("%s: Attempt to use special function\n", __FUNCTION__);
1661 s->enable = (value & 9) == 1; /* ENB && !RST*/
1662 pxa2xx_i2s_update(s);
1663 break;
1664 case SACR1:
1665 s->control[1] = value & 0x0039;
1666 if (value & (1 << 5)) /* ENLBF */
1667 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1668 if (value & (1 << 4)) /* DPRL */
1669 s->fifo_len = 0;
1670 pxa2xx_i2s_update(s);
1671 break;
1672 case SAIMR:
1673 s->mask = value & 0x0078;
1674 pxa2xx_i2s_update(s);
1675 break;
1676 case SAICR:
1677 s->status &= ~(value & (3 << 5));
1678 pxa2xx_i2s_update(s);
1679 break;
1680 case SADIV:
1681 s->clk = value & 0x007f;
1682 break;
1683 case SADR:
1684 if (s->tx_len && s->enable) {
1685 s->tx_len --;
1686 pxa2xx_i2s_update(s);
1687 s->codec_out(s->opaque, value);
1688 } else if (s->fifo_len < 16) {
1689 s->fifo[s->fifo_len ++] = value;
1690 pxa2xx_i2s_update(s);
1691 }
1692 break;
1693 default:
1694 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1695 }
1696 }
1697
1698 static const MemoryRegionOps pxa2xx_i2s_ops = {
1699 .read = pxa2xx_i2s_read,
1700 .write = pxa2xx_i2s_write,
1701 .endianness = DEVICE_NATIVE_ENDIAN,
1702 };
1703
1704 static const VMStateDescription vmstate_pxa2xx_i2s = {
1705 .name = "pxa2xx_i2s",
1706 .version_id = 0,
1707 .minimum_version_id = 0,
1708 .minimum_version_id_old = 0,
1709 .fields = (VMStateField[]) {
1710 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1711 VMSTATE_UINT32(status, PXA2xxI2SState),
1712 VMSTATE_UINT32(mask, PXA2xxI2SState),
1713 VMSTATE_UINT32(clk, PXA2xxI2SState),
1714 VMSTATE_INT32(enable, PXA2xxI2SState),
1715 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1716 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1717 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1718 VMSTATE_END_OF_LIST()
1719 }
1720 };
1721
1722 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1723 {
1724 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1725 uint32_t *sample;
1726
1727 /* Signal FIFO errors */
1728 if (s->enable && s->tx_len)
1729 s->status |= 1 << 5; /* TUR */
1730 if (s->enable && s->rx_len)
1731 s->status |= 1 << 6; /* ROR */
1732
1733 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1734 * handle the cases where it makes a difference. */
1735 s->tx_len = tx - s->fifo_len;
1736 s->rx_len = rx;
1737 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1738 if (s->enable)
1739 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1740 s->codec_out(s->opaque, *sample);
1741 pxa2xx_i2s_update(s);
1742 }
1743
1744 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1745 hwaddr base,
1746 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1747 {
1748 PXA2xxI2SState *s = (PXA2xxI2SState *)
1749 g_malloc0(sizeof(PXA2xxI2SState));
1750
1751 s->irq = irq;
1752 s->rx_dma = rx_dma;
1753 s->tx_dma = tx_dma;
1754 s->data_req = pxa2xx_i2s_data_req;
1755
1756 pxa2xx_i2s_reset(s);
1757
1758 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1759 "pxa2xx-i2s", 0x100000);
1760 memory_region_add_subregion(sysmem, base, &s->iomem);
1761
1762 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1763
1764 return s;
1765 }
1766
1767 /* PXA Fast Infra-red Communications Port */
1768 struct PXA2xxFIrState {
1769 MemoryRegion iomem;
1770 qemu_irq irq;
1771 qemu_irq rx_dma;
1772 qemu_irq tx_dma;
1773 int enable;
1774 CharDriverState *chr;
1775
1776 uint8_t control[3];
1777 uint8_t status[2];
1778
1779 int rx_len;
1780 int rx_start;
1781 uint8_t rx_fifo[64];
1782 };
1783
1784 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1785 {
1786 s->control[0] = 0x00;
1787 s->control[1] = 0x00;
1788 s->control[2] = 0x00;
1789 s->status[0] = 0x00;
1790 s->status[1] = 0x00;
1791 s->enable = 0;
1792 }
1793
1794 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1795 {
1796 static const int tresh[4] = { 8, 16, 32, 0 };
1797 int intr = 0;
1798 if ((s->control[0] & (1 << 4)) && /* RXE */
1799 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1800 s->status[0] |= 1 << 4; /* RFS */
1801 else
1802 s->status[0] &= ~(1 << 4); /* RFS */
1803 if (s->control[0] & (1 << 3)) /* TXE */
1804 s->status[0] |= 1 << 3; /* TFS */
1805 else
1806 s->status[0] &= ~(1 << 3); /* TFS */
1807 if (s->rx_len)
1808 s->status[1] |= 1 << 2; /* RNE */
1809 else
1810 s->status[1] &= ~(1 << 2); /* RNE */
1811 if (s->control[0] & (1 << 4)) /* RXE */
1812 s->status[1] |= 1 << 0; /* RSY */
1813 else
1814 s->status[1] &= ~(1 << 0); /* RSY */
1815
1816 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1817 (s->status[0] & (1 << 4)); /* RFS */
1818 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1819 (s->status[0] & (1 << 3)); /* TFS */
1820 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1821 (s->status[0] & (1 << 6)); /* EOC */
1822 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1823 (s->status[0] & (1 << 1)); /* TUR */
1824 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1825
1826 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1827 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1828
1829 qemu_set_irq(s->irq, intr && s->enable);
1830 }
1831
1832 #define ICCR0 0x00 /* FICP Control register 0 */
1833 #define ICCR1 0x04 /* FICP Control register 1 */
1834 #define ICCR2 0x08 /* FICP Control register 2 */
1835 #define ICDR 0x0c /* FICP Data register */
1836 #define ICSR0 0x14 /* FICP Status register 0 */
1837 #define ICSR1 0x18 /* FICP Status register 1 */
1838 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1839
1840 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1841 unsigned size)
1842 {
1843 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1844 uint8_t ret;
1845
1846 switch (addr) {
1847 case ICCR0:
1848 return s->control[0];
1849 case ICCR1:
1850 return s->control[1];
1851 case ICCR2:
1852 return s->control[2];
1853 case ICDR:
1854 s->status[0] &= ~0x01;
1855 s->status[1] &= ~0x72;
1856 if (s->rx_len) {
1857 s->rx_len --;
1858 ret = s->rx_fifo[s->rx_start ++];
1859 s->rx_start &= 63;
1860 pxa2xx_fir_update(s);
1861 return ret;
1862 }
1863 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1864 break;
1865 case ICSR0:
1866 return s->status[0];
1867 case ICSR1:
1868 return s->status[1] | (1 << 3); /* TNF */
1869 case ICFOR:
1870 return s->rx_len;
1871 default:
1872 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1873 break;
1874 }
1875 return 0;
1876 }
1877
1878 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1879 uint64_t value64, unsigned size)
1880 {
1881 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1882 uint32_t value = value64;
1883 uint8_t ch;
1884
1885 switch (addr) {
1886 case ICCR0:
1887 s->control[0] = value;
1888 if (!(value & (1 << 4))) /* RXE */
1889 s->rx_len = s->rx_start = 0;
1890 if (!(value & (1 << 3))) { /* TXE */
1891 /* Nop */
1892 }
1893 s->enable = value & 1; /* ITR */
1894 if (!s->enable)
1895 s->status[0] = 0;
1896 pxa2xx_fir_update(s);
1897 break;
1898 case ICCR1:
1899 s->control[1] = value;
1900 break;
1901 case ICCR2:
1902 s->control[2] = value & 0x3f;
1903 pxa2xx_fir_update(s);
1904 break;
1905 case ICDR:
1906 if (s->control[2] & (1 << 2)) /* TXP */
1907 ch = value;
1908 else
1909 ch = ~value;
1910 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1911 qemu_chr_fe_write(s->chr, &ch, 1);
1912 break;
1913 case ICSR0:
1914 s->status[0] &= ~(value & 0x66);
1915 pxa2xx_fir_update(s);
1916 break;
1917 case ICFOR:
1918 break;
1919 default:
1920 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1921 }
1922 }
1923
1924 static const MemoryRegionOps pxa2xx_fir_ops = {
1925 .read = pxa2xx_fir_read,
1926 .write = pxa2xx_fir_write,
1927 .endianness = DEVICE_NATIVE_ENDIAN,
1928 };
1929
1930 static int pxa2xx_fir_is_empty(void *opaque)
1931 {
1932 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1933 return (s->rx_len < 64);
1934 }
1935
1936 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1937 {
1938 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1939 if (!(s->control[0] & (1 << 4))) /* RXE */
1940 return;
1941
1942 while (size --) {
1943 s->status[1] |= 1 << 4; /* EOF */
1944 if (s->rx_len >= 64) {
1945 s->status[1] |= 1 << 6; /* ROR */
1946 break;
1947 }
1948
1949 if (s->control[2] & (1 << 3)) /* RXP */
1950 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1951 else
1952 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1953 }
1954
1955 pxa2xx_fir_update(s);
1956 }
1957
1958 static void pxa2xx_fir_event(void *opaque, int event)
1959 {
1960 }
1961
1962 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1963 {
1964 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1965 int i;
1966
1967 qemu_put_be32(f, s->enable);
1968
1969 qemu_put_8s(f, &s->control[0]);
1970 qemu_put_8s(f, &s->control[1]);
1971 qemu_put_8s(f, &s->control[2]);
1972 qemu_put_8s(f, &s->status[0]);
1973 qemu_put_8s(f, &s->status[1]);
1974
1975 qemu_put_byte(f, s->rx_len);
1976 for (i = 0; i < s->rx_len; i ++)
1977 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1978 }
1979
1980 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1981 {
1982 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1983 int i;
1984
1985 s->enable = qemu_get_be32(f);
1986
1987 qemu_get_8s(f, &s->control[0]);
1988 qemu_get_8s(f, &s->control[1]);
1989 qemu_get_8s(f, &s->control[2]);
1990 qemu_get_8s(f, &s->status[0]);
1991 qemu_get_8s(f, &s->status[1]);
1992
1993 s->rx_len = qemu_get_byte(f);
1994 s->rx_start = 0;
1995 for (i = 0; i < s->rx_len; i ++)
1996 s->rx_fifo[i] = qemu_get_byte(f);
1997
1998 return 0;
1999 }
2000
2001 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
2002 hwaddr base,
2003 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
2004 CharDriverState *chr)
2005 {
2006 PXA2xxFIrState *s = (PXA2xxFIrState *)
2007 g_malloc0(sizeof(PXA2xxFIrState));
2008
2009 s->irq = irq;
2010 s->rx_dma = rx_dma;
2011 s->tx_dma = tx_dma;
2012 s->chr = chr;
2013
2014 pxa2xx_fir_reset(s);
2015
2016 memory_region_init_io(&s->iomem, NULL, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
2017 memory_region_add_subregion(sysmem, base, &s->iomem);
2018
2019 if (chr) {
2020 qemu_chr_fe_claim_no_fail(chr);
2021 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2022 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2023 }
2024
2025 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2026 pxa2xx_fir_load, s);
2027
2028 return s;
2029 }
2030
2031 static void pxa2xx_reset(void *opaque, int line, int level)
2032 {
2033 PXA2xxState *s = (PXA2xxState *) opaque;
2034
2035 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2036 cpu_reset(CPU(s->cpu));
2037 /* TODO: reset peripherals */
2038 }
2039 }
2040
2041 /* Initialise a PXA270 integrated chip (ARM based core). */
2042 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2043 unsigned int sdram_size, const char *revision)
2044 {
2045 PXA2xxState *s;
2046 int i;
2047 DriveInfo *dinfo;
2048 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2049
2050 if (revision && strncmp(revision, "pxa27", 5)) {
2051 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2052 exit(1);
2053 }
2054 if (!revision)
2055 revision = "pxa270";
2056
2057 s->cpu = cpu_arm_init(revision);
2058 if (s->cpu == NULL) {
2059 fprintf(stderr, "Unable to find CPU definition\n");
2060 exit(1);
2061 }
2062 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2063
2064 /* SDRAM & Internal Memory Storage */
2065 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
2066 vmstate_register_ram_global(&s->sdram);
2067 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2068 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
2069 vmstate_register_ram_global(&s->internal);
2070 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2071 &s->internal);
2072
2073 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2074
2075 s->dma = pxa27x_dma_init(0x40000000,
2076 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2077
2078 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2079 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2080 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2081 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2082 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2083 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2084 NULL);
2085
2086 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2087
2088 dinfo = drive_get(IF_SD, 0, 0);
2089 if (!dinfo) {
2090 fprintf(stderr, "qemu: missing SecureDigital device\n");
2091 exit(1);
2092 }
2093 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2094 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2095 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2096 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2097
2098 for (i = 0; pxa270_serial[i].io_base; i++) {
2099 if (serial_hds[i]) {
2100 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2101 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2102 14857000 / 16, serial_hds[i],
2103 DEVICE_NATIVE_ENDIAN);
2104 } else {
2105 break;
2106 }
2107 }
2108 if (serial_hds[i])
2109 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2110 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2111 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2112 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2113 serial_hds[i]);
2114
2115 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2116 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2117
2118 s->cm_base = 0x41300000;
2119 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2120 s->clkcfg = 0x00000009; /* Turbo mode active */
2121 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2122 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2123 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2124
2125 pxa2xx_setup_cp14(s);
2126
2127 s->mm_base = 0x48000000;
2128 s->mm_regs[MDMRS >> 2] = 0x00020002;
2129 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2130 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2131 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2132 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2133 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2134
2135 s->pm_base = 0x40f00000;
2136 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2137 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2138 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2139
2140 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2141 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2142 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2143 DeviceState *dev;
2144 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2145 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2146 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2147 }
2148
2149 if (usb_enabled(false)) {
2150 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2151 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2152 }
2153
2154 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2155 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2156
2157 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2158 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2159
2160 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2161 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2162 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2163 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2164
2165 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2166 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2167 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2168 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2169
2170 s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2171 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2172
2173 /* GPIO1 resets the processor */
2174 /* The handler can be overridden by board-specific code */
2175 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2176 return s;
2177 }
2178
2179 /* Initialise a PXA255 integrated chip (ARM based core). */
2180 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2181 {
2182 PXA2xxState *s;
2183 int i;
2184 DriveInfo *dinfo;
2185
2186 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2187
2188 s->cpu = cpu_arm_init("pxa255");
2189 if (s->cpu == NULL) {
2190 fprintf(stderr, "Unable to find CPU definition\n");
2191 exit(1);
2192 }
2193 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2194
2195 /* SDRAM & Internal Memory Storage */
2196 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
2197 vmstate_register_ram_global(&s->sdram);
2198 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2199 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2200 PXA2XX_INTERNAL_SIZE);
2201 vmstate_register_ram_global(&s->internal);
2202 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2203 &s->internal);
2204
2205 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2206
2207 s->dma = pxa255_dma_init(0x40000000,
2208 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2209
2210 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2211 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2212 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2213 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2214 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2215 NULL);
2216
2217 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2218
2219 dinfo = drive_get(IF_SD, 0, 0);
2220 if (!dinfo) {
2221 fprintf(stderr, "qemu: missing SecureDigital device\n");
2222 exit(1);
2223 }
2224 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, dinfo->bdrv,
2225 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2226 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2227 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2228
2229 for (i = 0; pxa255_serial[i].io_base; i++) {
2230 if (serial_hds[i]) {
2231 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2232 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2233 14745600 / 16, serial_hds[i],
2234 DEVICE_NATIVE_ENDIAN);
2235 } else {
2236 break;
2237 }
2238 }
2239 if (serial_hds[i])
2240 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2241 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2242 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2243 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2244 serial_hds[i]);
2245
2246 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2247 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2248
2249 s->cm_base = 0x41300000;
2250 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2251 s->clkcfg = 0x00000009; /* Turbo mode active */
2252 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2253 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2254 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2255
2256 pxa2xx_setup_cp14(s);
2257
2258 s->mm_base = 0x48000000;
2259 s->mm_regs[MDMRS >> 2] = 0x00020002;
2260 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2261 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2262 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2263 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2264 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2265
2266 s->pm_base = 0x40f00000;
2267 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2268 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2269 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2270
2271 for (i = 0; pxa255_ssp[i].io_base; i ++);
2272 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2273 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2274 DeviceState *dev;
2275 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2276 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2277 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2278 }
2279
2280 if (usb_enabled(false)) {
2281 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2282 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2283 }
2284
2285 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2286 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2287
2288 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2289 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2290
2291 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2292 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2293 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2294 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2295
2296 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2297 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2298 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2299 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2300
2301 /* GPIO1 resets the processor */
2302 /* The handler can be overridden by board-specific code */
2303 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2304 return s;
2305 }
2306
2307 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2308 {
2309 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
2310
2311 sdc->init = pxa2xx_ssp_init;
2312 }
2313
2314 static const TypeInfo pxa2xx_ssp_info = {
2315 .name = TYPE_PXA2XX_SSP,
2316 .parent = TYPE_SYS_BUS_DEVICE,
2317 .instance_size = sizeof(PXA2xxSSPState),
2318 .class_init = pxa2xx_ssp_class_init,
2319 };
2320
2321 static void pxa2xx_register_types(void)
2322 {
2323 type_register_static(&pxa2xx_i2c_slave_info);
2324 type_register_static(&pxa2xx_ssp_info);
2325 type_register_static(&pxa2xx_i2c_info);
2326 type_register_static(&pxa2xx_rtc_sysbus_info);
2327 }
2328
2329 type_init(pxa2xx_register_types)
AR7 emulation for QEMU