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io: get rid of bounce buffering in websock write path
[qemu/ar7.git] / target / ppc / translate_init.c
blobc6399a3a0d0d99558d5e8b42ffc0b6d6cee76f09
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/hw_accel.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/visitor.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ppc/ppc.h"
35 #include "mmu-book3s-v3.h"
36 #include "sysemu/qtest.h"
37 #include "qemu/cutils.h"
38
39 //#define PPC_DUMP_CPU
40 //#define PPC_DEBUG_SPR
41 //#define PPC_DUMP_SPR_ACCESSES
42 /* #define USE_APPLE_GDB */
43
44 /* Generic callbacks:
45 * do nothing but store/retrieve spr value
46 */
47 static void spr_load_dump_spr(int sprn)
48 {
49 #ifdef PPC_DUMP_SPR_ACCESSES
50 TCGv_i32 t0 = tcg_const_i32(sprn);
51 gen_helper_load_dump_spr(cpu_env, t0);
52 tcg_temp_free_i32(t0);
53 #endif
54 }
55
56 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
57 {
58 gen_load_spr(cpu_gpr[gprn], sprn);
59 spr_load_dump_spr(sprn);
60 }
61
62 static void spr_store_dump_spr(int sprn)
63 {
64 #ifdef PPC_DUMP_SPR_ACCESSES
65 TCGv_i32 t0 = tcg_const_i32(sprn);
66 gen_helper_store_dump_spr(cpu_env, t0);
67 tcg_temp_free_i32(t0);
68 #endif
69 }
70
71 static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
72 {
73 gen_store_spr(sprn, cpu_gpr[gprn]);
74 spr_store_dump_spr(sprn);
75 }
76
77 #if !defined(CONFIG_USER_ONLY)
78 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
79 {
80 #ifdef TARGET_PPC64
81 TCGv t0 = tcg_temp_new();
82 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
83 gen_store_spr(sprn, t0);
84 tcg_temp_free(t0);
85 spr_store_dump_spr(sprn);
86 #else
87 spr_write_generic(ctx, sprn, gprn);
88 #endif
89 }
90
91 static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
92 {
93 TCGv t0 = tcg_temp_new();
94 TCGv t1 = tcg_temp_new();
95 gen_load_spr(t0, sprn);
96 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
97 tcg_gen_and_tl(t0, t0, t1);
98 gen_store_spr(sprn, t0);
99 tcg_temp_free(t0);
100 tcg_temp_free(t1);
101 }
102
103 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
104 {
105 }
106
107 #endif
108
109 /* SPR common to all PowerPC */
110 /* XER */
111 static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
112 {
113 gen_read_xer(ctx, cpu_gpr[gprn]);
114 }
115
116 static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
117 {
118 gen_write_xer(cpu_gpr[gprn]);
119 }
120
121 /* LR */
122 static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
123 {
124 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
125 }
126
127 static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
128 {
129 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
130 }
131
132 /* CFAR */
133 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
134 static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
135 {
136 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
137 }
138
139 static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
140 {
141 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
142 }
143 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
144
145 /* CTR */
146 static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
147 {
148 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
149 }
150
151 static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
152 {
153 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
154 }
155
156 /* User read access to SPR */
157 /* USPRx */
158 /* UMMCRx */
159 /* UPMCx */
160 /* USIA */
161 /* UDECR */
162 static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
163 {
164 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
165 }
166
167 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
168 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
169 {
170 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
171 }
172 #endif
173
174 /* SPR common to all non-embedded PowerPC */
175 /* DECR */
176 #if !defined(CONFIG_USER_ONLY)
177 static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
178 {
179 if (ctx->tb->cflags & CF_USE_ICOUNT) {
180 gen_io_start();
181 }
182 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
183 if (ctx->tb->cflags & CF_USE_ICOUNT) {
184 gen_io_end();
185 gen_stop_exception(ctx);
186 }
187 }
188
189 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
190 {
191 if (ctx->tb->cflags & CF_USE_ICOUNT) {
192 gen_io_start();
193 }
194 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
195 if (ctx->tb->cflags & CF_USE_ICOUNT) {
196 gen_io_end();
197 gen_stop_exception(ctx);
198 }
199 }
200 #endif
201
202 /* SPR common to all non-embedded PowerPC, except 601 */
203 /* Time base */
204 static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
205 {
206 if (ctx->tb->cflags & CF_USE_ICOUNT) {
207 gen_io_start();
208 }
209 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
210 if (ctx->tb->cflags & CF_USE_ICOUNT) {
211 gen_io_end();
212 gen_stop_exception(ctx);
213 }
214 }
215
216 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
217 {
218 if (ctx->tb->cflags & CF_USE_ICOUNT) {
219 gen_io_start();
220 }
221 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
222 if (ctx->tb->cflags & CF_USE_ICOUNT) {
223 gen_io_end();
224 gen_stop_exception(ctx);
225 }
226 }
227
228 __attribute__ (( unused ))
229 static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
230 {
231 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
232 }
233
234 __attribute__ (( unused ))
235 static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
236 {
237 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
238 }
239
240 #if !defined(CONFIG_USER_ONLY)
241 static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
242 {
243 if (ctx->tb->cflags & CF_USE_ICOUNT) {
244 gen_io_start();
245 }
246 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
247 if (ctx->tb->cflags & CF_USE_ICOUNT) {
248 gen_io_end();
249 gen_stop_exception(ctx);
250 }
251 }
252
253 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
254 {
255 if (ctx->tb->cflags & CF_USE_ICOUNT) {
256 gen_io_start();
257 }
258 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
259 if (ctx->tb->cflags & CF_USE_ICOUNT) {
260 gen_io_end();
261 gen_stop_exception(ctx);
262 }
263 }
264
265 __attribute__ (( unused ))
266 static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
267 {
268 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
269 }
270
271 __attribute__ (( unused ))
272 static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
273 {
274 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
275 }
276
277 #if defined(TARGET_PPC64)
278 __attribute__ (( unused ))
279 static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
280 {
281 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
282 }
283
284 /* HDECR */
285 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
286 {
287 if (ctx->tb->cflags & CF_USE_ICOUNT) {
288 gen_io_start();
289 }
290 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
291 if (ctx->tb->cflags & CF_USE_ICOUNT) {
292 gen_io_end();
293 gen_stop_exception(ctx);
294 }
295 }
296
297 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
298 {
299 if (ctx->tb->cflags & CF_USE_ICOUNT) {
300 gen_io_start();
301 }
302 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
303 if (ctx->tb->cflags & CF_USE_ICOUNT) {
304 gen_io_end();
305 gen_stop_exception(ctx);
306 }
307 }
308
309 #endif
310 #endif
311
312 #if !defined(CONFIG_USER_ONLY)
313 /* IBAT0U...IBAT0U */
314 /* IBAT0L...IBAT7L */
315 static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
316 {
317 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
318 }
319
320 static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
321 {
322 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
323 }
324
325 static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
326 {
327 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
328 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
329 tcg_temp_free_i32(t0);
330 }
331
332 static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
333 {
334 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
335 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
336 tcg_temp_free_i32(t0);
337 }
338
339 static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
340 {
341 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
342 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
343 tcg_temp_free_i32(t0);
344 }
345
346 static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
347 {
348 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
349 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
350 tcg_temp_free_i32(t0);
351 }
352
353 /* DBAT0U...DBAT7U */
354 /* DBAT0L...DBAT7L */
355 static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
356 {
357 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
358 }
359
360 static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
361 {
362 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
363 }
364
365 static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
366 {
367 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
368 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
369 tcg_temp_free_i32(t0);
370 }
371
372 static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
373 {
374 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
375 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
376 tcg_temp_free_i32(t0);
377 }
378
379 static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
380 {
381 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
382 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
383 tcg_temp_free_i32(t0);
384 }
385
386 static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
387 {
388 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
389 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
390 tcg_temp_free_i32(t0);
391 }
392
393 /* SDR1 */
394 static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
395 {
396 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
397 }
398
399 #if defined(TARGET_PPC64)
400 /* 64 bits PowerPC specific SPRs */
401 /* PIDR */
402 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
403 {
404 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
405 }
406
407 static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
408 {
409 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
410 }
411
412 static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
413 {
414 TCGv t0 = tcg_temp_new();
415 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
416 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
417 tcg_temp_free(t0);
418 }
419 #endif
420 #endif
421
422 /* PowerPC 601 specific registers */
423 /* RTC */
424 static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
425 {
426 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
427 }
428
429 static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
430 {
431 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
432 }
433
434 #if !defined(CONFIG_USER_ONLY)
435 static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
436 {
437 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
438 }
439
440 static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
441 {
442 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
443 }
444
445 static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
446 {
447 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
448 /* Must stop the translation as endianness may have changed */
449 gen_stop_exception(ctx);
450 }
451 #endif
452
453 /* Unified bats */
454 #if !defined(CONFIG_USER_ONLY)
455 static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
456 {
457 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
458 }
459
460 static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
461 {
462 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
463 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
464 tcg_temp_free_i32(t0);
465 }
466
467 static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
468 {
469 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
470 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
471 tcg_temp_free_i32(t0);
472 }
473 #endif
474
475 /* PowerPC 40x specific registers */
476 #if !defined(CONFIG_USER_ONLY)
477 static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
478 {
479 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
480 }
481
482 static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
483 {
484 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
485 }
486
487 static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
488 {
489 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
490 /* We must stop translation as we may have rebooted */
491 gen_stop_exception(ctx);
492 }
493
494 static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
495 {
496 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
497 }
498
499 static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
500 {
501 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
502 }
503
504 static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
505 {
506 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
507 }
508 #endif
509
510 /* PowerPC 403 specific registers */
511 /* PBL1 / PBU1 / PBL2 / PBU2 */
512 #if !defined(CONFIG_USER_ONLY)
513 static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
514 {
515 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
516 }
517
518 static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
519 {
520 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
521 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
522 tcg_temp_free_i32(t0);
523 }
524
525 static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
526 {
527 TCGv t0 = tcg_temp_new();
528 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
529 gen_store_spr(SPR_PIR, t0);
530 tcg_temp_free(t0);
531 }
532 #endif
533
534 /* SPE specific registers */
535 static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
536 {
537 TCGv_i32 t0 = tcg_temp_new_i32();
538 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
539 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
540 tcg_temp_free_i32(t0);
541 }
542
543 static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
544 {
545 TCGv_i32 t0 = tcg_temp_new_i32();
546 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
547 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
548 tcg_temp_free_i32(t0);
549 }
550
551 #if !defined(CONFIG_USER_ONLY)
552 /* Callback used to write the exception vector base */
553 static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
554 {
555 TCGv t0 = tcg_temp_new();
556 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
557 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
558 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
559 gen_store_spr(sprn, t0);
560 tcg_temp_free(t0);
561 }
562
563 static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
564 {
565 int sprn_offs;
566
567 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
568 sprn_offs = sprn - SPR_BOOKE_IVOR0;
569 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
570 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
571 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
572 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
573 } else {
574 printf("Trying to write an unknown exception vector %d %03x\n",
575 sprn, sprn);
576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
577 return;
578 }
579
580 TCGv t0 = tcg_temp_new();
581 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
582 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
583 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
584 gen_store_spr(sprn, t0);
585 tcg_temp_free(t0);
586 }
587 #endif
588
589 static inline void vscr_init(CPUPPCState *env, uint32_t val)
590 {
591 env->vscr = val;
592 /* Altivec always uses round-to-nearest */
593 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
594 set_flush_to_zero(vscr_nj, &env->vec_status);
595 }
596
597 #ifdef CONFIG_USER_ONLY
598 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
599 oea_read, oea_write, one_reg_id, initial_value) \
600 _spr_register(env, num, name, uea_read, uea_write, initial_value)
601 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
602 oea_read, oea_write, hea_read, hea_write, \
603 one_reg_id, initial_value) \
604 _spr_register(env, num, name, uea_read, uea_write, initial_value)
605 #else
606 #if !defined(CONFIG_KVM)
607 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
608 oea_read, oea_write, one_reg_id, initial_value) \
609 _spr_register(env, num, name, uea_read, uea_write, \
610 oea_read, oea_write, oea_read, oea_write, initial_value)
611 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
612 oea_read, oea_write, hea_read, hea_write, \
613 one_reg_id, initial_value) \
614 _spr_register(env, num, name, uea_read, uea_write, \
615 oea_read, oea_write, hea_read, hea_write, initial_value)
616 #else
617 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
618 oea_read, oea_write, one_reg_id, initial_value) \
619 _spr_register(env, num, name, uea_read, uea_write, \
620 oea_read, oea_write, oea_read, oea_write, \
621 one_reg_id, initial_value)
622 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
623 oea_read, oea_write, hea_read, hea_write, \
624 one_reg_id, initial_value) \
625 _spr_register(env, num, name, uea_read, uea_write, \
626 oea_read, oea_write, hea_read, hea_write, \
627 one_reg_id, initial_value)
628 #endif
629 #endif
630
631 #define spr_register(env, num, name, uea_read, uea_write, \
632 oea_read, oea_write, initial_value) \
633 spr_register_kvm(env, num, name, uea_read, uea_write, \
634 oea_read, oea_write, 0, initial_value)
635
636 #define spr_register_hv(env, num, name, uea_read, uea_write, \
637 oea_read, oea_write, hea_read, hea_write, \
638 initial_value) \
639 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
640 oea_read, oea_write, hea_read, hea_write, \
641 0, initial_value)
642
643 static inline void _spr_register(CPUPPCState *env, int num,
644 const char *name,
645 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
646 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
647 #if !defined(CONFIG_USER_ONLY)
648
649 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
650 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
651 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
652 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
653 #endif
654 #if defined(CONFIG_KVM)
655 uint64_t one_reg_id,
656 #endif
657 target_ulong initial_value)
658 {
659 ppc_spr_t *spr;
660
661 spr = &env->spr_cb[num];
662 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
663 #if !defined(CONFIG_USER_ONLY)
664 spr->oea_read != NULL || spr->oea_write != NULL ||
665 #endif
666 spr->uea_read != NULL || spr->uea_write != NULL) {
667 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
668 exit(1);
669 }
670 #if defined(PPC_DEBUG_SPR)
671 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
672 name, initial_value);
673 #endif
674 spr->name = name;
675 spr->uea_read = uea_read;
676 spr->uea_write = uea_write;
677 #if !defined(CONFIG_USER_ONLY)
678 spr->oea_read = oea_read;
679 spr->oea_write = oea_write;
680 spr->hea_read = hea_read;
681 spr->hea_write = hea_write;
682 #endif
683 #if defined(CONFIG_KVM)
684 spr->one_reg_id = one_reg_id,
685 #endif
686 env->spr[num] = spr->default_value = initial_value;
687 }
688
689 /* Generic PowerPC SPRs */
690 static void gen_spr_generic(CPUPPCState *env)
691 {
692 /* Integer processing */
693 spr_register(env, SPR_XER, "XER",
694 &spr_read_xer, &spr_write_xer,
695 &spr_read_xer, &spr_write_xer,
696 0x00000000);
697 /* Branch contol */
698 spr_register(env, SPR_LR, "LR",
699 &spr_read_lr, &spr_write_lr,
700 &spr_read_lr, &spr_write_lr,
701 0x00000000);
702 spr_register(env, SPR_CTR, "CTR",
703 &spr_read_ctr, &spr_write_ctr,
704 &spr_read_ctr, &spr_write_ctr,
705 0x00000000);
706 /* Interrupt processing */
707 spr_register(env, SPR_SRR0, "SRR0",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_generic, &spr_write_generic,
710 0x00000000);
711 spr_register(env, SPR_SRR1, "SRR1",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, &spr_write_generic,
714 0x00000000);
715 /* Processor control */
716 spr_register(env, SPR_SPRG0, "SPRG0",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_generic, &spr_write_generic,
719 0x00000000);
720 spr_register(env, SPR_SPRG1, "SPRG1",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_generic,
723 0x00000000);
724 spr_register(env, SPR_SPRG2, "SPRG2",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, &spr_write_generic,
727 0x00000000);
728 spr_register(env, SPR_SPRG3, "SPRG3",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_generic, &spr_write_generic,
731 0x00000000);
732 }
733
734 /* SPR common to all non-embedded PowerPC, including 601 */
735 static void gen_spr_ne_601(CPUPPCState *env)
736 {
737 /* Exception processing */
738 spr_register_kvm(env, SPR_DSISR, "DSISR",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
741 KVM_REG_PPC_DSISR, 0x00000000);
742 spr_register_kvm(env, SPR_DAR, "DAR",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_generic, &spr_write_generic,
745 KVM_REG_PPC_DAR, 0x00000000);
746 /* Timer */
747 spr_register(env, SPR_DECR, "DECR",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_decr, &spr_write_decr,
750 0x00000000);
751 }
752
753 /* Storage Description Register 1 */
754 static void gen_spr_sdr1(CPUPPCState *env)
755 {
756 #ifndef CONFIG_USER_ONLY
757 if (env->has_hv_mode) {
758 /* SDR1 is a hypervisor resource on CPUs which have a
759 * hypervisor mode */
760 spr_register_hv(env, SPR_SDR1, "SDR1",
761 SPR_NOACCESS, SPR_NOACCESS,
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_sdr1,
764 0x00000000);
765 } else {
766 spr_register(env, SPR_SDR1, "SDR1",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_generic, &spr_write_sdr1,
769 0x00000000);
770 }
771 #endif
772 }
773
774 /* BATs 0-3 */
775 static void gen_low_BATs(CPUPPCState *env)
776 {
777 #if !defined(CONFIG_USER_ONLY)
778 spr_register(env, SPR_IBAT0U, "IBAT0U",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_ibat, &spr_write_ibatu,
781 0x00000000);
782 spr_register(env, SPR_IBAT0L, "IBAT0L",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat, &spr_write_ibatl,
785 0x00000000);
786 spr_register(env, SPR_IBAT1U, "IBAT1U",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat, &spr_write_ibatu,
789 0x00000000);
790 spr_register(env, SPR_IBAT1L, "IBAT1L",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat, &spr_write_ibatl,
793 0x00000000);
794 spr_register(env, SPR_IBAT2U, "IBAT2U",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat, &spr_write_ibatu,
797 0x00000000);
798 spr_register(env, SPR_IBAT2L, "IBAT2L",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_ibat, &spr_write_ibatl,
801 0x00000000);
802 spr_register(env, SPR_IBAT3U, "IBAT3U",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_ibat, &spr_write_ibatu,
805 0x00000000);
806 spr_register(env, SPR_IBAT3L, "IBAT3L",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_ibat, &spr_write_ibatl,
809 0x00000000);
810 spr_register(env, SPR_DBAT0U, "DBAT0U",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_dbat, &spr_write_dbatu,
813 0x00000000);
814 spr_register(env, SPR_DBAT0L, "DBAT0L",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat, &spr_write_dbatl,
817 0x00000000);
818 spr_register(env, SPR_DBAT1U, "DBAT1U",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat, &spr_write_dbatu,
821 0x00000000);
822 spr_register(env, SPR_DBAT1L, "DBAT1L",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat, &spr_write_dbatl,
825 0x00000000);
826 spr_register(env, SPR_DBAT2U, "DBAT2U",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat, &spr_write_dbatu,
829 0x00000000);
830 spr_register(env, SPR_DBAT2L, "DBAT2L",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_dbat, &spr_write_dbatl,
833 0x00000000);
834 spr_register(env, SPR_DBAT3U, "DBAT3U",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_dbat, &spr_write_dbatu,
837 0x00000000);
838 spr_register(env, SPR_DBAT3L, "DBAT3L",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_dbat, &spr_write_dbatl,
841 0x00000000);
842 env->nb_BATs += 4;
843 #endif
844 }
845
846 /* BATs 4-7 */
847 static void gen_high_BATs(CPUPPCState *env)
848 {
849 #if !defined(CONFIG_USER_ONLY)
850 spr_register(env, SPR_IBAT4U, "IBAT4U",
851 SPR_NOACCESS, SPR_NOACCESS,
852 &spr_read_ibat_h, &spr_write_ibatu_h,
853 0x00000000);
854 spr_register(env, SPR_IBAT4L, "IBAT4L",
855 SPR_NOACCESS, SPR_NOACCESS,
856 &spr_read_ibat_h, &spr_write_ibatl_h,
857 0x00000000);
858 spr_register(env, SPR_IBAT5U, "IBAT5U",
859 SPR_NOACCESS, SPR_NOACCESS,
860 &spr_read_ibat_h, &spr_write_ibatu_h,
861 0x00000000);
862 spr_register(env, SPR_IBAT5L, "IBAT5L",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_ibat_h, &spr_write_ibatl_h,
865 0x00000000);
866 spr_register(env, SPR_IBAT6U, "IBAT6U",
867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_ibat_h, &spr_write_ibatu_h,
869 0x00000000);
870 spr_register(env, SPR_IBAT6L, "IBAT6L",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_ibat_h, &spr_write_ibatl_h,
873 0x00000000);
874 spr_register(env, SPR_IBAT7U, "IBAT7U",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_ibat_h, &spr_write_ibatu_h,
877 0x00000000);
878 spr_register(env, SPR_IBAT7L, "IBAT7L",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_ibat_h, &spr_write_ibatl_h,
881 0x00000000);
882 spr_register(env, SPR_DBAT4U, "DBAT4U",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_dbat_h, &spr_write_dbatu_h,
885 0x00000000);
886 spr_register(env, SPR_DBAT4L, "DBAT4L",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_dbat_h, &spr_write_dbatl_h,
889 0x00000000);
890 spr_register(env, SPR_DBAT5U, "DBAT5U",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_dbat_h, &spr_write_dbatu_h,
893 0x00000000);
894 spr_register(env, SPR_DBAT5L, "DBAT5L",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_dbat_h, &spr_write_dbatl_h,
897 0x00000000);
898 spr_register(env, SPR_DBAT6U, "DBAT6U",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_dbat_h, &spr_write_dbatu_h,
901 0x00000000);
902 spr_register(env, SPR_DBAT6L, "DBAT6L",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_dbat_h, &spr_write_dbatl_h,
905 0x00000000);
906 spr_register(env, SPR_DBAT7U, "DBAT7U",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_dbat_h, &spr_write_dbatu_h,
909 0x00000000);
910 spr_register(env, SPR_DBAT7L, "DBAT7L",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_dbat_h, &spr_write_dbatl_h,
913 0x00000000);
914 env->nb_BATs += 4;
915 #endif
916 }
917
918 /* Generic PowerPC time base */
919 static void gen_tbl(CPUPPCState *env)
920 {
921 spr_register(env, SPR_VTBL, "TBL",
922 &spr_read_tbl, SPR_NOACCESS,
923 &spr_read_tbl, SPR_NOACCESS,
924 0x00000000);
925 spr_register(env, SPR_TBL, "TBL",
926 &spr_read_tbl, SPR_NOACCESS,
927 &spr_read_tbl, &spr_write_tbl,
928 0x00000000);
929 spr_register(env, SPR_VTBU, "TBU",
930 &spr_read_tbu, SPR_NOACCESS,
931 &spr_read_tbu, SPR_NOACCESS,
932 0x00000000);
933 spr_register(env, SPR_TBU, "TBU",
934 &spr_read_tbu, SPR_NOACCESS,
935 &spr_read_tbu, &spr_write_tbu,
936 0x00000000);
937 }
938
939 /* Softare table search registers */
940 static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
941 {
942 #if !defined(CONFIG_USER_ONLY)
943 env->nb_tlb = nb_tlbs;
944 env->nb_ways = nb_ways;
945 env->id_tlbs = 1;
946 env->tlb_type = TLB_6XX;
947 spr_register(env, SPR_DMISS, "DMISS",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, SPR_NOACCESS,
950 0x00000000);
951 spr_register(env, SPR_DCMP, "DCMP",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, SPR_NOACCESS,
954 0x00000000);
955 spr_register(env, SPR_HASH1, "HASH1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, SPR_NOACCESS,
958 0x00000000);
959 spr_register(env, SPR_HASH2, "HASH2",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, SPR_NOACCESS,
962 0x00000000);
963 spr_register(env, SPR_IMISS, "IMISS",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, SPR_NOACCESS,
966 0x00000000);
967 spr_register(env, SPR_ICMP, "ICMP",
968 SPR_NOACCESS, SPR_NOACCESS,
969 &spr_read_generic, SPR_NOACCESS,
970 0x00000000);
971 spr_register(env, SPR_RPA, "RPA",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 #endif
976 }
977
978 /* SPR common to MPC755 and G2 */
979 static void gen_spr_G2_755(CPUPPCState *env)
980 {
981 /* SGPRs */
982 spr_register(env, SPR_SPRG4, "SPRG4",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986 spr_register(env, SPR_SPRG5, "SPRG5",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 spr_register(env, SPR_SPRG6, "SPRG6",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, &spr_write_generic,
993 0x00000000);
994 spr_register(env, SPR_SPRG7, "SPRG7",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998 }
999
1000 /* SPR common to all 7xx PowerPC implementations */
1001 static void gen_spr_7xx(CPUPPCState *env)
1002 {
1003 /* Breakpoints */
1004 /* XXX : not implemented */
1005 spr_register_kvm(env, SPR_DABR, "DABR",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 KVM_REG_PPC_DABR, 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_IABR, "IABR",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014 /* Cache management */
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_ICTC, "ICTC",
1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
1020 /* Performance monitors */
1021 /* XXX : not implemented */
1022 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, &spr_write_generic,
1025 0x00000000);
1026 /* XXX : not implemented */
1027 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, &spr_write_generic,
1030 0x00000000);
1031 /* XXX : not implemented */
1032 spr_register(env, SPR_7XX_PMC1, "PMC1",
1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, &spr_write_generic,
1035 0x00000000);
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_7XX_PMC2, "PMC2",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_7XX_PMC3, "PMC3",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_7XX_PMC4, "PMC4",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_7XX_SIAR, "SIAR",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, SPR_NOACCESS,
1055 0x00000000);
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1058 &spr_read_ureg, SPR_NOACCESS,
1059 &spr_read_ureg, SPR_NOACCESS,
1060 0x00000000);
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1063 &spr_read_ureg, SPR_NOACCESS,
1064 &spr_read_ureg, SPR_NOACCESS,
1065 0x00000000);
1066 /* XXX : not implemented */
1067 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1068 &spr_read_ureg, SPR_NOACCESS,
1069 &spr_read_ureg, SPR_NOACCESS,
1070 0x00000000);
1071 /* XXX : not implemented */
1072 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1073 &spr_read_ureg, SPR_NOACCESS,
1074 &spr_read_ureg, SPR_NOACCESS,
1075 0x00000000);
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1078 &spr_read_ureg, SPR_NOACCESS,
1079 &spr_read_ureg, SPR_NOACCESS,
1080 0x00000000);
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1083 &spr_read_ureg, SPR_NOACCESS,
1084 &spr_read_ureg, SPR_NOACCESS,
1085 0x00000000);
1086 /* XXX : not implemented */
1087 spr_register(env, SPR_7XX_USIAR, "USIAR",
1088 &spr_read_ureg, SPR_NOACCESS,
1089 &spr_read_ureg, SPR_NOACCESS,
1090 0x00000000);
1091 /* External access control */
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_EAR, "EAR",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 }
1098
1099 #ifdef TARGET_PPC64
1100 #ifndef CONFIG_USER_ONLY
1101 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1102 {
1103 TCGv t0 = tcg_temp_new();
1104 TCGv t1 = tcg_temp_new();
1105 TCGv t2 = tcg_temp_new();
1106
1107 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1108 * spr_write_generic for HV mode in the SPR table
1109 */
1110
1111 /* Build insertion mask into t1 based on context */
1112 if (ctx->pr) {
1113 gen_load_spr(t1, SPR_UAMOR);
1114 } else {
1115 gen_load_spr(t1, SPR_AMOR);
1116 }
1117
1118 /* Mask new bits into t2 */
1119 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1120
1121 /* Load AMR and clear new bits in t0 */
1122 gen_load_spr(t0, SPR_AMR);
1123 tcg_gen_andc_tl(t0, t0, t1);
1124
1125 /* Or'in new bits and write it out */
1126 tcg_gen_or_tl(t0, t0, t2);
1127 gen_store_spr(SPR_AMR, t0);
1128 spr_store_dump_spr(SPR_AMR);
1129
1130 tcg_temp_free(t0);
1131 tcg_temp_free(t1);
1132 tcg_temp_free(t2);
1133 }
1134
1135 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1136 {
1137 TCGv t0 = tcg_temp_new();
1138 TCGv t1 = tcg_temp_new();
1139 TCGv t2 = tcg_temp_new();
1140
1141 /* Note, the HV=1 case is handled earlier by simply using
1142 * spr_write_generic for HV mode in the SPR table
1143 */
1144
1145 /* Build insertion mask into t1 based on context */
1146 gen_load_spr(t1, SPR_AMOR);
1147
1148 /* Mask new bits into t2 */
1149 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1150
1151 /* Load AMR and clear new bits in t0 */
1152 gen_load_spr(t0, SPR_UAMOR);
1153 tcg_gen_andc_tl(t0, t0, t1);
1154
1155 /* Or'in new bits and write it out */
1156 tcg_gen_or_tl(t0, t0, t2);
1157 gen_store_spr(SPR_UAMOR, t0);
1158 spr_store_dump_spr(SPR_UAMOR);
1159
1160 tcg_temp_free(t0);
1161 tcg_temp_free(t1);
1162 tcg_temp_free(t2);
1163 }
1164
1165 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1166 {
1167 TCGv t0 = tcg_temp_new();
1168 TCGv t1 = tcg_temp_new();
1169 TCGv t2 = tcg_temp_new();
1170
1171 /* Note, the HV=1 case is handled earlier by simply using
1172 * spr_write_generic for HV mode in the SPR table
1173 */
1174
1175 /* Build insertion mask into t1 based on context */
1176 gen_load_spr(t1, SPR_AMOR);
1177
1178 /* Mask new bits into t2 */
1179 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1180
1181 /* Load AMR and clear new bits in t0 */
1182 gen_load_spr(t0, SPR_IAMR);
1183 tcg_gen_andc_tl(t0, t0, t1);
1184
1185 /* Or'in new bits and write it out */
1186 tcg_gen_or_tl(t0, t0, t2);
1187 gen_store_spr(SPR_IAMR, t0);
1188 spr_store_dump_spr(SPR_IAMR);
1189
1190 tcg_temp_free(t0);
1191 tcg_temp_free(t1);
1192 tcg_temp_free(t2);
1193 }
1194 #endif /* CONFIG_USER_ONLY */
1195
1196 static void gen_spr_amr(CPUPPCState *env)
1197 {
1198 #ifndef CONFIG_USER_ONLY
1199 /* Virtual Page Class Key protection */
1200 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1201 * userspace accessible, 29 is privileged. So we only need to set
1202 * the kvm ONE_REG id on one of them, we use 29 */
1203 spr_register(env, SPR_UAMR, "UAMR",
1204 &spr_read_generic, &spr_write_amr,
1205 &spr_read_generic, &spr_write_amr,
1206 0);
1207 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_amr,
1210 &spr_read_generic, &spr_write_generic,
1211 KVM_REG_PPC_AMR, 0);
1212 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_uamor,
1215 &spr_read_generic, &spr_write_generic,
1216 KVM_REG_PPC_UAMOR, 0);
1217 spr_register_hv(env, SPR_AMOR, "AMOR",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0);
1222 #endif /* !CONFIG_USER_ONLY */
1223 }
1224
1225 static void gen_spr_iamr(CPUPPCState *env)
1226 {
1227 #ifndef CONFIG_USER_ONLY
1228 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_iamr,
1231 &spr_read_generic, &spr_write_generic,
1232 KVM_REG_PPC_IAMR, 0);
1233 #endif /* !CONFIG_USER_ONLY */
1234 }
1235 #endif /* TARGET_PPC64 */
1236
1237 #ifndef CONFIG_USER_ONLY
1238 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1239 {
1240 gen_helper_fixup_thrm(cpu_env);
1241 gen_load_spr(cpu_gpr[gprn], sprn);
1242 spr_load_dump_spr(sprn);
1243 }
1244 #endif /* !CONFIG_USER_ONLY */
1245
1246 static void gen_spr_thrm(CPUPPCState *env)
1247 {
1248 /* Thermal management */
1249 /* XXX : not implemented */
1250 spr_register(env, SPR_THRM1, "THRM1",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_thrm, &spr_write_generic,
1253 0x00000000);
1254 /* XXX : not implemented */
1255 spr_register(env, SPR_THRM2, "THRM2",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_thrm, &spr_write_generic,
1258 0x00000000);
1259 /* XXX : not implemented */
1260 spr_register(env, SPR_THRM3, "THRM3",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_thrm, &spr_write_generic,
1263 0x00000000);
1264 }
1265
1266 /* SPR specific to PowerPC 604 implementation */
1267 static void gen_spr_604(CPUPPCState *env)
1268 {
1269 /* Processor identification */
1270 spr_register(env, SPR_PIR, "PIR",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_pir,
1273 0x00000000);
1274 /* Breakpoints */
1275 /* XXX : not implemented */
1276 spr_register(env, SPR_IABR, "IABR",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1279 0x00000000);
1280 /* XXX : not implemented */
1281 spr_register_kvm(env, SPR_DABR, "DABR",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 KVM_REG_PPC_DABR, 0x00000000);
1285 /* Performance counters */
1286 /* XXX : not implemented */
1287 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1288 SPR_NOACCESS, SPR_NOACCESS,
1289 &spr_read_generic, &spr_write_generic,
1290 0x00000000);
1291 /* XXX : not implemented */
1292 spr_register(env, SPR_7XX_PMC1, "PMC1",
1293 SPR_NOACCESS, SPR_NOACCESS,
1294 &spr_read_generic, &spr_write_generic,
1295 0x00000000);
1296 /* XXX : not implemented */
1297 spr_register(env, SPR_7XX_PMC2, "PMC2",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_generic, &spr_write_generic,
1300 0x00000000);
1301 /* XXX : not implemented */
1302 spr_register(env, SPR_7XX_SIAR, "SIAR",
1303 SPR_NOACCESS, SPR_NOACCESS,
1304 &spr_read_generic, SPR_NOACCESS,
1305 0x00000000);
1306 /* XXX : not implemented */
1307 spr_register(env, SPR_SDA, "SDA",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_generic, SPR_NOACCESS,
1310 0x00000000);
1311 /* External access control */
1312 /* XXX : not implemented */
1313 spr_register(env, SPR_EAR, "EAR",
1314 SPR_NOACCESS, SPR_NOACCESS,
1315 &spr_read_generic, &spr_write_generic,
1316 0x00000000);
1317 }
1318
1319 /* SPR specific to PowerPC 603 implementation */
1320 static void gen_spr_603(CPUPPCState *env)
1321 {
1322 /* External access control */
1323 /* XXX : not implemented */
1324 spr_register(env, SPR_EAR, "EAR",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328 /* Breakpoints */
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_IABR, "IABR",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334
1335 }
1336
1337 /* SPR specific to PowerPC G2 implementation */
1338 static void gen_spr_G2(CPUPPCState *env)
1339 {
1340 /* Memory base address */
1341 /* MBAR */
1342 /* XXX : not implemented */
1343 spr_register(env, SPR_MBAR, "MBAR",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
1347 /* Exception processing */
1348 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
1352 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_generic,
1355 0x00000000);
1356 /* Breakpoints */
1357 /* XXX : not implemented */
1358 spr_register(env, SPR_DABR, "DABR",
1359 SPR_NOACCESS, SPR_NOACCESS,
1360 &spr_read_generic, &spr_write_generic,
1361 0x00000000);
1362 /* XXX : not implemented */
1363 spr_register(env, SPR_DABR2, "DABR2",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367 /* XXX : not implemented */
1368 spr_register(env, SPR_IABR, "IABR",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372 /* XXX : not implemented */
1373 spr_register(env, SPR_IABR2, "IABR2",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 /* XXX : not implemented */
1378 spr_register(env, SPR_IBCR, "IBCR",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382 /* XXX : not implemented */
1383 spr_register(env, SPR_DBCR, "DBCR",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387 }
1388
1389 /* SPR specific to PowerPC 602 implementation */
1390 static void gen_spr_602(CPUPPCState *env)
1391 {
1392 /* ESA registers */
1393 /* XXX : not implemented */
1394 spr_register(env, SPR_SER, "SER",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398 /* XXX : not implemented */
1399 spr_register(env, SPR_SEBR, "SEBR",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
1403 /* XXX : not implemented */
1404 spr_register(env, SPR_ESASRR, "ESASRR",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_generic,
1407 0x00000000);
1408 /* Floating point status */
1409 /* XXX : not implemented */
1410 spr_register(env, SPR_SP, "SP",
1411 SPR_NOACCESS, SPR_NOACCESS,
1412 &spr_read_generic, &spr_write_generic,
1413 0x00000000);
1414 /* XXX : not implemented */
1415 spr_register(env, SPR_LT, "LT",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419 /* Watchdog timer */
1420 /* XXX : not implemented */
1421 spr_register(env, SPR_TCR, "TCR",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425 /* Interrupt base */
1426 spr_register(env, SPR_IBR, "IBR",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_generic, &spr_write_generic,
1429 0x00000000);
1430 /* XXX : not implemented */
1431 spr_register(env, SPR_IABR, "IABR",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435 }
1436
1437 /* SPR specific to PowerPC 601 implementation */
1438 static void gen_spr_601(CPUPPCState *env)
1439 {
1440 /* Multiplication/division register */
1441 /* MQ */
1442 spr_register(env, SPR_MQ, "MQ",
1443 &spr_read_generic, &spr_write_generic,
1444 &spr_read_generic, &spr_write_generic,
1445 0x00000000);
1446 /* RTC registers */
1447 spr_register(env, SPR_601_RTCU, "RTCU",
1448 SPR_NOACCESS, SPR_NOACCESS,
1449 SPR_NOACCESS, &spr_write_601_rtcu,
1450 0x00000000);
1451 spr_register(env, SPR_601_VRTCU, "RTCU",
1452 &spr_read_601_rtcu, SPR_NOACCESS,
1453 &spr_read_601_rtcu, SPR_NOACCESS,
1454 0x00000000);
1455 spr_register(env, SPR_601_RTCL, "RTCL",
1456 SPR_NOACCESS, SPR_NOACCESS,
1457 SPR_NOACCESS, &spr_write_601_rtcl,
1458 0x00000000);
1459 spr_register(env, SPR_601_VRTCL, "RTCL",
1460 &spr_read_601_rtcl, SPR_NOACCESS,
1461 &spr_read_601_rtcl, SPR_NOACCESS,
1462 0x00000000);
1463 /* Timer */
1464 #if 0 /* ? */
1465 spr_register(env, SPR_601_UDECR, "UDECR",
1466 &spr_read_decr, SPR_NOACCESS,
1467 &spr_read_decr, SPR_NOACCESS,
1468 0x00000000);
1469 #endif
1470 /* External access control */
1471 /* XXX : not implemented */
1472 spr_register(env, SPR_EAR, "EAR",
1473 SPR_NOACCESS, SPR_NOACCESS,
1474 &spr_read_generic, &spr_write_generic,
1475 0x00000000);
1476 /* Memory management */
1477 #if !defined(CONFIG_USER_ONLY)
1478 spr_register(env, SPR_IBAT0U, "IBAT0U",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_601_ubat, &spr_write_601_ubatu,
1481 0x00000000);
1482 spr_register(env, SPR_IBAT0L, "IBAT0L",
1483 SPR_NOACCESS, SPR_NOACCESS,
1484 &spr_read_601_ubat, &spr_write_601_ubatl,
1485 0x00000000);
1486 spr_register(env, SPR_IBAT1U, "IBAT1U",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_601_ubat, &spr_write_601_ubatu,
1489 0x00000000);
1490 spr_register(env, SPR_IBAT1L, "IBAT1L",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_601_ubat, &spr_write_601_ubatl,
1493 0x00000000);
1494 spr_register(env, SPR_IBAT2U, "IBAT2U",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_601_ubat, &spr_write_601_ubatu,
1497 0x00000000);
1498 spr_register(env, SPR_IBAT2L, "IBAT2L",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_601_ubat, &spr_write_601_ubatl,
1501 0x00000000);
1502 spr_register(env, SPR_IBAT3U, "IBAT3U",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_601_ubat, &spr_write_601_ubatu,
1505 0x00000000);
1506 spr_register(env, SPR_IBAT3L, "IBAT3L",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_601_ubat, &spr_write_601_ubatl,
1509 0x00000000);
1510 env->nb_BATs = 4;
1511 #endif
1512 }
1513
1514 static void gen_spr_74xx(CPUPPCState *env)
1515 {
1516 /* Processor identification */
1517 spr_register(env, SPR_PIR, "PIR",
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_pir,
1520 0x00000000);
1521 /* XXX : not implemented */
1522 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526 /* XXX : not implemented */
1527 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1528 &spr_read_ureg, SPR_NOACCESS,
1529 &spr_read_ureg, SPR_NOACCESS,
1530 0x00000000);
1531 /* XXX: not implemented */
1532 spr_register(env, SPR_BAMR, "BAMR",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, &spr_write_generic,
1535 0x00000000);
1536 /* XXX : not implemented */
1537 spr_register(env, SPR_MSSCR0, "MSSCR0",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
1541 /* Hardware implementation registers */
1542 /* XXX : not implemented */
1543 spr_register(env, SPR_HID0, "HID0",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_HID1, "HID1",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 /* Altivec */
1553 spr_register(env, SPR_VRSAVE, "VRSAVE",
1554 &spr_read_generic, &spr_write_generic,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_L2CR, "L2CR",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, spr_access_nop,
1561 0x00000000);
1562 /* Not strictly an SPR */
1563 vscr_init(env, 0x00010000);
1564 }
1565
1566 static void gen_l3_ctrl(CPUPPCState *env)
1567 {
1568 /* L3CR */
1569 /* XXX : not implemented */
1570 spr_register(env, SPR_L3CR, "L3CR",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
1574 /* L3ITCR0 */
1575 /* XXX : not implemented */
1576 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, &spr_write_generic,
1579 0x00000000);
1580 /* L3PM */
1581 /* XXX : not implemented */
1582 spr_register(env, SPR_L3PM, "L3PM",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
1586 }
1587
1588 static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1589 {
1590 #if !defined(CONFIG_USER_ONLY)
1591 env->nb_tlb = nb_tlbs;
1592 env->nb_ways = nb_ways;
1593 env->id_tlbs = 1;
1594 env->tlb_type = TLB_6XX;
1595 /* XXX : not implemented */
1596 spr_register(env, SPR_PTEHI, "PTEHI",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_generic,
1599 0x00000000);
1600 /* XXX : not implemented */
1601 spr_register(env, SPR_PTELO, "PTELO",
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605 /* XXX : not implemented */
1606 spr_register(env, SPR_TLBMISS, "TLBMISS",
1607 SPR_NOACCESS, SPR_NOACCESS,
1608 &spr_read_generic, &spr_write_generic,
1609 0x00000000);
1610 #endif
1611 }
1612
1613 #if !defined(CONFIG_USER_ONLY)
1614 static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1615 {
1616 TCGv t0 = tcg_temp_new();
1617
1618 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1619 gen_store_spr(sprn, t0);
1620 tcg_temp_free(t0);
1621 }
1622
1623 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1624 {
1625 TCGv t0 = tcg_temp_new();
1626
1627 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1628 gen_store_spr(sprn, t0);
1629 tcg_temp_free(t0);
1630 }
1631
1632 static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1633 {
1634 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1635 }
1636
1637 static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1638 {
1639 TCGv_i32 t0 = tcg_const_i32(sprn);
1640 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1641 tcg_temp_free_i32(t0);
1642 }
1643 #endif
1644
1645 static void gen_spr_usprg3(CPUPPCState *env)
1646 {
1647 spr_register(env, SPR_USPRG3, "USPRG3",
1648 &spr_read_ureg, SPR_NOACCESS,
1649 &spr_read_ureg, SPR_NOACCESS,
1650 0x00000000);
1651 }
1652
1653 static void gen_spr_usprgh(CPUPPCState *env)
1654 {
1655 spr_register(env, SPR_USPRG4, "USPRG4",
1656 &spr_read_ureg, SPR_NOACCESS,
1657 &spr_read_ureg, SPR_NOACCESS,
1658 0x00000000);
1659 spr_register(env, SPR_USPRG5, "USPRG5",
1660 &spr_read_ureg, SPR_NOACCESS,
1661 &spr_read_ureg, SPR_NOACCESS,
1662 0x00000000);
1663 spr_register(env, SPR_USPRG6, "USPRG6",
1664 &spr_read_ureg, SPR_NOACCESS,
1665 &spr_read_ureg, SPR_NOACCESS,
1666 0x00000000);
1667 spr_register(env, SPR_USPRG7, "USPRG7",
1668 &spr_read_ureg, SPR_NOACCESS,
1669 &spr_read_ureg, SPR_NOACCESS,
1670 0x00000000);
1671 }
1672
1673 /* PowerPC BookE SPR */
1674 static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1675 {
1676 const char *ivor_names[64] = {
1677 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1678 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1679 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1680 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1681 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1682 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1683 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1684 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1685 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1686 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1687 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1688 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1689 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1690 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1691 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1692 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1693 };
1694 #define SPR_BOOKE_IVORxx (-1)
1695 int ivor_sprn[64] = {
1696 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1697 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1698 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1699 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1700 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1701 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1702 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1703 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1704 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1705 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1706 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1707 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1708 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1709 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1710 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1711 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1712 };
1713 int i;
1714
1715 /* Interrupt processing */
1716 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_generic,
1719 0x00000000);
1720 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724 /* Debug */
1725 /* XXX : not implemented */
1726 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_generic,
1729 0x00000000);
1730 /* XXX : not implemented */
1731 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_generic,
1734 0x00000000);
1735 /* XXX : not implemented */
1736 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 /* XXX : not implemented */
1741 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, &spr_write_generic,
1744 0x00000000);
1745 /* XXX : not implemented */
1746 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1747 SPR_NOACCESS, SPR_NOACCESS,
1748 &spr_read_generic, &spr_write_40x_dbcr0,
1749 0x00000000);
1750 /* XXX : not implemented */
1751 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1752 SPR_NOACCESS, SPR_NOACCESS,
1753 &spr_read_generic, &spr_write_generic,
1754 0x00000000);
1755 /* XXX : not implemented */
1756 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1757 SPR_NOACCESS, SPR_NOACCESS,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
1760 /* XXX : not implemented */
1761 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, &spr_write_clear,
1764 0x00000000);
1765 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
1769 spr_register(env, SPR_BOOKE_ESR, "ESR",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_excp_prefix,
1776 0x00000000);
1777 /* Exception vectors */
1778 for (i = 0; i < 64; i++) {
1779 if (ivor_mask & (1ULL << i)) {
1780 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1781 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1782 exit(1);
1783 }
1784 spr_register(env, ivor_sprn[i], ivor_names[i],
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_excp_vector,
1787 0x00000000);
1788 }
1789 }
1790 spr_register(env, SPR_BOOKE_PID, "PID",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_booke_pid,
1793 0x00000000);
1794 spr_register(env, SPR_BOOKE_TCR, "TCR",
1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, &spr_write_booke_tcr,
1797 0x00000000);
1798 spr_register(env, SPR_BOOKE_TSR, "TSR",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_booke_tsr,
1801 0x00000000);
1802 /* Timer */
1803 spr_register(env, SPR_DECR, "DECR",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_decr, &spr_write_decr,
1806 0x00000000);
1807 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 SPR_NOACCESS, &spr_write_generic,
1810 0x00000000);
1811 /* SPRGs */
1812 spr_register(env, SPR_USPRG0, "USPRG0",
1813 &spr_read_generic, &spr_write_generic,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 spr_register(env, SPR_SPRG4, "SPRG4",
1817 SPR_NOACCESS, SPR_NOACCESS,
1818 &spr_read_generic, &spr_write_generic,
1819 0x00000000);
1820 spr_register(env, SPR_SPRG5, "SPRG5",
1821 SPR_NOACCESS, SPR_NOACCESS,
1822 &spr_read_generic, &spr_write_generic,
1823 0x00000000);
1824 spr_register(env, SPR_SPRG6, "SPRG6",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 spr_register(env, SPR_SPRG7, "SPRG7",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 }
1833
1834 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1835 uint32_t maxsize, uint32_t flags,
1836 uint32_t nentries)
1837 {
1838 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1839 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1840 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1841 flags | nentries;
1842 }
1843
1844 /* BookE 2.06 storage control registers */
1845 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1846 uint32_t *tlbncfg, uint32_t mmucfg)
1847 {
1848 #if !defined(CONFIG_USER_ONLY)
1849 const char *mas_names[8] = {
1850 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1851 };
1852 int mas_sprn[8] = {
1853 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1854 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1855 };
1856 int i;
1857
1858 /* TLB assist registers */
1859 /* XXX : not implemented */
1860 for (i = 0; i < 8; i++) {
1861 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1862 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1863 uea_write = &spr_write_generic;
1864 }
1865 if (mas_mask & (1 << i)) {
1866 spr_register(env, mas_sprn[i], mas_names[i],
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, uea_write,
1869 0x00000000);
1870 }
1871 }
1872 if (env->nb_pids > 1) {
1873 /* XXX : not implemented */
1874 spr_register(env, SPR_BOOKE_PID1, "PID1",
1875 SPR_NOACCESS, SPR_NOACCESS,
1876 &spr_read_generic, &spr_write_booke_pid,
1877 0x00000000);
1878 }
1879 if (env->nb_pids > 2) {
1880 /* XXX : not implemented */
1881 spr_register(env, SPR_BOOKE_PID2, "PID2",
1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_booke_pid,
1884 0x00000000);
1885 }
1886 /* XXX : not implemented */
1887 spr_register(env, SPR_MMUCFG, "MMUCFG",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, SPR_NOACCESS,
1890 mmucfg);
1891 switch (env->nb_ways) {
1892 case 4:
1893 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, SPR_NOACCESS,
1896 tlbncfg[3]);
1897 /* Fallthru */
1898 case 3:
1899 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, SPR_NOACCESS,
1902 tlbncfg[2]);
1903 /* Fallthru */
1904 case 2:
1905 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, SPR_NOACCESS,
1908 tlbncfg[1]);
1909 /* Fallthru */
1910 case 1:
1911 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, SPR_NOACCESS,
1914 tlbncfg[0]);
1915 /* Fallthru */
1916 case 0:
1917 default:
1918 break;
1919 }
1920 #endif
1921
1922 gen_spr_usprgh(env);
1923 }
1924
1925 /* SPR specific to PowerPC 440 implementation */
1926 static void gen_spr_440(CPUPPCState *env)
1927 {
1928 /* Cache control */
1929 /* XXX : not implemented */
1930 spr_register(env, SPR_440_DNV0, "DNV0",
1931 SPR_NOACCESS, SPR_NOACCESS,
1932 &spr_read_generic, &spr_write_generic,
1933 0x00000000);
1934 /* XXX : not implemented */
1935 spr_register(env, SPR_440_DNV1, "DNV1",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 &spr_read_generic, &spr_write_generic,
1938 0x00000000);
1939 /* XXX : not implemented */
1940 spr_register(env, SPR_440_DNV2, "DNV2",
1941 SPR_NOACCESS, SPR_NOACCESS,
1942 &spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 /* XXX : not implemented */
1945 spr_register(env, SPR_440_DNV3, "DNV3",
1946 SPR_NOACCESS, SPR_NOACCESS,
1947 &spr_read_generic, &spr_write_generic,
1948 0x00000000);
1949 /* XXX : not implemented */
1950 spr_register(env, SPR_440_DTV0, "DTV0",
1951 SPR_NOACCESS, SPR_NOACCESS,
1952 &spr_read_generic, &spr_write_generic,
1953 0x00000000);
1954 /* XXX : not implemented */
1955 spr_register(env, SPR_440_DTV1, "DTV1",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959 /* XXX : not implemented */
1960 spr_register(env, SPR_440_DTV2, "DTV2",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00000000);
1964 /* XXX : not implemented */
1965 spr_register(env, SPR_440_DTV3, "DTV3",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, &spr_write_generic,
1968 0x00000000);
1969 /* XXX : not implemented */
1970 spr_register(env, SPR_440_DVLIM, "DVLIM",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974 /* XXX : not implemented */
1975 spr_register(env, SPR_440_INV0, "INV0",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979 /* XXX : not implemented */
1980 spr_register(env, SPR_440_INV1, "INV1",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, &spr_write_generic,
1983 0x00000000);
1984 /* XXX : not implemented */
1985 spr_register(env, SPR_440_INV2, "INV2",
1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, &spr_write_generic,
1988 0x00000000);
1989 /* XXX : not implemented */
1990 spr_register(env, SPR_440_INV3, "INV3",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994 /* XXX : not implemented */
1995 spr_register(env, SPR_440_ITV0, "ITV0",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999 /* XXX : not implemented */
2000 spr_register(env, SPR_440_ITV1, "ITV1",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004 /* XXX : not implemented */
2005 spr_register(env, SPR_440_ITV2, "ITV2",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 /* XXX : not implemented */
2010 spr_register(env, SPR_440_ITV3, "ITV3",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_generic,
2013 0x00000000);
2014 /* XXX : not implemented */
2015 spr_register(env, SPR_440_IVLIM, "IVLIM",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0x00000000);
2019 /* Cache debug */
2020 /* XXX : not implemented */
2021 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, SPR_NOACCESS,
2024 0x00000000);
2025 /* XXX : not implemented */
2026 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, SPR_NOACCESS,
2029 0x00000000);
2030 /* XXX : not implemented */
2031 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, SPR_NOACCESS,
2034 0x00000000);
2035 /* XXX : not implemented */
2036 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, SPR_NOACCESS,
2039 0x00000000);
2040 /* XXX : not implemented */
2041 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 &spr_read_generic, SPR_NOACCESS,
2044 0x00000000);
2045 /* XXX : not implemented */
2046 spr_register(env, SPR_440_DBDR, "DBDR",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, &spr_write_generic,
2049 0x00000000);
2050 /* Processor control */
2051 spr_register(env, SPR_4xx_CCR0, "CCR0",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 &spr_read_generic, &spr_write_generic,
2054 0x00000000);
2055 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, SPR_NOACCESS,
2058 0x00000000);
2059 /* Storage control */
2060 spr_register(env, SPR_440_MMUCR, "MMUCR",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 }
2065
2066 /* SPR shared between PowerPC 40x implementations */
2067 static void gen_spr_40x(CPUPPCState *env)
2068 {
2069 /* Cache */
2070 /* not emulated, as QEMU do not emulate caches */
2071 spr_register(env, SPR_40x_DCCR, "DCCR",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, &spr_write_generic,
2074 0x00000000);
2075 /* not emulated, as QEMU do not emulate caches */
2076 spr_register(env, SPR_40x_ICCR, "ICCR",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, &spr_write_generic,
2079 0x00000000);
2080 /* not emulated, as QEMU do not emulate caches */
2081 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2082 SPR_NOACCESS, SPR_NOACCESS,
2083 &spr_read_generic, SPR_NOACCESS,
2084 0x00000000);
2085 /* Exception */
2086 spr_register(env, SPR_40x_DEAR, "DEAR",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_generic, &spr_write_generic,
2089 0x00000000);
2090 spr_register(env, SPR_40x_ESR, "ESR",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, &spr_write_generic,
2093 0x00000000);
2094 spr_register(env, SPR_40x_EVPR, "EVPR",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_excp_prefix,
2097 0x00000000);
2098 spr_register(env, SPR_40x_SRR2, "SRR2",
2099 &spr_read_generic, &spr_write_generic,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 spr_register(env, SPR_40x_SRR3, "SRR3",
2103 &spr_read_generic, &spr_write_generic,
2104 &spr_read_generic, &spr_write_generic,
2105 0x00000000);
2106 /* Timers */
2107 spr_register(env, SPR_40x_PIT, "PIT",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_40x_pit, &spr_write_40x_pit,
2110 0x00000000);
2111 spr_register(env, SPR_40x_TCR, "TCR",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_booke_tcr,
2114 0x00000000);
2115 spr_register(env, SPR_40x_TSR, "TSR",
2116 SPR_NOACCESS, SPR_NOACCESS,
2117 &spr_read_generic, &spr_write_booke_tsr,
2118 0x00000000);
2119 }
2120
2121 /* SPR specific to PowerPC 405 implementation */
2122 static void gen_spr_405(CPUPPCState *env)
2123 {
2124 /* MMU */
2125 spr_register(env, SPR_40x_PID, "PID",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_generic,
2128 0x00000000);
2129 spr_register(env, SPR_4xx_CCR0, "CCR0",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00700000);
2133 /* Debug interface */
2134 /* XXX : not implemented */
2135 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_40x_dbcr0,
2138 0x00000000);
2139 /* XXX : not implemented */
2140 spr_register(env, SPR_405_DBCR1, "DBCR1",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
2144 /* XXX : not implemented */
2145 spr_register(env, SPR_40x_DBSR, "DBSR",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_clear,
2148 /* Last reset was system reset */
2149 0x00000300);
2150 /* XXX : not implemented */
2151 spr_register(env, SPR_40x_DAC1, "DAC1",
2152 SPR_NOACCESS, SPR_NOACCESS,
2153 &spr_read_generic, &spr_write_generic,
2154 0x00000000);
2155 spr_register(env, SPR_40x_DAC2, "DAC2",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
2159 /* XXX : not implemented */
2160 spr_register(env, SPR_405_DVC1, "DVC1",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 /* XXX : not implemented */
2165 spr_register(env, SPR_405_DVC2, "DVC2",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_40x_IAC1, "IAC1",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, &spr_write_generic,
2173 0x00000000);
2174 spr_register(env, SPR_40x_IAC2, "IAC2",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_405_IAC3, "IAC3",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
2183 /* XXX : not implemented */
2184 spr_register(env, SPR_405_IAC4, "IAC4",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
2188 /* Storage control */
2189 /* XXX: TODO: not implemented */
2190 spr_register(env, SPR_405_SLER, "SLER",
2191 SPR_NOACCESS, SPR_NOACCESS,
2192 &spr_read_generic, &spr_write_40x_sler,
2193 0x00000000);
2194 spr_register(env, SPR_40x_ZPR, "ZPR",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
2198 /* XXX : not implemented */
2199 spr_register(env, SPR_405_SU0R, "SU0R",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
2203 /* SPRG */
2204 spr_register(env, SPR_USPRG0, "USPRG0",
2205 &spr_read_ureg, SPR_NOACCESS,
2206 &spr_read_ureg, SPR_NOACCESS,
2207 0x00000000);
2208 spr_register(env, SPR_SPRG4, "SPRG4",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 spr_register(env, SPR_SPRG5, "SPRG5",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 spr_read_generic, &spr_write_generic,
2215 0x00000000);
2216 spr_register(env, SPR_SPRG6, "SPRG6",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 spr_read_generic, &spr_write_generic,
2219 0x00000000);
2220 spr_register(env, SPR_SPRG7, "SPRG7",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 gen_spr_usprgh(env);
2225 }
2226
2227 /* SPR shared between PowerPC 401 & 403 implementations */
2228 static void gen_spr_401_403(CPUPPCState *env)
2229 {
2230 /* Time base */
2231 spr_register(env, SPR_403_VTBL, "TBL",
2232 &spr_read_tbl, SPR_NOACCESS,
2233 &spr_read_tbl, SPR_NOACCESS,
2234 0x00000000);
2235 spr_register(env, SPR_403_TBL, "TBL",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 SPR_NOACCESS, &spr_write_tbl,
2238 0x00000000);
2239 spr_register(env, SPR_403_VTBU, "TBU",
2240 &spr_read_tbu, SPR_NOACCESS,
2241 &spr_read_tbu, SPR_NOACCESS,
2242 0x00000000);
2243 spr_register(env, SPR_403_TBU, "TBU",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 SPR_NOACCESS, &spr_write_tbu,
2246 0x00000000);
2247 /* Debug */
2248 /* not emulated, as QEMU do not emulate caches */
2249 spr_register(env, SPR_403_CDBCR, "CDBCR",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 }
2254
2255 /* SPR specific to PowerPC 401 implementation */
2256 static void gen_spr_401(CPUPPCState *env)
2257 {
2258 /* Debug interface */
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_40x_DBCR0, "DBCR",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_40x_dbcr0,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_40x_DBSR, "DBSR",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_clear,
2268 /* Last reset was system reset */
2269 0x00000300);
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_40x_DAC1, "DAC",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_40x_IAC1, "IAC",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 /* Storage control */
2281 /* XXX: TODO: not implemented */
2282 spr_register(env, SPR_405_SLER, "SLER",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_40x_sler,
2285 0x00000000);
2286 /* not emulated, as QEMU never does speculative access */
2287 spr_register(env, SPR_40x_SGR, "SGR",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0xFFFFFFFF);
2291 /* not emulated, as QEMU do not emulate caches */
2292 spr_register(env, SPR_40x_DCWR, "DCWR",
2293 SPR_NOACCESS, SPR_NOACCESS,
2294 &spr_read_generic, &spr_write_generic,
2295 0x00000000);
2296 }
2297
2298 static void gen_spr_401x2(CPUPPCState *env)
2299 {
2300 gen_spr_401(env);
2301 spr_register(env, SPR_40x_PID, "PID",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 &spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 spr_register(env, SPR_40x_ZPR, "ZPR",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 }
2310
2311 /* SPR specific to PowerPC 403 implementation */
2312 static void gen_spr_403(CPUPPCState *env)
2313 {
2314 /* Debug interface */
2315 /* XXX : not implemented */
2316 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 &spr_read_generic, &spr_write_40x_dbcr0,
2319 0x00000000);
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_40x_DBSR, "DBSR",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_clear,
2324 /* Last reset was system reset */
2325 0x00000300);
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_40x_DAC1, "DAC1",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
2331 /* XXX : not implemented */
2332 spr_register(env, SPR_40x_DAC2, "DAC2",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 /* XXX : not implemented */
2337 spr_register(env, SPR_40x_IAC1, "IAC1",
2338 SPR_NOACCESS, SPR_NOACCESS,
2339 &spr_read_generic, &spr_write_generic,
2340 0x00000000);
2341 /* XXX : not implemented */
2342 spr_register(env, SPR_40x_IAC2, "IAC2",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 }
2347
2348 static void gen_spr_403_real(CPUPPCState *env)
2349 {
2350 spr_register(env, SPR_403_PBL1, "PBL1",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_403_pbr, &spr_write_403_pbr,
2353 0x00000000);
2354 spr_register(env, SPR_403_PBU1, "PBU1",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_403_pbr, &spr_write_403_pbr,
2357 0x00000000);
2358 spr_register(env, SPR_403_PBL2, "PBL2",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_403_pbr, &spr_write_403_pbr,
2361 0x00000000);
2362 spr_register(env, SPR_403_PBU2, "PBU2",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_403_pbr, &spr_write_403_pbr,
2365 0x00000000);
2366 }
2367
2368 static void gen_spr_403_mmu(CPUPPCState *env)
2369 {
2370 /* MMU */
2371 spr_register(env, SPR_40x_PID, "PID",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 spr_register(env, SPR_40x_ZPR, "ZPR",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379 }
2380
2381 /* SPR specific to PowerPC compression coprocessor extension */
2382 static void gen_spr_compress(CPUPPCState *env)
2383 {
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_401_SKR, "SKR",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2388 0x00000000);
2389 }
2390
2391 static void gen_spr_5xx_8xx(CPUPPCState *env)
2392 {
2393 /* Exception processing */
2394 spr_register_kvm(env, SPR_DSISR, "DSISR",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 KVM_REG_PPC_DSISR, 0x00000000);
2398 spr_register_kvm(env, SPR_DAR, "DAR",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 KVM_REG_PPC_DAR, 0x00000000);
2402 /* Timer */
2403 spr_register(env, SPR_DECR, "DECR",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_decr, &spr_write_decr,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_EIE, "EIE",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_EID, "EID",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_MPC_NRI, "NRI",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_CMPA, "CMPA",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_MPC_CMPB, "CMPB",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_MPC_CMPC, "CMPC",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_MPC_CMPD, "CMPD",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_MPC_ECR, "ECR",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_DER, "DER",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_CMPE, "CMPE",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_CMPF, "CMPF",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_CMPG, "CMPG",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_CMPH, "CMPH",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_BAR, "BAR",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_DPDR, "DPDR",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_IMMR, "IMMR",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 }
2508
2509 static void gen_spr_5xx(CPUPPCState *env)
2510 {
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 /* XXX : not implemented */
2577 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2578 SPR_NOACCESS, SPR_NOACCESS,
2579 &spr_read_generic, &spr_write_generic,
2580 0x00000000);
2581 /* XXX : not implemented */
2582 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2583 SPR_NOACCESS, SPR_NOACCESS,
2584 &spr_read_generic, &spr_write_generic,
2585 0x00000000);
2586 /* XXX : not implemented */
2587 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2588 SPR_NOACCESS, SPR_NOACCESS,
2589 &spr_read_generic, &spr_write_generic,
2590 0x00000000);
2591 /* XXX : not implemented */
2592 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2593 SPR_NOACCESS, SPR_NOACCESS,
2594 &spr_read_generic, &spr_write_generic,
2595 0x00000000);
2596 /* XXX : not implemented */
2597 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2598 SPR_NOACCESS, SPR_NOACCESS,
2599 &spr_read_generic, &spr_write_generic,
2600 0x00000000);
2601 /* XXX : not implemented */
2602 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2603 SPR_NOACCESS, SPR_NOACCESS,
2604 &spr_read_generic, &spr_write_generic,
2605 0x00000000);
2606 /* XXX : not implemented */
2607 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2608 SPR_NOACCESS, SPR_NOACCESS,
2609 &spr_read_generic, &spr_write_generic,
2610 0x00000000);
2611 /* XXX : not implemented */
2612 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2613 SPR_NOACCESS, SPR_NOACCESS,
2614 &spr_read_generic, &spr_write_generic,
2615 0x00000000);
2616 }
2617
2618 static void gen_spr_8xx(CPUPPCState *env)
2619 {
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 /* XXX : not implemented */
2641 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645 /* XXX : not implemented */
2646 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 /* XXX : not implemented */
2651 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
2655 /* XXX : not implemented */
2656 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660 /* XXX : not implemented */
2661 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665 /* XXX : not implemented */
2666 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2667 SPR_NOACCESS, SPR_NOACCESS,
2668 &spr_read_generic, &spr_write_generic,
2669 0x00000000);
2670 /* XXX : not implemented */
2671 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2672 SPR_NOACCESS, SPR_NOACCESS,
2673 &spr_read_generic, &spr_write_generic,
2674 0x00000000);
2675 /* XXX : not implemented */
2676 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2677 SPR_NOACCESS, SPR_NOACCESS,
2678 &spr_read_generic, &spr_write_generic,
2679 0x00000000);
2680 /* XXX : not implemented */
2681 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2682 SPR_NOACCESS, SPR_NOACCESS,
2683 &spr_read_generic, &spr_write_generic,
2684 0x00000000);
2685 /* XXX : not implemented */
2686 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2687 SPR_NOACCESS, SPR_NOACCESS,
2688 &spr_read_generic, &spr_write_generic,
2689 0x00000000);
2690 /* XXX : not implemented */
2691 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2692 SPR_NOACCESS, SPR_NOACCESS,
2693 &spr_read_generic, &spr_write_generic,
2694 0x00000000);
2695 /* XXX : not implemented */
2696 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2697 SPR_NOACCESS, SPR_NOACCESS,
2698 &spr_read_generic, &spr_write_generic,
2699 0x00000000);
2700 /* XXX : not implemented */
2701 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2702 SPR_NOACCESS, SPR_NOACCESS,
2703 &spr_read_generic, &spr_write_generic,
2704 0x00000000);
2705 /* XXX : not implemented */
2706 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2707 SPR_NOACCESS, SPR_NOACCESS,
2708 &spr_read_generic, &spr_write_generic,
2709 0x00000000);
2710 /* XXX : not implemented */
2711 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2712 SPR_NOACCESS, SPR_NOACCESS,
2713 &spr_read_generic, &spr_write_generic,
2714 0x00000000);
2715 /* XXX : not implemented */
2716 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2717 SPR_NOACCESS, SPR_NOACCESS,
2718 &spr_read_generic, &spr_write_generic,
2719 0x00000000);
2720 /* XXX : not implemented */
2721 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2722 SPR_NOACCESS, SPR_NOACCESS,
2723 &spr_read_generic, &spr_write_generic,
2724 0x00000000);
2725 /* XXX : not implemented */
2726 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2727 SPR_NOACCESS, SPR_NOACCESS,
2728 &spr_read_generic, &spr_write_generic,
2729 0x00000000);
2730 /* XXX : not implemented */
2731 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2732 SPR_NOACCESS, SPR_NOACCESS,
2733 &spr_read_generic, &spr_write_generic,
2734 0x00000000);
2735 /* XXX : not implemented */
2736 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2737 SPR_NOACCESS, SPR_NOACCESS,
2738 &spr_read_generic, &spr_write_generic,
2739 0x00000000);
2740 /* XXX : not implemented */
2741 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2742 SPR_NOACCESS, SPR_NOACCESS,
2743 &spr_read_generic, &spr_write_generic,
2744 0x00000000);
2745 }
2746
2747 // XXX: TODO
2748 /*
2749 * AMR => SPR 29 (Power 2.04)
2750 * CTRL => SPR 136 (Power 2.04)
2751 * CTRL => SPR 152 (Power 2.04)
2752 * SCOMC => SPR 276 (64 bits ?)
2753 * SCOMD => SPR 277 (64 bits ?)
2754 * TBU40 => SPR 286 (Power 2.04 hypv)
2755 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2756 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2757 * HDSISR => SPR 306 (Power 2.04 hypv)
2758 * HDAR => SPR 307 (Power 2.04 hypv)
2759 * PURR => SPR 309 (Power 2.04 hypv)
2760 * HDEC => SPR 310 (Power 2.04 hypv)
2761 * HIOR => SPR 311 (hypv)
2762 * RMOR => SPR 312 (970)
2763 * HRMOR => SPR 313 (Power 2.04 hypv)
2764 * HSRR0 => SPR 314 (Power 2.04 hypv)
2765 * HSRR1 => SPR 315 (Power 2.04 hypv)
2766 * LPIDR => SPR 317 (970)
2767 * EPR => SPR 702 (Power 2.04 emb)
2768 * perf => 768-783 (Power 2.04)
2769 * perf => 784-799 (Power 2.04)
2770 * PPR => SPR 896 (Power 2.04)
2771 * EPLC => SPR 947 (Power 2.04 emb)
2772 * EPSC => SPR 948 (Power 2.04 emb)
2773 * DABRX => 1015 (Power 2.04 hypv)
2774 * FPECR => SPR 1022 (?)
2775 * ... and more (thermal management, performance counters, ...)
2776 */
2777
2778 /*****************************************************************************/
2779 /* Exception vectors models */
2780 static void init_excp_4xx_real(CPUPPCState *env)
2781 {
2782 #if !defined(CONFIG_USER_ONLY)
2783 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2784 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2785 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2786 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2787 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2788 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2789 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2790 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2791 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2792 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2793 env->ivor_mask = 0x0000FFF0UL;
2794 env->ivpr_mask = 0xFFFF0000UL;
2795 /* Hardware reset vector */
2796 env->hreset_vector = 0xFFFFFFFCUL;
2797 #endif
2798 }
2799
2800 static void init_excp_4xx_softmmu(CPUPPCState *env)
2801 {
2802 #if !defined(CONFIG_USER_ONLY)
2803 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2804 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2805 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2806 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2807 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2808 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2809 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2810 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2811 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2812 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2813 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2814 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2815 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2816 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2817 env->ivor_mask = 0x0000FFF0UL;
2818 env->ivpr_mask = 0xFFFF0000UL;
2819 /* Hardware reset vector */
2820 env->hreset_vector = 0xFFFFFFFCUL;
2821 #endif
2822 }
2823
2824 static void init_excp_MPC5xx(CPUPPCState *env)
2825 {
2826 #if !defined(CONFIG_USER_ONLY)
2827 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2828 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2829 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2830 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2831 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2832 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2833 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2834 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2835 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2836 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2837 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2838 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2839 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2840 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2841 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2842 env->ivor_mask = 0x0000FFF0UL;
2843 env->ivpr_mask = 0xFFFF0000UL;
2844 /* Hardware reset vector */
2845 env->hreset_vector = 0x00000100UL;
2846 #endif
2847 }
2848
2849 static void init_excp_MPC8xx(CPUPPCState *env)
2850 {
2851 #if !defined(CONFIG_USER_ONLY)
2852 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2853 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2854 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2855 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2856 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2857 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2858 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2859 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2860 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2861 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2862 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2863 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2864 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2865 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2866 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2867 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2868 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2869 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2870 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2871 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2872 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2873 env->ivor_mask = 0x0000FFF0UL;
2874 env->ivpr_mask = 0xFFFF0000UL;
2875 /* Hardware reset vector */
2876 env->hreset_vector = 0x00000100UL;
2877 #endif
2878 }
2879
2880 static void init_excp_G2(CPUPPCState *env)
2881 {
2882 #if !defined(CONFIG_USER_ONLY)
2883 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2884 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2885 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2886 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2887 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2888 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2889 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2890 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2891 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2892 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2893 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2894 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2895 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2896 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2897 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2898 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2899 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2900 /* Hardware reset vector */
2901 env->hreset_vector = 0x00000100UL;
2902 #endif
2903 }
2904
2905 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2906 {
2907 #if !defined(CONFIG_USER_ONLY)
2908 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2909 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2910 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2911 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2912 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2913 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2914 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2915 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2916 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2917 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2918 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2919 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2920 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2921 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2922 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2923 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2924 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2925 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2926 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2927 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2928 env->ivor_mask = 0x0000FFF7UL;
2929 env->ivpr_mask = ivpr_mask;
2930 /* Hardware reset vector */
2931 env->hreset_vector = 0xFFFFFFFCUL;
2932 #endif
2933 }
2934
2935 static void init_excp_BookE(CPUPPCState *env)
2936 {
2937 #if !defined(CONFIG_USER_ONLY)
2938 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2939 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2940 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2941 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2942 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2943 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2944 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2945 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2946 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2947 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2948 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2949 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2950 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2951 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2952 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2953 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2954 env->ivor_mask = 0x0000FFF0UL;
2955 env->ivpr_mask = 0xFFFF0000UL;
2956 /* Hardware reset vector */
2957 env->hreset_vector = 0xFFFFFFFCUL;
2958 #endif
2959 }
2960
2961 static void init_excp_601(CPUPPCState *env)
2962 {
2963 #if !defined(CONFIG_USER_ONLY)
2964 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2965 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2966 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2967 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2968 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2969 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2970 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2971 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2972 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2973 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2974 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2975 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2976 /* Hardware reset vector */
2977 env->hreset_vector = 0x00000100UL;
2978 #endif
2979 }
2980
2981 static void init_excp_602(CPUPPCState *env)
2982 {
2983 #if !defined(CONFIG_USER_ONLY)
2984 /* XXX: exception prefix has a special behavior on 602 */
2985 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2986 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2987 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2988 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2989 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2990 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2991 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2992 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2993 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2994 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2995 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2996 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2997 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2998 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2999 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3000 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3001 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
3002 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
3003 /* Hardware reset vector */
3004 env->hreset_vector = 0x00000100UL;
3005 #endif
3006 }
3007
3008 static void init_excp_603(CPUPPCState *env)
3009 {
3010 #if !defined(CONFIG_USER_ONLY)
3011 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3012 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3013 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3014 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3015 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3016 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3017 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3018 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3019 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3020 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3021 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3022 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3023 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3024 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3025 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3026 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3027 /* Hardware reset vector */
3028 env->hreset_vector = 0x00000100UL;
3029 #endif
3030 }
3031
3032 static void init_excp_604(CPUPPCState *env)
3033 {
3034 #if !defined(CONFIG_USER_ONLY)
3035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3038 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3039 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3040 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3041 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3042 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3043 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3044 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3045 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3046 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3047 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3048 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3049 /* Hardware reset vector */
3050 env->hreset_vector = 0x00000100UL;
3051 #endif
3052 }
3053
3054 static void init_excp_7x0(CPUPPCState *env)
3055 {
3056 #if !defined(CONFIG_USER_ONLY)
3057 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3058 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3059 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3060 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3061 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3062 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3063 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3064 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3065 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3066 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3067 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3068 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3069 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3070 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3071 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3072 /* Hardware reset vector */
3073 env->hreset_vector = 0x00000100UL;
3074 #endif
3075 }
3076
3077 static void init_excp_750cl(CPUPPCState *env)
3078 {
3079 #if !defined(CONFIG_USER_ONLY)
3080 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3081 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3082 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3083 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3084 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3085 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3086 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3087 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3088 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3089 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3090 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3091 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3092 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3093 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3094 /* Hardware reset vector */
3095 env->hreset_vector = 0x00000100UL;
3096 #endif
3097 }
3098
3099 static void init_excp_750cx(CPUPPCState *env)
3100 {
3101 #if !defined(CONFIG_USER_ONLY)
3102 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3103 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3104 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3105 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3106 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3107 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3108 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3109 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3110 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3111 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3112 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3113 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3114 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3115 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3116 /* Hardware reset vector */
3117 env->hreset_vector = 0x00000100UL;
3118 #endif
3119 }
3120
3121 /* XXX: Check if this is correct */
3122 static void init_excp_7x5(CPUPPCState *env)
3123 {
3124 #if !defined(CONFIG_USER_ONLY)
3125 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3126 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3127 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3128 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3129 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3130 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3131 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3132 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3133 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3134 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3135 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3136 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3137 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3138 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3139 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3140 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3141 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3142 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3143 /* Hardware reset vector */
3144 env->hreset_vector = 0x00000100UL;
3145 #endif
3146 }
3147
3148 static void init_excp_7400(CPUPPCState *env)
3149 {
3150 #if !defined(CONFIG_USER_ONLY)
3151 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3152 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3153 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3154 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3155 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3156 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3157 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3158 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3159 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3160 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3161 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3162 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3163 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3164 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3165 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3166 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3167 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3168 /* Hardware reset vector */
3169 env->hreset_vector = 0x00000100UL;
3170 #endif
3171 }
3172
3173 static void init_excp_7450(CPUPPCState *env)
3174 {
3175 #if !defined(CONFIG_USER_ONLY)
3176 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3177 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3178 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3179 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3180 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3181 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3182 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3183 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3184 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3185 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3186 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3187 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3188 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3189 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3190 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3191 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3192 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3193 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3194 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3195 /* Hardware reset vector */
3196 env->hreset_vector = 0x00000100UL;
3197 #endif
3198 }
3199
3200 #if defined(TARGET_PPC64)
3201 static void init_excp_970(CPUPPCState *env)
3202 {
3203 #if !defined(CONFIG_USER_ONLY)
3204 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3205 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3206 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3207 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3208 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3209 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3210 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3211 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3212 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3213 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3214 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3215 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3216 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3217 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3218 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3219 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3220 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3221 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3222 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3223 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3224 /* Hardware reset vector */
3225 env->hreset_vector = 0x0000000000000100ULL;
3226 #endif
3227 }
3228
3229 static void init_excp_POWER7(CPUPPCState *env)
3230 {
3231 #if !defined(CONFIG_USER_ONLY)
3232 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3233 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3234 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3235 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3236 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3237 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3238 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3239 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3240 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3241 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3242 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3243 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3244 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3245 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3246 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
3247 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
3248 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
3249 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
3250 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3251 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3252 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3253 /* Hardware reset vector */
3254 env->hreset_vector = 0x0000000000000100ULL;
3255 #endif
3256 }
3257
3258 static void init_excp_POWER8(CPUPPCState *env)
3259 {
3260 init_excp_POWER7(env);
3261
3262 #if !defined(CONFIG_USER_ONLY)
3263 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
3264 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3265 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
3266 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3267 #endif
3268 }
3269
3270 #endif
3271
3272 /*****************************************************************************/
3273 /* Power management enable checks */
3274 static int check_pow_none(CPUPPCState *env)
3275 {
3276 return 0;
3277 }
3278
3279 static int check_pow_nocheck(CPUPPCState *env)
3280 {
3281 return 1;
3282 }
3283
3284 static int check_pow_hid0(CPUPPCState *env)
3285 {
3286 if (env->spr[SPR_HID0] & 0x00E00000)
3287 return 1;
3288
3289 return 0;
3290 }
3291
3292 static int check_pow_hid0_74xx(CPUPPCState *env)
3293 {
3294 if (env->spr[SPR_HID0] & 0x00600000)
3295 return 1;
3296
3297 return 0;
3298 }
3299
3300 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3301 {
3302 return true;
3303 }
3304
3305 #ifdef TARGET_PPC64
3306 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3307 {
3308 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3309 }
3310 #endif
3311
3312 /*****************************************************************************/
3313 /* PowerPC implementations definitions */
3314
3315 #define POWERPC_FAMILY(_name) \
3316 static void \
3317 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3318 \
3319 static const TypeInfo \
3320 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3321 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3322 .parent = TYPE_POWERPC_CPU, \
3323 .abstract = true, \
3324 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3325 }; \
3326 \
3327 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3328 { \
3329 type_register_static( \
3330 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3331 } \
3332 \
3333 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3334 \
3335 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3336
3337 static void init_proc_401(CPUPPCState *env)
3338 {
3339 gen_spr_40x(env);
3340 gen_spr_401_403(env);
3341 gen_spr_401(env);
3342 init_excp_4xx_real(env);
3343 env->dcache_line_size = 32;
3344 env->icache_line_size = 32;
3345 /* Allocate hardware IRQ controller */
3346 ppc40x_irq_init(ppc_env_get_cpu(env));
3347
3348 SET_FIT_PERIOD(12, 16, 20, 24);
3349 SET_WDT_PERIOD(16, 20, 24, 28);
3350 }
3351
3352 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3353 {
3354 DeviceClass *dc = DEVICE_CLASS(oc);
3355 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3356
3357 dc->desc = "PowerPC 401";
3358 pcc->init_proc = init_proc_401;
3359 pcc->check_pow = check_pow_nocheck;
3360 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3361 PPC_WRTEE | PPC_DCR |
3362 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3363 PPC_CACHE_DCBZ |
3364 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3365 PPC_4xx_COMMON | PPC_40x_EXCP;
3366 pcc->msr_mask = (1ull << MSR_KEY) |
3367 (1ull << MSR_POW) |
3368 (1ull << MSR_CE) |
3369 (1ull << MSR_ILE) |
3370 (1ull << MSR_EE) |
3371 (1ull << MSR_PR) |
3372 (1ull << MSR_ME) |
3373 (1ull << MSR_DE) |
3374 (1ull << MSR_LE);
3375 pcc->mmu_model = POWERPC_MMU_REAL;
3376 pcc->excp_model = POWERPC_EXCP_40x;
3377 pcc->bus_model = PPC_FLAGS_INPUT_401;
3378 pcc->bfd_mach = bfd_mach_ppc_403;
3379 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3380 POWERPC_FLAG_BUS_CLK;
3381 }
3382
3383 static void init_proc_401x2(CPUPPCState *env)
3384 {
3385 gen_spr_40x(env);
3386 gen_spr_401_403(env);
3387 gen_spr_401x2(env);
3388 gen_spr_compress(env);
3389 /* Memory management */
3390 #if !defined(CONFIG_USER_ONLY)
3391 env->nb_tlb = 64;
3392 env->nb_ways = 1;
3393 env->id_tlbs = 0;
3394 env->tlb_type = TLB_EMB;
3395 #endif
3396 init_excp_4xx_softmmu(env);
3397 env->dcache_line_size = 32;
3398 env->icache_line_size = 32;
3399 /* Allocate hardware IRQ controller */
3400 ppc40x_irq_init(ppc_env_get_cpu(env));
3401
3402 SET_FIT_PERIOD(12, 16, 20, 24);
3403 SET_WDT_PERIOD(16, 20, 24, 28);
3404 }
3405
3406 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3407 {
3408 DeviceClass *dc = DEVICE_CLASS(oc);
3409 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3410
3411 dc->desc = "PowerPC 401x2";
3412 pcc->init_proc = init_proc_401x2;
3413 pcc->check_pow = check_pow_nocheck;
3414 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3415 PPC_DCR | PPC_WRTEE |
3416 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3417 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3418 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3419 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3420 PPC_4xx_COMMON | PPC_40x_EXCP;
3421 pcc->msr_mask = (1ull << 20) |
3422 (1ull << MSR_KEY) |
3423 (1ull << MSR_POW) |
3424 (1ull << MSR_CE) |
3425 (1ull << MSR_ILE) |
3426 (1ull << MSR_EE) |
3427 (1ull << MSR_PR) |
3428 (1ull << MSR_ME) |
3429 (1ull << MSR_DE) |
3430 (1ull << MSR_IR) |
3431 (1ull << MSR_DR) |
3432 (1ull << MSR_LE);
3433 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3434 pcc->excp_model = POWERPC_EXCP_40x;
3435 pcc->bus_model = PPC_FLAGS_INPUT_401;
3436 pcc->bfd_mach = bfd_mach_ppc_403;
3437 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3438 POWERPC_FLAG_BUS_CLK;
3439 }
3440
3441 static void init_proc_401x3(CPUPPCState *env)
3442 {
3443 gen_spr_40x(env);
3444 gen_spr_401_403(env);
3445 gen_spr_401(env);
3446 gen_spr_401x2(env);
3447 gen_spr_compress(env);
3448 init_excp_4xx_softmmu(env);
3449 env->dcache_line_size = 32;
3450 env->icache_line_size = 32;
3451 /* Allocate hardware IRQ controller */
3452 ppc40x_irq_init(ppc_env_get_cpu(env));
3453
3454 SET_FIT_PERIOD(12, 16, 20, 24);
3455 SET_WDT_PERIOD(16, 20, 24, 28);
3456 }
3457
3458 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3459 {
3460 DeviceClass *dc = DEVICE_CLASS(oc);
3461 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3462
3463 dc->desc = "PowerPC 401x3";
3464 pcc->init_proc = init_proc_401x3;
3465 pcc->check_pow = check_pow_nocheck;
3466 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3467 PPC_DCR | PPC_WRTEE |
3468 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3469 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3470 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3471 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3472 PPC_4xx_COMMON | PPC_40x_EXCP;
3473 pcc->msr_mask = (1ull << 20) |
3474 (1ull << MSR_KEY) |
3475 (1ull << MSR_POW) |
3476 (1ull << MSR_CE) |
3477 (1ull << MSR_ILE) |
3478 (1ull << MSR_EE) |
3479 (1ull << MSR_PR) |
3480 (1ull << MSR_ME) |
3481 (1ull << MSR_DWE) |
3482 (1ull << MSR_DE) |
3483 (1ull << MSR_IR) |
3484 (1ull << MSR_DR) |
3485 (1ull << MSR_LE);
3486 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3487 pcc->excp_model = POWERPC_EXCP_40x;
3488 pcc->bus_model = PPC_FLAGS_INPUT_401;
3489 pcc->bfd_mach = bfd_mach_ppc_403;
3490 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3491 POWERPC_FLAG_BUS_CLK;
3492 }
3493
3494 static void init_proc_IOP480(CPUPPCState *env)
3495 {
3496 gen_spr_40x(env);
3497 gen_spr_401_403(env);
3498 gen_spr_401x2(env);
3499 gen_spr_compress(env);
3500 /* Memory management */
3501 #if !defined(CONFIG_USER_ONLY)
3502 env->nb_tlb = 64;
3503 env->nb_ways = 1;
3504 env->id_tlbs = 0;
3505 env->tlb_type = TLB_EMB;
3506 #endif
3507 init_excp_4xx_softmmu(env);
3508 env->dcache_line_size = 32;
3509 env->icache_line_size = 32;
3510 /* Allocate hardware IRQ controller */
3511 ppc40x_irq_init(ppc_env_get_cpu(env));
3512
3513 SET_FIT_PERIOD(8, 12, 16, 20);
3514 SET_WDT_PERIOD(16, 20, 24, 28);
3515 }
3516
3517 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3518 {
3519 DeviceClass *dc = DEVICE_CLASS(oc);
3520 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3521
3522 dc->desc = "IOP480";
3523 pcc->init_proc = init_proc_IOP480;
3524 pcc->check_pow = check_pow_nocheck;
3525 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3526 PPC_DCR | PPC_WRTEE |
3527 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3528 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3529 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3530 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3531 PPC_4xx_COMMON | PPC_40x_EXCP;
3532 pcc->msr_mask = (1ull << 20) |
3533 (1ull << MSR_KEY) |
3534 (1ull << MSR_POW) |
3535 (1ull << MSR_CE) |
3536 (1ull << MSR_ILE) |
3537 (1ull << MSR_EE) |
3538 (1ull << MSR_PR) |
3539 (1ull << MSR_ME) |
3540 (1ull << MSR_DE) |
3541 (1ull << MSR_IR) |
3542 (1ull << MSR_DR) |
3543 (1ull << MSR_LE);
3544 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3545 pcc->excp_model = POWERPC_EXCP_40x;
3546 pcc->bus_model = PPC_FLAGS_INPUT_401;
3547 pcc->bfd_mach = bfd_mach_ppc_403;
3548 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3549 POWERPC_FLAG_BUS_CLK;
3550 }
3551
3552 static void init_proc_403(CPUPPCState *env)
3553 {
3554 gen_spr_40x(env);
3555 gen_spr_401_403(env);
3556 gen_spr_403(env);
3557 gen_spr_403_real(env);
3558 init_excp_4xx_real(env);
3559 env->dcache_line_size = 32;
3560 env->icache_line_size = 32;
3561 /* Allocate hardware IRQ controller */
3562 ppc40x_irq_init(ppc_env_get_cpu(env));
3563
3564 SET_FIT_PERIOD(8, 12, 16, 20);
3565 SET_WDT_PERIOD(16, 20, 24, 28);
3566 }
3567
3568 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3569 {
3570 DeviceClass *dc = DEVICE_CLASS(oc);
3571 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3572
3573 dc->desc = "PowerPC 403";
3574 pcc->init_proc = init_proc_403;
3575 pcc->check_pow = check_pow_nocheck;
3576 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3577 PPC_DCR | PPC_WRTEE |
3578 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3579 PPC_CACHE_DCBZ |
3580 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3581 PPC_4xx_COMMON | PPC_40x_EXCP;
3582 pcc->msr_mask = (1ull << MSR_POW) |
3583 (1ull << MSR_CE) |
3584 (1ull << MSR_ILE) |
3585 (1ull << MSR_EE) |
3586 (1ull << MSR_PR) |
3587 (1ull << MSR_ME) |
3588 (1ull << MSR_PE) |
3589 (1ull << MSR_PX) |
3590 (1ull << MSR_LE);
3591 pcc->mmu_model = POWERPC_MMU_REAL;
3592 pcc->excp_model = POWERPC_EXCP_40x;
3593 pcc->bus_model = PPC_FLAGS_INPUT_401;
3594 pcc->bfd_mach = bfd_mach_ppc_403;
3595 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3596 POWERPC_FLAG_BUS_CLK;
3597 }
3598
3599 static void init_proc_403GCX(CPUPPCState *env)
3600 {
3601 gen_spr_40x(env);
3602 gen_spr_401_403(env);
3603 gen_spr_403(env);
3604 gen_spr_403_real(env);
3605 gen_spr_403_mmu(env);
3606 /* Bus access control */
3607 /* not emulated, as QEMU never does speculative access */
3608 spr_register(env, SPR_40x_SGR, "SGR",
3609 SPR_NOACCESS, SPR_NOACCESS,
3610 &spr_read_generic, &spr_write_generic,
3611 0xFFFFFFFF);
3612 /* not emulated, as QEMU do not emulate caches */
3613 spr_register(env, SPR_40x_DCWR, "DCWR",
3614 SPR_NOACCESS, SPR_NOACCESS,
3615 &spr_read_generic, &spr_write_generic,
3616 0x00000000);
3617 /* Memory management */
3618 #if !defined(CONFIG_USER_ONLY)
3619 env->nb_tlb = 64;
3620 env->nb_ways = 1;
3621 env->id_tlbs = 0;
3622 env->tlb_type = TLB_EMB;
3623 #endif
3624 init_excp_4xx_softmmu(env);
3625 env->dcache_line_size = 32;
3626 env->icache_line_size = 32;
3627 /* Allocate hardware IRQ controller */
3628 ppc40x_irq_init(ppc_env_get_cpu(env));
3629
3630 SET_FIT_PERIOD(8, 12, 16, 20);
3631 SET_WDT_PERIOD(16, 20, 24, 28);
3632 }
3633
3634 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3635 {
3636 DeviceClass *dc = DEVICE_CLASS(oc);
3637 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3638
3639 dc->desc = "PowerPC 403 GCX";
3640 pcc->init_proc = init_proc_403GCX;
3641 pcc->check_pow = check_pow_nocheck;
3642 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3643 PPC_DCR | PPC_WRTEE |
3644 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3645 PPC_CACHE_DCBZ |
3646 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3647 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3648 PPC_4xx_COMMON | PPC_40x_EXCP;
3649 pcc->msr_mask = (1ull << MSR_POW) |
3650 (1ull << MSR_CE) |
3651 (1ull << MSR_ILE) |
3652 (1ull << MSR_EE) |
3653 (1ull << MSR_PR) |
3654 (1ull << MSR_ME) |
3655 (1ull << MSR_PE) |
3656 (1ull << MSR_PX) |
3657 (1ull << MSR_LE);
3658 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3659 pcc->excp_model = POWERPC_EXCP_40x;
3660 pcc->bus_model = PPC_FLAGS_INPUT_401;
3661 pcc->bfd_mach = bfd_mach_ppc_403;
3662 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3663 POWERPC_FLAG_BUS_CLK;
3664 }
3665
3666 static void init_proc_405(CPUPPCState *env)
3667 {
3668 /* Time base */
3669 gen_tbl(env);
3670 gen_spr_40x(env);
3671 gen_spr_405(env);
3672 /* Bus access control */
3673 /* not emulated, as QEMU never does speculative access */
3674 spr_register(env, SPR_40x_SGR, "SGR",
3675 SPR_NOACCESS, SPR_NOACCESS,
3676 &spr_read_generic, &spr_write_generic,
3677 0xFFFFFFFF);
3678 /* not emulated, as QEMU do not emulate caches */
3679 spr_register(env, SPR_40x_DCWR, "DCWR",
3680 SPR_NOACCESS, SPR_NOACCESS,
3681 &spr_read_generic, &spr_write_generic,
3682 0x00000000);
3683 /* Memory management */
3684 #if !defined(CONFIG_USER_ONLY)
3685 env->nb_tlb = 64;
3686 env->nb_ways = 1;
3687 env->id_tlbs = 0;
3688 env->tlb_type = TLB_EMB;
3689 #endif
3690 init_excp_4xx_softmmu(env);
3691 env->dcache_line_size = 32;
3692 env->icache_line_size = 32;
3693 /* Allocate hardware IRQ controller */
3694 ppc40x_irq_init(ppc_env_get_cpu(env));
3695
3696 SET_FIT_PERIOD(8, 12, 16, 20);
3697 SET_WDT_PERIOD(16, 20, 24, 28);
3698 }
3699
3700 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3701 {
3702 DeviceClass *dc = DEVICE_CLASS(oc);
3703 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3704
3705 dc->desc = "PowerPC 405";
3706 pcc->init_proc = init_proc_405;
3707 pcc->check_pow = check_pow_nocheck;
3708 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3709 PPC_DCR | PPC_WRTEE |
3710 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3711 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3712 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3713 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3714 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3715 pcc->msr_mask = (1ull << MSR_POW) |
3716 (1ull << MSR_CE) |
3717 (1ull << MSR_EE) |
3718 (1ull << MSR_PR) |
3719 (1ull << MSR_FP) |
3720 (1ull << MSR_DWE) |
3721 (1ull << MSR_DE) |
3722 (1ull << MSR_IR) |
3723 (1ull << MSR_DR);
3724 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3725 pcc->excp_model = POWERPC_EXCP_40x;
3726 pcc->bus_model = PPC_FLAGS_INPUT_405;
3727 pcc->bfd_mach = bfd_mach_ppc_403;
3728 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3729 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3730 }
3731
3732 static void init_proc_440EP(CPUPPCState *env)
3733 {
3734 /* Time base */
3735 gen_tbl(env);
3736 gen_spr_BookE(env, 0x000000000000FFFFULL);
3737 gen_spr_440(env);
3738 gen_spr_usprgh(env);
3739 /* Processor identification */
3740 spr_register(env, SPR_BOOKE_PIR, "PIR",
3741 SPR_NOACCESS, SPR_NOACCESS,
3742 &spr_read_generic, &spr_write_pir,
3743 0x00000000);
3744 /* XXX : not implemented */
3745 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3746 SPR_NOACCESS, SPR_NOACCESS,
3747 &spr_read_generic, &spr_write_generic,
3748 0x00000000);
3749 /* XXX : not implemented */
3750 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3751 SPR_NOACCESS, SPR_NOACCESS,
3752 &spr_read_generic, &spr_write_generic,
3753 0x00000000);
3754 /* XXX : not implemented */
3755 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3756 SPR_NOACCESS, SPR_NOACCESS,
3757 &spr_read_generic, &spr_write_generic,
3758 0x00000000);
3759 /* XXX : not implemented */
3760 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3761 SPR_NOACCESS, SPR_NOACCESS,
3762 &spr_read_generic, &spr_write_generic,
3763 0x00000000);
3764 /* XXX : not implemented */
3765 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3766 SPR_NOACCESS, SPR_NOACCESS,
3767 &spr_read_generic, &spr_write_generic,
3768 0x00000000);
3769 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3770 SPR_NOACCESS, SPR_NOACCESS,
3771 &spr_read_generic, &spr_write_generic,
3772 0x00000000);
3773 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3774 SPR_NOACCESS, SPR_NOACCESS,
3775 &spr_read_generic, &spr_write_generic,
3776 0x00000000);
3777 /* XXX : not implemented */
3778 spr_register(env, SPR_440_CCR1, "CCR1",
3779 SPR_NOACCESS, SPR_NOACCESS,
3780 &spr_read_generic, &spr_write_generic,
3781 0x00000000);
3782 /* Memory management */
3783 #if !defined(CONFIG_USER_ONLY)
3784 env->nb_tlb = 64;
3785 env->nb_ways = 1;
3786 env->id_tlbs = 0;
3787 env->tlb_type = TLB_EMB;
3788 #endif
3789 init_excp_BookE(env);
3790 env->dcache_line_size = 32;
3791 env->icache_line_size = 32;
3792 ppc40x_irq_init(ppc_env_get_cpu(env));
3793
3794 SET_FIT_PERIOD(12, 16, 20, 24);
3795 SET_WDT_PERIOD(20, 24, 28, 32);
3796 }
3797
3798 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3799 {
3800 DeviceClass *dc = DEVICE_CLASS(oc);
3801 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3802
3803 dc->desc = "PowerPC 440 EP";
3804 pcc->init_proc = init_proc_440EP;
3805 pcc->check_pow = check_pow_nocheck;
3806 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3807 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3808 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3809 PPC_FLOAT_STFIWX |
3810 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3811 PPC_CACHE | PPC_CACHE_ICBI |
3812 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3813 PPC_MEM_TLBSYNC | PPC_MFTB |
3814 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3815 PPC_440_SPEC;
3816 pcc->msr_mask = (1ull << MSR_POW) |
3817 (1ull << MSR_CE) |
3818 (1ull << MSR_EE) |
3819 (1ull << MSR_PR) |
3820 (1ull << MSR_FP) |
3821 (1ull << MSR_ME) |
3822 (1ull << MSR_FE0) |
3823 (1ull << MSR_DWE) |
3824 (1ull << MSR_DE) |
3825 (1ull << MSR_FE1) |
3826 (1ull << MSR_IR) |
3827 (1ull << MSR_DR);
3828 pcc->mmu_model = POWERPC_MMU_BOOKE;
3829 pcc->excp_model = POWERPC_EXCP_BOOKE;
3830 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3831 pcc->bfd_mach = bfd_mach_ppc_403;
3832 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3833 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3834 }
3835
3836 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
3837 {
3838 DeviceClass *dc = DEVICE_CLASS(oc);
3839 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3840
3841 dc->desc = "PowerPC 460 EX";
3842 pcc->init_proc = init_proc_440EP;
3843 pcc->check_pow = check_pow_nocheck;
3844 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3845 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3846 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3847 PPC_FLOAT_STFIWX |
3848 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
3849 PPC_CACHE | PPC_CACHE_ICBI |
3850 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3851 PPC_MEM_TLBSYNC | PPC_MFTB |
3852 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3853 PPC_440_SPEC;
3854 pcc->msr_mask = (1ull << MSR_POW) |
3855 (1ull << MSR_CE) |
3856 (1ull << MSR_EE) |
3857 (1ull << MSR_PR) |
3858 (1ull << MSR_FP) |
3859 (1ull << MSR_ME) |
3860 (1ull << MSR_FE0) |
3861 (1ull << MSR_DWE) |
3862 (1ull << MSR_DE) |
3863 (1ull << MSR_FE1) |
3864 (1ull << MSR_IR) |
3865 (1ull << MSR_DR);
3866 pcc->mmu_model = POWERPC_MMU_BOOKE;
3867 pcc->excp_model = POWERPC_EXCP_BOOKE;
3868 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3869 pcc->bfd_mach = bfd_mach_ppc_403;
3870 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3871 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3872 }
3873
3874 static void init_proc_440GP(CPUPPCState *env)
3875 {
3876 /* Time base */
3877 gen_tbl(env);
3878 gen_spr_BookE(env, 0x000000000000FFFFULL);
3879 gen_spr_440(env);
3880 gen_spr_usprgh(env);
3881 /* Processor identification */
3882 spr_register(env, SPR_BOOKE_PIR, "PIR",
3883 SPR_NOACCESS, SPR_NOACCESS,
3884 &spr_read_generic, &spr_write_pir,
3885 0x00000000);
3886 /* XXX : not implemented */
3887 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3888 SPR_NOACCESS, SPR_NOACCESS,
3889 &spr_read_generic, &spr_write_generic,
3890 0x00000000);
3891 /* XXX : not implemented */
3892 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3893 SPR_NOACCESS, SPR_NOACCESS,
3894 &spr_read_generic, &spr_write_generic,
3895 0x00000000);
3896 /* XXX : not implemented */
3897 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3898 SPR_NOACCESS, SPR_NOACCESS,
3899 &spr_read_generic, &spr_write_generic,
3900 0x00000000);
3901 /* XXX : not implemented */
3902 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3903 SPR_NOACCESS, SPR_NOACCESS,
3904 &spr_read_generic, &spr_write_generic,
3905 0x00000000);
3906 /* Memory management */
3907 #if !defined(CONFIG_USER_ONLY)
3908 env->nb_tlb = 64;
3909 env->nb_ways = 1;
3910 env->id_tlbs = 0;
3911 env->tlb_type = TLB_EMB;
3912 #endif
3913 init_excp_BookE(env);
3914 env->dcache_line_size = 32;
3915 env->icache_line_size = 32;
3916 /* XXX: TODO: allocate internal IRQ controller */
3917
3918 SET_FIT_PERIOD(12, 16, 20, 24);
3919 SET_WDT_PERIOD(20, 24, 28, 32);
3920 }
3921
3922 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3923 {
3924 DeviceClass *dc = DEVICE_CLASS(oc);
3925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3926
3927 dc->desc = "PowerPC 440 GP";
3928 pcc->init_proc = init_proc_440GP;
3929 pcc->check_pow = check_pow_nocheck;
3930 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3931 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3932 PPC_CACHE | PPC_CACHE_ICBI |
3933 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3934 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3935 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3936 PPC_440_SPEC;
3937 pcc->msr_mask = (1ull << MSR_POW) |
3938 (1ull << MSR_CE) |
3939 (1ull << MSR_EE) |
3940 (1ull << MSR_PR) |
3941 (1ull << MSR_FP) |
3942 (1ull << MSR_ME) |
3943 (1ull << MSR_FE0) |
3944 (1ull << MSR_DWE) |
3945 (1ull << MSR_DE) |
3946 (1ull << MSR_FE1) |
3947 (1ull << MSR_IR) |
3948 (1ull << MSR_DR);
3949 pcc->mmu_model = POWERPC_MMU_BOOKE;
3950 pcc->excp_model = POWERPC_EXCP_BOOKE;
3951 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3952 pcc->bfd_mach = bfd_mach_ppc_403;
3953 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3954 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3955 }
3956
3957 static void init_proc_440x4(CPUPPCState *env)
3958 {
3959 /* Time base */
3960 gen_tbl(env);
3961 gen_spr_BookE(env, 0x000000000000FFFFULL);
3962 gen_spr_440(env);
3963 gen_spr_usprgh(env);
3964 /* Processor identification */
3965 spr_register(env, SPR_BOOKE_PIR, "PIR",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, &spr_write_pir,
3968 0x00000000);
3969 /* XXX : not implemented */
3970 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 /* XXX : not implemented */
3975 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* XXX : not implemented */
3980 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3981 SPR_NOACCESS, SPR_NOACCESS,
3982 &spr_read_generic, &spr_write_generic,
3983 0x00000000);
3984 /* XXX : not implemented */
3985 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3986 SPR_NOACCESS, SPR_NOACCESS,
3987 &spr_read_generic, &spr_write_generic,
3988 0x00000000);
3989 /* Memory management */
3990 #if !defined(CONFIG_USER_ONLY)
3991 env->nb_tlb = 64;
3992 env->nb_ways = 1;
3993 env->id_tlbs = 0;
3994 env->tlb_type = TLB_EMB;
3995 #endif
3996 init_excp_BookE(env);
3997 env->dcache_line_size = 32;
3998 env->icache_line_size = 32;
3999 /* XXX: TODO: allocate internal IRQ controller */
4000
4001 SET_FIT_PERIOD(12, 16, 20, 24);
4002 SET_WDT_PERIOD(20, 24, 28, 32);
4003 }
4004
4005 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
4006 {
4007 DeviceClass *dc = DEVICE_CLASS(oc);
4008 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4009
4010 dc->desc = "PowerPC 440x4";
4011 pcc->init_proc = init_proc_440x4;
4012 pcc->check_pow = check_pow_nocheck;
4013 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4014 PPC_DCR | PPC_WRTEE |
4015 PPC_CACHE | PPC_CACHE_ICBI |
4016 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4017 PPC_MEM_TLBSYNC | PPC_MFTB |
4018 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4019 PPC_440_SPEC;
4020 pcc->msr_mask = (1ull << MSR_POW) |
4021 (1ull << MSR_CE) |
4022 (1ull << MSR_EE) |
4023 (1ull << MSR_PR) |
4024 (1ull << MSR_FP) |
4025 (1ull << MSR_ME) |
4026 (1ull << MSR_FE0) |
4027 (1ull << MSR_DWE) |
4028 (1ull << MSR_DE) |
4029 (1ull << MSR_FE1) |
4030 (1ull << MSR_IR) |
4031 (1ull << MSR_DR);
4032 pcc->mmu_model = POWERPC_MMU_BOOKE;
4033 pcc->excp_model = POWERPC_EXCP_BOOKE;
4034 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4035 pcc->bfd_mach = bfd_mach_ppc_403;
4036 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4037 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4038 }
4039
4040 static void init_proc_440x5(CPUPPCState *env)
4041 {
4042 /* Time base */
4043 gen_tbl(env);
4044 gen_spr_BookE(env, 0x000000000000FFFFULL);
4045 gen_spr_440(env);
4046 gen_spr_usprgh(env);
4047 /* Processor identification */
4048 spr_register(env, SPR_BOOKE_PIR, "PIR",
4049 SPR_NOACCESS, SPR_NOACCESS,
4050 &spr_read_generic, &spr_write_pir,
4051 0x00000000);
4052 /* XXX : not implemented */
4053 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4054 SPR_NOACCESS, SPR_NOACCESS,
4055 &spr_read_generic, &spr_write_generic,
4056 0x00000000);
4057 /* XXX : not implemented */
4058 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4059 SPR_NOACCESS, SPR_NOACCESS,
4060 &spr_read_generic, &spr_write_generic,
4061 0x00000000);
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4078 SPR_NOACCESS, SPR_NOACCESS,
4079 &spr_read_generic, &spr_write_generic,
4080 0x00000000);
4081 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4082 SPR_NOACCESS, SPR_NOACCESS,
4083 &spr_read_generic, &spr_write_generic,
4084 0x00000000);
4085 /* XXX : not implemented */
4086 spr_register(env, SPR_440_CCR1, "CCR1",
4087 SPR_NOACCESS, SPR_NOACCESS,
4088 &spr_read_generic, &spr_write_generic,
4089 0x00000000);
4090 /* Memory management */
4091 #if !defined(CONFIG_USER_ONLY)
4092 env->nb_tlb = 64;
4093 env->nb_ways = 1;
4094 env->id_tlbs = 0;
4095 env->tlb_type = TLB_EMB;
4096 #endif
4097 init_excp_BookE(env);
4098 env->dcache_line_size = 32;
4099 env->icache_line_size = 32;
4100 ppc40x_irq_init(ppc_env_get_cpu(env));
4101
4102 SET_FIT_PERIOD(12, 16, 20, 24);
4103 SET_WDT_PERIOD(20, 24, 28, 32);
4104 }
4105
4106 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4107 {
4108 DeviceClass *dc = DEVICE_CLASS(oc);
4109 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4110
4111 dc->desc = "PowerPC 440x5";
4112 pcc->init_proc = init_proc_440x5;
4113 pcc->check_pow = check_pow_nocheck;
4114 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4115 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4116 PPC_CACHE | PPC_CACHE_ICBI |
4117 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4118 PPC_MEM_TLBSYNC | PPC_MFTB |
4119 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4120 PPC_440_SPEC;
4121 pcc->msr_mask = (1ull << MSR_POW) |
4122 (1ull << MSR_CE) |
4123 (1ull << MSR_EE) |
4124 (1ull << MSR_PR) |
4125 (1ull << MSR_FP) |
4126 (1ull << MSR_ME) |
4127 (1ull << MSR_FE0) |
4128 (1ull << MSR_DWE) |
4129 (1ull << MSR_DE) |
4130 (1ull << MSR_FE1) |
4131 (1ull << MSR_IR) |
4132 (1ull << MSR_DR);
4133 pcc->mmu_model = POWERPC_MMU_BOOKE;
4134 pcc->excp_model = POWERPC_EXCP_BOOKE;
4135 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4136 pcc->bfd_mach = bfd_mach_ppc_403;
4137 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4138 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4139 }
4140
4141 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4142 {
4143 DeviceClass *dc = DEVICE_CLASS(oc);
4144 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4145
4146 dc->desc = "PowerPC 440x5 with double precision FPU";
4147 pcc->init_proc = init_proc_440x5;
4148 pcc->check_pow = check_pow_nocheck;
4149 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4150 PPC_FLOAT | PPC_FLOAT_FSQRT |
4151 PPC_FLOAT_STFIWX |
4152 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4153 PPC_CACHE | PPC_CACHE_ICBI |
4154 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4155 PPC_MEM_TLBSYNC | PPC_MFTB |
4156 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4157 PPC_440_SPEC;
4158 pcc->insns_flags2 = PPC2_FP_CVT_S64;
4159 pcc->msr_mask = (1ull << MSR_POW) |
4160 (1ull << MSR_CE) |
4161 (1ull << MSR_EE) |
4162 (1ull << MSR_PR) |
4163 (1ull << MSR_FP) |
4164 (1ull << MSR_ME) |
4165 (1ull << MSR_FE0) |
4166 (1ull << MSR_DWE) |
4167 (1ull << MSR_DE) |
4168 (1ull << MSR_FE1) |
4169 (1ull << MSR_IR) |
4170 (1ull << MSR_DR);
4171 pcc->mmu_model = POWERPC_MMU_BOOKE;
4172 pcc->excp_model = POWERPC_EXCP_BOOKE;
4173 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4174 pcc->bfd_mach = bfd_mach_ppc_403;
4175 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4176 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4177 }
4178
4179 static void init_proc_460 (CPUPPCState *env)
4180 {
4181 /* Time base */
4182 gen_tbl(env);
4183 gen_spr_BookE(env, 0x000000000000FFFFULL);
4184 gen_spr_440(env);
4185 gen_spr_usprgh(env);
4186 /* Processor identification */
4187 spr_register(env, SPR_BOOKE_PIR, "PIR",
4188 SPR_NOACCESS, SPR_NOACCESS,
4189 &spr_read_generic, &spr_write_pir,
4190 0x00000000);
4191 /* XXX : not implemented */
4192 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4193 SPR_NOACCESS, SPR_NOACCESS,
4194 &spr_read_generic, &spr_write_generic,
4195 0x00000000);
4196 /* XXX : not implemented */
4197 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4198 SPR_NOACCESS, SPR_NOACCESS,
4199 &spr_read_generic, &spr_write_generic,
4200 0x00000000);
4201 /* XXX : not implemented */
4202 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4203 SPR_NOACCESS, SPR_NOACCESS,
4204 &spr_read_generic, &spr_write_generic,
4205 0x00000000);
4206 /* XXX : not implemented */
4207 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4208 SPR_NOACCESS, SPR_NOACCESS,
4209 &spr_read_generic, &spr_write_generic,
4210 0x00000000);
4211 /* XXX : not implemented */
4212 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4213 SPR_NOACCESS, SPR_NOACCESS,
4214 &spr_read_generic, &spr_write_generic,
4215 0x00000000);
4216 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4217 SPR_NOACCESS, SPR_NOACCESS,
4218 &spr_read_generic, &spr_write_generic,
4219 0x00000000);
4220 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4221 SPR_NOACCESS, SPR_NOACCESS,
4222 &spr_read_generic, &spr_write_generic,
4223 0x00000000);
4224 /* XXX : not implemented */
4225 spr_register(env, SPR_440_CCR1, "CCR1",
4226 SPR_NOACCESS, SPR_NOACCESS,
4227 &spr_read_generic, &spr_write_generic,
4228 0x00000000);
4229 /* XXX : not implemented */
4230 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4231 &spr_read_generic, &spr_write_generic,
4232 &spr_read_generic, &spr_write_generic,
4233 0x00000000);
4234 /* Memory management */
4235 #if !defined(CONFIG_USER_ONLY)
4236 env->nb_tlb = 64;
4237 env->nb_ways = 1;
4238 env->id_tlbs = 0;
4239 env->tlb_type = TLB_EMB;
4240 #endif
4241 init_excp_BookE(env);
4242 env->dcache_line_size = 32;
4243 env->icache_line_size = 32;
4244 /* XXX: TODO: allocate internal IRQ controller */
4245
4246 SET_FIT_PERIOD(12, 16, 20, 24);
4247 SET_WDT_PERIOD(20, 24, 28, 32);
4248 }
4249
4250 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4251 {
4252 DeviceClass *dc = DEVICE_CLASS(oc);
4253 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4254
4255 dc->desc = "PowerPC 460 (guessed)";
4256 pcc->init_proc = init_proc_460;
4257 pcc->check_pow = check_pow_nocheck;
4258 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4259 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4260 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4261 PPC_CACHE | PPC_CACHE_ICBI |
4262 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4263 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4264 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4265 PPC_440_SPEC;
4266 pcc->msr_mask = (1ull << MSR_POW) |
4267 (1ull << MSR_CE) |
4268 (1ull << MSR_EE) |
4269 (1ull << MSR_PR) |
4270 (1ull << MSR_FP) |
4271 (1ull << MSR_ME) |
4272 (1ull << MSR_FE0) |
4273 (1ull << MSR_DWE) |
4274 (1ull << MSR_DE) |
4275 (1ull << MSR_FE1) |
4276 (1ull << MSR_IR) |
4277 (1ull << MSR_DR);
4278 pcc->mmu_model = POWERPC_MMU_BOOKE;
4279 pcc->excp_model = POWERPC_EXCP_BOOKE;
4280 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4281 pcc->bfd_mach = bfd_mach_ppc_403;
4282 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4283 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4284 }
4285
4286 static void init_proc_460F(CPUPPCState *env)
4287 {
4288 /* Time base */
4289 gen_tbl(env);
4290 gen_spr_BookE(env, 0x000000000000FFFFULL);
4291 gen_spr_440(env);
4292 gen_spr_usprgh(env);
4293 /* Processor identification */
4294 spr_register(env, SPR_BOOKE_PIR, "PIR",
4295 SPR_NOACCESS, SPR_NOACCESS,
4296 &spr_read_generic, &spr_write_pir,
4297 0x00000000);
4298 /* XXX : not implemented */
4299 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4300 SPR_NOACCESS, SPR_NOACCESS,
4301 &spr_read_generic, &spr_write_generic,
4302 0x00000000);
4303 /* XXX : not implemented */
4304 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4305 SPR_NOACCESS, SPR_NOACCESS,
4306 &spr_read_generic, &spr_write_generic,
4307 0x00000000);
4308 /* XXX : not implemented */
4309 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4310 SPR_NOACCESS, SPR_NOACCESS,
4311 &spr_read_generic, &spr_write_generic,
4312 0x00000000);
4313 /* XXX : not implemented */
4314 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4315 SPR_NOACCESS, SPR_NOACCESS,
4316 &spr_read_generic, &spr_write_generic,
4317 0x00000000);
4318 /* XXX : not implemented */
4319 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4320 SPR_NOACCESS, SPR_NOACCESS,
4321 &spr_read_generic, &spr_write_generic,
4322 0x00000000);
4323 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4324 SPR_NOACCESS, SPR_NOACCESS,
4325 &spr_read_generic, &spr_write_generic,
4326 0x00000000);
4327 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4328 SPR_NOACCESS, SPR_NOACCESS,
4329 &spr_read_generic, &spr_write_generic,
4330 0x00000000);
4331 /* XXX : not implemented */
4332 spr_register(env, SPR_440_CCR1, "CCR1",
4333 SPR_NOACCESS, SPR_NOACCESS,
4334 &spr_read_generic, &spr_write_generic,
4335 0x00000000);
4336 /* XXX : not implemented */
4337 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4338 &spr_read_generic, &spr_write_generic,
4339 &spr_read_generic, &spr_write_generic,
4340 0x00000000);
4341 /* Memory management */
4342 #if !defined(CONFIG_USER_ONLY)
4343 env->nb_tlb = 64;
4344 env->nb_ways = 1;
4345 env->id_tlbs = 0;
4346 env->tlb_type = TLB_EMB;
4347 #endif
4348 init_excp_BookE(env);
4349 env->dcache_line_size = 32;
4350 env->icache_line_size = 32;
4351 /* XXX: TODO: allocate internal IRQ controller */
4352
4353 SET_FIT_PERIOD(12, 16, 20, 24);
4354 SET_WDT_PERIOD(20, 24, 28, 32);
4355 }
4356
4357 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4358 {
4359 DeviceClass *dc = DEVICE_CLASS(oc);
4360 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4361
4362 dc->desc = "PowerPC 460F (guessed)";
4363 pcc->init_proc = init_proc_460F;
4364 pcc->check_pow = check_pow_nocheck;
4365 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4366 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4367 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4368 PPC_FLOAT_STFIWX | PPC_MFTB |
4369 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4370 PPC_WRTEE | PPC_MFAPIDI |
4371 PPC_CACHE | PPC_CACHE_ICBI |
4372 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4373 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4374 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4375 PPC_440_SPEC;
4376 pcc->msr_mask = (1ull << MSR_POW) |
4377 (1ull << MSR_CE) |
4378 (1ull << MSR_EE) |
4379 (1ull << MSR_PR) |
4380 (1ull << MSR_FP) |
4381 (1ull << MSR_ME) |
4382 (1ull << MSR_FE0) |
4383 (1ull << MSR_DWE) |
4384 (1ull << MSR_DE) |
4385 (1ull << MSR_FE1) |
4386 (1ull << MSR_IR) |
4387 (1ull << MSR_DR);
4388 pcc->mmu_model = POWERPC_MMU_BOOKE;
4389 pcc->excp_model = POWERPC_EXCP_BOOKE;
4390 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4391 pcc->bfd_mach = bfd_mach_ppc_403;
4392 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4393 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4394 }
4395
4396 static void init_proc_MPC5xx(CPUPPCState *env)
4397 {
4398 /* Time base */
4399 gen_tbl(env);
4400 gen_spr_5xx_8xx(env);
4401 gen_spr_5xx(env);
4402 init_excp_MPC5xx(env);
4403 env->dcache_line_size = 32;
4404 env->icache_line_size = 32;
4405 /* XXX: TODO: allocate internal IRQ controller */
4406 }
4407
4408 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4409 {
4410 DeviceClass *dc = DEVICE_CLASS(oc);
4411 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4412
4413 dc->desc = "Freescale 5xx cores (aka RCPU)";
4414 pcc->init_proc = init_proc_MPC5xx;
4415 pcc->check_pow = check_pow_none;
4416 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4417 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4418 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4419 PPC_MFTB;
4420 pcc->msr_mask = (1ull << MSR_ILE) |
4421 (1ull << MSR_EE) |
4422 (1ull << MSR_PR) |
4423 (1ull << MSR_FP) |
4424 (1ull << MSR_ME) |
4425 (1ull << MSR_FE0) |
4426 (1ull << MSR_SE) |
4427 (1ull << MSR_DE) |
4428 (1ull << MSR_FE1) |
4429 (1ull << MSR_EP) |
4430 (1ull << MSR_RI) |
4431 (1ull << MSR_LE);
4432 pcc->mmu_model = POWERPC_MMU_REAL;
4433 pcc->excp_model = POWERPC_EXCP_603;
4434 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4435 pcc->bfd_mach = bfd_mach_ppc_505;
4436 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4437 POWERPC_FLAG_BUS_CLK;
4438 }
4439
4440 static void init_proc_MPC8xx(CPUPPCState *env)
4441 {
4442 /* Time base */
4443 gen_tbl(env);
4444 gen_spr_5xx_8xx(env);
4445 gen_spr_8xx(env);
4446 init_excp_MPC8xx(env);
4447 env->dcache_line_size = 32;
4448 env->icache_line_size = 32;
4449 /* XXX: TODO: allocate internal IRQ controller */
4450 }
4451
4452 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4453 {
4454 DeviceClass *dc = DEVICE_CLASS(oc);
4455 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4456
4457 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4458 pcc->init_proc = init_proc_MPC8xx;
4459 pcc->check_pow = check_pow_none;
4460 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4461 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4462 PPC_CACHE_ICBI | PPC_MFTB;
4463 pcc->msr_mask = (1ull << MSR_ILE) |
4464 (1ull << MSR_EE) |
4465 (1ull << MSR_PR) |
4466 (1ull << MSR_FP) |
4467 (1ull << MSR_ME) |
4468 (1ull << MSR_SE) |
4469 (1ull << MSR_DE) |
4470 (1ull << MSR_EP) |
4471 (1ull << MSR_IR) |
4472 (1ull << MSR_DR) |
4473 (1ull << MSR_RI) |
4474 (1ull << MSR_LE);
4475 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4476 pcc->excp_model = POWERPC_EXCP_603;
4477 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4478 pcc->bfd_mach = bfd_mach_ppc_860;
4479 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4480 POWERPC_FLAG_BUS_CLK;
4481 }
4482
4483 /* Freescale 82xx cores (aka PowerQUICC-II) */
4484
4485 static void init_proc_G2(CPUPPCState *env)
4486 {
4487 gen_spr_ne_601(env);
4488 gen_spr_sdr1(env);
4489 gen_spr_G2_755(env);
4490 gen_spr_G2(env);
4491 /* Time base */
4492 gen_tbl(env);
4493 /* External access control */
4494 /* XXX : not implemented */
4495 spr_register(env, SPR_EAR, "EAR",
4496 SPR_NOACCESS, SPR_NOACCESS,
4497 &spr_read_generic, &spr_write_generic,
4498 0x00000000);
4499 /* Hardware implementation register */
4500 /* XXX : not implemented */
4501 spr_register(env, SPR_HID0, "HID0",
4502 SPR_NOACCESS, SPR_NOACCESS,
4503 &spr_read_generic, &spr_write_generic,
4504 0x00000000);
4505 /* XXX : not implemented */
4506 spr_register(env, SPR_HID1, "HID1",
4507 SPR_NOACCESS, SPR_NOACCESS,
4508 &spr_read_generic, &spr_write_generic,
4509 0x00000000);
4510 /* XXX : not implemented */
4511 spr_register(env, SPR_HID2, "HID2",
4512 SPR_NOACCESS, SPR_NOACCESS,
4513 &spr_read_generic, &spr_write_generic,
4514 0x00000000);
4515 /* Memory management */
4516 gen_low_BATs(env);
4517 gen_high_BATs(env);
4518 gen_6xx_7xx_soft_tlb(env, 64, 2);
4519 init_excp_G2(env);
4520 env->dcache_line_size = 32;
4521 env->icache_line_size = 32;
4522 /* Allocate hardware IRQ controller */
4523 ppc6xx_irq_init(ppc_env_get_cpu(env));
4524 }
4525
4526 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4527 {
4528 DeviceClass *dc = DEVICE_CLASS(oc);
4529 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4530
4531 dc->desc = "PowerPC G2";
4532 pcc->init_proc = init_proc_G2;
4533 pcc->check_pow = check_pow_hid0;
4534 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4535 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4536 PPC_FLOAT_STFIWX |
4537 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4538 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4539 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4540 PPC_SEGMENT | PPC_EXTERN;
4541 pcc->msr_mask = (1ull << MSR_POW) |
4542 (1ull << MSR_TGPR) |
4543 (1ull << MSR_EE) |
4544 (1ull << MSR_PR) |
4545 (1ull << MSR_FP) |
4546 (1ull << MSR_ME) |
4547 (1ull << MSR_FE0) |
4548 (1ull << MSR_SE) |
4549 (1ull << MSR_DE) |
4550 (1ull << MSR_FE1) |
4551 (1ull << MSR_AL) |
4552 (1ull << MSR_EP) |
4553 (1ull << MSR_IR) |
4554 (1ull << MSR_DR) |
4555 (1ull << MSR_RI);
4556 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4557 pcc->excp_model = POWERPC_EXCP_G2;
4558 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4559 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4560 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4561 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4562 }
4563
4564 static void init_proc_G2LE(CPUPPCState *env)
4565 {
4566 gen_spr_ne_601(env);
4567 gen_spr_sdr1(env);
4568 gen_spr_G2_755(env);
4569 gen_spr_G2(env);
4570 /* Time base */
4571 gen_tbl(env);
4572 /* External access control */
4573 /* XXX : not implemented */
4574 spr_register(env, SPR_EAR, "EAR",
4575 SPR_NOACCESS, SPR_NOACCESS,
4576 &spr_read_generic, &spr_write_generic,
4577 0x00000000);
4578 /* Hardware implementation register */
4579 /* XXX : not implemented */
4580 spr_register(env, SPR_HID0, "HID0",
4581 SPR_NOACCESS, SPR_NOACCESS,
4582 &spr_read_generic, &spr_write_generic,
4583 0x00000000);
4584 /* XXX : not implemented */
4585 spr_register(env, SPR_HID1, "HID1",
4586 SPR_NOACCESS, SPR_NOACCESS,
4587 &spr_read_generic, &spr_write_generic,
4588 0x00000000);
4589 /* XXX : not implemented */
4590 spr_register(env, SPR_HID2, "HID2",
4591 SPR_NOACCESS, SPR_NOACCESS,
4592 &spr_read_generic, &spr_write_generic,
4593 0x00000000);
4594
4595 /* Memory management */
4596 gen_low_BATs(env);
4597 gen_high_BATs(env);
4598 gen_6xx_7xx_soft_tlb(env, 64, 2);
4599 init_excp_G2(env);
4600 env->dcache_line_size = 32;
4601 env->icache_line_size = 32;
4602 /* Allocate hardware IRQ controller */
4603 ppc6xx_irq_init(ppc_env_get_cpu(env));
4604 }
4605
4606 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4607 {
4608 DeviceClass *dc = DEVICE_CLASS(oc);
4609 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4610
4611 dc->desc = "PowerPC G2LE";
4612 pcc->init_proc = init_proc_G2LE;
4613 pcc->check_pow = check_pow_hid0;
4614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4615 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4616 PPC_FLOAT_STFIWX |
4617 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4618 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4620 PPC_SEGMENT | PPC_EXTERN;
4621 pcc->msr_mask = (1ull << MSR_POW) |
4622 (1ull << MSR_TGPR) |
4623 (1ull << MSR_ILE) |
4624 (1ull << MSR_EE) |
4625 (1ull << MSR_PR) |
4626 (1ull << MSR_FP) |
4627 (1ull << MSR_ME) |
4628 (1ull << MSR_FE0) |
4629 (1ull << MSR_SE) |
4630 (1ull << MSR_DE) |
4631 (1ull << MSR_FE1) |
4632 (1ull << MSR_AL) |
4633 (1ull << MSR_EP) |
4634 (1ull << MSR_IR) |
4635 (1ull << MSR_DR) |
4636 (1ull << MSR_RI) |
4637 (1ull << MSR_LE);
4638 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4639 pcc->excp_model = POWERPC_EXCP_G2;
4640 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4641 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4642 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4643 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4644 }
4645
4646 static void init_proc_e200(CPUPPCState *env)
4647 {
4648 /* Time base */
4649 gen_tbl(env);
4650 gen_spr_BookE(env, 0x000000070000FFFFULL);
4651 /* XXX : not implemented */
4652 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4653 &spr_read_spefscr, &spr_write_spefscr,
4654 &spr_read_spefscr, &spr_write_spefscr,
4655 0x00000000);
4656 /* Memory management */
4657 gen_spr_BookE206(env, 0x0000005D, NULL, 0);
4658 /* XXX : not implemented */
4659 spr_register(env, SPR_HID0, "HID0",
4660 SPR_NOACCESS, SPR_NOACCESS,
4661 &spr_read_generic, &spr_write_generic,
4662 0x00000000);
4663 /* XXX : not implemented */
4664 spr_register(env, SPR_HID1, "HID1",
4665 SPR_NOACCESS, SPR_NOACCESS,
4666 &spr_read_generic, &spr_write_generic,
4667 0x00000000);
4668 /* XXX : not implemented */
4669 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4670 SPR_NOACCESS, SPR_NOACCESS,
4671 &spr_read_generic, &spr_write_generic,
4672 0x00000000);
4673 /* XXX : not implemented */
4674 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4675 SPR_NOACCESS, SPR_NOACCESS,
4676 &spr_read_generic, &spr_write_generic,
4677 0x00000000);
4678 /* XXX : not implemented */
4679 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4680 SPR_NOACCESS, SPR_NOACCESS,
4681 &spr_read_generic, &spr_write_generic,
4682 0x00000000);
4683 /* XXX : not implemented */
4684 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4685 SPR_NOACCESS, SPR_NOACCESS,
4686 &spr_read_generic, &spr_write_generic,
4687 0x00000000);
4688 /* XXX : not implemented */
4689 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4690 SPR_NOACCESS, SPR_NOACCESS,
4691 &spr_read_generic, &spr_write_generic,
4692 0x00000000);
4693 /* XXX : not implemented */
4694 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4695 &spr_read_generic, SPR_NOACCESS,
4696 &spr_read_generic, SPR_NOACCESS,
4697 0x00000000);
4698 /* XXX : not implemented */
4699 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4700 SPR_NOACCESS, SPR_NOACCESS,
4701 &spr_read_generic, &spr_write_generic,
4702 0x00000000);
4703 /* XXX : not implemented */
4704 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4705 SPR_NOACCESS, SPR_NOACCESS,
4706 &spr_read_generic, &spr_write_generic,
4707 0x00000000);
4708 /* XXX : not implemented */
4709 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4710 SPR_NOACCESS, SPR_NOACCESS,
4711 &spr_read_generic, &spr_write_generic,
4712 0x00000000);
4713 /* XXX : not implemented */
4714 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4715 SPR_NOACCESS, SPR_NOACCESS,
4716 &spr_read_generic, &spr_write_generic,
4717 0x00000000);
4718 /* XXX : not implemented */
4719 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4720 SPR_NOACCESS, SPR_NOACCESS,
4721 &spr_read_generic, &spr_write_generic,
4722 0x00000000);
4723 /* XXX : not implemented */
4724 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4725 SPR_NOACCESS, SPR_NOACCESS,
4726 &spr_read_generic, &spr_write_generic,
4727 0x00000000);
4728 /* XXX : not implemented */
4729 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4730 SPR_NOACCESS, SPR_NOACCESS,
4731 &spr_read_generic, &spr_write_generic,
4732 0x00000000); /* TOFIX */
4733 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4734 SPR_NOACCESS, SPR_NOACCESS,
4735 &spr_read_generic, &spr_write_generic,
4736 0x00000000);
4737 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4738 SPR_NOACCESS, SPR_NOACCESS,
4739 &spr_read_generic, &spr_write_generic,
4740 0x00000000);
4741 #if !defined(CONFIG_USER_ONLY)
4742 env->nb_tlb = 64;
4743 env->nb_ways = 1;
4744 env->id_tlbs = 0;
4745 env->tlb_type = TLB_EMB;
4746 #endif
4747 init_excp_e200(env, 0xFFFF0000UL);
4748 env->dcache_line_size = 32;
4749 env->icache_line_size = 32;
4750 /* XXX: TODO: allocate internal IRQ controller */
4751 }
4752
4753 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4754 {
4755 DeviceClass *dc = DEVICE_CLASS(oc);
4756 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4757
4758 dc->desc = "e200 core";
4759 pcc->init_proc = init_proc_e200;
4760 pcc->check_pow = check_pow_hid0;
4761 /* XXX: unimplemented instructions:
4762 * dcblc
4763 * dcbtlst
4764 * dcbtstls
4765 * icblc
4766 * icbtls
4767 * tlbivax
4768 * all SPE multiply-accumulate instructions
4769 */
4770 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4771 PPC_SPE | PPC_SPE_SINGLE |
4772 PPC_WRTEE | PPC_RFDI |
4773 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4774 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4775 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4776 PPC_BOOKE;
4777 pcc->msr_mask = (1ull << MSR_UCLE) |
4778 (1ull << MSR_SPE) |
4779 (1ull << MSR_POW) |
4780 (1ull << MSR_CE) |
4781 (1ull << MSR_EE) |
4782 (1ull << MSR_PR) |
4783 (1ull << MSR_FP) |
4784 (1ull << MSR_ME) |
4785 (1ull << MSR_FE0) |
4786 (1ull << MSR_DWE) |
4787 (1ull << MSR_DE) |
4788 (1ull << MSR_FE1) |
4789 (1ull << MSR_IR) |
4790 (1ull << MSR_DR);
4791 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4792 pcc->excp_model = POWERPC_EXCP_BOOKE;
4793 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4794 pcc->bfd_mach = bfd_mach_ppc_860;
4795 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4796 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4797 POWERPC_FLAG_BUS_CLK;
4798 }
4799
4800 static void init_proc_e300(CPUPPCState *env)
4801 {
4802 gen_spr_ne_601(env);
4803 gen_spr_sdr1(env);
4804 gen_spr_603(env);
4805 /* Time base */
4806 gen_tbl(env);
4807 /* hardware implementation registers */
4808 /* XXX : not implemented */
4809 spr_register(env, SPR_HID0, "HID0",
4810 SPR_NOACCESS, SPR_NOACCESS,
4811 &spr_read_generic, &spr_write_generic,
4812 0x00000000);
4813 /* XXX : not implemented */
4814 spr_register(env, SPR_HID1, "HID1",
4815 SPR_NOACCESS, SPR_NOACCESS,
4816 &spr_read_generic, &spr_write_generic,
4817 0x00000000);
4818 /* XXX : not implemented */
4819 spr_register(env, SPR_HID2, "HID2",
4820 SPR_NOACCESS, SPR_NOACCESS,
4821 &spr_read_generic, &spr_write_generic,
4822 0x00000000);
4823 /* Breakpoints */
4824 /* XXX : not implemented */
4825 spr_register(env, SPR_DABR, "DABR",
4826 SPR_NOACCESS, SPR_NOACCESS,
4827 &spr_read_generic, &spr_write_generic,
4828 0x00000000);
4829 /* XXX : not implemented */
4830 spr_register(env, SPR_DABR2, "DABR2",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 /* XXX : not implemented */
4835 spr_register(env, SPR_IABR2, "IABR2",
4836 SPR_NOACCESS, SPR_NOACCESS,
4837 &spr_read_generic, &spr_write_generic,
4838 0x00000000);
4839 /* XXX : not implemented */
4840 spr_register(env, SPR_IBCR, "IBCR",
4841 SPR_NOACCESS, SPR_NOACCESS,
4842 &spr_read_generic, &spr_write_generic,
4843 0x00000000);
4844 /* XXX : not implemented */
4845 spr_register(env, SPR_DBCR, "DBCR",
4846 SPR_NOACCESS, SPR_NOACCESS,
4847 &spr_read_generic, &spr_write_generic,
4848 0x00000000);
4849 /* Memory management */
4850 gen_low_BATs(env);
4851 gen_high_BATs(env);
4852 gen_6xx_7xx_soft_tlb(env, 64, 2);
4853 init_excp_603(env);
4854 env->dcache_line_size = 32;
4855 env->icache_line_size = 32;
4856 /* Allocate hardware IRQ controller */
4857 ppc6xx_irq_init(ppc_env_get_cpu(env));
4858 }
4859
4860 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4861 {
4862 DeviceClass *dc = DEVICE_CLASS(oc);
4863 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4864
4865 dc->desc = "e300 core";
4866 pcc->init_proc = init_proc_e300;
4867 pcc->check_pow = check_pow_hid0;
4868 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4869 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4870 PPC_FLOAT_STFIWX |
4871 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4872 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4873 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4874 PPC_SEGMENT | PPC_EXTERN;
4875 pcc->msr_mask = (1ull << MSR_POW) |
4876 (1ull << MSR_TGPR) |
4877 (1ull << MSR_ILE) |
4878 (1ull << MSR_EE) |
4879 (1ull << MSR_PR) |
4880 (1ull << MSR_FP) |
4881 (1ull << MSR_ME) |
4882 (1ull << MSR_FE0) |
4883 (1ull << MSR_SE) |
4884 (1ull << MSR_DE) |
4885 (1ull << MSR_FE1) |
4886 (1ull << MSR_AL) |
4887 (1ull << MSR_EP) |
4888 (1ull << MSR_IR) |
4889 (1ull << MSR_DR) |
4890 (1ull << MSR_RI) |
4891 (1ull << MSR_LE);
4892 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4893 pcc->excp_model = POWERPC_EXCP_603;
4894 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4895 pcc->bfd_mach = bfd_mach_ppc_603;
4896 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4897 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4898 }
4899
4900 #if !defined(CONFIG_USER_ONLY)
4901 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4902 {
4903 TCGv val = tcg_temp_new();
4904 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4905 gen_store_spr(SPR_BOOKE_MAS3, val);
4906 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4907 gen_store_spr(SPR_BOOKE_MAS7, val);
4908 tcg_temp_free(val);
4909 }
4910
4911 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4912 {
4913 TCGv mas7 = tcg_temp_new();
4914 TCGv mas3 = tcg_temp_new();
4915 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4916 tcg_gen_shli_tl(mas7, mas7, 32);
4917 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4918 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4919 tcg_temp_free(mas3);
4920 tcg_temp_free(mas7);
4921 }
4922
4923 #endif
4924
4925 enum fsl_e500_version {
4926 fsl_e500v1,
4927 fsl_e500v2,
4928 fsl_e500mc,
4929 fsl_e5500,
4930 fsl_e6500,
4931 };
4932
4933 static void init_proc_e500(CPUPPCState *env, int version)
4934 {
4935 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4936 uint32_t tlbncfg[2];
4937 uint64_t ivor_mask;
4938 uint64_t ivpr_mask = 0xFFFF0000ULL;
4939 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4940 | 0x0020; /* 32 kb */
4941 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4942 | 0x0020; /* 32 kb */
4943 uint32_t mmucfg = 0;
4944 #if !defined(CONFIG_USER_ONLY)
4945 int i;
4946 #endif
4947
4948 /* Time base */
4949 gen_tbl(env);
4950 /*
4951 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4952 * complain when accessing them.
4953 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4954 */
4955 switch (version) {
4956 case fsl_e500v1:
4957 case fsl_e500v2:
4958 default:
4959 ivor_mask = 0x0000000F0000FFFFULL;
4960 break;
4961 case fsl_e500mc:
4962 case fsl_e5500:
4963 ivor_mask = 0x000003FE0000FFFFULL;
4964 break;
4965 case fsl_e6500:
4966 ivor_mask = 0x000003FF0000FFFFULL;
4967 break;
4968 }
4969 gen_spr_BookE(env, ivor_mask);
4970 gen_spr_usprg3(env);
4971 /* Processor identification */
4972 spr_register(env, SPR_BOOKE_PIR, "PIR",
4973 SPR_NOACCESS, SPR_NOACCESS,
4974 &spr_read_generic, &spr_write_pir,
4975 0x00000000);
4976 /* XXX : not implemented */
4977 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4978 &spr_read_spefscr, &spr_write_spefscr,
4979 &spr_read_spefscr, &spr_write_spefscr,
4980 0x00000000);
4981 #if !defined(CONFIG_USER_ONLY)
4982 /* Memory management */
4983 env->nb_pids = 3;
4984 env->nb_ways = 2;
4985 env->id_tlbs = 0;
4986 switch (version) {
4987 case fsl_e500v1:
4988 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4989 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4990 break;
4991 case fsl_e500v2:
4992 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4993 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4994 break;
4995 case fsl_e500mc:
4996 case fsl_e5500:
4997 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4998 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4999 break;
5000 case fsl_e6500:
5001 mmucfg = 0x6510B45;
5002 env->nb_pids = 1;
5003 tlbncfg[0] = 0x08052400;
5004 tlbncfg[1] = 0x40028040;
5005 break;
5006 default:
5007 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
5008 }
5009 #endif
5010 /* Cache sizes */
5011 switch (version) {
5012 case fsl_e500v1:
5013 case fsl_e500v2:
5014 env->dcache_line_size = 32;
5015 env->icache_line_size = 32;
5016 break;
5017 case fsl_e500mc:
5018 case fsl_e5500:
5019 env->dcache_line_size = 64;
5020 env->icache_line_size = 64;
5021 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
5022 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
5023 break;
5024 case fsl_e6500:
5025 env->dcache_line_size = 32;
5026 env->icache_line_size = 32;
5027 l1cfg0 |= 0x0F83820;
5028 l1cfg1 |= 0x0B83820;
5029 break;
5030 default:
5031 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
5032 }
5033 gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
5034 /* XXX : not implemented */
5035 spr_register(env, SPR_HID0, "HID0",
5036 SPR_NOACCESS, SPR_NOACCESS,
5037 &spr_read_generic, &spr_write_generic,
5038 0x00000000);
5039 /* XXX : not implemented */
5040 spr_register(env, SPR_HID1, "HID1",
5041 SPR_NOACCESS, SPR_NOACCESS,
5042 &spr_read_generic, &spr_write_generic,
5043 0x00000000);
5044 /* XXX : not implemented */
5045 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
5046 SPR_NOACCESS, SPR_NOACCESS,
5047 &spr_read_generic, &spr_write_generic,
5048 0x00000000);
5049 /* XXX : not implemented */
5050 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
5051 SPR_NOACCESS, SPR_NOACCESS,
5052 &spr_read_generic, &spr_write_generic,
5053 0x00000000);
5054 /* XXX : not implemented */
5055 spr_register(env, SPR_Exxx_MCAR, "MCAR",
5056 SPR_NOACCESS, SPR_NOACCESS,
5057 &spr_read_generic, &spr_write_generic,
5058 0x00000000);
5059 /* XXX : not implemented */
5060 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
5061 SPR_NOACCESS, SPR_NOACCESS,
5062 &spr_read_generic, &spr_write_generic,
5063 0x00000000);
5064 /* XXX : not implemented */
5065 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
5066 SPR_NOACCESS, SPR_NOACCESS,
5067 &spr_read_generic, &spr_write_generic,
5068 0x00000000);
5069 /* XXX : not implemented */
5070 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
5071 SPR_NOACCESS, SPR_NOACCESS,
5072 &spr_read_generic, &spr_write_generic,
5073 0x00000000);
5074 /* XXX : not implemented */
5075 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
5076 &spr_read_generic, SPR_NOACCESS,
5077 &spr_read_generic, SPR_NOACCESS,
5078 l1cfg0);
5079 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
5080 &spr_read_generic, SPR_NOACCESS,
5081 &spr_read_generic, SPR_NOACCESS,
5082 l1cfg1);
5083 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
5084 SPR_NOACCESS, SPR_NOACCESS,
5085 &spr_read_generic, &spr_write_e500_l1csr0,
5086 0x00000000);
5087 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
5088 SPR_NOACCESS, SPR_NOACCESS,
5089 &spr_read_generic, &spr_write_e500_l1csr1,
5090 0x00000000);
5091 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
5092 SPR_NOACCESS, SPR_NOACCESS,
5093 &spr_read_generic, &spr_write_generic,
5094 0x00000000);
5095 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
5096 SPR_NOACCESS, SPR_NOACCESS,
5097 &spr_read_generic, &spr_write_generic,
5098 0x00000000);
5099 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5100 SPR_NOACCESS, SPR_NOACCESS,
5101 &spr_read_generic, &spr_write_booke206_mmucsr0,
5102 0x00000000);
5103 spr_register(env, SPR_BOOKE_EPR, "EPR",
5104 SPR_NOACCESS, SPR_NOACCESS,
5105 &spr_read_generic, SPR_NOACCESS,
5106 0x00000000);
5107 /* XXX better abstract into Emb.xxx features */
5108 if ((version == fsl_e5500) || (version == fsl_e6500)) {
5109 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
5110 SPR_NOACCESS, SPR_NOACCESS,
5111 &spr_read_generic, &spr_write_generic,
5112 0x00000000);
5113 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
5114 SPR_NOACCESS, SPR_NOACCESS,
5115 &spr_read_mas73, &spr_write_mas73,
5116 0x00000000);
5117 ivpr_mask = (target_ulong)~0xFFFFULL;
5118 }
5119
5120 if (version == fsl_e6500) {
5121 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 &spr_read_generic, &spr_write_generic,
5124 0x00000000);
5125 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
5126 SPR_NOACCESS, SPR_NOACCESS,
5127 &spr_read_generic, &spr_write_generic,
5128 0x00000000);
5129 /* Thread identification */
5130 spr_register(env, SPR_TIR, "TIR",
5131 SPR_NOACCESS, SPR_NOACCESS,
5132 &spr_read_generic, SPR_NOACCESS,
5133 0x00000000);
5134 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
5135 SPR_NOACCESS, SPR_NOACCESS,
5136 &spr_read_generic, SPR_NOACCESS,
5137 0x00000004);
5138 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
5139 SPR_NOACCESS, SPR_NOACCESS,
5140 &spr_read_generic, SPR_NOACCESS,
5141 0x7FFFFFFC);
5142 }
5143
5144 #if !defined(CONFIG_USER_ONLY)
5145 env->nb_tlb = 0;
5146 env->tlb_type = TLB_MAS;
5147 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
5148 env->nb_tlb += booke206_tlb_size(env, i);
5149 }
5150 #endif
5151
5152 init_excp_e200(env, ivpr_mask);
5153 /* Allocate hardware IRQ controller */
5154 ppce500_irq_init(ppc_env_get_cpu(env));
5155 }
5156
5157 static void init_proc_e500v1(CPUPPCState *env)
5158 {
5159 init_proc_e500(env, fsl_e500v1);
5160 }
5161
5162 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
5163 {
5164 DeviceClass *dc = DEVICE_CLASS(oc);
5165 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5166
5167 dc->desc = "e500v1 core";
5168 pcc->init_proc = init_proc_e500v1;
5169 pcc->check_pow = check_pow_hid0;
5170 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5171 PPC_SPE | PPC_SPE_SINGLE |
5172 PPC_WRTEE | PPC_RFDI |
5173 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5174 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5175 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5176 pcc->insns_flags2 = PPC2_BOOKE206;
5177 pcc->msr_mask = (1ull << MSR_UCLE) |
5178 (1ull << MSR_SPE) |
5179 (1ull << MSR_POW) |
5180 (1ull << MSR_CE) |
5181 (1ull << MSR_EE) |
5182 (1ull << MSR_PR) |
5183 (1ull << MSR_FP) |
5184 (1ull << MSR_ME) |
5185 (1ull << MSR_FE0) |
5186 (1ull << MSR_DWE) |
5187 (1ull << MSR_DE) |
5188 (1ull << MSR_FE1) |
5189 (1ull << MSR_IR) |
5190 (1ull << MSR_DR);
5191 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5192 pcc->excp_model = POWERPC_EXCP_BOOKE;
5193 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5194 pcc->bfd_mach = bfd_mach_ppc_860;
5195 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5196 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5197 POWERPC_FLAG_BUS_CLK;
5198 }
5199
5200 static void init_proc_e500v2(CPUPPCState *env)
5201 {
5202 init_proc_e500(env, fsl_e500v2);
5203 }
5204
5205 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5206 {
5207 DeviceClass *dc = DEVICE_CLASS(oc);
5208 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5209
5210 dc->desc = "e500v2 core";
5211 pcc->init_proc = init_proc_e500v2;
5212 pcc->check_pow = check_pow_hid0;
5213 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5214 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5215 PPC_WRTEE | PPC_RFDI |
5216 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5217 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5218 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5219 pcc->insns_flags2 = PPC2_BOOKE206;
5220 pcc->msr_mask = (1ull << MSR_UCLE) |
5221 (1ull << MSR_SPE) |
5222 (1ull << MSR_POW) |
5223 (1ull << MSR_CE) |
5224 (1ull << MSR_EE) |
5225 (1ull << MSR_PR) |
5226 (1ull << MSR_FP) |
5227 (1ull << MSR_ME) |
5228 (1ull << MSR_FE0) |
5229 (1ull << MSR_DWE) |
5230 (1ull << MSR_DE) |
5231 (1ull << MSR_FE1) |
5232 (1ull << MSR_IR) |
5233 (1ull << MSR_DR);
5234 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5235 pcc->excp_model = POWERPC_EXCP_BOOKE;
5236 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5237 pcc->bfd_mach = bfd_mach_ppc_860;
5238 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5239 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5240 POWERPC_FLAG_BUS_CLK;
5241 }
5242
5243 static void init_proc_e500mc(CPUPPCState *env)
5244 {
5245 init_proc_e500(env, fsl_e500mc);
5246 }
5247
5248 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5249 {
5250 DeviceClass *dc = DEVICE_CLASS(oc);
5251 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5252
5253 dc->desc = "e500mc core";
5254 pcc->init_proc = init_proc_e500mc;
5255 pcc->check_pow = check_pow_none;
5256 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5257 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5258 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5259 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5260 PPC_FLOAT | PPC_FLOAT_FRES |
5261 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5262 PPC_FLOAT_STFIWX | PPC_WAIT |
5263 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5264 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5265 pcc->msr_mask = (1ull << MSR_GS) |
5266 (1ull << MSR_UCLE) |
5267 (1ull << MSR_CE) |
5268 (1ull << MSR_EE) |
5269 (1ull << MSR_PR) |
5270 (1ull << MSR_FP) |
5271 (1ull << MSR_ME) |
5272 (1ull << MSR_FE0) |
5273 (1ull << MSR_DE) |
5274 (1ull << MSR_FE1) |
5275 (1ull << MSR_IR) |
5276 (1ull << MSR_DR) |
5277 (1ull << MSR_PX) |
5278 (1ull << MSR_RI);
5279 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5280 pcc->excp_model = POWERPC_EXCP_BOOKE;
5281 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5282 /* FIXME: figure out the correct flag for e500mc */
5283 pcc->bfd_mach = bfd_mach_ppc_e500;
5284 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5285 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5286 }
5287
5288 #ifdef TARGET_PPC64
5289 static void init_proc_e5500(CPUPPCState *env)
5290 {
5291 init_proc_e500(env, fsl_e5500);
5292 }
5293
5294 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5295 {
5296 DeviceClass *dc = DEVICE_CLASS(oc);
5297 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5298
5299 dc->desc = "e5500 core";
5300 pcc->init_proc = init_proc_e5500;
5301 pcc->check_pow = check_pow_none;
5302 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5303 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5304 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5305 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5306 PPC_FLOAT | PPC_FLOAT_FRES |
5307 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5308 PPC_FLOAT_STFIWX | PPC_WAIT |
5309 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5310 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5311 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5312 PPC2_FP_CVT_S64;
5313 pcc->msr_mask = (1ull << MSR_CM) |
5314 (1ull << MSR_GS) |
5315 (1ull << MSR_UCLE) |
5316 (1ull << MSR_CE) |
5317 (1ull << MSR_EE) |
5318 (1ull << MSR_PR) |
5319 (1ull << MSR_FP) |
5320 (1ull << MSR_ME) |
5321 (1ull << MSR_FE0) |
5322 (1ull << MSR_DE) |
5323 (1ull << MSR_FE1) |
5324 (1ull << MSR_IR) |
5325 (1ull << MSR_DR) |
5326 (1ull << MSR_PX) |
5327 (1ull << MSR_RI);
5328 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5329 pcc->excp_model = POWERPC_EXCP_BOOKE;
5330 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5331 /* FIXME: figure out the correct flag for e5500 */
5332 pcc->bfd_mach = bfd_mach_ppc_e500;
5333 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5334 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5335 }
5336
5337 static void init_proc_e6500(CPUPPCState *env)
5338 {
5339 init_proc_e500(env, fsl_e6500);
5340 }
5341
5342 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
5343 {
5344 DeviceClass *dc = DEVICE_CLASS(oc);
5345 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5346
5347 dc->desc = "e6500 core";
5348 pcc->init_proc = init_proc_e6500;
5349 pcc->check_pow = check_pow_none;
5350 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5351 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5352 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5353 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5354 PPC_FLOAT | PPC_FLOAT_FRES |
5355 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5356 PPC_FLOAT_STFIWX | PPC_WAIT |
5357 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5358 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
5359 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5360 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
5361 pcc->msr_mask = (1ull << MSR_CM) |
5362 (1ull << MSR_GS) |
5363 (1ull << MSR_UCLE) |
5364 (1ull << MSR_CE) |
5365 (1ull << MSR_EE) |
5366 (1ull << MSR_PR) |
5367 (1ull << MSR_FP) |
5368 (1ull << MSR_ME) |
5369 (1ull << MSR_FE0) |
5370 (1ull << MSR_DE) |
5371 (1ull << MSR_FE1) |
5372 (1ull << MSR_IS) |
5373 (1ull << MSR_DS) |
5374 (1ull << MSR_PX) |
5375 (1ull << MSR_RI) |
5376 (1ull << MSR_VR);
5377 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5378 pcc->excp_model = POWERPC_EXCP_BOOKE;
5379 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5380 pcc->bfd_mach = bfd_mach_ppc_e500;
5381 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5382 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
5383 }
5384
5385 #endif
5386
5387 /* Non-embedded PowerPC */
5388
5389 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5390
5391 static void init_proc_601(CPUPPCState *env)
5392 {
5393 gen_spr_ne_601(env);
5394 gen_spr_sdr1(env);
5395 gen_spr_601(env);
5396 /* Hardware implementation registers */
5397 /* XXX : not implemented */
5398 spr_register(env, SPR_HID0, "HID0",
5399 SPR_NOACCESS, SPR_NOACCESS,
5400 &spr_read_generic, &spr_write_hid0_601,
5401 0x80010080);
5402 /* XXX : not implemented */
5403 spr_register(env, SPR_HID1, "HID1",
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 &spr_read_generic, &spr_write_generic,
5406 0x00000000);
5407 /* XXX : not implemented */
5408 spr_register(env, SPR_601_HID2, "HID2",
5409 SPR_NOACCESS, SPR_NOACCESS,
5410 &spr_read_generic, &spr_write_generic,
5411 0x00000000);
5412 /* XXX : not implemented */
5413 spr_register(env, SPR_601_HID5, "HID5",
5414 SPR_NOACCESS, SPR_NOACCESS,
5415 &spr_read_generic, &spr_write_generic,
5416 0x00000000);
5417 /* Memory management */
5418 init_excp_601(env);
5419 /* XXX: beware that dcache line size is 64
5420 * but dcbz uses 32 bytes "sectors"
5421 * XXX: this breaks clcs instruction !
5422 */
5423 env->dcache_line_size = 32;
5424 env->icache_line_size = 64;
5425 /* Allocate hardware IRQ controller */
5426 ppc6xx_irq_init(ppc_env_get_cpu(env));
5427 }
5428
5429 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5430 {
5431 DeviceClass *dc = DEVICE_CLASS(oc);
5432 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5433
5434 dc->desc = "PowerPC 601";
5435 pcc->init_proc = init_proc_601;
5436 pcc->check_pow = check_pow_none;
5437 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5438 PPC_FLOAT |
5439 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5440 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5441 PPC_SEGMENT | PPC_EXTERN;
5442 pcc->msr_mask = (1ull << MSR_EE) |
5443 (1ull << MSR_PR) |
5444 (1ull << MSR_FP) |
5445 (1ull << MSR_ME) |
5446 (1ull << MSR_FE0) |
5447 (1ull << MSR_SE) |
5448 (1ull << MSR_FE1) |
5449 (1ull << MSR_EP) |
5450 (1ull << MSR_IR) |
5451 (1ull << MSR_DR);
5452 pcc->mmu_model = POWERPC_MMU_601;
5453 #if defined(CONFIG_SOFTMMU)
5454 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5455 #endif
5456 pcc->excp_model = POWERPC_EXCP_601;
5457 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5458 pcc->bfd_mach = bfd_mach_ppc_601;
5459 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5460 }
5461
5462 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5463
5464 static void init_proc_601v(CPUPPCState *env)
5465 {
5466 init_proc_601(env);
5467 /* XXX : not implemented */
5468 spr_register(env, SPR_601_HID15, "HID15",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 &spr_read_generic, &spr_write_generic,
5471 0x00000000);
5472 }
5473
5474 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5475 {
5476 DeviceClass *dc = DEVICE_CLASS(oc);
5477 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5478
5479 dc->desc = "PowerPC 601v";
5480 pcc->init_proc = init_proc_601v;
5481 pcc->check_pow = check_pow_none;
5482 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5483 PPC_FLOAT |
5484 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5485 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5486 PPC_SEGMENT | PPC_EXTERN;
5487 pcc->msr_mask = (1ull << MSR_EE) |
5488 (1ull << MSR_PR) |
5489 (1ull << MSR_FP) |
5490 (1ull << MSR_ME) |
5491 (1ull << MSR_FE0) |
5492 (1ull << MSR_SE) |
5493 (1ull << MSR_FE1) |
5494 (1ull << MSR_EP) |
5495 (1ull << MSR_IR) |
5496 (1ull << MSR_DR);
5497 pcc->mmu_model = POWERPC_MMU_601;
5498 #if defined(CONFIG_SOFTMMU)
5499 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5500 #endif
5501 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5502 pcc->bfd_mach = bfd_mach_ppc_601;
5503 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5504 }
5505
5506 static void init_proc_602(CPUPPCState *env)
5507 {
5508 gen_spr_ne_601(env);
5509 gen_spr_sdr1(env);
5510 gen_spr_602(env);
5511 /* Time base */
5512 gen_tbl(env);
5513 /* hardware implementation registers */
5514 /* XXX : not implemented */
5515 spr_register(env, SPR_HID0, "HID0",
5516 SPR_NOACCESS, SPR_NOACCESS,
5517 &spr_read_generic, &spr_write_generic,
5518 0x00000000);
5519 /* XXX : not implemented */
5520 spr_register(env, SPR_HID1, "HID1",
5521 SPR_NOACCESS, SPR_NOACCESS,
5522 &spr_read_generic, &spr_write_generic,
5523 0x00000000);
5524 /* Memory management */
5525 gen_low_BATs(env);
5526 gen_6xx_7xx_soft_tlb(env, 64, 2);
5527 init_excp_602(env);
5528 env->dcache_line_size = 32;
5529 env->icache_line_size = 32;
5530 /* Allocate hardware IRQ controller */
5531 ppc6xx_irq_init(ppc_env_get_cpu(env));
5532 }
5533
5534 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5535 {
5536 DeviceClass *dc = DEVICE_CLASS(oc);
5537 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5538
5539 dc->desc = "PowerPC 602";
5540 pcc->init_proc = init_proc_602;
5541 pcc->check_pow = check_pow_hid0;
5542 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5543 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5544 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5545 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5546 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5547 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5548 PPC_SEGMENT | PPC_602_SPEC;
5549 pcc->msr_mask = (1ull << MSR_VSX) |
5550 (1ull << MSR_SA) |
5551 (1ull << MSR_POW) |
5552 (1ull << MSR_TGPR) |
5553 (1ull << MSR_ILE) |
5554 (1ull << MSR_EE) |
5555 (1ull << MSR_PR) |
5556 (1ull << MSR_FP) |
5557 (1ull << MSR_ME) |
5558 (1ull << MSR_FE0) |
5559 (1ull << MSR_SE) |
5560 (1ull << MSR_DE) |
5561 (1ull << MSR_FE1) |
5562 (1ull << MSR_EP) |
5563 (1ull << MSR_IR) |
5564 (1ull << MSR_DR) |
5565 (1ull << MSR_RI) |
5566 (1ull << MSR_LE);
5567 /* XXX: 602 MMU is quite specific. Should add a special case */
5568 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5569 pcc->excp_model = POWERPC_EXCP_602;
5570 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5571 pcc->bfd_mach = bfd_mach_ppc_602;
5572 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5573 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5574 }
5575
5576 static void init_proc_603(CPUPPCState *env)
5577 {
5578 gen_spr_ne_601(env);
5579 gen_spr_sdr1(env);
5580 gen_spr_603(env);
5581 /* Time base */
5582 gen_tbl(env);
5583 /* hardware implementation registers */
5584 /* XXX : not implemented */
5585 spr_register(env, SPR_HID0, "HID0",
5586 SPR_NOACCESS, SPR_NOACCESS,
5587 &spr_read_generic, &spr_write_generic,
5588 0x00000000);
5589 /* XXX : not implemented */
5590 spr_register(env, SPR_HID1, "HID1",
5591 SPR_NOACCESS, SPR_NOACCESS,
5592 &spr_read_generic, &spr_write_generic,
5593 0x00000000);
5594 /* Memory management */
5595 gen_low_BATs(env);
5596 gen_6xx_7xx_soft_tlb(env, 64, 2);
5597 init_excp_603(env);
5598 env->dcache_line_size = 32;
5599 env->icache_line_size = 32;
5600 /* Allocate hardware IRQ controller */
5601 ppc6xx_irq_init(ppc_env_get_cpu(env));
5602 }
5603
5604 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5605 {
5606 DeviceClass *dc = DEVICE_CLASS(oc);
5607 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5608
5609 dc->desc = "PowerPC 603";
5610 pcc->init_proc = init_proc_603;
5611 pcc->check_pow = check_pow_hid0;
5612 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5613 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5614 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5615 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5616 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5617 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5618 PPC_SEGMENT | PPC_EXTERN;
5619 pcc->msr_mask = (1ull << MSR_POW) |
5620 (1ull << MSR_TGPR) |
5621 (1ull << MSR_ILE) |
5622 (1ull << MSR_EE) |
5623 (1ull << MSR_PR) |
5624 (1ull << MSR_FP) |
5625 (1ull << MSR_ME) |
5626 (1ull << MSR_FE0) |
5627 (1ull << MSR_SE) |
5628 (1ull << MSR_DE) |
5629 (1ull << MSR_FE1) |
5630 (1ull << MSR_EP) |
5631 (1ull << MSR_IR) |
5632 (1ull << MSR_DR) |
5633 (1ull << MSR_RI) |
5634 (1ull << MSR_LE);
5635 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5636 pcc->excp_model = POWERPC_EXCP_603;
5637 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5638 pcc->bfd_mach = bfd_mach_ppc_603;
5639 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5640 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5641 }
5642
5643 static void init_proc_603E(CPUPPCState *env)
5644 {
5645 gen_spr_ne_601(env);
5646 gen_spr_sdr1(env);
5647 gen_spr_603(env);
5648 /* Time base */
5649 gen_tbl(env);
5650 /* hardware implementation registers */
5651 /* XXX : not implemented */
5652 spr_register(env, SPR_HID0, "HID0",
5653 SPR_NOACCESS, SPR_NOACCESS,
5654 &spr_read_generic, &spr_write_generic,
5655 0x00000000);
5656 /* XXX : not implemented */
5657 spr_register(env, SPR_HID1, "HID1",
5658 SPR_NOACCESS, SPR_NOACCESS,
5659 &spr_read_generic, &spr_write_generic,
5660 0x00000000);
5661 /* Memory management */
5662 gen_low_BATs(env);
5663 gen_6xx_7xx_soft_tlb(env, 64, 2);
5664 init_excp_603(env);
5665 env->dcache_line_size = 32;
5666 env->icache_line_size = 32;
5667 /* Allocate hardware IRQ controller */
5668 ppc6xx_irq_init(ppc_env_get_cpu(env));
5669 }
5670
5671 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5672 {
5673 DeviceClass *dc = DEVICE_CLASS(oc);
5674 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5675
5676 dc->desc = "PowerPC 603e";
5677 pcc->init_proc = init_proc_603E;
5678 pcc->check_pow = check_pow_hid0;
5679 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5680 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5681 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5682 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5683 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5684 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5685 PPC_SEGMENT | PPC_EXTERN;
5686 pcc->msr_mask = (1ull << MSR_POW) |
5687 (1ull << MSR_TGPR) |
5688 (1ull << MSR_ILE) |
5689 (1ull << MSR_EE) |
5690 (1ull << MSR_PR) |
5691 (1ull << MSR_FP) |
5692 (1ull << MSR_ME) |
5693 (1ull << MSR_FE0) |
5694 (1ull << MSR_SE) |
5695 (1ull << MSR_DE) |
5696 (1ull << MSR_FE1) |
5697 (1ull << MSR_EP) |
5698 (1ull << MSR_IR) |
5699 (1ull << MSR_DR) |
5700 (1ull << MSR_RI) |
5701 (1ull << MSR_LE);
5702 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5703 pcc->excp_model = POWERPC_EXCP_603E;
5704 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5705 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5706 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5707 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5708 }
5709
5710 static void init_proc_604(CPUPPCState *env)
5711 {
5712 gen_spr_ne_601(env);
5713 gen_spr_sdr1(env);
5714 gen_spr_604(env);
5715 /* Time base */
5716 gen_tbl(env);
5717 /* Hardware implementation registers */
5718 /* XXX : not implemented */
5719 spr_register(env, SPR_HID0, "HID0",
5720 SPR_NOACCESS, SPR_NOACCESS,
5721 &spr_read_generic, &spr_write_generic,
5722 0x00000000);
5723 /* Memory management */
5724 gen_low_BATs(env);
5725 init_excp_604(env);
5726 env->dcache_line_size = 32;
5727 env->icache_line_size = 32;
5728 /* Allocate hardware IRQ controller */
5729 ppc6xx_irq_init(ppc_env_get_cpu(env));
5730 }
5731
5732 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5733 {
5734 DeviceClass *dc = DEVICE_CLASS(oc);
5735 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5736
5737 dc->desc = "PowerPC 604";
5738 pcc->init_proc = init_proc_604;
5739 pcc->check_pow = check_pow_nocheck;
5740 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5741 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5742 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5743 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5744 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5745 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5746 PPC_SEGMENT | PPC_EXTERN;
5747 pcc->msr_mask = (1ull << MSR_POW) |
5748 (1ull << MSR_ILE) |
5749 (1ull << MSR_EE) |
5750 (1ull << MSR_PR) |
5751 (1ull << MSR_FP) |
5752 (1ull << MSR_ME) |
5753 (1ull << MSR_FE0) |
5754 (1ull << MSR_SE) |
5755 (1ull << MSR_DE) |
5756 (1ull << MSR_FE1) |
5757 (1ull << MSR_EP) |
5758 (1ull << MSR_IR) |
5759 (1ull << MSR_DR) |
5760 (1ull << MSR_PMM) |
5761 (1ull << MSR_RI) |
5762 (1ull << MSR_LE);
5763 pcc->mmu_model = POWERPC_MMU_32B;
5764 #if defined(CONFIG_SOFTMMU)
5765 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5766 #endif
5767 pcc->excp_model = POWERPC_EXCP_604;
5768 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5769 pcc->bfd_mach = bfd_mach_ppc_604;
5770 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5771 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5772 }
5773
5774 static void init_proc_604E(CPUPPCState *env)
5775 {
5776 gen_spr_ne_601(env);
5777 gen_spr_sdr1(env);
5778 gen_spr_604(env);
5779 /* XXX : not implemented */
5780 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x00000000);
5784 /* XXX : not implemented */
5785 spr_register(env, SPR_7XX_PMC3, "PMC3",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 0x00000000);
5789 /* XXX : not implemented */
5790 spr_register(env, SPR_7XX_PMC4, "PMC4",
5791 SPR_NOACCESS, SPR_NOACCESS,
5792 &spr_read_generic, &spr_write_generic,
5793 0x00000000);
5794 /* Time base */
5795 gen_tbl(env);
5796 /* Hardware implementation registers */
5797 /* XXX : not implemented */
5798 spr_register(env, SPR_HID0, "HID0",
5799 SPR_NOACCESS, SPR_NOACCESS,
5800 &spr_read_generic, &spr_write_generic,
5801 0x00000000);
5802 /* XXX : not implemented */
5803 spr_register(env, SPR_HID1, "HID1",
5804 SPR_NOACCESS, SPR_NOACCESS,
5805 &spr_read_generic, &spr_write_generic,
5806 0x00000000);
5807 /* Memory management */
5808 gen_low_BATs(env);
5809 init_excp_604(env);
5810 env->dcache_line_size = 32;
5811 env->icache_line_size = 32;
5812 /* Allocate hardware IRQ controller */
5813 ppc6xx_irq_init(ppc_env_get_cpu(env));
5814 }
5815
5816 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5817 {
5818 DeviceClass *dc = DEVICE_CLASS(oc);
5819 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5820
5821 dc->desc = "PowerPC 604E";
5822 pcc->init_proc = init_proc_604E;
5823 pcc->check_pow = check_pow_nocheck;
5824 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5825 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5826 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5827 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5828 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5829 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5830 PPC_SEGMENT | PPC_EXTERN;
5831 pcc->msr_mask = (1ull << MSR_POW) |
5832 (1ull << MSR_ILE) |
5833 (1ull << MSR_EE) |
5834 (1ull << MSR_PR) |
5835 (1ull << MSR_FP) |
5836 (1ull << MSR_ME) |
5837 (1ull << MSR_FE0) |
5838 (1ull << MSR_SE) |
5839 (1ull << MSR_DE) |
5840 (1ull << MSR_FE1) |
5841 (1ull << MSR_EP) |
5842 (1ull << MSR_IR) |
5843 (1ull << MSR_DR) |
5844 (1ull << MSR_PMM) |
5845 (1ull << MSR_RI) |
5846 (1ull << MSR_LE);
5847 pcc->mmu_model = POWERPC_MMU_32B;
5848 #if defined(CONFIG_SOFTMMU)
5849 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5850 #endif
5851 pcc->excp_model = POWERPC_EXCP_604;
5852 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5853 pcc->bfd_mach = bfd_mach_ppc_604;
5854 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5855 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5856 }
5857
5858 static void init_proc_740(CPUPPCState *env)
5859 {
5860 gen_spr_ne_601(env);
5861 gen_spr_sdr1(env);
5862 gen_spr_7xx(env);
5863 /* Time base */
5864 gen_tbl(env);
5865 /* Thermal management */
5866 gen_spr_thrm(env);
5867 /* Hardware implementation registers */
5868 /* XXX : not implemented */
5869 spr_register(env, SPR_HID0, "HID0",
5870 SPR_NOACCESS, SPR_NOACCESS,
5871 &spr_read_generic, &spr_write_generic,
5872 0x00000000);
5873 /* XXX : not implemented */
5874 spr_register(env, SPR_HID1, "HID1",
5875 SPR_NOACCESS, SPR_NOACCESS,
5876 &spr_read_generic, &spr_write_generic,
5877 0x00000000);
5878 /* Memory management */
5879 gen_low_BATs(env);
5880 init_excp_7x0(env);
5881 env->dcache_line_size = 32;
5882 env->icache_line_size = 32;
5883 /* Allocate hardware IRQ controller */
5884 ppc6xx_irq_init(ppc_env_get_cpu(env));
5885 }
5886
5887 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5888 {
5889 DeviceClass *dc = DEVICE_CLASS(oc);
5890 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5891
5892 dc->desc = "PowerPC 740";
5893 pcc->init_proc = init_proc_740;
5894 pcc->check_pow = check_pow_hid0;
5895 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5896 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5897 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5898 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5899 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5900 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5901 PPC_SEGMENT | PPC_EXTERN;
5902 pcc->msr_mask = (1ull << MSR_POW) |
5903 (1ull << MSR_ILE) |
5904 (1ull << MSR_EE) |
5905 (1ull << MSR_PR) |
5906 (1ull << MSR_FP) |
5907 (1ull << MSR_ME) |
5908 (1ull << MSR_FE0) |
5909 (1ull << MSR_SE) |
5910 (1ull << MSR_DE) |
5911 (1ull << MSR_FE1) |
5912 (1ull << MSR_EP) |
5913 (1ull << MSR_IR) |
5914 (1ull << MSR_DR) |
5915 (1ull << MSR_PMM) |
5916 (1ull << MSR_RI) |
5917 (1ull << MSR_LE);
5918 pcc->mmu_model = POWERPC_MMU_32B;
5919 #if defined(CONFIG_SOFTMMU)
5920 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5921 #endif
5922 pcc->excp_model = POWERPC_EXCP_7x0;
5923 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5924 pcc->bfd_mach = bfd_mach_ppc_750;
5925 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5926 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5927 }
5928
5929 static void init_proc_750(CPUPPCState *env)
5930 {
5931 gen_spr_ne_601(env);
5932 gen_spr_sdr1(env);
5933 gen_spr_7xx(env);
5934 /* XXX : not implemented */
5935 spr_register(env, SPR_L2CR, "L2CR",
5936 SPR_NOACCESS, SPR_NOACCESS,
5937 &spr_read_generic, spr_access_nop,
5938 0x00000000);
5939 /* Time base */
5940 gen_tbl(env);
5941 /* Thermal management */
5942 gen_spr_thrm(env);
5943 /* Hardware implementation registers */
5944 /* XXX : not implemented */
5945 spr_register(env, SPR_HID0, "HID0",
5946 SPR_NOACCESS, SPR_NOACCESS,
5947 &spr_read_generic, &spr_write_generic,
5948 0x00000000);
5949 /* XXX : not implemented */
5950 spr_register(env, SPR_HID1, "HID1",
5951 SPR_NOACCESS, SPR_NOACCESS,
5952 &spr_read_generic, &spr_write_generic,
5953 0x00000000);
5954 /* Memory management */
5955 gen_low_BATs(env);
5956 /* XXX: high BATs are also present but are known to be bugged on
5957 * die version 1.x
5958 */
5959 init_excp_7x0(env);
5960 env->dcache_line_size = 32;
5961 env->icache_line_size = 32;
5962 /* Allocate hardware IRQ controller */
5963 ppc6xx_irq_init(ppc_env_get_cpu(env));
5964 }
5965
5966 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5967 {
5968 DeviceClass *dc = DEVICE_CLASS(oc);
5969 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5970
5971 dc->desc = "PowerPC 750";
5972 pcc->init_proc = init_proc_750;
5973 pcc->check_pow = check_pow_hid0;
5974 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5975 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5976 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5977 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5978 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5979 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5980 PPC_SEGMENT | PPC_EXTERN;
5981 pcc->msr_mask = (1ull << MSR_POW) |
5982 (1ull << MSR_ILE) |
5983 (1ull << MSR_EE) |
5984 (1ull << MSR_PR) |
5985 (1ull << MSR_FP) |
5986 (1ull << MSR_ME) |
5987 (1ull << MSR_FE0) |
5988 (1ull << MSR_SE) |
5989 (1ull << MSR_DE) |
5990 (1ull << MSR_FE1) |
5991 (1ull << MSR_EP) |
5992 (1ull << MSR_IR) |
5993 (1ull << MSR_DR) |
5994 (1ull << MSR_PMM) |
5995 (1ull << MSR_RI) |
5996 (1ull << MSR_LE);
5997 pcc->mmu_model = POWERPC_MMU_32B;
5998 #if defined(CONFIG_SOFTMMU)
5999 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6000 #endif
6001 pcc->excp_model = POWERPC_EXCP_7x0;
6002 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6003 pcc->bfd_mach = bfd_mach_ppc_750;
6004 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6005 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6006 }
6007
6008 static void init_proc_750cl(CPUPPCState *env)
6009 {
6010 gen_spr_ne_601(env);
6011 gen_spr_sdr1(env);
6012 gen_spr_7xx(env);
6013 /* XXX : not implemented */
6014 spr_register(env, SPR_L2CR, "L2CR",
6015 SPR_NOACCESS, SPR_NOACCESS,
6016 &spr_read_generic, spr_access_nop,
6017 0x00000000);
6018 /* Time base */
6019 gen_tbl(env);
6020 /* Thermal management */
6021 /* Those registers are fake on 750CL */
6022 spr_register(env, SPR_THRM1, "THRM1",
6023 SPR_NOACCESS, SPR_NOACCESS,
6024 &spr_read_generic, &spr_write_generic,
6025 0x00000000);
6026 spr_register(env, SPR_THRM2, "THRM2",
6027 SPR_NOACCESS, SPR_NOACCESS,
6028 &spr_read_generic, &spr_write_generic,
6029 0x00000000);
6030 spr_register(env, SPR_THRM3, "THRM3",
6031 SPR_NOACCESS, SPR_NOACCESS,
6032 &spr_read_generic, &spr_write_generic,
6033 0x00000000);
6034 /* XXX: not implemented */
6035 spr_register(env, SPR_750_TDCL, "TDCL",
6036 SPR_NOACCESS, SPR_NOACCESS,
6037 &spr_read_generic, &spr_write_generic,
6038 0x00000000);
6039 spr_register(env, SPR_750_TDCH, "TDCH",
6040 SPR_NOACCESS, SPR_NOACCESS,
6041 &spr_read_generic, &spr_write_generic,
6042 0x00000000);
6043 /* DMA */
6044 /* XXX : not implemented */
6045 spr_register(env, SPR_750_WPAR, "WPAR",
6046 SPR_NOACCESS, SPR_NOACCESS,
6047 &spr_read_generic, &spr_write_generic,
6048 0x00000000);
6049 spr_register(env, SPR_750_DMAL, "DMAL",
6050 SPR_NOACCESS, SPR_NOACCESS,
6051 &spr_read_generic, &spr_write_generic,
6052 0x00000000);
6053 spr_register(env, SPR_750_DMAU, "DMAU",
6054 SPR_NOACCESS, SPR_NOACCESS,
6055 &spr_read_generic, &spr_write_generic,
6056 0x00000000);
6057 /* Hardware implementation registers */
6058 /* XXX : not implemented */
6059 spr_register(env, SPR_HID0, "HID0",
6060 SPR_NOACCESS, SPR_NOACCESS,
6061 &spr_read_generic, &spr_write_generic,
6062 0x00000000);
6063 /* XXX : not implemented */
6064 spr_register(env, SPR_HID1, "HID1",
6065 SPR_NOACCESS, SPR_NOACCESS,
6066 &spr_read_generic, &spr_write_generic,
6067 0x00000000);
6068 /* XXX : not implemented */
6069 spr_register(env, SPR_750CL_HID2, "HID2",
6070 SPR_NOACCESS, SPR_NOACCESS,
6071 &spr_read_generic, &spr_write_generic,
6072 0x00000000);
6073 /* XXX : not implemented */
6074 spr_register(env, SPR_750CL_HID4, "HID4",
6075 SPR_NOACCESS, SPR_NOACCESS,
6076 &spr_read_generic, &spr_write_generic,
6077 0x00000000);
6078 /* Quantization registers */
6079 /* XXX : not implemented */
6080 spr_register(env, SPR_750_GQR0, "GQR0",
6081 SPR_NOACCESS, SPR_NOACCESS,
6082 &spr_read_generic, &spr_write_generic,
6083 0x00000000);
6084 /* XXX : not implemented */
6085 spr_register(env, SPR_750_GQR1, "GQR1",
6086 SPR_NOACCESS, SPR_NOACCESS,
6087 &spr_read_generic, &spr_write_generic,
6088 0x00000000);
6089 /* XXX : not implemented */
6090 spr_register(env, SPR_750_GQR2, "GQR2",
6091 SPR_NOACCESS, SPR_NOACCESS,
6092 &spr_read_generic, &spr_write_generic,
6093 0x00000000);
6094 /* XXX : not implemented */
6095 spr_register(env, SPR_750_GQR3, "GQR3",
6096 SPR_NOACCESS, SPR_NOACCESS,
6097 &spr_read_generic, &spr_write_generic,
6098 0x00000000);
6099 /* XXX : not implemented */
6100 spr_register(env, SPR_750_GQR4, "GQR4",
6101 SPR_NOACCESS, SPR_NOACCESS,
6102 &spr_read_generic, &spr_write_generic,
6103 0x00000000);
6104 /* XXX : not implemented */
6105 spr_register(env, SPR_750_GQR5, "GQR5",
6106 SPR_NOACCESS, SPR_NOACCESS,
6107 &spr_read_generic, &spr_write_generic,
6108 0x00000000);
6109 /* XXX : not implemented */
6110 spr_register(env, SPR_750_GQR6, "GQR6",
6111 SPR_NOACCESS, SPR_NOACCESS,
6112 &spr_read_generic, &spr_write_generic,
6113 0x00000000);
6114 /* XXX : not implemented */
6115 spr_register(env, SPR_750_GQR7, "GQR7",
6116 SPR_NOACCESS, SPR_NOACCESS,
6117 &spr_read_generic, &spr_write_generic,
6118 0x00000000);
6119 /* Memory management */
6120 gen_low_BATs(env);
6121 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
6122 gen_high_BATs(env);
6123 init_excp_750cl(env);
6124 env->dcache_line_size = 32;
6125 env->icache_line_size = 32;
6126 /* Allocate hardware IRQ controller */
6127 ppc6xx_irq_init(ppc_env_get_cpu(env));
6128 }
6129
6130 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
6131 {
6132 DeviceClass *dc = DEVICE_CLASS(oc);
6133 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6134
6135 dc->desc = "PowerPC 750 CL";
6136 pcc->init_proc = init_proc_750cl;
6137 pcc->check_pow = check_pow_hid0;
6138 /* XXX: not implemented:
6139 * cache lock instructions:
6140 * dcbz_l
6141 * floating point paired instructions
6142 * psq_lux
6143 * psq_lx
6144 * psq_stux
6145 * psq_stx
6146 * ps_abs
6147 * ps_add
6148 * ps_cmpo0
6149 * ps_cmpo1
6150 * ps_cmpu0
6151 * ps_cmpu1
6152 * ps_div
6153 * ps_madd
6154 * ps_madds0
6155 * ps_madds1
6156 * ps_merge00
6157 * ps_merge01
6158 * ps_merge10
6159 * ps_merge11
6160 * ps_mr
6161 * ps_msub
6162 * ps_mul
6163 * ps_muls0
6164 * ps_muls1
6165 * ps_nabs
6166 * ps_neg
6167 * ps_nmadd
6168 * ps_nmsub
6169 * ps_res
6170 * ps_rsqrte
6171 * ps_sel
6172 * ps_sub
6173 * ps_sum0
6174 * ps_sum1
6175 */
6176 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6177 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6178 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6179 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6180 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6181 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6182 PPC_SEGMENT | PPC_EXTERN;
6183 pcc->msr_mask = (1ull << MSR_POW) |
6184 (1ull << MSR_ILE) |
6185 (1ull << MSR_EE) |
6186 (1ull << MSR_PR) |
6187 (1ull << MSR_FP) |
6188 (1ull << MSR_ME) |
6189 (1ull << MSR_FE0) |
6190 (1ull << MSR_SE) |
6191 (1ull << MSR_DE) |
6192 (1ull << MSR_FE1) |
6193 (1ull << MSR_EP) |
6194 (1ull << MSR_IR) |
6195 (1ull << MSR_DR) |
6196 (1ull << MSR_PMM) |
6197 (1ull << MSR_RI) |
6198 (1ull << MSR_LE);
6199 pcc->mmu_model = POWERPC_MMU_32B;
6200 #if defined(CONFIG_SOFTMMU)
6201 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6202 #endif
6203 pcc->excp_model = POWERPC_EXCP_7x0;
6204 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6205 pcc->bfd_mach = bfd_mach_ppc_750;
6206 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6207 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6208 }
6209
6210 static void init_proc_750cx(CPUPPCState *env)
6211 {
6212 gen_spr_ne_601(env);
6213 gen_spr_sdr1(env);
6214 gen_spr_7xx(env);
6215 /* XXX : not implemented */
6216 spr_register(env, SPR_L2CR, "L2CR",
6217 SPR_NOACCESS, SPR_NOACCESS,
6218 &spr_read_generic, spr_access_nop,
6219 0x00000000);
6220 /* Time base */
6221 gen_tbl(env);
6222 /* Thermal management */
6223 gen_spr_thrm(env);
6224 /* This register is not implemented but is present for compatibility */
6225 spr_register(env, SPR_SDA, "SDA",
6226 SPR_NOACCESS, SPR_NOACCESS,
6227 &spr_read_generic, &spr_write_generic,
6228 0x00000000);
6229 /* Hardware implementation registers */
6230 /* XXX : not implemented */
6231 spr_register(env, SPR_HID0, "HID0",
6232 SPR_NOACCESS, SPR_NOACCESS,
6233 &spr_read_generic, &spr_write_generic,
6234 0x00000000);
6235 /* XXX : not implemented */
6236 spr_register(env, SPR_HID1, "HID1",
6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
6240 /* Memory management */
6241 gen_low_BATs(env);
6242 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6243 gen_high_BATs(env);
6244 init_excp_750cx(env);
6245 env->dcache_line_size = 32;
6246 env->icache_line_size = 32;
6247 /* Allocate hardware IRQ controller */
6248 ppc6xx_irq_init(ppc_env_get_cpu(env));
6249 }
6250
6251 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6252 {
6253 DeviceClass *dc = DEVICE_CLASS(oc);
6254 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6255
6256 dc->desc = "PowerPC 750CX";
6257 pcc->init_proc = init_proc_750cx;
6258 pcc->check_pow = check_pow_hid0;
6259 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6260 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6261 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6262 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6263 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6264 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6265 PPC_SEGMENT | PPC_EXTERN;
6266 pcc->msr_mask = (1ull << MSR_POW) |
6267 (1ull << MSR_ILE) |
6268 (1ull << MSR_EE) |
6269 (1ull << MSR_PR) |
6270 (1ull << MSR_FP) |
6271 (1ull << MSR_ME) |
6272 (1ull << MSR_FE0) |
6273 (1ull << MSR_SE) |
6274 (1ull << MSR_DE) |
6275 (1ull << MSR_FE1) |
6276 (1ull << MSR_EP) |
6277 (1ull << MSR_IR) |
6278 (1ull << MSR_DR) |
6279 (1ull << MSR_PMM) |
6280 (1ull << MSR_RI) |
6281 (1ull << MSR_LE);
6282 pcc->mmu_model = POWERPC_MMU_32B;
6283 #if defined(CONFIG_SOFTMMU)
6284 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6285 #endif
6286 pcc->excp_model = POWERPC_EXCP_7x0;
6287 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6288 pcc->bfd_mach = bfd_mach_ppc_750;
6289 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6290 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6291 }
6292
6293 static void init_proc_750fx(CPUPPCState *env)
6294 {
6295 gen_spr_ne_601(env);
6296 gen_spr_sdr1(env);
6297 gen_spr_7xx(env);
6298 /* XXX : not implemented */
6299 spr_register(env, SPR_L2CR, "L2CR",
6300 SPR_NOACCESS, SPR_NOACCESS,
6301 &spr_read_generic, spr_access_nop,
6302 0x00000000);
6303 /* Time base */
6304 gen_tbl(env);
6305 /* Thermal management */
6306 gen_spr_thrm(env);
6307 /* XXX : not implemented */
6308 spr_register(env, SPR_750_THRM4, "THRM4",
6309 SPR_NOACCESS, SPR_NOACCESS,
6310 &spr_read_generic, &spr_write_generic,
6311 0x00000000);
6312 /* Hardware implementation registers */
6313 /* XXX : not implemented */
6314 spr_register(env, SPR_HID0, "HID0",
6315 SPR_NOACCESS, SPR_NOACCESS,
6316 &spr_read_generic, &spr_write_generic,
6317 0x00000000);
6318 /* XXX : not implemented */
6319 spr_register(env, SPR_HID1, "HID1",
6320 SPR_NOACCESS, SPR_NOACCESS,
6321 &spr_read_generic, &spr_write_generic,
6322 0x00000000);
6323 /* XXX : not implemented */
6324 spr_register(env, SPR_750FX_HID2, "HID2",
6325 SPR_NOACCESS, SPR_NOACCESS,
6326 &spr_read_generic, &spr_write_generic,
6327 0x00000000);
6328 /* Memory management */
6329 gen_low_BATs(env);
6330 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6331 gen_high_BATs(env);
6332 init_excp_7x0(env);
6333 env->dcache_line_size = 32;
6334 env->icache_line_size = 32;
6335 /* Allocate hardware IRQ controller */
6336 ppc6xx_irq_init(ppc_env_get_cpu(env));
6337 }
6338
6339 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6340 {
6341 DeviceClass *dc = DEVICE_CLASS(oc);
6342 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6343
6344 dc->desc = "PowerPC 750FX";
6345 pcc->init_proc = init_proc_750fx;
6346 pcc->check_pow = check_pow_hid0;
6347 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6348 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6349 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6350 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6351 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6352 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6353 PPC_SEGMENT | PPC_EXTERN;
6354 pcc->msr_mask = (1ull << MSR_POW) |
6355 (1ull << MSR_ILE) |
6356 (1ull << MSR_EE) |
6357 (1ull << MSR_PR) |
6358 (1ull << MSR_FP) |
6359 (1ull << MSR_ME) |
6360 (1ull << MSR_FE0) |
6361 (1ull << MSR_SE) |
6362 (1ull << MSR_DE) |
6363 (1ull << MSR_FE1) |
6364 (1ull << MSR_EP) |
6365 (1ull << MSR_IR) |
6366 (1ull << MSR_DR) |
6367 (1ull << MSR_PMM) |
6368 (1ull << MSR_RI) |
6369 (1ull << MSR_LE);
6370 pcc->mmu_model = POWERPC_MMU_32B;
6371 #if defined(CONFIG_SOFTMMU)
6372 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6373 #endif
6374 pcc->excp_model = POWERPC_EXCP_7x0;
6375 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6376 pcc->bfd_mach = bfd_mach_ppc_750;
6377 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6378 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6379 }
6380
6381 static void init_proc_750gx(CPUPPCState *env)
6382 {
6383 gen_spr_ne_601(env);
6384 gen_spr_sdr1(env);
6385 gen_spr_7xx(env);
6386 /* XXX : not implemented (XXX: different from 750fx) */
6387 spr_register(env, SPR_L2CR, "L2CR",
6388 SPR_NOACCESS, SPR_NOACCESS,
6389 &spr_read_generic, spr_access_nop,
6390 0x00000000);
6391 /* Time base */
6392 gen_tbl(env);
6393 /* Thermal management */
6394 gen_spr_thrm(env);
6395 /* XXX : not implemented */
6396 spr_register(env, SPR_750_THRM4, "THRM4",
6397 SPR_NOACCESS, SPR_NOACCESS,
6398 &spr_read_generic, &spr_write_generic,
6399 0x00000000);
6400 /* Hardware implementation registers */
6401 /* XXX : not implemented (XXX: different from 750fx) */
6402 spr_register(env, SPR_HID0, "HID0",
6403 SPR_NOACCESS, SPR_NOACCESS,
6404 &spr_read_generic, &spr_write_generic,
6405 0x00000000);
6406 /* XXX : not implemented */
6407 spr_register(env, SPR_HID1, "HID1",
6408 SPR_NOACCESS, SPR_NOACCESS,
6409 &spr_read_generic, &spr_write_generic,
6410 0x00000000);
6411 /* XXX : not implemented (XXX: different from 750fx) */
6412 spr_register(env, SPR_750FX_HID2, "HID2",
6413 SPR_NOACCESS, SPR_NOACCESS,
6414 &spr_read_generic, &spr_write_generic,
6415 0x00000000);
6416 /* Memory management */
6417 gen_low_BATs(env);
6418 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6419 gen_high_BATs(env);
6420 init_excp_7x0(env);
6421 env->dcache_line_size = 32;
6422 env->icache_line_size = 32;
6423 /* Allocate hardware IRQ controller */
6424 ppc6xx_irq_init(ppc_env_get_cpu(env));
6425 }
6426
6427 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6428 {
6429 DeviceClass *dc = DEVICE_CLASS(oc);
6430 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6431
6432 dc->desc = "PowerPC 750GX";
6433 pcc->init_proc = init_proc_750gx;
6434 pcc->check_pow = check_pow_hid0;
6435 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6436 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6437 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6438 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6439 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6440 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6441 PPC_SEGMENT | PPC_EXTERN;
6442 pcc->msr_mask = (1ull << MSR_POW) |
6443 (1ull << MSR_ILE) |
6444 (1ull << MSR_EE) |
6445 (1ull << MSR_PR) |
6446 (1ull << MSR_FP) |
6447 (1ull << MSR_ME) |
6448 (1ull << MSR_FE0) |
6449 (1ull << MSR_SE) |
6450 (1ull << MSR_DE) |
6451 (1ull << MSR_FE1) |
6452 (1ull << MSR_EP) |
6453 (1ull << MSR_IR) |
6454 (1ull << MSR_DR) |
6455 (1ull << MSR_PMM) |
6456 (1ull << MSR_RI) |
6457 (1ull << MSR_LE);
6458 pcc->mmu_model = POWERPC_MMU_32B;
6459 #if defined(CONFIG_SOFTMMU)
6460 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6461 #endif
6462 pcc->excp_model = POWERPC_EXCP_7x0;
6463 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6464 pcc->bfd_mach = bfd_mach_ppc_750;
6465 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6466 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6467 }
6468
6469 static void init_proc_745(CPUPPCState *env)
6470 {
6471 gen_spr_ne_601(env);
6472 gen_spr_sdr1(env);
6473 gen_spr_7xx(env);
6474 gen_spr_G2_755(env);
6475 /* Time base */
6476 gen_tbl(env);
6477 /* Thermal management */
6478 gen_spr_thrm(env);
6479 /* Hardware implementation registers */
6480 /* XXX : not implemented */
6481 spr_register(env, SPR_HID0, "HID0",
6482 SPR_NOACCESS, SPR_NOACCESS,
6483 &spr_read_generic, &spr_write_generic,
6484 0x00000000);
6485 /* XXX : not implemented */
6486 spr_register(env, SPR_HID1, "HID1",
6487 SPR_NOACCESS, SPR_NOACCESS,
6488 &spr_read_generic, &spr_write_generic,
6489 0x00000000);
6490 /* XXX : not implemented */
6491 spr_register(env, SPR_HID2, "HID2",
6492 SPR_NOACCESS, SPR_NOACCESS,
6493 &spr_read_generic, &spr_write_generic,
6494 0x00000000);
6495 /* Memory management */
6496 gen_low_BATs(env);
6497 gen_high_BATs(env);
6498 gen_6xx_7xx_soft_tlb(env, 64, 2);
6499 init_excp_7x5(env);
6500 env->dcache_line_size = 32;
6501 env->icache_line_size = 32;
6502 /* Allocate hardware IRQ controller */
6503 ppc6xx_irq_init(ppc_env_get_cpu(env));
6504 }
6505
6506 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6507 {
6508 DeviceClass *dc = DEVICE_CLASS(oc);
6509 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6510
6511 dc->desc = "PowerPC 745";
6512 pcc->init_proc = init_proc_745;
6513 pcc->check_pow = check_pow_hid0;
6514 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6515 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6516 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6517 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6518 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6519 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6520 PPC_SEGMENT | PPC_EXTERN;
6521 pcc->msr_mask = (1ull << MSR_POW) |
6522 (1ull << MSR_ILE) |
6523 (1ull << MSR_EE) |
6524 (1ull << MSR_PR) |
6525 (1ull << MSR_FP) |
6526 (1ull << MSR_ME) |
6527 (1ull << MSR_FE0) |
6528 (1ull << MSR_SE) |
6529 (1ull << MSR_DE) |
6530 (1ull << MSR_FE1) |
6531 (1ull << MSR_EP) |
6532 (1ull << MSR_IR) |
6533 (1ull << MSR_DR) |
6534 (1ull << MSR_PMM) |
6535 (1ull << MSR_RI) |
6536 (1ull << MSR_LE);
6537 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6538 pcc->excp_model = POWERPC_EXCP_7x5;
6539 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6540 pcc->bfd_mach = bfd_mach_ppc_750;
6541 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6542 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6543 }
6544
6545 static void init_proc_755(CPUPPCState *env)
6546 {
6547 gen_spr_ne_601(env);
6548 gen_spr_sdr1(env);
6549 gen_spr_7xx(env);
6550 gen_spr_G2_755(env);
6551 /* Time base */
6552 gen_tbl(env);
6553 /* L2 cache control */
6554 /* XXX : not implemented */
6555 spr_register(env, SPR_L2CR, "L2CR",
6556 SPR_NOACCESS, SPR_NOACCESS,
6557 &spr_read_generic, spr_access_nop,
6558 0x00000000);
6559 /* XXX : not implemented */
6560 spr_register(env, SPR_L2PMCR, "L2PMCR",
6561 SPR_NOACCESS, SPR_NOACCESS,
6562 &spr_read_generic, &spr_write_generic,
6563 0x00000000);
6564 /* Thermal management */
6565 gen_spr_thrm(env);
6566 /* Hardware implementation registers */
6567 /* XXX : not implemented */
6568 spr_register(env, SPR_HID0, "HID0",
6569 SPR_NOACCESS, SPR_NOACCESS,
6570 &spr_read_generic, &spr_write_generic,
6571 0x00000000);
6572 /* XXX : not implemented */
6573 spr_register(env, SPR_HID1, "HID1",
6574 SPR_NOACCESS, SPR_NOACCESS,
6575 &spr_read_generic, &spr_write_generic,
6576 0x00000000);
6577 /* XXX : not implemented */
6578 spr_register(env, SPR_HID2, "HID2",
6579 SPR_NOACCESS, SPR_NOACCESS,
6580 &spr_read_generic, &spr_write_generic,
6581 0x00000000);
6582 /* Memory management */
6583 gen_low_BATs(env);
6584 gen_high_BATs(env);
6585 gen_6xx_7xx_soft_tlb(env, 64, 2);
6586 init_excp_7x5(env);
6587 env->dcache_line_size = 32;
6588 env->icache_line_size = 32;
6589 /* Allocate hardware IRQ controller */
6590 ppc6xx_irq_init(ppc_env_get_cpu(env));
6591 }
6592
6593 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6594 {
6595 DeviceClass *dc = DEVICE_CLASS(oc);
6596 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6597
6598 dc->desc = "PowerPC 755";
6599 pcc->init_proc = init_proc_755;
6600 pcc->check_pow = check_pow_hid0;
6601 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6602 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6603 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6604 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6605 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6606 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6607 PPC_SEGMENT | PPC_EXTERN;
6608 pcc->msr_mask = (1ull << MSR_POW) |
6609 (1ull << MSR_ILE) |
6610 (1ull << MSR_EE) |
6611 (1ull << MSR_PR) |
6612 (1ull << MSR_FP) |
6613 (1ull << MSR_ME) |
6614 (1ull << MSR_FE0) |
6615 (1ull << MSR_SE) |
6616 (1ull << MSR_DE) |
6617 (1ull << MSR_FE1) |
6618 (1ull << MSR_EP) |
6619 (1ull << MSR_IR) |
6620 (1ull << MSR_DR) |
6621 (1ull << MSR_PMM) |
6622 (1ull << MSR_RI) |
6623 (1ull << MSR_LE);
6624 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6625 pcc->excp_model = POWERPC_EXCP_7x5;
6626 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6627 pcc->bfd_mach = bfd_mach_ppc_750;
6628 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6629 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6630 }
6631
6632 static void init_proc_7400(CPUPPCState *env)
6633 {
6634 gen_spr_ne_601(env);
6635 gen_spr_sdr1(env);
6636 gen_spr_7xx(env);
6637 /* Time base */
6638 gen_tbl(env);
6639 /* 74xx specific SPR */
6640 gen_spr_74xx(env);
6641 /* XXX : not implemented */
6642 spr_register(env, SPR_UBAMR, "UBAMR",
6643 &spr_read_ureg, SPR_NOACCESS,
6644 &spr_read_ureg, SPR_NOACCESS,
6645 0x00000000);
6646 /* XXX: this seems not implemented on all revisions. */
6647 /* XXX : not implemented */
6648 spr_register(env, SPR_MSSCR1, "MSSCR1",
6649 SPR_NOACCESS, SPR_NOACCESS,
6650 &spr_read_generic, &spr_write_generic,
6651 0x00000000);
6652 /* Thermal management */
6653 gen_spr_thrm(env);
6654 /* Memory management */
6655 gen_low_BATs(env);
6656 init_excp_7400(env);
6657 env->dcache_line_size = 32;
6658 env->icache_line_size = 32;
6659 /* Allocate hardware IRQ controller */
6660 ppc6xx_irq_init(ppc_env_get_cpu(env));
6661 }
6662
6663 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6664 {
6665 DeviceClass *dc = DEVICE_CLASS(oc);
6666 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6667
6668 dc->desc = "PowerPC 7400 (aka G4)";
6669 pcc->init_proc = init_proc_7400;
6670 pcc->check_pow = check_pow_hid0;
6671 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6672 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6673 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6674 PPC_FLOAT_STFIWX |
6675 PPC_CACHE | PPC_CACHE_ICBI |
6676 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6677 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6678 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6679 PPC_MEM_TLBIA |
6680 PPC_SEGMENT | PPC_EXTERN |
6681 PPC_ALTIVEC;
6682 pcc->msr_mask = (1ull << MSR_VR) |
6683 (1ull << MSR_POW) |
6684 (1ull << MSR_ILE) |
6685 (1ull << MSR_EE) |
6686 (1ull << MSR_PR) |
6687 (1ull << MSR_FP) |
6688 (1ull << MSR_ME) |
6689 (1ull << MSR_FE0) |
6690 (1ull << MSR_SE) |
6691 (1ull << MSR_DE) |
6692 (1ull << MSR_FE1) |
6693 (1ull << MSR_EP) |
6694 (1ull << MSR_IR) |
6695 (1ull << MSR_DR) |
6696 (1ull << MSR_PMM) |
6697 (1ull << MSR_RI) |
6698 (1ull << MSR_LE);
6699 pcc->mmu_model = POWERPC_MMU_32B;
6700 #if defined(CONFIG_SOFTMMU)
6701 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6702 #endif
6703 pcc->excp_model = POWERPC_EXCP_74xx;
6704 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6705 pcc->bfd_mach = bfd_mach_ppc_7400;
6706 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6707 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6708 POWERPC_FLAG_BUS_CLK;
6709 }
6710
6711 static void init_proc_7410(CPUPPCState *env)
6712 {
6713 gen_spr_ne_601(env);
6714 gen_spr_sdr1(env);
6715 gen_spr_7xx(env);
6716 /* Time base */
6717 gen_tbl(env);
6718 /* 74xx specific SPR */
6719 gen_spr_74xx(env);
6720 /* XXX : not implemented */
6721 spr_register(env, SPR_UBAMR, "UBAMR",
6722 &spr_read_ureg, SPR_NOACCESS,
6723 &spr_read_ureg, SPR_NOACCESS,
6724 0x00000000);
6725 /* Thermal management */
6726 gen_spr_thrm(env);
6727 /* L2PMCR */
6728 /* XXX : not implemented */
6729 spr_register(env, SPR_L2PMCR, "L2PMCR",
6730 SPR_NOACCESS, SPR_NOACCESS,
6731 &spr_read_generic, &spr_write_generic,
6732 0x00000000);
6733 /* LDSTDB */
6734 /* XXX : not implemented */
6735 spr_register(env, SPR_LDSTDB, "LDSTDB",
6736 SPR_NOACCESS, SPR_NOACCESS,
6737 &spr_read_generic, &spr_write_generic,
6738 0x00000000);
6739 /* Memory management */
6740 gen_low_BATs(env);
6741 init_excp_7400(env);
6742 env->dcache_line_size = 32;
6743 env->icache_line_size = 32;
6744 /* Allocate hardware IRQ controller */
6745 ppc6xx_irq_init(ppc_env_get_cpu(env));
6746 }
6747
6748 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6749 {
6750 DeviceClass *dc = DEVICE_CLASS(oc);
6751 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6752
6753 dc->desc = "PowerPC 7410 (aka G4)";
6754 pcc->init_proc = init_proc_7410;
6755 pcc->check_pow = check_pow_hid0;
6756 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6757 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6758 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6759 PPC_FLOAT_STFIWX |
6760 PPC_CACHE | PPC_CACHE_ICBI |
6761 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6762 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6763 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6764 PPC_MEM_TLBIA |
6765 PPC_SEGMENT | PPC_EXTERN |
6766 PPC_ALTIVEC;
6767 pcc->msr_mask = (1ull << MSR_VR) |
6768 (1ull << MSR_POW) |
6769 (1ull << MSR_ILE) |
6770 (1ull << MSR_EE) |
6771 (1ull << MSR_PR) |
6772 (1ull << MSR_FP) |
6773 (1ull << MSR_ME) |
6774 (1ull << MSR_FE0) |
6775 (1ull << MSR_SE) |
6776 (1ull << MSR_DE) |
6777 (1ull << MSR_FE1) |
6778 (1ull << MSR_EP) |
6779 (1ull << MSR_IR) |
6780 (1ull << MSR_DR) |
6781 (1ull << MSR_PMM) |
6782 (1ull << MSR_RI) |
6783 (1ull << MSR_LE);
6784 pcc->mmu_model = POWERPC_MMU_32B;
6785 #if defined(CONFIG_SOFTMMU)
6786 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6787 #endif
6788 pcc->excp_model = POWERPC_EXCP_74xx;
6789 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6790 pcc->bfd_mach = bfd_mach_ppc_7400;
6791 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6792 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6793 POWERPC_FLAG_BUS_CLK;
6794 }
6795
6796 static void init_proc_7440(CPUPPCState *env)
6797 {
6798 gen_spr_ne_601(env);
6799 gen_spr_sdr1(env);
6800 gen_spr_7xx(env);
6801 /* Time base */
6802 gen_tbl(env);
6803 /* 74xx specific SPR */
6804 gen_spr_74xx(env);
6805 /* XXX : not implemented */
6806 spr_register(env, SPR_UBAMR, "UBAMR",
6807 &spr_read_ureg, SPR_NOACCESS,
6808 &spr_read_ureg, SPR_NOACCESS,
6809 0x00000000);
6810 /* LDSTCR */
6811 /* XXX : not implemented */
6812 spr_register(env, SPR_LDSTCR, "LDSTCR",
6813 SPR_NOACCESS, SPR_NOACCESS,
6814 &spr_read_generic, &spr_write_generic,
6815 0x00000000);
6816 /* ICTRL */
6817 /* XXX : not implemented */
6818 spr_register(env, SPR_ICTRL, "ICTRL",
6819 SPR_NOACCESS, SPR_NOACCESS,
6820 &spr_read_generic, &spr_write_generic,
6821 0x00000000);
6822 /* MSSSR0 */
6823 /* XXX : not implemented */
6824 spr_register(env, SPR_MSSSR0, "MSSSR0",
6825 SPR_NOACCESS, SPR_NOACCESS,
6826 &spr_read_generic, &spr_write_generic,
6827 0x00000000);
6828 /* PMC */
6829 /* XXX : not implemented */
6830 spr_register(env, SPR_7XX_PMC5, "PMC5",
6831 SPR_NOACCESS, SPR_NOACCESS,
6832 &spr_read_generic, &spr_write_generic,
6833 0x00000000);
6834 /* XXX : not implemented */
6835 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6836 &spr_read_ureg, SPR_NOACCESS,
6837 &spr_read_ureg, SPR_NOACCESS,
6838 0x00000000);
6839 /* XXX : not implemented */
6840 spr_register(env, SPR_7XX_PMC6, "PMC6",
6841 SPR_NOACCESS, SPR_NOACCESS,
6842 &spr_read_generic, &spr_write_generic,
6843 0x00000000);
6844 /* XXX : not implemented */
6845 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6846 &spr_read_ureg, SPR_NOACCESS,
6847 &spr_read_ureg, SPR_NOACCESS,
6848 0x00000000);
6849 /* Memory management */
6850 gen_low_BATs(env);
6851 gen_74xx_soft_tlb(env, 128, 2);
6852 init_excp_7450(env);
6853 env->dcache_line_size = 32;
6854 env->icache_line_size = 32;
6855 /* Allocate hardware IRQ controller */
6856 ppc6xx_irq_init(ppc_env_get_cpu(env));
6857 }
6858
6859 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6860 {
6861 DeviceClass *dc = DEVICE_CLASS(oc);
6862 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6863
6864 dc->desc = "PowerPC 7440 (aka G4)";
6865 pcc->init_proc = init_proc_7440;
6866 pcc->check_pow = check_pow_hid0_74xx;
6867 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6868 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6869 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6870 PPC_FLOAT_STFIWX |
6871 PPC_CACHE | PPC_CACHE_ICBI |
6872 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6873 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6874 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6875 PPC_MEM_TLBIA | PPC_74xx_TLB |
6876 PPC_SEGMENT | PPC_EXTERN |
6877 PPC_ALTIVEC;
6878 pcc->msr_mask = (1ull << MSR_VR) |
6879 (1ull << MSR_POW) |
6880 (1ull << MSR_ILE) |
6881 (1ull << MSR_EE) |
6882 (1ull << MSR_PR) |
6883 (1ull << MSR_FP) |
6884 (1ull << MSR_ME) |
6885 (1ull << MSR_FE0) |
6886 (1ull << MSR_SE) |
6887 (1ull << MSR_DE) |
6888 (1ull << MSR_FE1) |
6889 (1ull << MSR_EP) |
6890 (1ull << MSR_IR) |
6891 (1ull << MSR_DR) |
6892 (1ull << MSR_PMM) |
6893 (1ull << MSR_RI) |
6894 (1ull << MSR_LE);
6895 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6896 pcc->excp_model = POWERPC_EXCP_74xx;
6897 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6898 pcc->bfd_mach = bfd_mach_ppc_7400;
6899 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6900 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6901 POWERPC_FLAG_BUS_CLK;
6902 }
6903
6904 static void init_proc_7450(CPUPPCState *env)
6905 {
6906 gen_spr_ne_601(env);
6907 gen_spr_sdr1(env);
6908 gen_spr_7xx(env);
6909 /* Time base */
6910 gen_tbl(env);
6911 /* 74xx specific SPR */
6912 gen_spr_74xx(env);
6913 /* Level 3 cache control */
6914 gen_l3_ctrl(env);
6915 /* L3ITCR1 */
6916 /* XXX : not implemented */
6917 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6918 SPR_NOACCESS, SPR_NOACCESS,
6919 &spr_read_generic, &spr_write_generic,
6920 0x00000000);
6921 /* L3ITCR2 */
6922 /* XXX : not implemented */
6923 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6924 SPR_NOACCESS, SPR_NOACCESS,
6925 &spr_read_generic, &spr_write_generic,
6926 0x00000000);
6927 /* L3ITCR3 */
6928 /* XXX : not implemented */
6929 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6930 SPR_NOACCESS, SPR_NOACCESS,
6931 &spr_read_generic, &spr_write_generic,
6932 0x00000000);
6933 /* L3OHCR */
6934 /* XXX : not implemented */
6935 spr_register(env, SPR_L3OHCR, "L3OHCR",
6936 SPR_NOACCESS, SPR_NOACCESS,
6937 &spr_read_generic, &spr_write_generic,
6938 0x00000000);
6939 /* XXX : not implemented */
6940 spr_register(env, SPR_UBAMR, "UBAMR",
6941 &spr_read_ureg, SPR_NOACCESS,
6942 &spr_read_ureg, SPR_NOACCESS,
6943 0x00000000);
6944 /* LDSTCR */
6945 /* XXX : not implemented */
6946 spr_register(env, SPR_LDSTCR, "LDSTCR",
6947 SPR_NOACCESS, SPR_NOACCESS,
6948 &spr_read_generic, &spr_write_generic,
6949 0x00000000);
6950 /* ICTRL */
6951 /* XXX : not implemented */
6952 spr_register(env, SPR_ICTRL, "ICTRL",
6953 SPR_NOACCESS, SPR_NOACCESS,
6954 &spr_read_generic, &spr_write_generic,
6955 0x00000000);
6956 /* MSSSR0 */
6957 /* XXX : not implemented */
6958 spr_register(env, SPR_MSSSR0, "MSSSR0",
6959 SPR_NOACCESS, SPR_NOACCESS,
6960 &spr_read_generic, &spr_write_generic,
6961 0x00000000);
6962 /* PMC */
6963 /* XXX : not implemented */
6964 spr_register(env, SPR_7XX_PMC5, "PMC5",
6965 SPR_NOACCESS, SPR_NOACCESS,
6966 &spr_read_generic, &spr_write_generic,
6967 0x00000000);
6968 /* XXX : not implemented */
6969 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6970 &spr_read_ureg, SPR_NOACCESS,
6971 &spr_read_ureg, SPR_NOACCESS,
6972 0x00000000);
6973 /* XXX : not implemented */
6974 spr_register(env, SPR_7XX_PMC6, "PMC6",
6975 SPR_NOACCESS, SPR_NOACCESS,
6976 &spr_read_generic, &spr_write_generic,
6977 0x00000000);
6978 /* XXX : not implemented */
6979 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6980 &spr_read_ureg, SPR_NOACCESS,
6981 &spr_read_ureg, SPR_NOACCESS,
6982 0x00000000);
6983 /* Memory management */
6984 gen_low_BATs(env);
6985 gen_74xx_soft_tlb(env, 128, 2);
6986 init_excp_7450(env);
6987 env->dcache_line_size = 32;
6988 env->icache_line_size = 32;
6989 /* Allocate hardware IRQ controller */
6990 ppc6xx_irq_init(ppc_env_get_cpu(env));
6991 }
6992
6993 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6994 {
6995 DeviceClass *dc = DEVICE_CLASS(oc);
6996 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6997
6998 dc->desc = "PowerPC 7450 (aka G4)";
6999 pcc->init_proc = init_proc_7450;
7000 pcc->check_pow = check_pow_hid0_74xx;
7001 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7002 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7003 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7004 PPC_FLOAT_STFIWX |
7005 PPC_CACHE | PPC_CACHE_ICBI |
7006 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7007 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7008 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7009 PPC_MEM_TLBIA | PPC_74xx_TLB |
7010 PPC_SEGMENT | PPC_EXTERN |
7011 PPC_ALTIVEC;
7012 pcc->msr_mask = (1ull << MSR_VR) |
7013 (1ull << MSR_POW) |
7014 (1ull << MSR_ILE) |
7015 (1ull << MSR_EE) |
7016 (1ull << MSR_PR) |
7017 (1ull << MSR_FP) |
7018 (1ull << MSR_ME) |
7019 (1ull << MSR_FE0) |
7020 (1ull << MSR_SE) |
7021 (1ull << MSR_DE) |
7022 (1ull << MSR_FE1) |
7023 (1ull << MSR_EP) |
7024 (1ull << MSR_IR) |
7025 (1ull << MSR_DR) |
7026 (1ull << MSR_PMM) |
7027 (1ull << MSR_RI) |
7028 (1ull << MSR_LE);
7029 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7030 pcc->excp_model = POWERPC_EXCP_74xx;
7031 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7032 pcc->bfd_mach = bfd_mach_ppc_7400;
7033 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7034 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7035 POWERPC_FLAG_BUS_CLK;
7036 }
7037
7038 static void init_proc_7445(CPUPPCState *env)
7039 {
7040 gen_spr_ne_601(env);
7041 gen_spr_sdr1(env);
7042 gen_spr_7xx(env);
7043 /* Time base */
7044 gen_tbl(env);
7045 /* 74xx specific SPR */
7046 gen_spr_74xx(env);
7047 /* LDSTCR */
7048 /* XXX : not implemented */
7049 spr_register(env, SPR_LDSTCR, "LDSTCR",
7050 SPR_NOACCESS, SPR_NOACCESS,
7051 &spr_read_generic, &spr_write_generic,
7052 0x00000000);
7053 /* ICTRL */
7054 /* XXX : not implemented */
7055 spr_register(env, SPR_ICTRL, "ICTRL",
7056 SPR_NOACCESS, SPR_NOACCESS,
7057 &spr_read_generic, &spr_write_generic,
7058 0x00000000);
7059 /* MSSSR0 */
7060 /* XXX : not implemented */
7061 spr_register(env, SPR_MSSSR0, "MSSSR0",
7062 SPR_NOACCESS, SPR_NOACCESS,
7063 &spr_read_generic, &spr_write_generic,
7064 0x00000000);
7065 /* PMC */
7066 /* XXX : not implemented */
7067 spr_register(env, SPR_7XX_PMC5, "PMC5",
7068 SPR_NOACCESS, SPR_NOACCESS,
7069 &spr_read_generic, &spr_write_generic,
7070 0x00000000);
7071 /* XXX : not implemented */
7072 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7073 &spr_read_ureg, SPR_NOACCESS,
7074 &spr_read_ureg, SPR_NOACCESS,
7075 0x00000000);
7076 /* XXX : not implemented */
7077 spr_register(env, SPR_7XX_PMC6, "PMC6",
7078 SPR_NOACCESS, SPR_NOACCESS,
7079 &spr_read_generic, &spr_write_generic,
7080 0x00000000);
7081 /* XXX : not implemented */
7082 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7083 &spr_read_ureg, SPR_NOACCESS,
7084 &spr_read_ureg, SPR_NOACCESS,
7085 0x00000000);
7086 /* SPRGs */
7087 spr_register(env, SPR_SPRG4, "SPRG4",
7088 SPR_NOACCESS, SPR_NOACCESS,
7089 &spr_read_generic, &spr_write_generic,
7090 0x00000000);
7091 spr_register(env, SPR_USPRG4, "USPRG4",
7092 &spr_read_ureg, SPR_NOACCESS,
7093 &spr_read_ureg, SPR_NOACCESS,
7094 0x00000000);
7095 spr_register(env, SPR_SPRG5, "SPRG5",
7096 SPR_NOACCESS, SPR_NOACCESS,
7097 &spr_read_generic, &spr_write_generic,
7098 0x00000000);
7099 spr_register(env, SPR_USPRG5, "USPRG5",
7100 &spr_read_ureg, SPR_NOACCESS,
7101 &spr_read_ureg, SPR_NOACCESS,
7102 0x00000000);
7103 spr_register(env, SPR_SPRG6, "SPRG6",
7104 SPR_NOACCESS, SPR_NOACCESS,
7105 &spr_read_generic, &spr_write_generic,
7106 0x00000000);
7107 spr_register(env, SPR_USPRG6, "USPRG6",
7108 &spr_read_ureg, SPR_NOACCESS,
7109 &spr_read_ureg, SPR_NOACCESS,
7110 0x00000000);
7111 spr_register(env, SPR_SPRG7, "SPRG7",
7112 SPR_NOACCESS, SPR_NOACCESS,
7113 &spr_read_generic, &spr_write_generic,
7114 0x00000000);
7115 spr_register(env, SPR_USPRG7, "USPRG7",
7116 &spr_read_ureg, SPR_NOACCESS,
7117 &spr_read_ureg, SPR_NOACCESS,
7118 0x00000000);
7119 /* Memory management */
7120 gen_low_BATs(env);
7121 gen_high_BATs(env);
7122 gen_74xx_soft_tlb(env, 128, 2);
7123 init_excp_7450(env);
7124 env->dcache_line_size = 32;
7125 env->icache_line_size = 32;
7126 /* Allocate hardware IRQ controller */
7127 ppc6xx_irq_init(ppc_env_get_cpu(env));
7128 }
7129
7130 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
7131 {
7132 DeviceClass *dc = DEVICE_CLASS(oc);
7133 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7134
7135 dc->desc = "PowerPC 7445 (aka G4)";
7136 pcc->init_proc = init_proc_7445;
7137 pcc->check_pow = check_pow_hid0_74xx;
7138 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7139 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7140 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7141 PPC_FLOAT_STFIWX |
7142 PPC_CACHE | PPC_CACHE_ICBI |
7143 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7144 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7145 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7146 PPC_MEM_TLBIA | PPC_74xx_TLB |
7147 PPC_SEGMENT | PPC_EXTERN |
7148 PPC_ALTIVEC;
7149 pcc->msr_mask = (1ull << MSR_VR) |
7150 (1ull << MSR_POW) |
7151 (1ull << MSR_ILE) |
7152 (1ull << MSR_EE) |
7153 (1ull << MSR_PR) |
7154 (1ull << MSR_FP) |
7155 (1ull << MSR_ME) |
7156 (1ull << MSR_FE0) |
7157 (1ull << MSR_SE) |
7158 (1ull << MSR_DE) |
7159 (1ull << MSR_FE1) |
7160 (1ull << MSR_EP) |
7161 (1ull << MSR_IR) |
7162 (1ull << MSR_DR) |
7163 (1ull << MSR_PMM) |
7164 (1ull << MSR_RI) |
7165 (1ull << MSR_LE);
7166 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7167 pcc->excp_model = POWERPC_EXCP_74xx;
7168 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7169 pcc->bfd_mach = bfd_mach_ppc_7400;
7170 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7171 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7172 POWERPC_FLAG_BUS_CLK;
7173 }
7174
7175 static void init_proc_7455(CPUPPCState *env)
7176 {
7177 gen_spr_ne_601(env);
7178 gen_spr_sdr1(env);
7179 gen_spr_7xx(env);
7180 /* Time base */
7181 gen_tbl(env);
7182 /* 74xx specific SPR */
7183 gen_spr_74xx(env);
7184 /* Level 3 cache control */
7185 gen_l3_ctrl(env);
7186 /* LDSTCR */
7187 /* XXX : not implemented */
7188 spr_register(env, SPR_LDSTCR, "LDSTCR",
7189 SPR_NOACCESS, SPR_NOACCESS,
7190 &spr_read_generic, &spr_write_generic,
7191 0x00000000);
7192 /* ICTRL */
7193 /* XXX : not implemented */
7194 spr_register(env, SPR_ICTRL, "ICTRL",
7195 SPR_NOACCESS, SPR_NOACCESS,
7196 &spr_read_generic, &spr_write_generic,
7197 0x00000000);
7198 /* MSSSR0 */
7199 /* XXX : not implemented */
7200 spr_register(env, SPR_MSSSR0, "MSSSR0",
7201 SPR_NOACCESS, SPR_NOACCESS,
7202 &spr_read_generic, &spr_write_generic,
7203 0x00000000);
7204 /* PMC */
7205 /* XXX : not implemented */
7206 spr_register(env, SPR_7XX_PMC5, "PMC5",
7207 SPR_NOACCESS, SPR_NOACCESS,
7208 &spr_read_generic, &spr_write_generic,
7209 0x00000000);
7210 /* XXX : not implemented */
7211 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7212 &spr_read_ureg, SPR_NOACCESS,
7213 &spr_read_ureg, SPR_NOACCESS,
7214 0x00000000);
7215 /* XXX : not implemented */
7216 spr_register(env, SPR_7XX_PMC6, "PMC6",
7217 SPR_NOACCESS, SPR_NOACCESS,
7218 &spr_read_generic, &spr_write_generic,
7219 0x00000000);
7220 /* XXX : not implemented */
7221 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7222 &spr_read_ureg, SPR_NOACCESS,
7223 &spr_read_ureg, SPR_NOACCESS,
7224 0x00000000);
7225 /* SPRGs */
7226 spr_register(env, SPR_SPRG4, "SPRG4",
7227 SPR_NOACCESS, SPR_NOACCESS,
7228 &spr_read_generic, &spr_write_generic,
7229 0x00000000);
7230 spr_register(env, SPR_USPRG4, "USPRG4",
7231 &spr_read_ureg, SPR_NOACCESS,
7232 &spr_read_ureg, SPR_NOACCESS,
7233 0x00000000);
7234 spr_register(env, SPR_SPRG5, "SPRG5",
7235 SPR_NOACCESS, SPR_NOACCESS,
7236 &spr_read_generic, &spr_write_generic,
7237 0x00000000);
7238 spr_register(env, SPR_USPRG5, "USPRG5",
7239 &spr_read_ureg, SPR_NOACCESS,
7240 &spr_read_ureg, SPR_NOACCESS,
7241 0x00000000);
7242 spr_register(env, SPR_SPRG6, "SPRG6",
7243 SPR_NOACCESS, SPR_NOACCESS,
7244 &spr_read_generic, &spr_write_generic,
7245 0x00000000);
7246 spr_register(env, SPR_USPRG6, "USPRG6",
7247 &spr_read_ureg, SPR_NOACCESS,
7248 &spr_read_ureg, SPR_NOACCESS,
7249 0x00000000);
7250 spr_register(env, SPR_SPRG7, "SPRG7",
7251 SPR_NOACCESS, SPR_NOACCESS,
7252 &spr_read_generic, &spr_write_generic,
7253 0x00000000);
7254 spr_register(env, SPR_USPRG7, "USPRG7",
7255 &spr_read_ureg, SPR_NOACCESS,
7256 &spr_read_ureg, SPR_NOACCESS,
7257 0x00000000);
7258 /* Memory management */
7259 gen_low_BATs(env);
7260 gen_high_BATs(env);
7261 gen_74xx_soft_tlb(env, 128, 2);
7262 init_excp_7450(env);
7263 env->dcache_line_size = 32;
7264 env->icache_line_size = 32;
7265 /* Allocate hardware IRQ controller */
7266 ppc6xx_irq_init(ppc_env_get_cpu(env));
7267 }
7268
7269 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7270 {
7271 DeviceClass *dc = DEVICE_CLASS(oc);
7272 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7273
7274 dc->desc = "PowerPC 7455 (aka G4)";
7275 pcc->init_proc = init_proc_7455;
7276 pcc->check_pow = check_pow_hid0_74xx;
7277 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7278 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7279 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7280 PPC_FLOAT_STFIWX |
7281 PPC_CACHE | PPC_CACHE_ICBI |
7282 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7283 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7284 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7285 PPC_MEM_TLBIA | PPC_74xx_TLB |
7286 PPC_SEGMENT | PPC_EXTERN |
7287 PPC_ALTIVEC;
7288 pcc->msr_mask = (1ull << MSR_VR) |
7289 (1ull << MSR_POW) |
7290 (1ull << MSR_ILE) |
7291 (1ull << MSR_EE) |
7292 (1ull << MSR_PR) |
7293 (1ull << MSR_FP) |
7294 (1ull << MSR_ME) |
7295 (1ull << MSR_FE0) |
7296 (1ull << MSR_SE) |
7297 (1ull << MSR_DE) |
7298 (1ull << MSR_FE1) |
7299 (1ull << MSR_EP) |
7300 (1ull << MSR_IR) |
7301 (1ull << MSR_DR) |
7302 (1ull << MSR_PMM) |
7303 (1ull << MSR_RI) |
7304 (1ull << MSR_LE);
7305 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7306 pcc->excp_model = POWERPC_EXCP_74xx;
7307 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7308 pcc->bfd_mach = bfd_mach_ppc_7400;
7309 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7310 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7311 POWERPC_FLAG_BUS_CLK;
7312 }
7313
7314 static void init_proc_7457(CPUPPCState *env)
7315 {
7316 gen_spr_ne_601(env);
7317 gen_spr_sdr1(env);
7318 gen_spr_7xx(env);
7319 /* Time base */
7320 gen_tbl(env);
7321 /* 74xx specific SPR */
7322 gen_spr_74xx(env);
7323 /* Level 3 cache control */
7324 gen_l3_ctrl(env);
7325 /* L3ITCR1 */
7326 /* XXX : not implemented */
7327 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7328 SPR_NOACCESS, SPR_NOACCESS,
7329 &spr_read_generic, &spr_write_generic,
7330 0x00000000);
7331 /* L3ITCR2 */
7332 /* XXX : not implemented */
7333 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7334 SPR_NOACCESS, SPR_NOACCESS,
7335 &spr_read_generic, &spr_write_generic,
7336 0x00000000);
7337 /* L3ITCR3 */
7338 /* XXX : not implemented */
7339 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7340 SPR_NOACCESS, SPR_NOACCESS,
7341 &spr_read_generic, &spr_write_generic,
7342 0x00000000);
7343 /* L3OHCR */
7344 /* XXX : not implemented */
7345 spr_register(env, SPR_L3OHCR, "L3OHCR",
7346 SPR_NOACCESS, SPR_NOACCESS,
7347 &spr_read_generic, &spr_write_generic,
7348 0x00000000);
7349 /* LDSTCR */
7350 /* XXX : not implemented */
7351 spr_register(env, SPR_LDSTCR, "LDSTCR",
7352 SPR_NOACCESS, SPR_NOACCESS,
7353 &spr_read_generic, &spr_write_generic,
7354 0x00000000);
7355 /* ICTRL */
7356 /* XXX : not implemented */
7357 spr_register(env, SPR_ICTRL, "ICTRL",
7358 SPR_NOACCESS, SPR_NOACCESS,
7359 &spr_read_generic, &spr_write_generic,
7360 0x00000000);
7361 /* MSSSR0 */
7362 /* XXX : not implemented */
7363 spr_register(env, SPR_MSSSR0, "MSSSR0",
7364 SPR_NOACCESS, SPR_NOACCESS,
7365 &spr_read_generic, &spr_write_generic,
7366 0x00000000);
7367 /* PMC */
7368 /* XXX : not implemented */
7369 spr_register(env, SPR_7XX_PMC5, "PMC5",
7370 SPR_NOACCESS, SPR_NOACCESS,
7371 &spr_read_generic, &spr_write_generic,
7372 0x00000000);
7373 /* XXX : not implemented */
7374 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7375 &spr_read_ureg, SPR_NOACCESS,
7376 &spr_read_ureg, SPR_NOACCESS,
7377 0x00000000);
7378 /* XXX : not implemented */
7379 spr_register(env, SPR_7XX_PMC6, "PMC6",
7380 SPR_NOACCESS, SPR_NOACCESS,
7381 &spr_read_generic, &spr_write_generic,
7382 0x00000000);
7383 /* XXX : not implemented */
7384 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7385 &spr_read_ureg, SPR_NOACCESS,
7386 &spr_read_ureg, SPR_NOACCESS,
7387 0x00000000);
7388 /* SPRGs */
7389 spr_register(env, SPR_SPRG4, "SPRG4",
7390 SPR_NOACCESS, SPR_NOACCESS,
7391 &spr_read_generic, &spr_write_generic,
7392 0x00000000);
7393 spr_register(env, SPR_USPRG4, "USPRG4",
7394 &spr_read_ureg, SPR_NOACCESS,
7395 &spr_read_ureg, SPR_NOACCESS,
7396 0x00000000);
7397 spr_register(env, SPR_SPRG5, "SPRG5",
7398 SPR_NOACCESS, SPR_NOACCESS,
7399 &spr_read_generic, &spr_write_generic,
7400 0x00000000);
7401 spr_register(env, SPR_USPRG5, "USPRG5",
7402 &spr_read_ureg, SPR_NOACCESS,
7403 &spr_read_ureg, SPR_NOACCESS,
7404 0x00000000);
7405 spr_register(env, SPR_SPRG6, "SPRG6",
7406 SPR_NOACCESS, SPR_NOACCESS,
7407 &spr_read_generic, &spr_write_generic,
7408 0x00000000);
7409 spr_register(env, SPR_USPRG6, "USPRG6",
7410 &spr_read_ureg, SPR_NOACCESS,
7411 &spr_read_ureg, SPR_NOACCESS,
7412 0x00000000);
7413 spr_register(env, SPR_SPRG7, "SPRG7",
7414 SPR_NOACCESS, SPR_NOACCESS,
7415 &spr_read_generic, &spr_write_generic,
7416 0x00000000);
7417 spr_register(env, SPR_USPRG7, "USPRG7",
7418 &spr_read_ureg, SPR_NOACCESS,
7419 &spr_read_ureg, SPR_NOACCESS,
7420 0x00000000);
7421 /* Memory management */
7422 gen_low_BATs(env);
7423 gen_high_BATs(env);
7424 gen_74xx_soft_tlb(env, 128, 2);
7425 init_excp_7450(env);
7426 env->dcache_line_size = 32;
7427 env->icache_line_size = 32;
7428 /* Allocate hardware IRQ controller */
7429 ppc6xx_irq_init(ppc_env_get_cpu(env));
7430 }
7431
7432 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7433 {
7434 DeviceClass *dc = DEVICE_CLASS(oc);
7435 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7436
7437 dc->desc = "PowerPC 7457 (aka G4)";
7438 pcc->init_proc = init_proc_7457;
7439 pcc->check_pow = check_pow_hid0_74xx;
7440 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7441 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7442 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7443 PPC_FLOAT_STFIWX |
7444 PPC_CACHE | PPC_CACHE_ICBI |
7445 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7446 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7447 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7448 PPC_MEM_TLBIA | PPC_74xx_TLB |
7449 PPC_SEGMENT | PPC_EXTERN |
7450 PPC_ALTIVEC;
7451 pcc->msr_mask = (1ull << MSR_VR) |
7452 (1ull << MSR_POW) |
7453 (1ull << MSR_ILE) |
7454 (1ull << MSR_EE) |
7455 (1ull << MSR_PR) |
7456 (1ull << MSR_FP) |
7457 (1ull << MSR_ME) |
7458 (1ull << MSR_FE0) |
7459 (1ull << MSR_SE) |
7460 (1ull << MSR_DE) |
7461 (1ull << MSR_FE1) |
7462 (1ull << MSR_EP) |
7463 (1ull << MSR_IR) |
7464 (1ull << MSR_DR) |
7465 (1ull << MSR_PMM) |
7466 (1ull << MSR_RI) |
7467 (1ull << MSR_LE);
7468 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7469 pcc->excp_model = POWERPC_EXCP_74xx;
7470 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7471 pcc->bfd_mach = bfd_mach_ppc_7400;
7472 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7473 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7474 POWERPC_FLAG_BUS_CLK;
7475 }
7476
7477 static void init_proc_e600(CPUPPCState *env)
7478 {
7479 gen_spr_ne_601(env);
7480 gen_spr_sdr1(env);
7481 gen_spr_7xx(env);
7482 /* Time base */
7483 gen_tbl(env);
7484 /* 74xx specific SPR */
7485 gen_spr_74xx(env);
7486 /* XXX : not implemented */
7487 spr_register(env, SPR_UBAMR, "UBAMR",
7488 &spr_read_ureg, SPR_NOACCESS,
7489 &spr_read_ureg, SPR_NOACCESS,
7490 0x00000000);
7491 /* XXX : not implemented */
7492 spr_register(env, SPR_LDSTCR, "LDSTCR",
7493 SPR_NOACCESS, SPR_NOACCESS,
7494 &spr_read_generic, &spr_write_generic,
7495 0x00000000);
7496 /* XXX : not implemented */
7497 spr_register(env, SPR_ICTRL, "ICTRL",
7498 SPR_NOACCESS, SPR_NOACCESS,
7499 &spr_read_generic, &spr_write_generic,
7500 0x00000000);
7501 /* XXX : not implemented */
7502 spr_register(env, SPR_MSSSR0, "MSSSR0",
7503 SPR_NOACCESS, SPR_NOACCESS,
7504 &spr_read_generic, &spr_write_generic,
7505 0x00000000);
7506 /* XXX : not implemented */
7507 spr_register(env, SPR_7XX_PMC5, "PMC5",
7508 SPR_NOACCESS, SPR_NOACCESS,
7509 &spr_read_generic, &spr_write_generic,
7510 0x00000000);
7511 /* XXX : not implemented */
7512 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7513 &spr_read_ureg, SPR_NOACCESS,
7514 &spr_read_ureg, SPR_NOACCESS,
7515 0x00000000);
7516 /* XXX : not implemented */
7517 spr_register(env, SPR_7XX_PMC6, "PMC6",
7518 SPR_NOACCESS, SPR_NOACCESS,
7519 &spr_read_generic, &spr_write_generic,
7520 0x00000000);
7521 /* XXX : not implemented */
7522 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7523 &spr_read_ureg, SPR_NOACCESS,
7524 &spr_read_ureg, SPR_NOACCESS,
7525 0x00000000);
7526 /* SPRGs */
7527 spr_register(env, SPR_SPRG4, "SPRG4",
7528 SPR_NOACCESS, SPR_NOACCESS,
7529 &spr_read_generic, &spr_write_generic,
7530 0x00000000);
7531 spr_register(env, SPR_USPRG4, "USPRG4",
7532 &spr_read_ureg, SPR_NOACCESS,
7533 &spr_read_ureg, SPR_NOACCESS,
7534 0x00000000);
7535 spr_register(env, SPR_SPRG5, "SPRG5",
7536 SPR_NOACCESS, SPR_NOACCESS,
7537 &spr_read_generic, &spr_write_generic,
7538 0x00000000);
7539 spr_register(env, SPR_USPRG5, "USPRG5",
7540 &spr_read_ureg, SPR_NOACCESS,
7541 &spr_read_ureg, SPR_NOACCESS,
7542 0x00000000);
7543 spr_register(env, SPR_SPRG6, "SPRG6",
7544 SPR_NOACCESS, SPR_NOACCESS,
7545 &spr_read_generic, &spr_write_generic,
7546 0x00000000);
7547 spr_register(env, SPR_USPRG6, "USPRG6",
7548 &spr_read_ureg, SPR_NOACCESS,
7549 &spr_read_ureg, SPR_NOACCESS,
7550 0x00000000);
7551 spr_register(env, SPR_SPRG7, "SPRG7",
7552 SPR_NOACCESS, SPR_NOACCESS,
7553 &spr_read_generic, &spr_write_generic,
7554 0x00000000);
7555 spr_register(env, SPR_USPRG7, "USPRG7",
7556 &spr_read_ureg, SPR_NOACCESS,
7557 &spr_read_ureg, SPR_NOACCESS,
7558 0x00000000);
7559 /* Memory management */
7560 gen_low_BATs(env);
7561 gen_high_BATs(env);
7562 gen_74xx_soft_tlb(env, 128, 2);
7563 init_excp_7450(env);
7564 env->dcache_line_size = 32;
7565 env->icache_line_size = 32;
7566 /* Allocate hardware IRQ controller */
7567 ppc6xx_irq_init(ppc_env_get_cpu(env));
7568 }
7569
7570 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7571 {
7572 DeviceClass *dc = DEVICE_CLASS(oc);
7573 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7574
7575 dc->desc = "PowerPC e600";
7576 pcc->init_proc = init_proc_e600;
7577 pcc->check_pow = check_pow_hid0_74xx;
7578 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7579 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7580 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7581 PPC_FLOAT_STFIWX |
7582 PPC_CACHE | PPC_CACHE_ICBI |
7583 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7584 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7585 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7586 PPC_MEM_TLBIA | PPC_74xx_TLB |
7587 PPC_SEGMENT | PPC_EXTERN |
7588 PPC_ALTIVEC;
7589 pcc->insns_flags2 = PPC_NONE;
7590 pcc->msr_mask = (1ull << MSR_VR) |
7591 (1ull << MSR_POW) |
7592 (1ull << MSR_ILE) |
7593 (1ull << MSR_EE) |
7594 (1ull << MSR_PR) |
7595 (1ull << MSR_FP) |
7596 (1ull << MSR_ME) |
7597 (1ull << MSR_FE0) |
7598 (1ull << MSR_SE) |
7599 (1ull << MSR_DE) |
7600 (1ull << MSR_FE1) |
7601 (1ull << MSR_EP) |
7602 (1ull << MSR_IR) |
7603 (1ull << MSR_DR) |
7604 (1ull << MSR_PMM) |
7605 (1ull << MSR_RI) |
7606 (1ull << MSR_LE);
7607 pcc->mmu_model = POWERPC_MMU_32B;
7608 #if defined(CONFIG_SOFTMMU)
7609 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7610 #endif
7611 pcc->excp_model = POWERPC_EXCP_74xx;
7612 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7613 pcc->bfd_mach = bfd_mach_ppc_7400;
7614 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7615 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7616 POWERPC_FLAG_BUS_CLK;
7617 }
7618
7619 #if defined(TARGET_PPC64)
7620 #if defined(CONFIG_USER_ONLY)
7621 #define POWERPC970_HID5_INIT 0x00000080
7622 #else
7623 #define POWERPC970_HID5_INIT 0x00000000
7624 #endif
7625
7626 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7627 int bit, int sprn, int cause)
7628 {
7629 TCGv_i32 t1 = tcg_const_i32(bit);
7630 TCGv_i32 t2 = tcg_const_i32(sprn);
7631 TCGv_i32 t3 = tcg_const_i32(cause);
7632
7633 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7634
7635 tcg_temp_free_i32(t3);
7636 tcg_temp_free_i32(t2);
7637 tcg_temp_free_i32(t1);
7638 }
7639
7640 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7641 int bit, int sprn, int cause)
7642 {
7643 TCGv_i32 t1 = tcg_const_i32(bit);
7644 TCGv_i32 t2 = tcg_const_i32(sprn);
7645 TCGv_i32 t3 = tcg_const_i32(cause);
7646
7647 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7648
7649 tcg_temp_free_i32(t3);
7650 tcg_temp_free_i32(t2);
7651 tcg_temp_free_i32(t1);
7652 }
7653
7654 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7655 {
7656 TCGv spr_up = tcg_temp_new();
7657 TCGv spr = tcg_temp_new();
7658
7659 gen_load_spr(spr, sprn - 1);
7660 tcg_gen_shri_tl(spr_up, spr, 32);
7661 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7662
7663 tcg_temp_free(spr);
7664 tcg_temp_free(spr_up);
7665 }
7666
7667 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7668 {
7669 TCGv spr = tcg_temp_new();
7670
7671 gen_load_spr(spr, sprn - 1);
7672 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7673 gen_store_spr(sprn - 1, spr);
7674
7675 tcg_temp_free(spr);
7676 }
7677
7678 static int check_pow_970(CPUPPCState *env)
7679 {
7680 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7681 return 1;
7682 }
7683
7684 return 0;
7685 }
7686
7687 static void gen_spr_970_hid(CPUPPCState *env)
7688 {
7689 /* Hardware implementation registers */
7690 /* XXX : not implemented */
7691 spr_register(env, SPR_HID0, "HID0",
7692 SPR_NOACCESS, SPR_NOACCESS,
7693 &spr_read_generic, &spr_write_clear,
7694 0x60000000);
7695 spr_register(env, SPR_HID1, "HID1",
7696 SPR_NOACCESS, SPR_NOACCESS,
7697 &spr_read_generic, &spr_write_generic,
7698 0x00000000);
7699 spr_register(env, SPR_970_HID5, "HID5",
7700 SPR_NOACCESS, SPR_NOACCESS,
7701 &spr_read_generic, &spr_write_generic,
7702 POWERPC970_HID5_INIT);
7703 }
7704
7705 static void gen_spr_970_hior(CPUPPCState *env)
7706 {
7707 spr_register(env, SPR_HIOR, "SPR_HIOR",
7708 SPR_NOACCESS, SPR_NOACCESS,
7709 &spr_read_hior, &spr_write_hior,
7710 0x00000000);
7711 }
7712
7713 static void gen_spr_book3s_ctrl(CPUPPCState *env)
7714 {
7715 spr_register(env, SPR_CTRL, "SPR_CTRL",
7716 SPR_NOACCESS, SPR_NOACCESS,
7717 SPR_NOACCESS, &spr_write_generic,
7718 0x00000000);
7719 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7720 &spr_read_ureg, SPR_NOACCESS,
7721 &spr_read_ureg, SPR_NOACCESS,
7722 0x00000000);
7723 }
7724
7725 static void gen_spr_book3s_altivec(CPUPPCState *env)
7726 {
7727 if (!(env->insns_flags & PPC_ALTIVEC)) {
7728 return;
7729 }
7730
7731 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7732 &spr_read_generic, &spr_write_generic,
7733 &spr_read_generic, &spr_write_generic,
7734 KVM_REG_PPC_VRSAVE, 0x00000000);
7735
7736 /* Can't find information on what this should be on reset. This
7737 * value is the one used by 74xx processors. */
7738 vscr_init(env, 0x00010000);
7739 }
7740
7741 static void gen_spr_book3s_dbg(CPUPPCState *env)
7742 {
7743 /*
7744 * TODO: different specs define different scopes for these,
7745 * will have to address this:
7746 * 970: super/write and super/read
7747 * powerisa 2.03..2.04: hypv/write and super/read.
7748 * powerisa 2.05 and newer: hypv/write and hypv/read.
7749 */
7750 spr_register_kvm(env, SPR_DABR, "DABR",
7751 SPR_NOACCESS, SPR_NOACCESS,
7752 &spr_read_generic, &spr_write_generic,
7753 KVM_REG_PPC_DABR, 0x00000000);
7754 spr_register_kvm(env, SPR_DABRX, "DABRX",
7755 SPR_NOACCESS, SPR_NOACCESS,
7756 &spr_read_generic, &spr_write_generic,
7757 KVM_REG_PPC_DABRX, 0x00000000);
7758 }
7759
7760 static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7761 {
7762 spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7763 SPR_NOACCESS, SPR_NOACCESS,
7764 SPR_NOACCESS, SPR_NOACCESS,
7765 &spr_read_generic, &spr_write_generic,
7766 KVM_REG_PPC_DAWR, 0x00000000);
7767 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7768 SPR_NOACCESS, SPR_NOACCESS,
7769 SPR_NOACCESS, SPR_NOACCESS,
7770 &spr_read_generic, &spr_write_generic,
7771 KVM_REG_PPC_DAWRX, 0x00000000);
7772 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7773 SPR_NOACCESS, SPR_NOACCESS,
7774 SPR_NOACCESS, SPR_NOACCESS,
7775 &spr_read_generic, &spr_write_generic,
7776 KVM_REG_PPC_CIABR, 0x00000000);
7777 }
7778
7779 static void gen_spr_970_dbg(CPUPPCState *env)
7780 {
7781 /* Breakpoints */
7782 spr_register(env, SPR_IABR, "IABR",
7783 SPR_NOACCESS, SPR_NOACCESS,
7784 &spr_read_generic, &spr_write_generic,
7785 0x00000000);
7786 }
7787
7788 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7789 {
7790 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7791 SPR_NOACCESS, SPR_NOACCESS,
7792 &spr_read_generic, &spr_write_generic,
7793 KVM_REG_PPC_MMCR0, 0x00000000);
7794 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7795 SPR_NOACCESS, SPR_NOACCESS,
7796 &spr_read_generic, &spr_write_generic,
7797 KVM_REG_PPC_MMCR1, 0x00000000);
7798 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7799 SPR_NOACCESS, SPR_NOACCESS,
7800 &spr_read_generic, &spr_write_generic,
7801 KVM_REG_PPC_MMCRA, 0x00000000);
7802 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7803 SPR_NOACCESS, SPR_NOACCESS,
7804 &spr_read_generic, &spr_write_generic,
7805 KVM_REG_PPC_PMC1, 0x00000000);
7806 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7807 SPR_NOACCESS, SPR_NOACCESS,
7808 &spr_read_generic, &spr_write_generic,
7809 KVM_REG_PPC_PMC2, 0x00000000);
7810 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7811 SPR_NOACCESS, SPR_NOACCESS,
7812 &spr_read_generic, &spr_write_generic,
7813 KVM_REG_PPC_PMC3, 0x00000000);
7814 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7815 SPR_NOACCESS, SPR_NOACCESS,
7816 &spr_read_generic, &spr_write_generic,
7817 KVM_REG_PPC_PMC4, 0x00000000);
7818 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7819 SPR_NOACCESS, SPR_NOACCESS,
7820 &spr_read_generic, &spr_write_generic,
7821 KVM_REG_PPC_PMC5, 0x00000000);
7822 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7823 SPR_NOACCESS, SPR_NOACCESS,
7824 &spr_read_generic, &spr_write_generic,
7825 KVM_REG_PPC_PMC6, 0x00000000);
7826 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7827 SPR_NOACCESS, SPR_NOACCESS,
7828 &spr_read_generic, &spr_write_generic,
7829 KVM_REG_PPC_SIAR, 0x00000000);
7830 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7831 SPR_NOACCESS, SPR_NOACCESS,
7832 &spr_read_generic, &spr_write_generic,
7833 KVM_REG_PPC_SDAR, 0x00000000);
7834 }
7835
7836 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7837 {
7838 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7839 &spr_read_ureg, SPR_NOACCESS,
7840 &spr_read_ureg, &spr_write_ureg,
7841 0x00000000);
7842 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7843 &spr_read_ureg, SPR_NOACCESS,
7844 &spr_read_ureg, &spr_write_ureg,
7845 0x00000000);
7846 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7847 &spr_read_ureg, SPR_NOACCESS,
7848 &spr_read_ureg, &spr_write_ureg,
7849 0x00000000);
7850 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7851 &spr_read_ureg, SPR_NOACCESS,
7852 &spr_read_ureg, &spr_write_ureg,
7853 0x00000000);
7854 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7855 &spr_read_ureg, SPR_NOACCESS,
7856 &spr_read_ureg, &spr_write_ureg,
7857 0x00000000);
7858 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7859 &spr_read_ureg, SPR_NOACCESS,
7860 &spr_read_ureg, &spr_write_ureg,
7861 0x00000000);
7862 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7863 &spr_read_ureg, SPR_NOACCESS,
7864 &spr_read_ureg, &spr_write_ureg,
7865 0x00000000);
7866 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7867 &spr_read_ureg, SPR_NOACCESS,
7868 &spr_read_ureg, &spr_write_ureg,
7869 0x00000000);
7870 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7871 &spr_read_ureg, SPR_NOACCESS,
7872 &spr_read_ureg, &spr_write_ureg,
7873 0x00000000);
7874 spr_register(env, SPR_POWER_USIAR, "USIAR",
7875 &spr_read_ureg, SPR_NOACCESS,
7876 &spr_read_ureg, &spr_write_ureg,
7877 0x00000000);
7878 spr_register(env, SPR_POWER_USDAR, "USDAR",
7879 &spr_read_ureg, SPR_NOACCESS,
7880 &spr_read_ureg, &spr_write_ureg,
7881 0x00000000);
7882 }
7883
7884 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7885 {
7886 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7887 SPR_NOACCESS, SPR_NOACCESS,
7888 &spr_read_generic, &spr_write_generic,
7889 KVM_REG_PPC_PMC7, 0x00000000);
7890 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7891 SPR_NOACCESS, SPR_NOACCESS,
7892 &spr_read_generic, &spr_write_generic,
7893 KVM_REG_PPC_PMC8, 0x00000000);
7894 }
7895
7896 static void gen_spr_970_pmu_user(CPUPPCState *env)
7897 {
7898 spr_register(env, SPR_970_UPMC7, "UPMC7",
7899 &spr_read_ureg, SPR_NOACCESS,
7900 &spr_read_ureg, &spr_write_ureg,
7901 0x00000000);
7902 spr_register(env, SPR_970_UPMC8, "UPMC8",
7903 &spr_read_ureg, SPR_NOACCESS,
7904 &spr_read_ureg, &spr_write_ureg,
7905 0x00000000);
7906 }
7907
7908 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7909 {
7910 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7911 SPR_NOACCESS, SPR_NOACCESS,
7912 &spr_read_generic, &spr_write_generic,
7913 KVM_REG_PPC_MMCR2, 0x00000000);
7914 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7915 SPR_NOACCESS, SPR_NOACCESS,
7916 &spr_read_generic, &spr_write_generic,
7917 KVM_REG_PPC_MMCRS, 0x00000000);
7918 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7919 SPR_NOACCESS, SPR_NOACCESS,
7920 &spr_read_generic, &spr_write_generic,
7921 KVM_REG_PPC_SIER, 0x00000000);
7922 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7923 SPR_NOACCESS, SPR_NOACCESS,
7924 &spr_read_generic, &spr_write_generic,
7925 KVM_REG_PPC_SPMC1, 0x00000000);
7926 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7927 SPR_NOACCESS, SPR_NOACCESS,
7928 &spr_read_generic, &spr_write_generic,
7929 KVM_REG_PPC_SPMC2, 0x00000000);
7930 spr_register_kvm(env, SPR_TACR, "TACR",
7931 SPR_NOACCESS, SPR_NOACCESS,
7932 &spr_read_generic, &spr_write_generic,
7933 KVM_REG_PPC_TACR, 0x00000000);
7934 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7935 SPR_NOACCESS, SPR_NOACCESS,
7936 &spr_read_generic, &spr_write_generic,
7937 KVM_REG_PPC_TCSCR, 0x00000000);
7938 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7939 SPR_NOACCESS, SPR_NOACCESS,
7940 &spr_read_generic, &spr_write_generic,
7941 KVM_REG_PPC_CSIGR, 0x00000000);
7942 }
7943
7944 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7945 {
7946 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7947 &spr_read_ureg, SPR_NOACCESS,
7948 &spr_read_ureg, &spr_write_ureg,
7949 0x00000000);
7950 spr_register(env, SPR_POWER_USIER, "USIER",
7951 &spr_read_generic, SPR_NOACCESS,
7952 &spr_read_generic, &spr_write_generic,
7953 0x00000000);
7954 }
7955
7956 static void gen_spr_power5p_ear(CPUPPCState *env)
7957 {
7958 /* External access control */
7959 spr_register(env, SPR_EAR, "EAR",
7960 SPR_NOACCESS, SPR_NOACCESS,
7961 &spr_read_generic, &spr_write_generic,
7962 0x00000000);
7963 }
7964
7965 #if !defined(CONFIG_USER_ONLY)
7966 static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
7967 {
7968 TCGv hmer = tcg_temp_new();
7969
7970 gen_load_spr(hmer, sprn);
7971 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
7972 gen_store_spr(sprn, hmer);
7973 spr_store_dump_spr(sprn);
7974 tcg_temp_free(hmer);
7975 }
7976
7977 static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
7978 {
7979 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7980 }
7981
7982 static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
7983 {
7984 #if defined(TARGET_PPC64)
7985 spr_write_generic(ctx, sprn, gprn);
7986 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7987 #endif
7988 }
7989
7990 #endif /* !defined(CONFIG_USER_ONLY) */
7991
7992 static void gen_spr_970_lpar(CPUPPCState *env)
7993 {
7994 #if !defined(CONFIG_USER_ONLY)
7995 /* Logical partitionning */
7996 /* PPC970: HID4 is effectively the LPCR */
7997 spr_register(env, SPR_970_HID4, "HID4",
7998 SPR_NOACCESS, SPR_NOACCESS,
7999 &spr_read_generic, &spr_write_970_hid4,
8000 0x00000000);
8001 #endif
8002 }
8003
8004 static void gen_spr_power5p_lpar(CPUPPCState *env)
8005 {
8006 #if !defined(CONFIG_USER_ONLY)
8007 /* Logical partitionning */
8008 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
8009 SPR_NOACCESS, SPR_NOACCESS,
8010 SPR_NOACCESS, SPR_NOACCESS,
8011 &spr_read_generic, &spr_write_lpcr,
8012 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
8013 spr_register_hv(env, SPR_HDEC, "HDEC",
8014 SPR_NOACCESS, SPR_NOACCESS,
8015 SPR_NOACCESS, SPR_NOACCESS,
8016 &spr_read_hdecr, &spr_write_hdecr, 0);
8017 #endif
8018 }
8019
8020 static void gen_spr_book3s_ids(CPUPPCState *env)
8021 {
8022 /* FIXME: Will need to deal with thread vs core only SPRs */
8023
8024 /* Processor identification */
8025 spr_register_hv(env, SPR_PIR, "PIR",
8026 SPR_NOACCESS, SPR_NOACCESS,
8027 SPR_NOACCESS, SPR_NOACCESS,
8028 &spr_read_generic, NULL,
8029 0x00000000);
8030 spr_register_hv(env, SPR_HID0, "HID0",
8031 SPR_NOACCESS, SPR_NOACCESS,
8032 SPR_NOACCESS, SPR_NOACCESS,
8033 &spr_read_generic, &spr_write_generic,
8034 0x00000000);
8035 spr_register_hv(env, SPR_TSCR, "TSCR",
8036 SPR_NOACCESS, SPR_NOACCESS,
8037 SPR_NOACCESS, SPR_NOACCESS,
8038 &spr_read_generic, &spr_write_generic,
8039 0x00000000);
8040 spr_register_hv(env, SPR_HMER, "HMER",
8041 SPR_NOACCESS, SPR_NOACCESS,
8042 SPR_NOACCESS, SPR_NOACCESS,
8043 &spr_read_generic, &spr_write_hmer,
8044 0x00000000);
8045 spr_register_hv(env, SPR_HMEER, "HMEER",
8046 SPR_NOACCESS, SPR_NOACCESS,
8047 SPR_NOACCESS, SPR_NOACCESS,
8048 &spr_read_generic, &spr_write_generic,
8049 0x00000000);
8050 spr_register_hv(env, SPR_TFMR, "TFMR",
8051 SPR_NOACCESS, SPR_NOACCESS,
8052 SPR_NOACCESS, SPR_NOACCESS,
8053 &spr_read_generic, &spr_write_generic,
8054 0x00000000);
8055 spr_register_hv(env, SPR_LPIDR, "LPIDR",
8056 SPR_NOACCESS, SPR_NOACCESS,
8057 SPR_NOACCESS, SPR_NOACCESS,
8058 &spr_read_generic, &spr_write_generic,
8059 0x00000000);
8060 spr_register_hv(env, SPR_HFSCR, "HFSCR",
8061 SPR_NOACCESS, SPR_NOACCESS,
8062 SPR_NOACCESS, SPR_NOACCESS,
8063 &spr_read_generic, &spr_write_generic,
8064 0x00000000);
8065 spr_register_hv(env, SPR_MMCRC, "MMCRC",
8066 SPR_NOACCESS, SPR_NOACCESS,
8067 SPR_NOACCESS, SPR_NOACCESS,
8068 &spr_read_generic, &spr_write_generic,
8069 0x00000000);
8070 spr_register_hv(env, SPR_MMCRH, "MMCRH",
8071 SPR_NOACCESS, SPR_NOACCESS,
8072 SPR_NOACCESS, SPR_NOACCESS,
8073 &spr_read_generic, &spr_write_generic,
8074 0x00000000);
8075 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
8076 SPR_NOACCESS, SPR_NOACCESS,
8077 SPR_NOACCESS, SPR_NOACCESS,
8078 &spr_read_generic, &spr_write_generic,
8079 0x00000000);
8080 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
8081 SPR_NOACCESS, SPR_NOACCESS,
8082 SPR_NOACCESS, SPR_NOACCESS,
8083 &spr_read_generic, &spr_write_generic,
8084 0x00000000);
8085 spr_register_hv(env, SPR_HSRR0, "HSRR0",
8086 SPR_NOACCESS, SPR_NOACCESS,
8087 SPR_NOACCESS, SPR_NOACCESS,
8088 &spr_read_generic, &spr_write_generic,
8089 0x00000000);
8090 spr_register_hv(env, SPR_HSRR1, "HSRR1",
8091 SPR_NOACCESS, SPR_NOACCESS,
8092 SPR_NOACCESS, SPR_NOACCESS,
8093 &spr_read_generic, &spr_write_generic,
8094 0x00000000);
8095 spr_register_hv(env, SPR_HDAR, "HDAR",
8096 SPR_NOACCESS, SPR_NOACCESS,
8097 SPR_NOACCESS, SPR_NOACCESS,
8098 &spr_read_generic, &spr_write_generic,
8099 0x00000000);
8100 spr_register_hv(env, SPR_HDSISR, "HDSISR",
8101 SPR_NOACCESS, SPR_NOACCESS,
8102 SPR_NOACCESS, SPR_NOACCESS,
8103 &spr_read_generic, &spr_write_generic,
8104 0x00000000);
8105 spr_register_hv(env, SPR_RMOR, "RMOR",
8106 SPR_NOACCESS, SPR_NOACCESS,
8107 SPR_NOACCESS, SPR_NOACCESS,
8108 &spr_read_generic, &spr_write_generic,
8109 0x00000000);
8110 spr_register_hv(env, SPR_HRMOR, "HRMOR",
8111 SPR_NOACCESS, SPR_NOACCESS,
8112 SPR_NOACCESS, SPR_NOACCESS,
8113 &spr_read_generic, &spr_write_generic,
8114 0x00000000);
8115 }
8116
8117 static void gen_spr_power8_ids(CPUPPCState *env)
8118 {
8119 /* Thread identification */
8120 spr_register(env, SPR_TIR, "TIR",
8121 SPR_NOACCESS, SPR_NOACCESS,
8122 &spr_read_generic, SPR_NOACCESS,
8123 0x00000000);
8124 }
8125
8126 static void gen_spr_book3s_purr(CPUPPCState *env)
8127 {
8128 #if !defined(CONFIG_USER_ONLY)
8129 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
8130 spr_register_kvm(env, SPR_PURR, "PURR",
8131 &spr_read_purr, SPR_NOACCESS,
8132 &spr_read_purr, SPR_NOACCESS,
8133 KVM_REG_PPC_PURR, 0x00000000);
8134 spr_register_kvm(env, SPR_SPURR, "SPURR",
8135 &spr_read_purr, SPR_NOACCESS,
8136 &spr_read_purr, SPR_NOACCESS,
8137 KVM_REG_PPC_SPURR, 0x00000000);
8138 #endif
8139 }
8140
8141 static void gen_spr_power6_dbg(CPUPPCState *env)
8142 {
8143 #if !defined(CONFIG_USER_ONLY)
8144 spr_register(env, SPR_CFAR, "SPR_CFAR",
8145 SPR_NOACCESS, SPR_NOACCESS,
8146 &spr_read_cfar, &spr_write_cfar,
8147 0x00000000);
8148 #endif
8149 }
8150
8151 static void gen_spr_power5p_common(CPUPPCState *env)
8152 {
8153 spr_register_kvm(env, SPR_PPR, "PPR",
8154 &spr_read_generic, &spr_write_generic,
8155 &spr_read_generic, &spr_write_generic,
8156 KVM_REG_PPC_PPR, 0x00000000);
8157 }
8158
8159 static void gen_spr_power6_common(CPUPPCState *env)
8160 {
8161 #if !defined(CONFIG_USER_ONLY)
8162 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
8163 SPR_NOACCESS, SPR_NOACCESS,
8164 &spr_read_generic, &spr_write_generic,
8165 KVM_REG_PPC_DSCR, 0x00000000);
8166 #endif
8167 /*
8168 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
8169 * POWERPC_EXCP_INVAL_SPR.
8170 */
8171 spr_register(env, SPR_PCR, "PCR",
8172 SPR_NOACCESS, SPR_NOACCESS,
8173 SPR_NOACCESS, SPR_NOACCESS,
8174 0x00000000);
8175 }
8176
8177 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
8178 {
8179 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8180 spr_read_generic(ctx, gprn, sprn);
8181 }
8182
8183 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
8184 {
8185 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8186 spr_write_generic(ctx, sprn, gprn);
8187 }
8188
8189 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
8190 {
8191 spr_register_kvm(env, SPR_TAR, "TAR",
8192 &spr_read_tar, &spr_write_tar,
8193 &spr_read_generic, &spr_write_generic,
8194 KVM_REG_PPC_TAR, 0x00000000);
8195 }
8196
8197 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
8198 {
8199 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8200 spr_read_generic(ctx, gprn, sprn);
8201 }
8202
8203 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
8204 {
8205 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8206 spr_write_generic(ctx, sprn, gprn);
8207 }
8208
8209 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
8210 {
8211 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8212 spr_read_prev_upper32(ctx, gprn, sprn);
8213 }
8214
8215 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
8216 {
8217 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8218 spr_write_prev_upper32(ctx, sprn, gprn);
8219 }
8220
8221 static void gen_spr_power8_tm(CPUPPCState *env)
8222 {
8223 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
8224 &spr_read_tm, &spr_write_tm,
8225 &spr_read_tm, &spr_write_tm,
8226 KVM_REG_PPC_TFHAR, 0x00000000);
8227 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
8228 &spr_read_tm, &spr_write_tm,
8229 &spr_read_tm, &spr_write_tm,
8230 KVM_REG_PPC_TFIAR, 0x00000000);
8231 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
8232 &spr_read_tm, &spr_write_tm,
8233 &spr_read_tm, &spr_write_tm,
8234 KVM_REG_PPC_TEXASR, 0x00000000);
8235 spr_register(env, SPR_TEXASRU, "TEXASRU",
8236 &spr_read_tm_upper32, &spr_write_tm_upper32,
8237 &spr_read_tm_upper32, &spr_write_tm_upper32,
8238 0x00000000);
8239 }
8240
8241 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
8242 {
8243 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8244 spr_read_generic(ctx, gprn, sprn);
8245 }
8246
8247 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
8248 {
8249 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8250 spr_write_generic(ctx, sprn, gprn);
8251 }
8252
8253 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
8254 {
8255 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8256 spr_read_prev_upper32(ctx, gprn, sprn);
8257 }
8258
8259 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
8260 {
8261 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8262 spr_write_prev_upper32(ctx, sprn, gprn);
8263 }
8264
8265 static void gen_spr_power8_ebb(CPUPPCState *env)
8266 {
8267 spr_register(env, SPR_BESCRS, "BESCRS",
8268 &spr_read_ebb, &spr_write_ebb,
8269 &spr_read_generic, &spr_write_generic,
8270 0x00000000);
8271 spr_register(env, SPR_BESCRSU, "BESCRSU",
8272 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8273 &spr_read_prev_upper32, &spr_write_prev_upper32,
8274 0x00000000);
8275 spr_register(env, SPR_BESCRR, "BESCRR",
8276 &spr_read_ebb, &spr_write_ebb,
8277 &spr_read_generic, &spr_write_generic,
8278 0x00000000);
8279 spr_register(env, SPR_BESCRRU, "BESCRRU",
8280 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8281 &spr_read_prev_upper32, &spr_write_prev_upper32,
8282 0x00000000);
8283 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
8284 &spr_read_ebb, &spr_write_ebb,
8285 &spr_read_generic, &spr_write_generic,
8286 KVM_REG_PPC_EBBHR, 0x00000000);
8287 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
8288 &spr_read_ebb, &spr_write_ebb,
8289 &spr_read_generic, &spr_write_generic,
8290 KVM_REG_PPC_EBBRR, 0x00000000);
8291 spr_register_kvm(env, SPR_BESCR, "BESCR",
8292 &spr_read_ebb, &spr_write_ebb,
8293 &spr_read_generic, &spr_write_generic,
8294 KVM_REG_PPC_BESCR, 0x00000000);
8295 }
8296
8297 /* Virtual Time Base */
8298 static void gen_spr_vtb(CPUPPCState *env)
8299 {
8300 spr_register(env, SPR_VTB, "VTB",
8301 SPR_NOACCESS, SPR_NOACCESS,
8302 &spr_read_tbl, SPR_NOACCESS,
8303 0x00000000);
8304 }
8305
8306 static void gen_spr_power8_fscr(CPUPPCState *env)
8307 {
8308 #if defined(CONFIG_USER_ONLY)
8309 target_ulong initval = 1ULL << FSCR_TAR;
8310 #else
8311 target_ulong initval = 0;
8312 #endif
8313 spr_register_kvm(env, SPR_FSCR, "FSCR",
8314 SPR_NOACCESS, SPR_NOACCESS,
8315 &spr_read_generic, &spr_write_generic,
8316 KVM_REG_PPC_FSCR, initval);
8317 }
8318
8319 static void gen_spr_power8_pspb(CPUPPCState *env)
8320 {
8321 spr_register_kvm(env, SPR_PSPB, "PSPB",
8322 SPR_NOACCESS, SPR_NOACCESS,
8323 &spr_read_generic, &spr_write_generic32,
8324 KVM_REG_PPC_PSPB, 0);
8325 }
8326
8327 static void gen_spr_power8_ic(CPUPPCState *env)
8328 {
8329 #if !defined(CONFIG_USER_ONLY)
8330 spr_register_hv(env, SPR_IC, "IC",
8331 SPR_NOACCESS, SPR_NOACCESS,
8332 &spr_read_generic, SPR_NOACCESS,
8333 &spr_read_generic, &spr_write_generic,
8334 0);
8335 #endif
8336 }
8337
8338 static void gen_spr_power8_book4(CPUPPCState *env)
8339 {
8340 /* Add a number of P8 book4 registers */
8341 #if !defined(CONFIG_USER_ONLY)
8342 spr_register_kvm(env, SPR_ACOP, "ACOP",
8343 SPR_NOACCESS, SPR_NOACCESS,
8344 &spr_read_generic, &spr_write_generic,
8345 KVM_REG_PPC_ACOP, 0);
8346 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8347 SPR_NOACCESS, SPR_NOACCESS,
8348 &spr_read_generic, &spr_write_pidr,
8349 KVM_REG_PPC_PID, 0);
8350 spr_register_kvm(env, SPR_WORT, "WORT",
8351 SPR_NOACCESS, SPR_NOACCESS,
8352 &spr_read_generic, &spr_write_generic,
8353 KVM_REG_PPC_WORT, 0);
8354 #endif
8355 }
8356
8357 static void gen_spr_power7_book4(CPUPPCState *env)
8358 {
8359 /* Add a number of P7 book4 registers */
8360 #if !defined(CONFIG_USER_ONLY)
8361 spr_register_kvm(env, SPR_ACOP, "ACOP",
8362 SPR_NOACCESS, SPR_NOACCESS,
8363 &spr_read_generic, &spr_write_generic,
8364 KVM_REG_PPC_ACOP, 0);
8365 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8366 SPR_NOACCESS, SPR_NOACCESS,
8367 &spr_read_generic, &spr_write_generic,
8368 KVM_REG_PPC_PID, 0);
8369 #endif
8370 }
8371
8372 static void gen_spr_power8_rpr(CPUPPCState *env)
8373 {
8374 #if !defined(CONFIG_USER_ONLY)
8375 spr_register_hv(env, SPR_RPR, "RPR",
8376 SPR_NOACCESS, SPR_NOACCESS,
8377 SPR_NOACCESS, SPR_NOACCESS,
8378 &spr_read_generic, &spr_write_generic,
8379 0x00000103070F1F3F);
8380 #endif
8381 }
8382
8383 static void init_proc_book3s_common(CPUPPCState *env)
8384 {
8385 gen_spr_ne_601(env);
8386 gen_tbl(env);
8387 gen_spr_usprg3(env);
8388 gen_spr_book3s_altivec(env);
8389 gen_spr_book3s_pmu_sup(env);
8390 gen_spr_book3s_pmu_user(env);
8391 gen_spr_book3s_ctrl(env);
8392 }
8393
8394 static void init_proc_970(CPUPPCState *env)
8395 {
8396 /* Common Registers */
8397 init_proc_book3s_common(env);
8398 gen_spr_sdr1(env);
8399 gen_spr_book3s_dbg(env);
8400
8401 /* 970 Specific Registers */
8402 gen_spr_970_hid(env);
8403 gen_spr_970_hior(env);
8404 gen_low_BATs(env);
8405 gen_spr_970_pmu_sup(env);
8406 gen_spr_970_pmu_user(env);
8407 gen_spr_970_lpar(env);
8408 gen_spr_970_dbg(env);
8409
8410 /* env variables */
8411 #if !defined(CONFIG_USER_ONLY)
8412 env->slb_nr = 64;
8413 #endif
8414 env->dcache_line_size = 128;
8415 env->icache_line_size = 128;
8416
8417 /* Allocate hardware IRQ controller */
8418 init_excp_970(env);
8419 ppc970_irq_init(ppc_env_get_cpu(env));
8420 }
8421
8422 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8423 {
8424 DeviceClass *dc = DEVICE_CLASS(oc);
8425 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8426
8427 dc->desc = "PowerPC 970";
8428 pcc->init_proc = init_proc_970;
8429 pcc->check_pow = check_pow_970;
8430 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8431 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8432 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8433 PPC_FLOAT_STFIWX |
8434 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8435 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8436 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8437 PPC_64B | PPC_ALTIVEC |
8438 PPC_SEGMENT_64B | PPC_SLBI;
8439 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8440 pcc->msr_mask = (1ull << MSR_SF) |
8441 (1ull << MSR_VR) |
8442 (1ull << MSR_POW) |
8443 (1ull << MSR_EE) |
8444 (1ull << MSR_PR) |
8445 (1ull << MSR_FP) |
8446 (1ull << MSR_ME) |
8447 (1ull << MSR_FE0) |
8448 (1ull << MSR_SE) |
8449 (1ull << MSR_DE) |
8450 (1ull << MSR_FE1) |
8451 (1ull << MSR_IR) |
8452 (1ull << MSR_DR) |
8453 (1ull << MSR_PMM) |
8454 (1ull << MSR_RI);
8455 pcc->mmu_model = POWERPC_MMU_64B;
8456 #if defined(CONFIG_SOFTMMU)
8457 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8458 #endif
8459 pcc->excp_model = POWERPC_EXCP_970;
8460 pcc->bus_model = PPC_FLAGS_INPUT_970;
8461 pcc->bfd_mach = bfd_mach_ppc64;
8462 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8463 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8464 POWERPC_FLAG_BUS_CLK;
8465 pcc->l1_dcache_size = 0x8000;
8466 pcc->l1_icache_size = 0x10000;
8467 }
8468
8469 static void init_proc_power5plus(CPUPPCState *env)
8470 {
8471 /* Common Registers */
8472 init_proc_book3s_common(env);
8473 gen_spr_sdr1(env);
8474 gen_spr_book3s_dbg(env);
8475
8476 /* POWER5+ Specific Registers */
8477 gen_spr_970_hid(env);
8478 gen_spr_970_hior(env);
8479 gen_low_BATs(env);
8480 gen_spr_970_pmu_sup(env);
8481 gen_spr_970_pmu_user(env);
8482 gen_spr_power5p_common(env);
8483 gen_spr_power5p_lpar(env);
8484 gen_spr_power5p_ear(env);
8485
8486 /* env variables */
8487 #if !defined(CONFIG_USER_ONLY)
8488 env->slb_nr = 64;
8489 #endif
8490 env->dcache_line_size = 128;
8491 env->icache_line_size = 128;
8492
8493 /* Allocate hardware IRQ controller */
8494 init_excp_970(env);
8495 ppc970_irq_init(ppc_env_get_cpu(env));
8496 }
8497
8498 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8499 {
8500 DeviceClass *dc = DEVICE_CLASS(oc);
8501 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8502
8503 dc->fw_name = "PowerPC,POWER5";
8504 dc->desc = "POWER5+";
8505 pcc->init_proc = init_proc_power5plus;
8506 pcc->check_pow = check_pow_970;
8507 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8508 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8509 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8510 PPC_FLOAT_STFIWX |
8511 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8512 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8513 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8514 PPC_64B |
8515 PPC_SEGMENT_64B | PPC_SLBI;
8516 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8517 pcc->msr_mask = (1ull << MSR_SF) |
8518 (1ull << MSR_VR) |
8519 (1ull << MSR_POW) |
8520 (1ull << MSR_EE) |
8521 (1ull << MSR_PR) |
8522 (1ull << MSR_FP) |
8523 (1ull << MSR_ME) |
8524 (1ull << MSR_FE0) |
8525 (1ull << MSR_SE) |
8526 (1ull << MSR_DE) |
8527 (1ull << MSR_FE1) |
8528 (1ull << MSR_IR) |
8529 (1ull << MSR_DR) |
8530 (1ull << MSR_PMM) |
8531 (1ull << MSR_RI);
8532 pcc->mmu_model = POWERPC_MMU_2_03;
8533 #if defined(CONFIG_SOFTMMU)
8534 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8535 #endif
8536 pcc->excp_model = POWERPC_EXCP_970;
8537 pcc->bus_model = PPC_FLAGS_INPUT_970;
8538 pcc->bfd_mach = bfd_mach_ppc64;
8539 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8540 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8541 POWERPC_FLAG_BUS_CLK;
8542 pcc->l1_dcache_size = 0x8000;
8543 pcc->l1_icache_size = 0x10000;
8544 }
8545
8546 /*
8547 * The CPU used to have a "compat" property which set the
8548 * compatibility mode PVR. However, this was conceptually broken - it
8549 * only makes sense on the pseries machine type (otherwise the guest
8550 * owns the PCR and can control the compatibility mode itself). It's
8551 * been replaced with the 'max-cpu-compat' property on the pseries
8552 * machine type. For backwards compatibility, pseries specially
8553 * parses the -cpu parameter and converts old compat= parameters into
8554 * the appropriate machine parameters. This stub implementation of
8555 * the parameter catches any uses on explicitly created CPUs.
8556 */
8557 static void getset_compat_deprecated(Object *obj, Visitor *v, const char *name,
8558 void *opaque, Error **errp)
8559 {
8560 QNull *null = NULL;
8561
8562 if (!qtest_enabled()) {
8563 error_report("CPU 'compat' property is deprecated and has no effect; "
8564 "use max-cpu-compat machine property instead");
8565 }
8566 visit_type_null(v, name, &null, NULL);
8567 QDECREF(null);
8568 }
8569
8570 static const PropertyInfo ppc_compat_deprecated_propinfo = {
8571 .name = "str",
8572 .description = "compatibility mode (deprecated)",
8573 .get = getset_compat_deprecated,
8574 .set = getset_compat_deprecated,
8575 };
8576 static Property powerpc_servercpu_properties[] = {
8577 {
8578 .name = "compat",
8579 .info = &ppc_compat_deprecated_propinfo,
8580 },
8581 DEFINE_PROP_END_OF_LIST(),
8582 };
8583
8584 #ifdef CONFIG_SOFTMMU
8585 static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
8586 .sps = {
8587 {
8588 .page_shift = 12, /* 4K */
8589 .slb_enc = 0,
8590 .enc = { { .page_shift = 12, .pte_enc = 0 },
8591 { .page_shift = 16, .pte_enc = 0x7 },
8592 { .page_shift = 24, .pte_enc = 0x38 }, },
8593 },
8594 {
8595 .page_shift = 16, /* 64K */
8596 .slb_enc = SLB_VSID_64K,
8597 .enc = { { .page_shift = 16, .pte_enc = 0x1 },
8598 { .page_shift = 24, .pte_enc = 0x8 }, },
8599 },
8600 {
8601 .page_shift = 24, /* 16M */
8602 .slb_enc = SLB_VSID_16M,
8603 .enc = { { .page_shift = 24, .pte_enc = 0 }, },
8604 },
8605 {
8606 .page_shift = 34, /* 16G */
8607 .slb_enc = SLB_VSID_16G,
8608 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
8609 },
8610 }
8611 };
8612 #endif /* CONFIG_SOFTMMU */
8613
8614 static void init_proc_POWER7(CPUPPCState *env)
8615 {
8616 /* Common Registers */
8617 init_proc_book3s_common(env);
8618 gen_spr_sdr1(env);
8619 gen_spr_book3s_dbg(env);
8620
8621 /* POWER7 Specific Registers */
8622 gen_spr_book3s_ids(env);
8623 gen_spr_amr(env);
8624 gen_spr_book3s_purr(env);
8625 gen_spr_power5p_common(env);
8626 gen_spr_power5p_lpar(env);
8627 gen_spr_power5p_ear(env);
8628 gen_spr_power6_common(env);
8629 gen_spr_power6_dbg(env);
8630 gen_spr_power7_book4(env);
8631
8632 /* env variables */
8633 #if !defined(CONFIG_USER_ONLY)
8634 env->slb_nr = 32;
8635 #endif
8636 env->ci_large_pages = true;
8637 env->dcache_line_size = 128;
8638 env->icache_line_size = 128;
8639
8640 /* Allocate hardware IRQ controller */
8641 init_excp_POWER7(env);
8642 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8643 }
8644
8645 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8646 {
8647 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8648 return true;
8649 }
8650 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8651 return true;
8652 }
8653 return false;
8654 }
8655
8656 static bool cpu_has_work_POWER7(CPUState *cs)
8657 {
8658 PowerPCCPU *cpu = POWERPC_CPU(cs);
8659 CPUPPCState *env = &cpu->env;
8660
8661 if (cs->halted) {
8662 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8663 return false;
8664 }
8665 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8666 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
8667 return true;
8668 }
8669 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8670 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
8671 return true;
8672 }
8673 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8674 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8675 return true;
8676 }
8677 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8678 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8679 return true;
8680 }
8681 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8682 return true;
8683 }
8684 return false;
8685 } else {
8686 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8687 }
8688 }
8689
8690 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8691 {
8692 DeviceClass *dc = DEVICE_CLASS(oc);
8693 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8694 CPUClass *cc = CPU_CLASS(oc);
8695
8696 dc->fw_name = "PowerPC,POWER7";
8697 dc->desc = "POWER7";
8698 dc->props = powerpc_servercpu_properties;
8699 pcc->pvr_match = ppc_pvr_match_power7;
8700 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8701 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8702 pcc->init_proc = init_proc_POWER7;
8703 pcc->check_pow = check_pow_nocheck;
8704 cc->has_work = cpu_has_work_POWER7;
8705 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8706 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8707 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8708 PPC_FLOAT_FRSQRTES |
8709 PPC_FLOAT_STFIWX |
8710 PPC_FLOAT_EXT |
8711 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8712 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8713 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8714 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8715 PPC_SEGMENT_64B | PPC_SLBI |
8716 PPC_POPCNTB | PPC_POPCNTWD |
8717 PPC_CILDST;
8718 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8719 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8720 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8721 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
8722 PPC2_PM_ISA206;
8723 pcc->msr_mask = (1ull << MSR_SF) |
8724 (1ull << MSR_VR) |
8725 (1ull << MSR_VSX) |
8726 (1ull << MSR_EE) |
8727 (1ull << MSR_PR) |
8728 (1ull << MSR_FP) |
8729 (1ull << MSR_ME) |
8730 (1ull << MSR_FE0) |
8731 (1ull << MSR_SE) |
8732 (1ull << MSR_DE) |
8733 (1ull << MSR_FE1) |
8734 (1ull << MSR_IR) |
8735 (1ull << MSR_DR) |
8736 (1ull << MSR_PMM) |
8737 (1ull << MSR_RI) |
8738 (1ull << MSR_LE);
8739 pcc->mmu_model = POWERPC_MMU_2_06;
8740 #if defined(CONFIG_SOFTMMU)
8741 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8742 pcc->sps = &POWER7_POWER8_sps;
8743 #endif
8744 pcc->excp_model = POWERPC_EXCP_POWER7;
8745 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8746 pcc->bfd_mach = bfd_mach_ppc64;
8747 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8748 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8749 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8750 POWERPC_FLAG_VSX;
8751 pcc->l1_dcache_size = 0x8000;
8752 pcc->l1_icache_size = 0x8000;
8753 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8754 }
8755
8756 static void init_proc_POWER8(CPUPPCState *env)
8757 {
8758 /* Common Registers */
8759 init_proc_book3s_common(env);
8760 gen_spr_sdr1(env);
8761 gen_spr_book3s_207_dbg(env);
8762
8763 /* POWER8 Specific Registers */
8764 gen_spr_book3s_ids(env);
8765 gen_spr_amr(env);
8766 gen_spr_iamr(env);
8767 gen_spr_book3s_purr(env);
8768 gen_spr_power5p_common(env);
8769 gen_spr_power5p_lpar(env);
8770 gen_spr_power5p_ear(env);
8771 gen_spr_power6_common(env);
8772 gen_spr_power6_dbg(env);
8773 gen_spr_power8_tce_address_control(env);
8774 gen_spr_power8_ids(env);
8775 gen_spr_power8_ebb(env);
8776 gen_spr_power8_fscr(env);
8777 gen_spr_power8_pmu_sup(env);
8778 gen_spr_power8_pmu_user(env);
8779 gen_spr_power8_tm(env);
8780 gen_spr_power8_pspb(env);
8781 gen_spr_vtb(env);
8782 gen_spr_power8_ic(env);
8783 gen_spr_power8_book4(env);
8784 gen_spr_power8_rpr(env);
8785
8786 /* env variables */
8787 #if !defined(CONFIG_USER_ONLY)
8788 env->slb_nr = 32;
8789 #endif
8790 env->ci_large_pages = true;
8791 env->dcache_line_size = 128;
8792 env->icache_line_size = 128;
8793
8794 /* Allocate hardware IRQ controller */
8795 init_excp_POWER8(env);
8796 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8797 }
8798
8799 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8800 {
8801 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8802 return true;
8803 }
8804 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8805 return true;
8806 }
8807 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8808 return true;
8809 }
8810 return false;
8811 }
8812
8813 static bool cpu_has_work_POWER8(CPUState *cs)
8814 {
8815 PowerPCCPU *cpu = POWERPC_CPU(cs);
8816 CPUPPCState *env = &cpu->env;
8817
8818 if (cs->halted) {
8819 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8820 return false;
8821 }
8822 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8823 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
8824 return true;
8825 }
8826 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8827 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
8828 return true;
8829 }
8830 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8831 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8832 return true;
8833 }
8834 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8835 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8836 return true;
8837 }
8838 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8839 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
8840 return true;
8841 }
8842 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8843 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
8844 return true;
8845 }
8846 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8847 return true;
8848 }
8849 return false;
8850 } else {
8851 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8852 }
8853 }
8854
8855 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8856 {
8857 DeviceClass *dc = DEVICE_CLASS(oc);
8858 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8859 CPUClass *cc = CPU_CLASS(oc);
8860
8861 dc->fw_name = "PowerPC,POWER8";
8862 dc->desc = "POWER8";
8863 dc->props = powerpc_servercpu_properties;
8864 pcc->pvr_match = ppc_pvr_match_power8;
8865 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8866 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8867 pcc->init_proc = init_proc_POWER8;
8868 pcc->check_pow = check_pow_nocheck;
8869 cc->has_work = cpu_has_work_POWER8;
8870 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8871 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8872 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8873 PPC_FLOAT_FRSQRTES |
8874 PPC_FLOAT_STFIWX |
8875 PPC_FLOAT_EXT |
8876 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8877 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8878 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8879 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8880 PPC_SEGMENT_64B | PPC_SLBI |
8881 PPC_POPCNTB | PPC_POPCNTWD |
8882 PPC_CILDST;
8883 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8884 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8885 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8886 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8887 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8888 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8889 PPC2_TM | PPC2_PM_ISA206;
8890 pcc->msr_mask = (1ull << MSR_SF) |
8891 (1ull << MSR_SHV) |
8892 (1ull << MSR_TM) |
8893 (1ull << MSR_VR) |
8894 (1ull << MSR_VSX) |
8895 (1ull << MSR_EE) |
8896 (1ull << MSR_PR) |
8897 (1ull << MSR_FP) |
8898 (1ull << MSR_ME) |
8899 (1ull << MSR_FE0) |
8900 (1ull << MSR_SE) |
8901 (1ull << MSR_DE) |
8902 (1ull << MSR_FE1) |
8903 (1ull << MSR_IR) |
8904 (1ull << MSR_DR) |
8905 (1ull << MSR_PMM) |
8906 (1ull << MSR_RI) |
8907 (1ull << MSR_LE);
8908 pcc->mmu_model = POWERPC_MMU_2_07;
8909 #if defined(CONFIG_SOFTMMU)
8910 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8911 pcc->sps = &POWER7_POWER8_sps;
8912 #endif
8913 pcc->excp_model = POWERPC_EXCP_POWER8;
8914 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8915 pcc->bfd_mach = bfd_mach_ppc64;
8916 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8917 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8918 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8919 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8920 pcc->l1_dcache_size = 0x8000;
8921 pcc->l1_icache_size = 0x8000;
8922 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8923 }
8924
8925 #ifdef CONFIG_SOFTMMU
8926 /*
8927 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8928 * Encoded as array of int_32s in the form:
8929 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8930 * x -> AP encoding
8931 * y -> radix mode supported page size (encoded as a shift)
8932 */
8933 static struct ppc_radix_page_info POWER9_radix_page_info = {
8934 .count = 4,
8935 .entries = {
8936 0x0000000c, /* 4K - enc: 0x0 */
8937 0xa0000010, /* 64K - enc: 0x5 */
8938 0x20000015, /* 2M - enc: 0x1 */
8939 0x4000001e /* 1G - enc: 0x2 */
8940 }
8941 };
8942 #endif /* CONFIG_SOFTMMU */
8943
8944 static void init_proc_POWER9(CPUPPCState *env)
8945 {
8946 /* Common Registers */
8947 init_proc_book3s_common(env);
8948 gen_spr_book3s_207_dbg(env);
8949
8950 /* POWER8 Specific Registers */
8951 gen_spr_book3s_ids(env);
8952 gen_spr_amr(env);
8953 gen_spr_iamr(env);
8954 gen_spr_book3s_purr(env);
8955 gen_spr_power5p_common(env);
8956 gen_spr_power5p_lpar(env);
8957 gen_spr_power5p_ear(env);
8958 gen_spr_power6_common(env);
8959 gen_spr_power6_dbg(env);
8960 gen_spr_power8_tce_address_control(env);
8961 gen_spr_power8_ids(env);
8962 gen_spr_power8_ebb(env);
8963 gen_spr_power8_fscr(env);
8964 gen_spr_power8_pmu_sup(env);
8965 gen_spr_power8_pmu_user(env);
8966 gen_spr_power8_tm(env);
8967 gen_spr_power8_pspb(env);
8968 gen_spr_vtb(env);
8969 gen_spr_power8_ic(env);
8970 gen_spr_power8_book4(env);
8971 gen_spr_power8_rpr(env);
8972
8973 /* POWER9 Specific registers */
8974 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
8975 spr_read_generic, spr_write_generic,
8976 KVM_REG_PPC_TIDR, 0);
8977
8978 /* FIXME: Filter fields properly based on privilege level */
8979 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8980 spr_read_generic, spr_write_generic,
8981 KVM_REG_PPC_PSSCR, 0);
8982
8983 /* env variables */
8984 #if !defined(CONFIG_USER_ONLY)
8985 env->slb_nr = 32;
8986 #endif
8987 env->ci_large_pages = true;
8988 env->dcache_line_size = 128;
8989 env->icache_line_size = 128;
8990
8991 /* Allocate hardware IRQ controller */
8992 init_excp_POWER8(env);
8993 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8994 }
8995
8996 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
8997 {
8998 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
8999 return true;
9000 }
9001 return false;
9002 }
9003
9004 static bool cpu_has_work_POWER9(CPUState *cs)
9005 {
9006 PowerPCCPU *cpu = POWERPC_CPU(cs);
9007 CPUPPCState *env = &cpu->env;
9008
9009 if (cs->halted) {
9010 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
9011 return false;
9012 }
9013 /* External Exception */
9014 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
9015 (env->spr[SPR_LPCR] & LPCR_EEE)) {
9016 return true;
9017 }
9018 /* Decrementer Exception */
9019 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
9020 (env->spr[SPR_LPCR] & LPCR_DEE)) {
9021 return true;
9022 }
9023 /* Machine Check or Hypervisor Maintenance Exception */
9024 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
9025 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
9026 return true;
9027 }
9028 /* Privileged Doorbell Exception */
9029 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
9030 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
9031 return true;
9032 }
9033 /* Hypervisor Doorbell Exception */
9034 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
9035 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
9036 return true;
9037 }
9038 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
9039 return true;
9040 }
9041 return false;
9042 } else {
9043 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9044 }
9045 }
9046
9047 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
9048 {
9049 DeviceClass *dc = DEVICE_CLASS(oc);
9050 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9051 CPUClass *cc = CPU_CLASS(oc);
9052
9053 dc->fw_name = "PowerPC,POWER9";
9054 dc->desc = "POWER9";
9055 dc->props = powerpc_servercpu_properties;
9056 pcc->pvr_match = ppc_pvr_match_power9;
9057 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
9058 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
9059 PCR_COMPAT_2_05;
9060 pcc->init_proc = init_proc_POWER9;
9061 pcc->check_pow = check_pow_nocheck;
9062 cc->has_work = cpu_has_work_POWER9;
9063 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
9064 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
9065 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
9066 PPC_FLOAT_FRSQRTES |
9067 PPC_FLOAT_STFIWX |
9068 PPC_FLOAT_EXT |
9069 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
9070 PPC_MEM_SYNC | PPC_MEM_EIEIO |
9071 PPC_MEM_TLBSYNC |
9072 PPC_64B | PPC_64BX | PPC_ALTIVEC |
9073 PPC_SEGMENT_64B | PPC_SLBI |
9074 PPC_POPCNTB | PPC_POPCNTWD |
9075 PPC_CILDST;
9076 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
9077 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
9078 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
9079 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
9080 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
9081 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
9082 PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300;
9083 pcc->msr_mask = (1ull << MSR_SF) |
9084 (1ull << MSR_TM) |
9085 (1ull << MSR_VR) |
9086 (1ull << MSR_VSX) |
9087 (1ull << MSR_EE) |
9088 (1ull << MSR_PR) |
9089 (1ull << MSR_FP) |
9090 (1ull << MSR_ME) |
9091 (1ull << MSR_FE0) |
9092 (1ull << MSR_SE) |
9093 (1ull << MSR_DE) |
9094 (1ull << MSR_FE1) |
9095 (1ull << MSR_IR) |
9096 (1ull << MSR_DR) |
9097 (1ull << MSR_PMM) |
9098 (1ull << MSR_RI) |
9099 (1ull << MSR_LE);
9100 pcc->mmu_model = POWERPC_MMU_3_00;
9101 #if defined(CONFIG_SOFTMMU)
9102 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
9103 /* segment page size remain the same */
9104 pcc->sps = &POWER7_POWER8_sps;
9105 pcc->radix_page_info = &POWER9_radix_page_info;
9106 #endif
9107 pcc->excp_model = POWERPC_EXCP_POWER8;
9108 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
9109 pcc->bfd_mach = bfd_mach_ppc64;
9110 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
9111 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
9112 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
9113 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
9114 pcc->l1_dcache_size = 0x8000;
9115 pcc->l1_icache_size = 0x8000;
9116 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
9117 }
9118
9119 #if !defined(CONFIG_USER_ONLY)
9120 void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
9121 {
9122 CPUPPCState *env = &cpu->env;
9123 ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
9124 ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
9125
9126 cpu->vhyp = vhyp;
9127
9128 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
9129 * MSR[IP] should never be set.
9130 *
9131 * We also disallow setting of MSR_HV
9132 */
9133 env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
9134
9135 /* Set emulated LPCR to not send interrupts to hypervisor. Note that
9136 * under KVM, the actual HW LPCR will be set differently by KVM itself,
9137 * the settings below ensure proper operations with TCG in absence of
9138 * a real hypervisor.
9139 *
9140 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
9141 * real mode accesses, which thankfully defaults to 0 and isn't
9142 * accessible in guest mode.
9143 */
9144 lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
9145 lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
9146
9147 /* Set RMLS to the max (ie, 16G) */
9148 lpcr->default_value &= ~LPCR_RMLS;
9149 lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
9150
9151 switch (env->mmu_model) {
9152 case POWERPC_MMU_3_00:
9153 /* By default we choose legacy mode and switch to new hash or radix
9154 * when a register process table hcall is made. So disable process
9155 * tables and guest translation shootdown by default
9156 *
9157 * Hot-plugged CPUs inherit from the guest radix setting under
9158 * KVM but not under TCG. Update the default LPCR to keep new
9159 * CPUs in sync when radix is enabled.
9160 */
9161 if (ppc64_radix_guest(cpu)) {
9162 lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
9163 } else {
9164 lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
9165 }
9166 lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
9167 LPCR_OEE;
9168 break;
9169 default:
9170 /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
9171 * bit 47 and 48 which are reserved on P7. Here we set them all, which
9172 * will work as expected for both implementations
9173 */
9174 lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
9175 LPCR_P8_PECE3 | LPCR_P8_PECE4;
9176 }
9177
9178 /* We should be followed by a CPU reset but update the active value
9179 * just in case...
9180 */
9181 env->spr[SPR_LPCR] = lpcr->default_value;
9182
9183 /* Set a full AMOR so guest can use the AMR as it sees fit */
9184 env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
9185
9186 /* Update some env bits based on new LPCR value */
9187 ppc_hash64_update_rmls(env);
9188 ppc_hash64_update_vrma(env);
9189
9190 /* Tell KVM that we're in PAPR mode */
9191 if (kvm_enabled()) {
9192 kvmppc_set_papr(cpu);
9193 }
9194 }
9195
9196 #endif /* !defined(CONFIG_USER_ONLY) */
9197
9198 #endif /* defined(TARGET_PPC64) */
9199
9200 /*****************************************************************************/
9201 /* Generic CPU instantiation routine */
9202 static void init_ppc_proc(PowerPCCPU *cpu)
9203 {
9204 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9205 CPUPPCState *env = &cpu->env;
9206 #if !defined(CONFIG_USER_ONLY)
9207 int i;
9208
9209 env->irq_inputs = NULL;
9210 /* Set all exception vectors to an invalid address */
9211 for (i = 0; i < POWERPC_EXCP_NB; i++)
9212 env->excp_vectors[i] = (target_ulong)(-1ULL);
9213 env->ivor_mask = 0x00000000;
9214 env->ivpr_mask = 0x00000000;
9215 /* Default MMU definitions */
9216 env->nb_BATs = 0;
9217 env->nb_tlb = 0;
9218 env->nb_ways = 0;
9219 env->tlb_type = TLB_NONE;
9220 #endif
9221 /* Register SPR common to all PowerPC implementations */
9222 gen_spr_generic(env);
9223 spr_register(env, SPR_PVR, "PVR",
9224 /* Linux permits userspace to read PVR */
9225 #if defined(CONFIG_LINUX_USER)
9226 &spr_read_generic,
9227 #else
9228 SPR_NOACCESS,
9229 #endif
9230 SPR_NOACCESS,
9231 &spr_read_generic, SPR_NOACCESS,
9232 pcc->pvr);
9233 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9234 if (pcc->svr != POWERPC_SVR_NONE) {
9235 if (pcc->svr & POWERPC_SVR_E500) {
9236 spr_register(env, SPR_E500_SVR, "SVR",
9237 SPR_NOACCESS, SPR_NOACCESS,
9238 &spr_read_generic, SPR_NOACCESS,
9239 pcc->svr & ~POWERPC_SVR_E500);
9240 } else {
9241 spr_register(env, SPR_SVR, "SVR",
9242 SPR_NOACCESS, SPR_NOACCESS,
9243 &spr_read_generic, SPR_NOACCESS,
9244 pcc->svr);
9245 }
9246 }
9247 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9248 (*pcc->init_proc)(env);
9249
9250 /* MSR bits & flags consistency checks */
9251 if (env->msr_mask & (1 << 25)) {
9252 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9253 case POWERPC_FLAG_SPE:
9254 case POWERPC_FLAG_VRE:
9255 break;
9256 default:
9257 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9258 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9259 exit(1);
9260 }
9261 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9262 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9263 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9264 exit(1);
9265 }
9266 if (env->msr_mask & (1 << 17)) {
9267 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9268 case POWERPC_FLAG_TGPR:
9269 case POWERPC_FLAG_CE:
9270 break;
9271 default:
9272 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9273 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9274 exit(1);
9275 }
9276 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9277 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9278 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9279 exit(1);
9280 }
9281 if (env->msr_mask & (1 << 10)) {
9282 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9283 POWERPC_FLAG_UBLE)) {
9284 case POWERPC_FLAG_SE:
9285 case POWERPC_FLAG_DWE:
9286 case POWERPC_FLAG_UBLE:
9287 break;
9288 default:
9289 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9290 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9291 "POWERPC_FLAG_UBLE\n");
9292 exit(1);
9293 }
9294 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9295 POWERPC_FLAG_UBLE)) {
9296 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9297 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9298 "POWERPC_FLAG_UBLE\n");
9299 exit(1);
9300 }
9301 if (env->msr_mask & (1 << 9)) {
9302 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9303 case POWERPC_FLAG_BE:
9304 case POWERPC_FLAG_DE:
9305 break;
9306 default:
9307 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9308 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9309 exit(1);
9310 }
9311 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9312 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9313 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9314 exit(1);
9315 }
9316 if (env->msr_mask & (1 << 2)) {
9317 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9318 case POWERPC_FLAG_PX:
9319 case POWERPC_FLAG_PMM:
9320 break;
9321 default:
9322 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9323 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9324 exit(1);
9325 }
9326 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9327 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9328 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9329 exit(1);
9330 }
9331 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9332 fprintf(stderr, "PowerPC flags inconsistency\n"
9333 "Should define the time-base and decrementer clock source\n");
9334 exit(1);
9335 }
9336 /* Allocate TLBs buffer when needed */
9337 #if !defined(CONFIG_USER_ONLY)
9338 if (env->nb_tlb != 0) {
9339 int nb_tlb = env->nb_tlb;
9340 if (env->id_tlbs != 0)
9341 nb_tlb *= 2;
9342 switch (env->tlb_type) {
9343 case TLB_6XX:
9344 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9345 break;
9346 case TLB_EMB:
9347 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9348 break;
9349 case TLB_MAS:
9350 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9351 break;
9352 }
9353 /* Pre-compute some useful values */
9354 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9355 }
9356 if (env->irq_inputs == NULL) {
9357 warn_report("no internal IRQ controller registered."
9358 " Attempt QEMU to crash very soon !");
9359 }
9360 #endif
9361 if (env->check_pow == NULL) {
9362 warn_report("no power management check handler registered."
9363 " Attempt QEMU to crash very soon !");
9364 }
9365 }
9366
9367 #if defined(PPC_DUMP_CPU)
9368 static void dump_ppc_sprs(CPUPPCState *env)
9369 {
9370 ppc_spr_t *spr;
9371 #if !defined(CONFIG_USER_ONLY)
9372 uint32_t sr, sw;
9373 #endif
9374 uint32_t ur, uw;
9375 int i, j, n;
9376
9377 printf("Special purpose registers:\n");
9378 for (i = 0; i < 32; i++) {
9379 for (j = 0; j < 32; j++) {
9380 n = (i << 5) | j;
9381 spr = &env->spr_cb[n];
9382 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9383 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9384 #if !defined(CONFIG_USER_ONLY)
9385 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9386 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9387 if (sw || sr || uw || ur) {
9388 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9389 (i << 5) | j, (i << 5) | j, spr->name,
9390 sw ? 'w' : '-', sr ? 'r' : '-',
9391 uw ? 'w' : '-', ur ? 'r' : '-');
9392 }
9393 #else
9394 if (uw || ur) {
9395 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9396 (i << 5) | j, (i << 5) | j, spr->name,
9397 uw ? 'w' : '-', ur ? 'r' : '-');
9398 }
9399 #endif
9400 }
9401 }
9402 fflush(stdout);
9403 fflush(stderr);
9404 }
9405 #endif
9406
9407 /*****************************************************************************/
9408
9409 /* Opcode types */
9410 enum {
9411 PPC_DIRECT = 0, /* Opcode routine */
9412 PPC_INDIRECT = 1, /* Indirect opcode table */
9413 };
9414
9415 #define PPC_OPCODE_MASK 0x3
9416
9417 static inline int is_indirect_opcode(void *handler)
9418 {
9419 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
9420 }
9421
9422 static inline opc_handler_t **ind_table(void *handler)
9423 {
9424 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
9425 }
9426
9427 /* Instruction table creation */
9428 /* Opcodes tables creation */
9429 static void fill_new_table(opc_handler_t **table, int len)
9430 {
9431 int i;
9432
9433 for (i = 0; i < len; i++)
9434 table[i] = &invalid_handler;
9435 }
9436
9437 static int create_new_table(opc_handler_t **table, unsigned char idx)
9438 {
9439 opc_handler_t **tmp;
9440
9441 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
9442 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
9443 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9444
9445 return 0;
9446 }
9447
9448 static int insert_in_table(opc_handler_t **table, unsigned char idx,
9449 opc_handler_t *handler)
9450 {
9451 if (table[idx] != &invalid_handler)
9452 return -1;
9453 table[idx] = handler;
9454
9455 return 0;
9456 }
9457
9458 static int register_direct_insn(opc_handler_t **ppc_opcodes,
9459 unsigned char idx, opc_handler_t *handler)
9460 {
9461 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9462 printf("*** ERROR: opcode %02x already assigned in main "
9463 "opcode table\n", idx);
9464 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9465 printf(" Registered handler '%s' - new handler '%s'\n",
9466 ppc_opcodes[idx]->oname, handler->oname);
9467 #endif
9468 return -1;
9469 }
9470
9471 return 0;
9472 }
9473
9474 static int register_ind_in_table(opc_handler_t **table,
9475 unsigned char idx1, unsigned char idx2,
9476 opc_handler_t *handler)
9477 {
9478 if (table[idx1] == &invalid_handler) {
9479 if (create_new_table(table, idx1) < 0) {
9480 printf("*** ERROR: unable to create indirect table "
9481 "idx=%02x\n", idx1);
9482 return -1;
9483 }
9484 } else {
9485 if (!is_indirect_opcode(table[idx1])) {
9486 printf("*** ERROR: idx %02x already assigned to a direct "
9487 "opcode\n", idx1);
9488 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9489 printf(" Registered handler '%s' - new handler '%s'\n",
9490 ind_table(table[idx1])[idx2]->oname, handler->oname);
9491 #endif
9492 return -1;
9493 }
9494 }
9495 if (handler != NULL &&
9496 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9497 printf("*** ERROR: opcode %02x already assigned in "
9498 "opcode table %02x\n", idx2, idx1);
9499 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9500 printf(" Registered handler '%s' - new handler '%s'\n",
9501 ind_table(table[idx1])[idx2]->oname, handler->oname);
9502 #endif
9503 return -1;
9504 }
9505
9506 return 0;
9507 }
9508
9509 static int register_ind_insn(opc_handler_t **ppc_opcodes,
9510 unsigned char idx1, unsigned char idx2,
9511 opc_handler_t *handler)
9512 {
9513 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9514 }
9515
9516 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
9517 unsigned char idx1, unsigned char idx2,
9518 unsigned char idx3, opc_handler_t *handler)
9519 {
9520 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9521 printf("*** ERROR: unable to join indirect table idx "
9522 "[%02x-%02x]\n", idx1, idx2);
9523 return -1;
9524 }
9525 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9526 handler) < 0) {
9527 printf("*** ERROR: unable to insert opcode "
9528 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9529 return -1;
9530 }
9531
9532 return 0;
9533 }
9534
9535 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
9536 unsigned char idx1, unsigned char idx2,
9537 unsigned char idx3, unsigned char idx4,
9538 opc_handler_t *handler)
9539 {
9540 opc_handler_t **table;
9541
9542 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9543 printf("*** ERROR: unable to join indirect table idx "
9544 "[%02x-%02x]\n", idx1, idx2);
9545 return -1;
9546 }
9547 table = ind_table(ppc_opcodes[idx1]);
9548 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
9549 printf("*** ERROR: unable to join 2nd-level indirect table idx "
9550 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9551 return -1;
9552 }
9553 table = ind_table(table[idx2]);
9554 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
9555 printf("*** ERROR: unable to insert opcode "
9556 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
9557 return -1;
9558 }
9559 return 0;
9560 }
9561 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
9562 {
9563 if (insn->opc2 != 0xFF) {
9564 if (insn->opc3 != 0xFF) {
9565 if (insn->opc4 != 0xFF) {
9566 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9567 insn->opc3, insn->opc4,
9568 &insn->handler) < 0) {
9569 return -1;
9570 }
9571 } else {
9572 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9573 insn->opc3, &insn->handler) < 0)
9574 return -1;
9575 }
9576 } else {
9577 if (register_ind_insn(ppc_opcodes, insn->opc1,
9578 insn->opc2, &insn->handler) < 0)
9579 return -1;
9580 }
9581 } else {
9582 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9583 return -1;
9584 }
9585
9586 return 0;
9587 }
9588
9589 static int test_opcode_table(opc_handler_t **table, int len)
9590 {
9591 int i, count, tmp;
9592
9593 for (i = 0, count = 0; i < len; i++) {
9594 /* Consistency fixup */
9595 if (table[i] == NULL)
9596 table[i] = &invalid_handler;
9597 if (table[i] != &invalid_handler) {
9598 if (is_indirect_opcode(table[i])) {
9599 tmp = test_opcode_table(ind_table(table[i]),
9600 PPC_CPU_INDIRECT_OPCODES_LEN);
9601 if (tmp == 0) {
9602 free(table[i]);
9603 table[i] = &invalid_handler;
9604 } else {
9605 count++;
9606 }
9607 } else {
9608 count++;
9609 }
9610 }
9611 }
9612
9613 return count;
9614 }
9615
9616 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
9617 {
9618 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
9619 printf("*** WARNING: no opcode defined !\n");
9620 }
9621
9622 /*****************************************************************************/
9623 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9624 {
9625 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9626 CPUPPCState *env = &cpu->env;
9627 opcode_t *opc;
9628
9629 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
9630 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9631 if (((opc->handler.type & pcc->insns_flags) != 0) ||
9632 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
9633 if (register_insn(env->opcodes, opc) < 0) {
9634 error_setg(errp, "ERROR initializing PowerPC instruction "
9635 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9636 opc->opc3);
9637 return;
9638 }
9639 }
9640 }
9641 fix_opcode_tables(env->opcodes);
9642 fflush(stdout);
9643 fflush(stderr);
9644 }
9645
9646 #if defined(PPC_DUMP_CPU)
9647 static void dump_ppc_insns(CPUPPCState *env)
9648 {
9649 opc_handler_t **table, *handler;
9650 const char *p, *q;
9651 uint8_t opc1, opc2, opc3, opc4;
9652
9653 printf("Instructions set:\n");
9654 /* opc1 is 6 bits long */
9655 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
9656 table = env->opcodes;
9657 handler = table[opc1];
9658 if (is_indirect_opcode(handler)) {
9659 /* opc2 is 5 bits long */
9660 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
9661 table = env->opcodes;
9662 handler = env->opcodes[opc1];
9663 table = ind_table(handler);
9664 handler = table[opc2];
9665 if (is_indirect_opcode(handler)) {
9666 table = ind_table(handler);
9667 /* opc3 is 5 bits long */
9668 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
9669 opc3++) {
9670 handler = table[opc3];
9671 if (is_indirect_opcode(handler)) {
9672 table = ind_table(handler);
9673 /* opc4 is 5 bits long */
9674 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
9675 opc4++) {
9676 handler = table[opc4];
9677 if (handler->handler != &gen_invalid) {
9678 printf("INSN: %02x %02x %02x %02x -- "
9679 "(%02d %04d %02d) : %s\n",
9680 opc1, opc2, opc3, opc4,
9681 opc1, (opc3 << 5) | opc2, opc4,
9682 handler->oname);
9683 }
9684 }
9685 } else {
9686 if (handler->handler != &gen_invalid) {
9687 /* Special hack to properly dump SPE insns */
9688 p = strchr(handler->oname, '_');
9689 if (p == NULL) {
9690 printf("INSN: %02x %02x %02x (%02d %04d) : "
9691 "%s\n",
9692 opc1, opc2, opc3, opc1,
9693 (opc3 << 5) | opc2,
9694 handler->oname);
9695 } else {
9696 q = "speundef";
9697 if ((p - handler->oname) != strlen(q)
9698 || (memcmp(handler->oname, q, strlen(q))
9699 != 0)) {
9700 /* First instruction */
9701 printf("INSN: %02x %02x %02x"
9702 "(%02d %04d) : %.*s\n",
9703 opc1, opc2 << 1, opc3, opc1,
9704 (opc3 << 6) | (opc2 << 1),
9705 (int)(p - handler->oname),
9706 handler->oname);
9707 }
9708 if (strcmp(p + 1, q) != 0) {
9709 /* Second instruction */
9710 printf("INSN: %02x %02x %02x "
9711 "(%02d %04d) : %s\n", opc1,
9712 (opc2 << 1) | 1, opc3, opc1,
9713 (opc3 << 6) | (opc2 << 1) | 1,
9714 p + 1);
9715 }
9716 }
9717 }
9718 }
9719 }
9720 } else {
9721 if (handler->handler != &gen_invalid) {
9722 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9723 opc1, opc2, opc1, opc2, handler->oname);
9724 }
9725 }
9726 }
9727 } else {
9728 if (handler->handler != &gen_invalid) {
9729 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9730 opc1, opc1, handler->oname);
9731 }
9732 }
9733 }
9734 }
9735 #endif
9736
9737 static bool avr_need_swap(CPUPPCState *env)
9738 {
9739 #ifdef HOST_WORDS_BIGENDIAN
9740 return msr_le;
9741 #else
9742 return !msr_le;
9743 #endif
9744 }
9745
9746 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9747 {
9748 if (n < 32) {
9749 stfq_p(mem_buf, env->fpr[n]);
9750 ppc_maybe_bswap_register(env, mem_buf, 8);
9751 return 8;
9752 }
9753 if (n == 32) {
9754 stl_p(mem_buf, env->fpscr);
9755 ppc_maybe_bswap_register(env, mem_buf, 4);
9756 return 4;
9757 }
9758 return 0;
9759 }
9760
9761 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9762 {
9763 if (n < 32) {
9764 ppc_maybe_bswap_register(env, mem_buf, 8);
9765 env->fpr[n] = ldfq_p(mem_buf);
9766 return 8;
9767 }
9768 if (n == 32) {
9769 ppc_maybe_bswap_register(env, mem_buf, 4);
9770 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9771 return 4;
9772 }
9773 return 0;
9774 }
9775
9776 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9777 {
9778 if (n < 32) {
9779 if (!avr_need_swap(env)) {
9780 stq_p(mem_buf, env->avr[n].u64[0]);
9781 stq_p(mem_buf+8, env->avr[n].u64[1]);
9782 } else {
9783 stq_p(mem_buf, env->avr[n].u64[1]);
9784 stq_p(mem_buf+8, env->avr[n].u64[0]);
9785 }
9786 ppc_maybe_bswap_register(env, mem_buf, 8);
9787 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9788 return 16;
9789 }
9790 if (n == 32) {
9791 stl_p(mem_buf, env->vscr);
9792 ppc_maybe_bswap_register(env, mem_buf, 4);
9793 return 4;
9794 }
9795 if (n == 33) {
9796 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9797 ppc_maybe_bswap_register(env, mem_buf, 4);
9798 return 4;
9799 }
9800 return 0;
9801 }
9802
9803 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9804 {
9805 if (n < 32) {
9806 ppc_maybe_bswap_register(env, mem_buf, 8);
9807 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9808 if (!avr_need_swap(env)) {
9809 env->avr[n].u64[0] = ldq_p(mem_buf);
9810 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9811 } else {
9812 env->avr[n].u64[1] = ldq_p(mem_buf);
9813 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9814 }
9815 return 16;
9816 }
9817 if (n == 32) {
9818 ppc_maybe_bswap_register(env, mem_buf, 4);
9819 env->vscr = ldl_p(mem_buf);
9820 return 4;
9821 }
9822 if (n == 33) {
9823 ppc_maybe_bswap_register(env, mem_buf, 4);
9824 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9825 return 4;
9826 }
9827 return 0;
9828 }
9829
9830 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9831 {
9832 if (n < 32) {
9833 #if defined(TARGET_PPC64)
9834 stl_p(mem_buf, env->gpr[n] >> 32);
9835 ppc_maybe_bswap_register(env, mem_buf, 4);
9836 #else
9837 stl_p(mem_buf, env->gprh[n]);
9838 #endif
9839 return 4;
9840 }
9841 if (n == 32) {
9842 stq_p(mem_buf, env->spe_acc);
9843 ppc_maybe_bswap_register(env, mem_buf, 8);
9844 return 8;
9845 }
9846 if (n == 33) {
9847 stl_p(mem_buf, env->spe_fscr);
9848 ppc_maybe_bswap_register(env, mem_buf, 4);
9849 return 4;
9850 }
9851 return 0;
9852 }
9853
9854 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9855 {
9856 if (n < 32) {
9857 #if defined(TARGET_PPC64)
9858 target_ulong lo = (uint32_t)env->gpr[n];
9859 target_ulong hi;
9860
9861 ppc_maybe_bswap_register(env, mem_buf, 4);
9862
9863 hi = (target_ulong)ldl_p(mem_buf) << 32;
9864 env->gpr[n] = lo | hi;
9865 #else
9866 env->gprh[n] = ldl_p(mem_buf);
9867 #endif
9868 return 4;
9869 }
9870 if (n == 32) {
9871 ppc_maybe_bswap_register(env, mem_buf, 8);
9872 env->spe_acc = ldq_p(mem_buf);
9873 return 8;
9874 }
9875 if (n == 33) {
9876 ppc_maybe_bswap_register(env, mem_buf, 4);
9877 env->spe_fscr = ldl_p(mem_buf);
9878 return 4;
9879 }
9880 return 0;
9881 }
9882
9883 static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9884 {
9885 if (n < 32) {
9886 stq_p(mem_buf, env->vsr[n]);
9887 ppc_maybe_bswap_register(env, mem_buf, 8);
9888 return 8;
9889 }
9890 return 0;
9891 }
9892
9893 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9894 {
9895 if (n < 32) {
9896 ppc_maybe_bswap_register(env, mem_buf, 8);
9897 env->vsr[n] = ldq_p(mem_buf);
9898 return 8;
9899 }
9900 return 0;
9901 }
9902
9903 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9904 {
9905 CPUPPCState *env = &cpu->env;
9906
9907 /* TCG doesn't (yet) emulate some groups of instructions that
9908 * are implemented on some otherwise supported CPUs (e.g. VSX
9909 * and decimal floating point instructions on POWER7). We
9910 * remove unsupported instruction groups from the cpu state's
9911 * instruction masks and hope the guest can cope. For at
9912 * least the pseries machine, the unavailability of these
9913 * instructions can be advertised to the guest via the device
9914 * tree. */
9915 if ((env->insns_flags & ~PPC_TCG_INSNS)
9916 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9917 warn_report("Disabling some instructions which are not "
9918 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
9919 env->insns_flags & ~PPC_TCG_INSNS,
9920 env->insns_flags2 & ~PPC_TCG_INSNS2);
9921 }
9922 env->insns_flags &= PPC_TCG_INSNS;
9923 env->insns_flags2 &= PPC_TCG_INSNS2;
9924 return 0;
9925 }
9926
9927 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
9928 {
9929 #ifdef TARGET_PPCEMB
9930 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
9931 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
9932 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
9933 #else
9934 return true;
9935 #endif
9936 }
9937
9938 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
9939 {
9940 CPUState *cs = CPU(dev);
9941 PowerPCCPU *cpu = POWERPC_CPU(dev);
9942 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9943 Error *local_err = NULL;
9944
9945 cpu_exec_realizefn(cs, &local_err);
9946 if (local_err != NULL) {
9947 error_propagate(errp, local_err);
9948 return;
9949 }
9950 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
9951 cpu->vcpu_id = cs->cpu_index;
9952 }
9953
9954 if (tcg_enabled()) {
9955 if (ppc_fixup_cpu(cpu) != 0) {
9956 error_setg(errp, "Unable to emulate selected CPU with TCG");
9957 goto unrealize;
9958 }
9959 }
9960
9961 #if defined(TARGET_PPCEMB)
9962 if (!ppc_cpu_is_valid(pcc)) {
9963 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
9964 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
9965 "or choose another CPU model.");
9966 goto unrealize;
9967 }
9968 #endif
9969
9970 create_ppc_opcodes(cpu, &local_err);
9971 if (local_err != NULL) {
9972 error_propagate(errp, local_err);
9973 goto unrealize;
9974 }
9975 init_ppc_proc(cpu);
9976
9977 if (pcc->insns_flags & PPC_FLOAT) {
9978 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9979 33, "power-fpu.xml", 0);
9980 }
9981 if (pcc->insns_flags & PPC_ALTIVEC) {
9982 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9983 34, "power-altivec.xml", 0);
9984 }
9985 if (pcc->insns_flags & PPC_SPE) {
9986 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9987 34, "power-spe.xml", 0);
9988 }
9989 if (pcc->insns_flags2 & PPC2_VSX) {
9990 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9991 32, "power-vsx.xml", 0);
9992 }
9993
9994 qemu_init_vcpu(cs);
9995
9996 pcc->parent_realize(dev, errp);
9997
9998 #if defined(PPC_DUMP_CPU)
9999 {
10000 CPUPPCState *env = &cpu->env;
10001 const char *mmu_model, *excp_model, *bus_model;
10002 switch (env->mmu_model) {
10003 case POWERPC_MMU_32B:
10004 mmu_model = "PowerPC 32";
10005 break;
10006 case POWERPC_MMU_SOFT_6xx:
10007 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
10008 break;
10009 case POWERPC_MMU_SOFT_74xx:
10010 mmu_model = "PowerPC 74xx with software driven TLBs";
10011 break;
10012 case POWERPC_MMU_SOFT_4xx:
10013 mmu_model = "PowerPC 4xx with software driven TLBs";
10014 break;
10015 case POWERPC_MMU_SOFT_4xx_Z:
10016 mmu_model = "PowerPC 4xx with software driven TLBs "
10017 "and zones protections";
10018 break;
10019 case POWERPC_MMU_REAL:
10020 mmu_model = "PowerPC real mode only";
10021 break;
10022 case POWERPC_MMU_MPC8xx:
10023 mmu_model = "PowerPC MPC8xx";
10024 break;
10025 case POWERPC_MMU_BOOKE:
10026 mmu_model = "PowerPC BookE";
10027 break;
10028 case POWERPC_MMU_BOOKE206:
10029 mmu_model = "PowerPC BookE 2.06";
10030 break;
10031 case POWERPC_MMU_601:
10032 mmu_model = "PowerPC 601";
10033 break;
10034 #if defined(TARGET_PPC64)
10035 case POWERPC_MMU_64B:
10036 mmu_model = "PowerPC 64";
10037 break;
10038 #endif
10039 default:
10040 mmu_model = "Unknown or invalid";
10041 break;
10042 }
10043 switch (env->excp_model) {
10044 case POWERPC_EXCP_STD:
10045 excp_model = "PowerPC";
10046 break;
10047 case POWERPC_EXCP_40x:
10048 excp_model = "PowerPC 40x";
10049 break;
10050 case POWERPC_EXCP_601:
10051 excp_model = "PowerPC 601";
10052 break;
10053 case POWERPC_EXCP_602:
10054 excp_model = "PowerPC 602";
10055 break;
10056 case POWERPC_EXCP_603:
10057 excp_model = "PowerPC 603";
10058 break;
10059 case POWERPC_EXCP_603E:
10060 excp_model = "PowerPC 603e";
10061 break;
10062 case POWERPC_EXCP_604:
10063 excp_model = "PowerPC 604";
10064 break;
10065 case POWERPC_EXCP_7x0:
10066 excp_model = "PowerPC 740/750";
10067 break;
10068 case POWERPC_EXCP_7x5:
10069 excp_model = "PowerPC 745/755";
10070 break;
10071 case POWERPC_EXCP_74xx:
10072 excp_model = "PowerPC 74xx";
10073 break;
10074 case POWERPC_EXCP_BOOKE:
10075 excp_model = "PowerPC BookE";
10076 break;
10077 #if defined(TARGET_PPC64)
10078 case POWERPC_EXCP_970:
10079 excp_model = "PowerPC 970";
10080 break;
10081 #endif
10082 default:
10083 excp_model = "Unknown or invalid";
10084 break;
10085 }
10086 switch (env->bus_model) {
10087 case PPC_FLAGS_INPUT_6xx:
10088 bus_model = "PowerPC 6xx";
10089 break;
10090 case PPC_FLAGS_INPUT_BookE:
10091 bus_model = "PowerPC BookE";
10092 break;
10093 case PPC_FLAGS_INPUT_405:
10094 bus_model = "PowerPC 405";
10095 break;
10096 case PPC_FLAGS_INPUT_401:
10097 bus_model = "PowerPC 401/403";
10098 break;
10099 case PPC_FLAGS_INPUT_RCPU:
10100 bus_model = "RCPU / MPC8xx";
10101 break;
10102 #if defined(TARGET_PPC64)
10103 case PPC_FLAGS_INPUT_970:
10104 bus_model = "PowerPC 970";
10105 break;
10106 #endif
10107 default:
10108 bus_model = "Unknown or invalid";
10109 break;
10110 }
10111 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10112 " MMU model : %s\n",
10113 object_class_get_name(OBJECT_CLASS(pcc)),
10114 pcc->pvr, pcc->msr_mask, mmu_model);
10115 #if !defined(CONFIG_USER_ONLY)
10116 if (env->tlb.tlb6) {
10117 printf(" %d %s TLB in %d ways\n",
10118 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10119 env->nb_ways);
10120 }
10121 #endif
10122 printf(" Exceptions model : %s\n"
10123 " Bus model : %s\n",
10124 excp_model, bus_model);
10125 printf(" MSR features :\n");
10126 if (env->flags & POWERPC_FLAG_SPE)
10127 printf(" signal processing engine enable"
10128 "\n");
10129 else if (env->flags & POWERPC_FLAG_VRE)
10130 printf(" vector processor enable\n");
10131 if (env->flags & POWERPC_FLAG_TGPR)
10132 printf(" temporary GPRs\n");
10133 else if (env->flags & POWERPC_FLAG_CE)
10134 printf(" critical input enable\n");
10135 if (env->flags & POWERPC_FLAG_SE)
10136 printf(" single-step trace mode\n");
10137 else if (env->flags & POWERPC_FLAG_DWE)
10138 printf(" debug wait enable\n");
10139 else if (env->flags & POWERPC_FLAG_UBLE)
10140 printf(" user BTB lock enable\n");
10141 if (env->flags & POWERPC_FLAG_BE)
10142 printf(" branch-step trace mode\n");
10143 else if (env->flags & POWERPC_FLAG_DE)
10144 printf(" debug interrupt enable\n");
10145 if (env->flags & POWERPC_FLAG_PX)
10146 printf(" inclusive protection\n");
10147 else if (env->flags & POWERPC_FLAG_PMM)
10148 printf(" performance monitor mark\n");
10149 if (env->flags == POWERPC_FLAG_NONE)
10150 printf(" none\n");
10151 printf(" Time-base/decrementer clock source: %s\n",
10152 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10153 dump_ppc_insns(env);
10154 dump_ppc_sprs(env);
10155 fflush(stdout);
10156 }
10157 #endif
10158 return;
10159
10160 unrealize:
10161 cpu_exec_unrealizefn(cs);
10162 }
10163
10164 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
10165 {
10166 PowerPCCPU *cpu = POWERPC_CPU(dev);
10167 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10168 CPUPPCState *env = &cpu->env;
10169 Error *local_err = NULL;
10170 opc_handler_t **table, **table_2;
10171 int i, j, k;
10172
10173 pcc->parent_unrealize(dev, &local_err);
10174 if (local_err != NULL) {
10175 error_propagate(errp, local_err);
10176 return;
10177 }
10178
10179 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
10180 if (env->opcodes[i] == &invalid_handler) {
10181 continue;
10182 }
10183 if (is_indirect_opcode(env->opcodes[i])) {
10184 table = ind_table(env->opcodes[i]);
10185 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
10186 if (table[j] == &invalid_handler) {
10187 continue;
10188 }
10189 if (is_indirect_opcode(table[j])) {
10190 table_2 = ind_table(table[j]);
10191 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
10192 if (table_2[k] != &invalid_handler &&
10193 is_indirect_opcode(table_2[k])) {
10194 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
10195 ~PPC_INDIRECT));
10196 }
10197 }
10198 g_free((opc_handler_t *)((uintptr_t)table[j] &
10199 ~PPC_INDIRECT));
10200 }
10201 }
10202 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
10203 ~PPC_INDIRECT));
10204 }
10205 }
10206 }
10207
10208 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
10209 {
10210 ObjectClass *oc = (ObjectClass *)a;
10211 uint32_t pvr = *(uint32_t *)b;
10212 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10213
10214 /* -cpu host does a PVR lookup during construction */
10215 if (unlikely(strcmp(object_class_get_name(oc),
10216 TYPE_HOST_POWERPC_CPU) == 0)) {
10217 return -1;
10218 }
10219
10220 if (!ppc_cpu_is_valid(pcc)) {
10221 return -1;
10222 }
10223
10224 return pcc->pvr == pvr ? 0 : -1;
10225 }
10226
10227 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
10228 {
10229 GSList *list, *item;
10230 PowerPCCPUClass *pcc = NULL;
10231
10232 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10233 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10234 if (item != NULL) {
10235 pcc = POWERPC_CPU_CLASS(item->data);
10236 }
10237 g_slist_free(list);
10238
10239 return pcc;
10240 }
10241
10242 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
10243 {
10244 ObjectClass *oc = (ObjectClass *)a;
10245 uint32_t pvr = *(uint32_t *)b;
10246 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10247
10248 /* -cpu host does a PVR lookup during construction */
10249 if (unlikely(strcmp(object_class_get_name(oc),
10250 TYPE_HOST_POWERPC_CPU) == 0)) {
10251 return -1;
10252 }
10253
10254 if (!ppc_cpu_is_valid(pcc)) {
10255 return -1;
10256 }
10257
10258 if (pcc->pvr_match(pcc, pvr)) {
10259 return 0;
10260 }
10261
10262 return -1;
10263 }
10264
10265 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
10266 {
10267 GSList *list, *item;
10268 PowerPCCPUClass *pcc = NULL;
10269
10270 list = object_class_get_list(TYPE_POWERPC_CPU, true);
10271 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
10272 if (item != NULL) {
10273 pcc = POWERPC_CPU_CLASS(item->data);
10274 }
10275 g_slist_free(list);
10276
10277 return pcc;
10278 }
10279
10280 static ObjectClass *ppc_cpu_class_by_name(const char *name)
10281 {
10282 char *cpu_model, *typename;
10283 ObjectClass *oc;
10284 const char *p;
10285 unsigned long pvr;
10286
10287 /* Lookup by PVR if cpu_model is valid 8 digit hex number
10288 * (excl: 0x prefix if present)
10289 */
10290 if (!qemu_strtoul(name, &p, 16, &pvr)) {
10291 int len = p - name;
10292 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
10293 if ((len == 8) && (*p == '\0')) {
10294 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
10295 }
10296 }
10297
10298 cpu_model = g_ascii_strdown(name, -1);
10299 p = ppc_cpu_lookup_alias(cpu_model);
10300 if (p) {
10301 g_free(cpu_model);
10302 cpu_model = g_strdup(p);
10303 }
10304
10305 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
10306 oc = object_class_by_name(typename);
10307 g_free(typename);
10308 g_free(cpu_model);
10309
10310 if (oc && ppc_cpu_is_valid(POWERPC_CPU_CLASS(oc))) {
10311 return oc;
10312 }
10313
10314 return NULL;
10315 }
10316
10317 const char *ppc_cpu_lookup_alias(const char *alias)
10318 {
10319 int ai;
10320
10321 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
10322 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
10323 return ppc_cpu_aliases[ai].model;
10324 }
10325 }
10326
10327 return NULL;
10328 }
10329
10330 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
10331 {
10332 ObjectClass *oc = OBJECT_CLASS(pcc);
10333
10334 while (oc && !object_class_is_abstract(oc)) {
10335 oc = object_class_get_parent(oc);
10336 }
10337 assert(oc);
10338
10339 return POWERPC_CPU_CLASS(oc);
10340 }
10341
10342 /* Sort by PVR, ordering special case "host" last. */
10343 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10344 {
10345 ObjectClass *oc_a = (ObjectClass *)a;
10346 ObjectClass *oc_b = (ObjectClass *)b;
10347 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10348 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10349 const char *name_a = object_class_get_name(oc_a);
10350 const char *name_b = object_class_get_name(oc_b);
10351
10352 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10353 return 1;
10354 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10355 return -1;
10356 } else {
10357 /* Avoid an integer overflow during subtraction */
10358 if (pcc_a->pvr < pcc_b->pvr) {
10359 return -1;
10360 } else if (pcc_a->pvr > pcc_b->pvr) {
10361 return 1;
10362 } else {
10363 return 0;
10364 }
10365 }
10366 }
10367
10368 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10369 {
10370 ObjectClass *oc = data;
10371 CPUListState *s = user_data;
10372 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10373 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
10374 const char *typename = object_class_get_name(oc);
10375 char *name;
10376 int i;
10377
10378 if (!ppc_cpu_is_valid(pcc)) {
10379 return;
10380 }
10381 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
10382 return;
10383 }
10384
10385 name = g_strndup(typename,
10386 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10387 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
10388 name, pcc->pvr);
10389 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10390 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10391 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
10392
10393 if (alias_oc != oc) {
10394 continue;
10395 }
10396 /*
10397 * If running with KVM, we might update the family alias later, so
10398 * avoid printing the wrong alias here and use "preferred" instead
10399 */
10400 if (strcmp(alias->alias, family->desc) == 0) {
10401 (*s->cpu_fprintf)(s->file,
10402 "PowerPC %-16s (alias for preferred %s CPU)\n",
10403 alias->alias, family->desc);
10404 } else {
10405 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
10406 alias->alias, name);
10407 }
10408 }
10409 g_free(name);
10410 }
10411
10412 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10413 {
10414 CPUListState s = {
10415 .file = f,
10416 .cpu_fprintf = cpu_fprintf,
10417 };
10418 GSList *list;
10419
10420 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10421 list = g_slist_sort(list, ppc_cpu_list_compare);
10422 g_slist_foreach(list, ppc_cpu_list_entry, &s);
10423 g_slist_free(list);
10424
10425 #ifdef CONFIG_KVM
10426 cpu_fprintf(f, "\n");
10427 cpu_fprintf(f, "PowerPC %-16s\n", "host");
10428 #endif
10429 }
10430
10431 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10432 {
10433 ObjectClass *oc = data;
10434 CpuDefinitionInfoList **first = user_data;
10435 const char *typename;
10436 CpuDefinitionInfoList *entry;
10437 CpuDefinitionInfo *info;
10438 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10439
10440 if (!ppc_cpu_is_valid(pcc)) {
10441 return;
10442 }
10443
10444 typename = object_class_get_name(oc);
10445 info = g_malloc0(sizeof(*info));
10446 info->name = g_strndup(typename,
10447 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
10448
10449 entry = g_malloc0(sizeof(*entry));
10450 entry->value = info;
10451 entry->next = *first;
10452 *first = entry;
10453 }
10454
10455 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
10456 {
10457 CpuDefinitionInfoList *cpu_list = NULL;
10458 GSList *list;
10459 int i;
10460
10461 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10462 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10463 g_slist_free(list);
10464
10465 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10466 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10467 ObjectClass *oc;
10468 CpuDefinitionInfoList *entry;
10469 CpuDefinitionInfo *info;
10470
10471 oc = ppc_cpu_class_by_name(alias->model);
10472 if (oc == NULL) {
10473 continue;
10474 }
10475
10476 info = g_malloc0(sizeof(*info));
10477 info->name = g_strdup(alias->alias);
10478 info->q_typename = g_strdup(object_class_get_name(oc));
10479
10480 entry = g_malloc0(sizeof(*entry));
10481 entry->value = info;
10482 entry->next = cpu_list;
10483 cpu_list = entry;
10484 }
10485
10486 return cpu_list;
10487 }
10488
10489 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
10490 {
10491 PowerPCCPU *cpu = POWERPC_CPU(cs);
10492
10493 cpu->env.nip = value;
10494 }
10495
10496 static bool ppc_cpu_has_work(CPUState *cs)
10497 {
10498 PowerPCCPU *cpu = POWERPC_CPU(cs);
10499 CPUPPCState *env = &cpu->env;
10500
10501 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
10502 }
10503
10504 /* CPUClass::reset() */
10505 static void ppc_cpu_reset(CPUState *s)
10506 {
10507 PowerPCCPU *cpu = POWERPC_CPU(s);
10508 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10509 CPUPPCState *env = &cpu->env;
10510 target_ulong msr;
10511 int i;
10512
10513 pcc->parent_reset(s);
10514
10515 msr = (target_ulong)0;
10516 msr |= (target_ulong)MSR_HVB;
10517 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10518 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10519 msr |= (target_ulong)1 << MSR_EP;
10520 #if defined(DO_SINGLE_STEP) && 0
10521 /* Single step trace mode */
10522 msr |= (target_ulong)1 << MSR_SE;
10523 msr |= (target_ulong)1 << MSR_BE;
10524 #endif
10525 #if defined(CONFIG_USER_ONLY)
10526 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10527 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10528 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
10529 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10530 msr |= (target_ulong)1 << MSR_PR;
10531 #if defined(TARGET_PPC64)
10532 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
10533 #endif
10534 #if !defined(TARGET_WORDS_BIGENDIAN)
10535 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
10536 if (!((env->msr_mask >> MSR_LE) & 1)) {
10537 fprintf(stderr, "Selected CPU does not support little-endian.\n");
10538 exit(1);
10539 }
10540 #endif
10541 #endif
10542
10543 #if defined(TARGET_PPC64)
10544 if (env->mmu_model & POWERPC_MMU_64) {
10545 msr |= (1ULL << MSR_SF);
10546 }
10547 #endif
10548
10549 hreg_store_msr(env, msr, 1);
10550
10551 #if !defined(CONFIG_USER_ONLY)
10552 env->nip = env->hreset_vector | env->excp_prefix;
10553 if (env->mmu_model != POWERPC_MMU_REAL) {
10554 ppc_tlb_invalidate_all(env);
10555 }
10556 #endif
10557
10558 hreg_compute_hflags(env);
10559 env->reserve_addr = (target_ulong)-1ULL;
10560 /* Be sure no exception or interrupt is pending */
10561 env->pending_interrupts = 0;
10562 s->exception_index = POWERPC_EXCP_NONE;
10563 env->error_code = 0;
10564
10565 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
10566 env->vpa_addr = 0;
10567 env->slb_shadow_addr = 0;
10568 env->slb_shadow_size = 0;
10569 env->dtl_addr = 0;
10570 env->dtl_size = 0;
10571 #endif /* TARGET_PPC64 */
10572
10573 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
10574 ppc_spr_t *spr = &env->spr_cb[i];
10575
10576 if (!spr->name) {
10577 continue;
10578 }
10579 env->spr[i] = spr->default_value;
10580 }
10581 }
10582
10583 #ifndef CONFIG_USER_ONLY
10584 static bool ppc_cpu_is_big_endian(CPUState *cs)
10585 {
10586 PowerPCCPU *cpu = POWERPC_CPU(cs);
10587 CPUPPCState *env = &cpu->env;
10588
10589 cpu_synchronize_state(cs);
10590
10591 return !msr_le;
10592 }
10593 #endif
10594
10595 static void ppc_cpu_initfn(Object *obj)
10596 {
10597 CPUState *cs = CPU(obj);
10598 PowerPCCPU *cpu = POWERPC_CPU(obj);
10599 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10600 CPUPPCState *env = &cpu->env;
10601
10602 cs->env_ptr = env;
10603 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
10604
10605 env->msr_mask = pcc->msr_mask;
10606 env->mmu_model = pcc->mmu_model;
10607 env->excp_model = pcc->excp_model;
10608 env->bus_model = pcc->bus_model;
10609 env->insns_flags = pcc->insns_flags;
10610 env->insns_flags2 = pcc->insns_flags2;
10611 env->flags = pcc->flags;
10612 env->bfd_mach = pcc->bfd_mach;
10613 env->check_pow = pcc->check_pow;
10614
10615 /* Mark HV mode as supported if the CPU has an MSR_HV bit
10616 * in the msr_mask. The mask can later be cleared by PAPR
10617 * mode but the hv mode support will remain, thus enforcing
10618 * that we cannot use priv. instructions in guest in PAPR
10619 * mode. For 970 we currently simply don't set HV in msr_mask
10620 * thus simulating an "Apple mode" 970. If we ever want to
10621 * support 970 HV mode, we'll have to add a processor attribute
10622 * of some sort.
10623 */
10624 #if !defined(CONFIG_USER_ONLY)
10625 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10626 #endif
10627
10628 #if defined(TARGET_PPC64)
10629 if (pcc->sps) {
10630 env->sps = *pcc->sps;
10631 } else if (env->mmu_model & POWERPC_MMU_64) {
10632 /* Use default sets of page sizes. We don't support MPSS */
10633 static const struct ppc_segment_page_sizes defsps_4k = {
10634 .sps = {
10635 { .page_shift = 12, /* 4K */
10636 .slb_enc = 0,
10637 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10638 },
10639 { .page_shift = 24, /* 16M */
10640 .slb_enc = 0x100,
10641 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10642 },
10643 },
10644 };
10645 static const struct ppc_segment_page_sizes defsps_64k = {
10646 .sps = {
10647 { .page_shift = 12, /* 4K */
10648 .slb_enc = 0,
10649 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10650 },
10651 { .page_shift = 16, /* 64K */
10652 .slb_enc = 0x110,
10653 .enc = { { .page_shift = 16, .pte_enc = 1 } }
10654 },
10655 { .page_shift = 24, /* 16M */
10656 .slb_enc = 0x100,
10657 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10658 },
10659 },
10660 };
10661 env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
10662 }
10663 #endif /* defined(TARGET_PPC64) */
10664
10665 if (tcg_enabled()) {
10666 ppc_translate_init();
10667 }
10668 }
10669
10670 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10671 {
10672 return pcc->pvr == pvr;
10673 }
10674
10675 static gchar *ppc_gdb_arch_name(CPUState *cs)
10676 {
10677 #if defined(TARGET_PPC64)
10678 return g_strdup("powerpc:common64");
10679 #else
10680 return g_strdup("powerpc:common");
10681 #endif
10682 }
10683
10684 static Property ppc_cpu_properties[] = {
10685 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
10686 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
10687 false),
10688 DEFINE_PROP_END_OF_LIST(),
10689 };
10690
10691 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10692 {
10693 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10694 CPUClass *cc = CPU_CLASS(oc);
10695 DeviceClass *dc = DEVICE_CLASS(oc);
10696
10697 pcc->parent_realize = dc->realize;
10698 pcc->parent_unrealize = dc->unrealize;
10699 pcc->pvr_match = ppc_pvr_match_default;
10700 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10701 dc->realize = ppc_cpu_realizefn;
10702 dc->unrealize = ppc_cpu_unrealizefn;
10703 dc->props = ppc_cpu_properties;
10704
10705 pcc->parent_reset = cc->reset;
10706 cc->reset = ppc_cpu_reset;
10707
10708 cc->class_by_name = ppc_cpu_class_by_name;
10709 cc->has_work = ppc_cpu_has_work;
10710 cc->do_interrupt = ppc_cpu_do_interrupt;
10711 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10712 cc->dump_state = ppc_cpu_dump_state;
10713 cc->dump_statistics = ppc_cpu_dump_statistics;
10714 cc->set_pc = ppc_cpu_set_pc;
10715 cc->gdb_read_register = ppc_cpu_gdb_read_register;
10716 cc->gdb_write_register = ppc_cpu_gdb_write_register;
10717 #ifdef CONFIG_USER_ONLY
10718 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
10719 #else
10720 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10721 cc->vmsd = &vmstate_ppc_cpu;
10722 #endif
10723 #if defined(CONFIG_SOFTMMU)
10724 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10725 cc->write_elf32_note = ppc32_cpu_write_elf32_note;
10726 #endif
10727
10728 cc->gdb_num_core_regs = 71;
10729
10730 #ifdef USE_APPLE_GDB
10731 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10732 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10733 cc->gdb_num_core_regs = 71 + 32;
10734 #endif
10735
10736 cc->gdb_arch_name = ppc_gdb_arch_name;
10737 #if defined(TARGET_PPC64)
10738 cc->gdb_core_xml_file = "power64-core.xml";
10739 #else
10740 cc->gdb_core_xml_file = "power-core.xml";
10741 #endif
10742 #ifndef CONFIG_USER_ONLY
10743 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10744 #endif
10745
10746 dc->fw_name = "PowerPC,UNKNOWN";
10747 }
10748
10749 static const TypeInfo ppc_cpu_type_info = {
10750 .name = TYPE_POWERPC_CPU,
10751 .parent = TYPE_CPU,
10752 .instance_size = sizeof(PowerPCCPU),
10753 .instance_init = ppc_cpu_initfn,
10754 .abstract = true,
10755 .class_size = sizeof(PowerPCCPUClass),
10756 .class_init = ppc_cpu_class_init,
10757 };
10758
10759 static const TypeInfo ppc_vhyp_type_info = {
10760 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
10761 .parent = TYPE_INTERFACE,
10762 .class_size = sizeof(PPCVirtualHypervisorClass),
10763 };
10764
10765 static void ppc_cpu_register_types(void)
10766 {
10767 type_register_static(&ppc_cpu_type_info);
10768 type_register_static(&ppc_vhyp_type_info);
10769 }
10770
10771 type_init(ppc_cpu_register_types)
AR7 emulation for QEMU