2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
4 * Copyright (c) 2014 Imagination Technologies
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
26 /* Data format min and max values */
27 #define DF_BITS(df) (1 << ((df) + 3))
29 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
30 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
32 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
33 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
35 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
36 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
38 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
39 #define SIGNED(x, df) \
40 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
42 /* Element-by-element access macros */
43 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
45 static inline void msa_move_v(wr_t
*pwd
, wr_t
*pws
)
49 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
50 pwd
->d
[i
] = pws
->d
[i
];
54 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
55 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
58 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
59 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
61 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
66 MSA_FN_IMM8(andi_b
, pwd
->b
[i
], pws
->b
[i
] & i8
)
67 MSA_FN_IMM8(ori_b
, pwd
->b
[i
], pws
->b
[i
] | i8
)
68 MSA_FN_IMM8(nori_b
, pwd
->b
[i
], ~(pws
->b
[i
] | i8
))
69 MSA_FN_IMM8(xori_b
, pwd
->b
[i
], pws
->b
[i
] ^ i8
)
71 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
72 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
73 MSA_FN_IMM8(bmnzi_b
, pwd
->b
[i
],
74 BIT_MOVE_IF_NOT_ZERO(pwd
->b
[i
], pws
->b
[i
], i8
, DF_BYTE
))
76 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
77 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
78 MSA_FN_IMM8(bmzi_b
, pwd
->b
[i
],
79 BIT_MOVE_IF_ZERO(pwd
->b
[i
], pws
->b
[i
], i8
, DF_BYTE
))
81 #define BIT_SELECT(dest, arg1, arg2, df) \
82 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
83 MSA_FN_IMM8(bseli_b
, pwd
->b
[i
],
84 BIT_SELECT(pwd
->b
[i
], pws
->b
[i
], i8
, DF_BYTE
))
88 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
90 void helper_msa_shf_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
91 uint32_t ws
, uint32_t imm
)
93 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
94 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
100 for (i
= 0; i
< DF_ELEMENTS(DF_BYTE
); i
++) {
101 pwx
->b
[i
] = pws
->b
[SHF_POS(i
, imm
)];
105 for (i
= 0; i
< DF_ELEMENTS(DF_HALF
); i
++) {
106 pwx
->h
[i
] = pws
->h
[SHF_POS(i
, imm
)];
110 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
111 pwx
->w
[i
] = pws
->w
[SHF_POS(i
, imm
)];
117 msa_move_v(pwd
, pwx
);
120 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
121 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
124 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
125 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
126 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
128 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
133 MSA_FN_VECTOR(and_v
, pwd
->d
[i
], pws
->d
[i
] & pwt
->d
[i
])
134 MSA_FN_VECTOR(or_v
, pwd
->d
[i
], pws
->d
[i
] | pwt
->d
[i
])
135 MSA_FN_VECTOR(nor_v
, pwd
->d
[i
], ~(pws
->d
[i
] | pwt
->d
[i
]))
136 MSA_FN_VECTOR(xor_v
, pwd
->d
[i
], pws
->d
[i
] ^ pwt
->d
[i
])
137 MSA_FN_VECTOR(bmnz_v
, pwd
->d
[i
],
138 BIT_MOVE_IF_NOT_ZERO(pwd
->d
[i
], pws
->d
[i
], pwt
->d
[i
], DF_DOUBLE
))
139 MSA_FN_VECTOR(bmz_v
, pwd
->d
[i
],
140 BIT_MOVE_IF_ZERO(pwd
->d
[i
], pws
->d
[i
], pwt
->d
[i
], DF_DOUBLE
))
141 MSA_FN_VECTOR(bsel_v
, pwd
->d
[i
],
142 BIT_SELECT(pwd
->d
[i
], pws
->d
[i
], pwt
->d
[i
], DF_DOUBLE
))
143 #undef BIT_MOVE_IF_NOT_ZERO
144 #undef BIT_MOVE_IF_ZERO
148 static inline int64_t msa_addv_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
153 static inline int64_t msa_subv_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
158 static inline int64_t msa_ceq_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
160 return arg1
== arg2
? -1 : 0;
163 static inline int64_t msa_cle_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
165 return arg1
<= arg2
? -1 : 0;
168 static inline int64_t msa_cle_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
170 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
171 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
172 return u_arg1
<= u_arg2
? -1 : 0;
175 static inline int64_t msa_clt_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
177 return arg1
< arg2
? -1 : 0;
180 static inline int64_t msa_clt_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
182 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
183 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
184 return u_arg1
< u_arg2
? -1 : 0;
187 static inline int64_t msa_max_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
189 return arg1
> arg2
? arg1
: arg2
;
192 static inline int64_t msa_max_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
194 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
195 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
196 return u_arg1
> u_arg2
? arg1
: arg2
;
199 static inline int64_t msa_min_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
201 return arg1
< arg2
? arg1
: arg2
;
204 static inline int64_t msa_min_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
206 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
207 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
208 return u_arg1
< u_arg2
? arg1
: arg2
;
211 #define MSA_BINOP_IMM_DF(helper, func) \
212 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
213 uint32_t wd, uint32_t ws, int32_t u5) \
215 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
216 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
221 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
222 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
226 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
227 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
231 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
232 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
236 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
237 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
245 MSA_BINOP_IMM_DF(addvi
, addv
)
246 MSA_BINOP_IMM_DF(subvi
, subv
)
247 MSA_BINOP_IMM_DF(ceqi
, ceq
)
248 MSA_BINOP_IMM_DF(clei_s
, cle_s
)
249 MSA_BINOP_IMM_DF(clei_u
, cle_u
)
250 MSA_BINOP_IMM_DF(clti_s
, clt_s
)
251 MSA_BINOP_IMM_DF(clti_u
, clt_u
)
252 MSA_BINOP_IMM_DF(maxi_s
, max_s
)
253 MSA_BINOP_IMM_DF(maxi_u
, max_u
)
254 MSA_BINOP_IMM_DF(mini_s
, min_s
)
255 MSA_BINOP_IMM_DF(mini_u
, min_u
)
256 #undef MSA_BINOP_IMM_DF
258 void helper_msa_ldi_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
261 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
266 for (i
= 0; i
< DF_ELEMENTS(DF_BYTE
); i
++) {
267 pwd
->b
[i
] = (int8_t)s10
;
271 for (i
= 0; i
< DF_ELEMENTS(DF_HALF
); i
++) {
272 pwd
->h
[i
] = (int16_t)s10
;
276 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
277 pwd
->w
[i
] = (int32_t)s10
;
281 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
282 pwd
->d
[i
] = (int64_t)s10
;
290 /* Data format bit position and unsigned values */
291 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
293 static inline int64_t msa_sll_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
295 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
296 return arg1
<< b_arg2
;
299 static inline int64_t msa_sra_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
301 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
302 return arg1
>> b_arg2
;
305 static inline int64_t msa_srl_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
307 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
308 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
309 return u_arg1
>> b_arg2
;
312 static inline int64_t msa_bclr_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
314 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
315 return UNSIGNED(arg1
& (~(1LL << b_arg2
)), df
);
318 static inline int64_t msa_bset_df(uint32_t df
, int64_t arg1
,
321 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
322 return UNSIGNED(arg1
| (1LL << b_arg2
), df
);
325 static inline int64_t msa_bneg_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
327 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
328 return UNSIGNED(arg1
^ (1LL << b_arg2
), df
);
331 static inline int64_t msa_binsl_df(uint32_t df
, int64_t dest
, int64_t arg1
,
334 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
335 uint64_t u_dest
= UNSIGNED(dest
, df
);
336 int32_t sh_d
= BIT_POSITION(arg2
, df
) + 1;
337 int32_t sh_a
= DF_BITS(df
) - sh_d
;
338 if (sh_d
== DF_BITS(df
)) {
341 return UNSIGNED(UNSIGNED(u_dest
<< sh_d
, df
) >> sh_d
, df
) |
342 UNSIGNED(UNSIGNED(u_arg1
>> sh_a
, df
) << sh_a
, df
);
346 static inline int64_t msa_binsr_df(uint32_t df
, int64_t dest
, int64_t arg1
,
349 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
350 uint64_t u_dest
= UNSIGNED(dest
, df
);
351 int32_t sh_d
= BIT_POSITION(arg2
, df
) + 1;
352 int32_t sh_a
= DF_BITS(df
) - sh_d
;
353 if (sh_d
== DF_BITS(df
)) {
356 return UNSIGNED(UNSIGNED(u_dest
>> sh_d
, df
) << sh_d
, df
) |
357 UNSIGNED(UNSIGNED(u_arg1
<< sh_a
, df
) >> sh_a
, df
);
361 static inline int64_t msa_sat_s_df(uint32_t df
, int64_t arg
, uint32_t m
)
363 return arg
< M_MIN_INT(m
+1) ? M_MIN_INT(m
+1) :
364 arg
> M_MAX_INT(m
+1) ? M_MAX_INT(m
+1) :
368 static inline int64_t msa_sat_u_df(uint32_t df
, int64_t arg
, uint32_t m
)
370 uint64_t u_arg
= UNSIGNED(arg
, df
);
371 return u_arg
< M_MAX_UINT(m
+1) ? u_arg
:
375 static inline int64_t msa_srar_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
377 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
381 int64_t r_bit
= (arg1
>> (b_arg2
- 1)) & 1;
382 return (arg1
>> b_arg2
) + r_bit
;
386 static inline int64_t msa_srlr_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
388 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
389 int32_t b_arg2
= BIT_POSITION(arg2
, df
);
393 uint64_t r_bit
= (u_arg1
>> (b_arg2
- 1)) & 1;
394 return (u_arg1
>> b_arg2
) + r_bit
;
398 #define MSA_BINOP_IMMU_DF(helper, func) \
399 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
400 uint32_t ws, uint32_t u5) \
402 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
403 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
408 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
409 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
413 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
414 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
418 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
419 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
423 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
424 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
432 MSA_BINOP_IMMU_DF(slli
, sll
)
433 MSA_BINOP_IMMU_DF(srai
, sra
)
434 MSA_BINOP_IMMU_DF(srli
, srl
)
435 MSA_BINOP_IMMU_DF(bclri
, bclr
)
436 MSA_BINOP_IMMU_DF(bseti
, bset
)
437 MSA_BINOP_IMMU_DF(bnegi
, bneg
)
438 MSA_BINOP_IMMU_DF(sat_s
, sat_s
)
439 MSA_BINOP_IMMU_DF(sat_u
, sat_u
)
440 MSA_BINOP_IMMU_DF(srari
, srar
)
441 MSA_BINOP_IMMU_DF(srlri
, srlr
)
442 #undef MSA_BINOP_IMMU_DF
444 #define MSA_TEROP_IMMU_DF(helper, func) \
445 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
446 uint32_t wd, uint32_t ws, uint32_t u5) \
448 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
449 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
454 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
455 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
460 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
461 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
466 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
467 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
472 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
473 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
482 MSA_TEROP_IMMU_DF(binsli
, binsl
)
483 MSA_TEROP_IMMU_DF(binsri
, binsr
)
484 #undef MSA_TEROP_IMMU_DF
486 static inline int64_t msa_max_a_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
488 uint64_t abs_arg1
= arg1
>= 0 ? arg1
: -arg1
;
489 uint64_t abs_arg2
= arg2
>= 0 ? arg2
: -arg2
;
490 return abs_arg1
> abs_arg2
? arg1
: arg2
;
493 static inline int64_t msa_min_a_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
495 uint64_t abs_arg1
= arg1
>= 0 ? arg1
: -arg1
;
496 uint64_t abs_arg2
= arg2
>= 0 ? arg2
: -arg2
;
497 return abs_arg1
< abs_arg2
? arg1
: arg2
;
500 static inline int64_t msa_add_a_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
502 uint64_t abs_arg1
= arg1
>= 0 ? arg1
: -arg1
;
503 uint64_t abs_arg2
= arg2
>= 0 ? arg2
: -arg2
;
504 return abs_arg1
+ abs_arg2
;
507 static inline int64_t msa_adds_a_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
509 uint64_t max_int
= (uint64_t)DF_MAX_INT(df
);
510 uint64_t abs_arg1
= arg1
>= 0 ? arg1
: -arg1
;
511 uint64_t abs_arg2
= arg2
>= 0 ? arg2
: -arg2
;
512 if (abs_arg1
> max_int
|| abs_arg2
> max_int
) {
513 return (int64_t)max_int
;
515 return (abs_arg1
< max_int
- abs_arg2
) ? abs_arg1
+ abs_arg2
: max_int
;
519 static inline int64_t msa_adds_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
521 int64_t max_int
= DF_MAX_INT(df
);
522 int64_t min_int
= DF_MIN_INT(df
);
524 return (min_int
- arg1
< arg2
) ? arg1
+ arg2
: min_int
;
526 return (arg2
< max_int
- arg1
) ? arg1
+ arg2
: max_int
;
530 static inline uint64_t msa_adds_u_df(uint32_t df
, uint64_t arg1
, uint64_t arg2
)
532 uint64_t max_uint
= DF_MAX_UINT(df
);
533 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
534 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
535 return (u_arg1
< max_uint
- u_arg2
) ? u_arg1
+ u_arg2
: max_uint
;
538 static inline int64_t msa_ave_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
541 return (arg1
>> 1) + (arg2
>> 1) + (arg1
& arg2
& 1);
544 static inline uint64_t msa_ave_u_df(uint32_t df
, uint64_t arg1
, uint64_t arg2
)
546 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
547 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
549 return (u_arg1
>> 1) + (u_arg2
>> 1) + (u_arg1
& u_arg2
& 1);
552 static inline int64_t msa_aver_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
555 return (arg1
>> 1) + (arg2
>> 1) + ((arg1
| arg2
) & 1);
558 static inline uint64_t msa_aver_u_df(uint32_t df
, uint64_t arg1
, uint64_t arg2
)
560 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
561 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
563 return (u_arg1
>> 1) + (u_arg2
>> 1) + ((u_arg1
| u_arg2
) & 1);
566 static inline int64_t msa_subs_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
568 int64_t max_int
= DF_MAX_INT(df
);
569 int64_t min_int
= DF_MIN_INT(df
);
571 return (min_int
+ arg2
< arg1
) ? arg1
- arg2
: min_int
;
573 return (arg1
< max_int
+ arg2
) ? arg1
- arg2
: max_int
;
577 static inline int64_t msa_subs_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
579 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
580 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
581 return (u_arg1
> u_arg2
) ? u_arg1
- u_arg2
: 0;
584 static inline int64_t msa_subsus_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
586 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
587 uint64_t max_uint
= DF_MAX_UINT(df
);
589 uint64_t u_arg2
= (uint64_t)arg2
;
590 return (u_arg1
> u_arg2
) ?
591 (int64_t)(u_arg1
- u_arg2
) :
594 uint64_t u_arg2
= (uint64_t)(-arg2
);
595 return (u_arg1
< max_uint
- u_arg2
) ?
596 (int64_t)(u_arg1
+ u_arg2
) :
601 static inline int64_t msa_subsuu_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
603 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
604 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
605 int64_t max_int
= DF_MAX_INT(df
);
606 int64_t min_int
= DF_MIN_INT(df
);
607 if (u_arg1
> u_arg2
) {
608 return u_arg1
- u_arg2
< (uint64_t)max_int
?
609 (int64_t)(u_arg1
- u_arg2
) :
612 return u_arg2
- u_arg1
< (uint64_t)(-min_int
) ?
613 (int64_t)(u_arg1
- u_arg2
) :
618 static inline int64_t msa_asub_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
621 return (arg1
< arg2
) ?
622 (uint64_t)(arg2
- arg1
) : (uint64_t)(arg1
- arg2
);
625 static inline uint64_t msa_asub_u_df(uint32_t df
, uint64_t arg1
, uint64_t arg2
)
627 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
628 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
629 /* unsigned compare */
630 return (u_arg1
< u_arg2
) ?
631 (uint64_t)(u_arg2
- u_arg1
) : (uint64_t)(u_arg1
- u_arg2
);
634 static inline int64_t msa_mulv_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
639 static inline int64_t msa_div_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
641 if (arg1
== DF_MIN_INT(df
) && arg2
== -1) {
642 return DF_MIN_INT(df
);
644 return arg2
? arg1
/ arg2
: 0;
647 static inline int64_t msa_div_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
649 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
650 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
651 return u_arg2
? u_arg1
/ u_arg2
: 0;
654 static inline int64_t msa_mod_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
656 if (arg1
== DF_MIN_INT(df
) && arg2
== -1) {
659 return arg2
? arg1
% arg2
: 0;
662 static inline int64_t msa_mod_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
664 uint64_t u_arg1
= UNSIGNED(arg1
, df
);
665 uint64_t u_arg2
= UNSIGNED(arg2
, df
);
666 return u_arg2
? u_arg1
% u_arg2
: 0;
669 #define SIGNED_EVEN(a, df) \
670 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
672 #define UNSIGNED_EVEN(a, df) \
673 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
675 #define SIGNED_ODD(a, df) \
676 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
678 #define UNSIGNED_ODD(a, df) \
679 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
681 #define SIGNED_EXTRACT(e, o, a, df) \
683 e = SIGNED_EVEN(a, df); \
684 o = SIGNED_ODD(a, df); \
687 #define UNSIGNED_EXTRACT(e, o, a, df) \
689 e = UNSIGNED_EVEN(a, df); \
690 o = UNSIGNED_ODD(a, df); \
693 static inline int64_t msa_dotp_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
699 SIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
700 SIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
701 return (even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
);
704 static inline int64_t msa_dotp_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
710 UNSIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
711 UNSIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
712 return (even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
);
715 #define CONCATENATE_AND_SLIDE(s, k) \
717 for (i = 0; i < s; i++) { \
718 v[i] = pws->b[s * k + i]; \
719 v[i + s] = pwd->b[s * k + i]; \
721 for (i = 0; i < s; i++) { \
722 pwd->b[s * k + i] = v[i + n]; \
726 static inline void msa_sld_df(uint32_t df
, wr_t
*pwd
,
727 wr_t
*pws
, target_ulong rt
)
729 uint32_t n
= rt
% DF_ELEMENTS(df
);
735 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE
), 0);
738 for (k
= 0; k
< 2; k
++) {
739 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF
), k
);
743 for (k
= 0; k
< 4; k
++) {
744 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD
), k
);
748 for (k
= 0; k
< 8; k
++) {
749 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE
), k
);
757 static inline int64_t msa_hadd_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
759 return SIGNED_ODD(arg1
, df
) + SIGNED_EVEN(arg2
, df
);
762 static inline int64_t msa_hadd_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
764 return UNSIGNED_ODD(arg1
, df
) + UNSIGNED_EVEN(arg2
, df
);
767 static inline int64_t msa_hsub_s_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
769 return SIGNED_ODD(arg1
, df
) - SIGNED_EVEN(arg2
, df
);
772 static inline int64_t msa_hsub_u_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
774 return UNSIGNED_ODD(arg1
, df
) - UNSIGNED_EVEN(arg2
, df
);
777 static inline int64_t msa_mul_q_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
779 int64_t q_min
= DF_MIN_INT(df
);
780 int64_t q_max
= DF_MAX_INT(df
);
782 if (arg1
== q_min
&& arg2
== q_min
) {
785 return (arg1
* arg2
) >> (DF_BITS(df
) - 1);
788 static inline int64_t msa_mulr_q_df(uint32_t df
, int64_t arg1
, int64_t arg2
)
790 int64_t q_min
= DF_MIN_INT(df
);
791 int64_t q_max
= DF_MAX_INT(df
);
792 int64_t r_bit
= 1 << (DF_BITS(df
) - 2);
794 if (arg1
== q_min
&& arg2
== q_min
) {
797 return (arg1
* arg2
+ r_bit
) >> (DF_BITS(df
) - 1);
800 #define MSA_BINOP_DF(func) \
801 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
802 uint32_t wd, uint32_t ws, uint32_t wt) \
804 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
805 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
806 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
811 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
812 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
816 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
817 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
821 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
822 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
826 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
827 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
864 MSA_BINOP_DF(subsus_u
)
865 MSA_BINOP_DF(subsuu_s
)
886 void helper_msa_sld_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
887 uint32_t ws
, uint32_t rt
)
889 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
890 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
892 msa_sld_df(df
, pwd
, pws
, env
->active_tc
.gpr
[rt
]);
895 static inline int64_t msa_maddv_df(uint32_t df
, int64_t dest
, int64_t arg1
,
898 return dest
+ arg1
* arg2
;
901 static inline int64_t msa_msubv_df(uint32_t df
, int64_t dest
, int64_t arg1
,
904 return dest
- arg1
* arg2
;
907 static inline int64_t msa_dpadd_s_df(uint32_t df
, int64_t dest
, int64_t arg1
,
914 SIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
915 SIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
916 return dest
+ (even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
);
919 static inline int64_t msa_dpadd_u_df(uint32_t df
, int64_t dest
, int64_t arg1
,
926 UNSIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
927 UNSIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
928 return dest
+ (even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
);
931 static inline int64_t msa_dpsub_s_df(uint32_t df
, int64_t dest
, int64_t arg1
,
938 SIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
939 SIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
940 return dest
- ((even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
));
943 static inline int64_t msa_dpsub_u_df(uint32_t df
, int64_t dest
, int64_t arg1
,
950 UNSIGNED_EXTRACT(even_arg1
, odd_arg1
, arg1
, df
);
951 UNSIGNED_EXTRACT(even_arg2
, odd_arg2
, arg2
, df
);
952 return dest
- ((even_arg1
* even_arg2
) + (odd_arg1
* odd_arg2
));
955 static inline int64_t msa_madd_q_df(uint32_t df
, int64_t dest
, int64_t arg1
,
958 int64_t q_prod
, q_ret
;
960 int64_t q_max
= DF_MAX_INT(df
);
961 int64_t q_min
= DF_MIN_INT(df
);
963 q_prod
= arg1
* arg2
;
964 q_ret
= ((dest
<< (DF_BITS(df
) - 1)) + q_prod
) >> (DF_BITS(df
) - 1);
966 return (q_ret
< q_min
) ? q_min
: (q_max
< q_ret
) ? q_max
: q_ret
;
969 static inline int64_t msa_msub_q_df(uint32_t df
, int64_t dest
, int64_t arg1
,
972 int64_t q_prod
, q_ret
;
974 int64_t q_max
= DF_MAX_INT(df
);
975 int64_t q_min
= DF_MIN_INT(df
);
977 q_prod
= arg1
* arg2
;
978 q_ret
= ((dest
<< (DF_BITS(df
) - 1)) - q_prod
) >> (DF_BITS(df
) - 1);
980 return (q_ret
< q_min
) ? q_min
: (q_max
< q_ret
) ? q_max
: q_ret
;
983 static inline int64_t msa_maddr_q_df(uint32_t df
, int64_t dest
, int64_t arg1
,
986 int64_t q_prod
, q_ret
;
988 int64_t q_max
= DF_MAX_INT(df
);
989 int64_t q_min
= DF_MIN_INT(df
);
990 int64_t r_bit
= 1 << (DF_BITS(df
) - 2);
992 q_prod
= arg1
* arg2
;
993 q_ret
= ((dest
<< (DF_BITS(df
) - 1)) + q_prod
+ r_bit
) >> (DF_BITS(df
) - 1);
995 return (q_ret
< q_min
) ? q_min
: (q_max
< q_ret
) ? q_max
: q_ret
;
998 static inline int64_t msa_msubr_q_df(uint32_t df
, int64_t dest
, int64_t arg1
,
1001 int64_t q_prod
, q_ret
;
1003 int64_t q_max
= DF_MAX_INT(df
);
1004 int64_t q_min
= DF_MIN_INT(df
);
1005 int64_t r_bit
= 1 << (DF_BITS(df
) - 2);
1007 q_prod
= arg1
* arg2
;
1008 q_ret
= ((dest
<< (DF_BITS(df
) - 1)) - q_prod
+ r_bit
) >> (DF_BITS(df
) - 1);
1010 return (q_ret
< q_min
) ? q_min
: (q_max
< q_ret
) ? q_max
: q_ret
;
1013 #define MSA_TEROP_DF(func) \
1014 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1015 uint32_t ws, uint32_t wt) \
1017 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1018 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1019 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1024 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1025 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1030 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1031 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1036 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1037 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1042 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1043 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1054 MSA_TEROP_DF(dpadd_s
)
1055 MSA_TEROP_DF(dpadd_u
)
1056 MSA_TEROP_DF(dpsub_s
)
1057 MSA_TEROP_DF(dpsub_u
)
1060 MSA_TEROP_DF(madd_q
)
1061 MSA_TEROP_DF(msub_q
)
1062 MSA_TEROP_DF(maddr_q
)
1063 MSA_TEROP_DF(msubr_q
)
1066 static inline void msa_splat_df(uint32_t df
, wr_t
*pwd
,
1067 wr_t
*pws
, target_ulong rt
)
1069 uint32_t n
= rt
% DF_ELEMENTS(df
);
1074 for (i
= 0; i
< DF_ELEMENTS(DF_BYTE
); i
++) {
1075 pwd
->b
[i
] = pws
->b
[n
];
1079 for (i
= 0; i
< DF_ELEMENTS(DF_HALF
); i
++) {
1080 pwd
->h
[i
] = pws
->h
[n
];
1084 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1085 pwd
->w
[i
] = pws
->w
[n
];
1089 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1090 pwd
->d
[i
] = pws
->d
[n
];
1098 void helper_msa_splat_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1099 uint32_t ws
, uint32_t rt
)
1101 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1102 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1104 msa_splat_df(df
, pwd
, pws
, env
->active_tc
.gpr
[rt
]);
1107 #define MSA_DO_B MSA_DO(b)
1108 #define MSA_DO_H MSA_DO(h)
1109 #define MSA_DO_W MSA_DO(w)
1110 #define MSA_DO_D MSA_DO(d)
1112 #define MSA_LOOP_B MSA_LOOP(B)
1113 #define MSA_LOOP_H MSA_LOOP(H)
1114 #define MSA_LOOP_W MSA_LOOP(W)
1115 #define MSA_LOOP_D MSA_LOOP(D)
1117 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1118 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1119 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1120 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1122 #define MSA_LOOP(DF) \
1123 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1127 #define MSA_FN_DF(FUNC) \
1128 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1129 uint32_t ws, uint32_t wt) \
1131 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1132 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1133 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1134 wr_t wx, *pwx = &wx; \
1152 msa_move_v(pwd, pwx); \
1155 #define MSA_LOOP_COND(DF) \
1156 (DF_ELEMENTS(DF) / 2)
1158 #define Rb(pwr, i) (pwr->b[i])
1159 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1160 #define Rh(pwr, i) (pwr->h[i])
1161 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1162 #define Rw(pwr, i) (pwr->w[i])
1163 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1164 #define Rd(pwr, i) (pwr->d[i])
1165 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1167 #define MSA_DO(DF) \
1169 R##DF(pwx, i) = pwt->DF[2*i]; \
1170 L##DF(pwx, i) = pws->DF[2*i]; \
1175 #define MSA_DO(DF) \
1177 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1178 L##DF(pwx, i) = pws->DF[2*i+1]; \
1183 #define MSA_DO(DF) \
1185 pwx->DF[2*i] = L##DF(pwt, i); \
1186 pwx->DF[2*i+1] = L##DF(pws, i); \
1191 #define MSA_DO(DF) \
1193 pwx->DF[2*i] = R##DF(pwt, i); \
1194 pwx->DF[2*i+1] = R##DF(pws, i); \
1199 #define MSA_DO(DF) \
1201 pwx->DF[2*i] = pwt->DF[2*i]; \
1202 pwx->DF[2*i+1] = pws->DF[2*i]; \
1207 #define MSA_DO(DF) \
1209 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1210 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1214 #undef MSA_LOOP_COND
1216 #define MSA_LOOP_COND(DF) \
1219 #define MSA_DO(DF) \
1221 uint32_t n = DF_ELEMENTS(df); \
1222 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1224 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1228 #undef MSA_LOOP_COND
1231 void helper_msa_sldi_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1232 uint32_t ws
, uint32_t n
)
1234 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1235 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1237 msa_sld_df(df
, pwd
, pws
, n
);
1240 void helper_msa_splati_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1241 uint32_t ws
, uint32_t n
)
1243 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1244 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1246 msa_splat_df(df
, pwd
, pws
, n
);
1249 void helper_msa_copy_s_df(CPUMIPSState
*env
, uint32_t df
, uint32_t rd
,
1250 uint32_t ws
, uint32_t n
)
1252 n
%= DF_ELEMENTS(df
);
1256 env
->active_tc
.gpr
[rd
] = (int8_t)env
->active_fpu
.fpr
[ws
].wr
.b
[n
];
1259 env
->active_tc
.gpr
[rd
] = (int16_t)env
->active_fpu
.fpr
[ws
].wr
.h
[n
];
1262 env
->active_tc
.gpr
[rd
] = (int32_t)env
->active_fpu
.fpr
[ws
].wr
.w
[n
];
1264 #ifdef TARGET_MIPS64
1266 env
->active_tc
.gpr
[rd
] = (int64_t)env
->active_fpu
.fpr
[ws
].wr
.d
[n
];
1274 void helper_msa_copy_u_df(CPUMIPSState
*env
, uint32_t df
, uint32_t rd
,
1275 uint32_t ws
, uint32_t n
)
1277 n
%= DF_ELEMENTS(df
);
1281 env
->active_tc
.gpr
[rd
] = (uint8_t)env
->active_fpu
.fpr
[ws
].wr
.b
[n
];
1284 env
->active_tc
.gpr
[rd
] = (uint16_t)env
->active_fpu
.fpr
[ws
].wr
.h
[n
];
1287 env
->active_tc
.gpr
[rd
] = (uint32_t)env
->active_fpu
.fpr
[ws
].wr
.w
[n
];
1289 #ifdef TARGET_MIPS64
1291 env
->active_tc
.gpr
[rd
] = (uint64_t)env
->active_fpu
.fpr
[ws
].wr
.d
[n
];
1299 void helper_msa_insert_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1300 uint32_t rs_num
, uint32_t n
)
1302 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1303 target_ulong rs
= env
->active_tc
.gpr
[rs_num
];
1307 pwd
->b
[n
] = (int8_t)rs
;
1310 pwd
->h
[n
] = (int16_t)rs
;
1313 pwd
->w
[n
] = (int32_t)rs
;
1316 pwd
->d
[n
] = (int64_t)rs
;
1323 void helper_msa_insve_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1324 uint32_t ws
, uint32_t n
)
1326 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1327 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1331 pwd
->b
[n
] = (int8_t)pws
->b
[0];
1334 pwd
->h
[n
] = (int16_t)pws
->h
[0];
1337 pwd
->w
[n
] = (int32_t)pws
->w
[0];
1340 pwd
->d
[n
] = (int64_t)pws
->d
[0];
1347 void helper_msa_ctcmsa(CPUMIPSState
*env
, target_ulong elm
, uint32_t cd
)
1353 env
->active_tc
.msacsr
= (int32_t)elm
& MSACSR_MASK
;
1354 restore_msa_fp_status(env
);
1355 /* check exception */
1356 if ((GET_FP_ENABLE(env
->active_tc
.msacsr
) | FP_UNIMPLEMENTED
)
1357 & GET_FP_CAUSE(env
->active_tc
.msacsr
)) {
1358 do_raise_exception(env
, EXCP_MSAFPE
, GETPC());
1364 target_ulong
helper_msa_cfcmsa(CPUMIPSState
*env
, uint32_t cs
)
1370 return env
->active_tc
.msacsr
& MSACSR_MASK
;
1375 void helper_msa_move_v(CPUMIPSState
*env
, uint32_t wd
, uint32_t ws
)
1377 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1378 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
1380 msa_move_v(pwd
, pws
);
1383 static inline int64_t msa_pcnt_df(uint32_t df
, int64_t arg
)
1387 x
= UNSIGNED(arg
, df
);
1389 x
= (x
& 0x5555555555555555ULL
) + ((x
>> 1) & 0x5555555555555555ULL
);
1390 x
= (x
& 0x3333333333333333ULL
) + ((x
>> 2) & 0x3333333333333333ULL
);
1391 x
= (x
& 0x0F0F0F0F0F0F0F0FULL
) + ((x
>> 4) & 0x0F0F0F0F0F0F0F0FULL
);
1392 x
= (x
& 0x00FF00FF00FF00FFULL
) + ((x
>> 8) & 0x00FF00FF00FF00FFULL
);
1393 x
= (x
& 0x0000FFFF0000FFFFULL
) + ((x
>> 16) & 0x0000FFFF0000FFFFULL
);
1394 x
= (x
& 0x00000000FFFFFFFFULL
) + ((x
>> 32));
1399 static inline int64_t msa_nlzc_df(uint32_t df
, int64_t arg
)
1404 x
= UNSIGNED(arg
, df
);
1406 c
= DF_BITS(df
) / 2;
1420 static inline int64_t msa_nloc_df(uint32_t df
, int64_t arg
)
1422 return msa_nlzc_df(df
, UNSIGNED((~arg
), df
));
1425 void helper_msa_fill_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
1428 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
1433 for (i
= 0; i
< DF_ELEMENTS(DF_BYTE
); i
++) {
1434 pwd
->b
[i
] = (int8_t)env
->active_tc
.gpr
[rs
];
1438 for (i
= 0; i
< DF_ELEMENTS(DF_HALF
); i
++) {
1439 pwd
->h
[i
] = (int16_t)env
->active_tc
.gpr
[rs
];
1443 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1444 pwd
->w
[i
] = (int32_t)env
->active_tc
.gpr
[rs
];
1448 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1449 pwd
->d
[i
] = (int64_t)env
->active_tc
.gpr
[rs
];
1457 #define MSA_UNOP_DF(func) \
1458 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1459 uint32_t wd, uint32_t ws) \
1461 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1462 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1467 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1468 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1472 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1473 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1477 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1478 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1482 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1483 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1496 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1497 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1499 #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
1501 #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
1503 #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
1504 /* 0x7ff0000000000020 */
1506 static inline void clear_msacsr_cause(CPUMIPSState
*env
)
1508 SET_FP_CAUSE(env
->active_tc
.msacsr
, 0);
1511 static inline void check_msacsr_cause(CPUMIPSState
*env
, uintptr_t retaddr
)
1513 if ((GET_FP_CAUSE(env
->active_tc
.msacsr
) &
1514 (GET_FP_ENABLE(env
->active_tc
.msacsr
) | FP_UNIMPLEMENTED
)) == 0) {
1515 UPDATE_FP_FLAGS(env
->active_tc
.msacsr
,
1516 GET_FP_CAUSE(env
->active_tc
.msacsr
));
1518 do_raise_exception(env
, EXCP_MSAFPE
, retaddr
);
1522 /* Flush-to-zero use cases for update_msacsr() */
1523 #define CLEAR_FS_UNDERFLOW 1
1524 #define CLEAR_IS_INEXACT 2
1525 #define RECIPROCAL_INEXACT 4
1527 static inline int update_msacsr(CPUMIPSState
*env
, int action
, int denormal
)
1535 ieee_ex
= get_float_exception_flags(&env
->active_tc
.msa_fp_status
);
1537 /* QEMU softfloat does not signal all underflow cases */
1539 ieee_ex
|= float_flag_underflow
;
1542 c
= ieee_ex_to_mips(ieee_ex
);
1543 enable
= GET_FP_ENABLE(env
->active_tc
.msacsr
) | FP_UNIMPLEMENTED
;
1545 /* Set Inexact (I) when flushing inputs to zero */
1546 if ((ieee_ex
& float_flag_input_denormal
) &&
1547 (env
->active_tc
.msacsr
& MSACSR_FS_MASK
) != 0) {
1548 if (action
& CLEAR_IS_INEXACT
) {
1555 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1556 if ((ieee_ex
& float_flag_output_denormal
) &&
1557 (env
->active_tc
.msacsr
& MSACSR_FS_MASK
) != 0) {
1559 if (action
& CLEAR_FS_UNDERFLOW
) {
1566 /* Set Inexact (I) when Overflow (O) is not enabled */
1567 if ((c
& FP_OVERFLOW
) != 0 && (enable
& FP_OVERFLOW
) == 0) {
1571 /* Clear Exact Underflow when Underflow (U) is not enabled */
1572 if ((c
& FP_UNDERFLOW
) != 0 && (enable
& FP_UNDERFLOW
) == 0 &&
1573 (c
& FP_INEXACT
) == 0) {
1577 /* Reciprocal operations set only Inexact when valid and not
1579 if ((action
& RECIPROCAL_INEXACT
) &&
1580 (c
& (FP_INVALID
| FP_DIV0
)) == 0) {
1584 cause
= c
& enable
; /* all current enabled exceptions */
1587 /* No enabled exception, update the MSACSR Cause
1588 with all current exceptions */
1589 SET_FP_CAUSE(env
->active_tc
.msacsr
,
1590 (GET_FP_CAUSE(env
->active_tc
.msacsr
) | c
));
1592 /* Current exceptions are enabled */
1593 if ((env
->active_tc
.msacsr
& MSACSR_NX_MASK
) == 0) {
1594 /* Exception(s) will trap, update MSACSR Cause
1595 with all enabled exceptions */
1596 SET_FP_CAUSE(env
->active_tc
.msacsr
,
1597 (GET_FP_CAUSE(env
->active_tc
.msacsr
) | c
));
1604 static inline int get_enabled_exceptions(const CPUMIPSState
*env
, int c
)
1606 int enable
= GET_FP_ENABLE(env
->active_tc
.msacsr
) | FP_UNIMPLEMENTED
;
1610 static inline float16
float16_from_float32(int32_t a
, flag ieee
,
1611 float_status
*status
)
1615 f_val
= float32_to_float16((float32
)a
, ieee
, status
);
1616 f_val
= float16_maybe_silence_nan(f_val
, status
);
1618 return a
< 0 ? (f_val
| (1 << 15)) : f_val
;
1621 static inline float32
float32_from_float64(int64_t a
, float_status
*status
)
1625 f_val
= float64_to_float32((float64
)a
, status
);
1626 f_val
= float32_maybe_silence_nan(f_val
, status
);
1628 return a
< 0 ? (f_val
| (1 << 31)) : f_val
;
1631 static inline float32
float32_from_float16(int16_t a
, flag ieee
,
1632 float_status
*status
)
1636 f_val
= float16_to_float32((float16
)a
, ieee
, status
);
1637 f_val
= float32_maybe_silence_nan(f_val
, status
);
1639 return a
< 0 ? (f_val
| (1 << 31)) : f_val
;
1642 static inline float64
float64_from_float32(int32_t a
, float_status
*status
)
1646 f_val
= float32_to_float64((float64
)a
, status
);
1647 f_val
= float64_maybe_silence_nan(f_val
, status
);
1649 return a
< 0 ? (f_val
| (1ULL << 63)) : f_val
;
1652 static inline float32
float32_from_q16(int16_t a
, float_status
*status
)
1656 /* conversion as integer and scaling */
1657 f_val
= int32_to_float32(a
, status
);
1658 f_val
= float32_scalbn(f_val
, -15, status
);
1663 static inline float64
float64_from_q32(int32_t a
, float_status
*status
)
1667 /* conversion as integer and scaling */
1668 f_val
= int32_to_float64(a
, status
);
1669 f_val
= float64_scalbn(f_val
, -31, status
);
1674 static inline int16_t float32_to_q16(float32 a
, float_status
*status
)
1677 int32_t q_min
= 0xffff8000;
1678 int32_t q_max
= 0x00007fff;
1682 if (float32_is_any_nan(a
)) {
1683 float_raise(float_flag_invalid
, status
);
1688 a
= float32_scalbn(a
, 15, status
);
1690 ieee_ex
= get_float_exception_flags(status
);
1691 set_float_exception_flags(ieee_ex
& (~float_flag_underflow
)
1694 if (ieee_ex
& float_flag_overflow
) {
1695 float_raise(float_flag_inexact
, status
);
1696 return (int32_t)a
< 0 ? q_min
: q_max
;
1699 /* conversion to int */
1700 q_val
= float32_to_int32(a
, status
);
1702 ieee_ex
= get_float_exception_flags(status
);
1703 set_float_exception_flags(ieee_ex
& (~float_flag_underflow
)
1706 if (ieee_ex
& float_flag_invalid
) {
1707 set_float_exception_flags(ieee_ex
& (~float_flag_invalid
)
1709 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1710 return (int32_t)a
< 0 ? q_min
: q_max
;
1713 if (q_val
< q_min
) {
1714 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1715 return (int16_t)q_min
;
1718 if (q_max
< q_val
) {
1719 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1720 return (int16_t)q_max
;
1723 return (int16_t)q_val
;
1726 static inline int32_t float64_to_q32(float64 a
, float_status
*status
)
1729 int64_t q_min
= 0xffffffff80000000LL
;
1730 int64_t q_max
= 0x000000007fffffffLL
;
1734 if (float64_is_any_nan(a
)) {
1735 float_raise(float_flag_invalid
, status
);
1740 a
= float64_scalbn(a
, 31, status
);
1742 ieee_ex
= get_float_exception_flags(status
);
1743 set_float_exception_flags(ieee_ex
& (~float_flag_underflow
)
1746 if (ieee_ex
& float_flag_overflow
) {
1747 float_raise(float_flag_inexact
, status
);
1748 return (int64_t)a
< 0 ? q_min
: q_max
;
1751 /* conversion to integer */
1752 q_val
= float64_to_int64(a
, status
);
1754 ieee_ex
= get_float_exception_flags(status
);
1755 set_float_exception_flags(ieee_ex
& (~float_flag_underflow
)
1758 if (ieee_ex
& float_flag_invalid
) {
1759 set_float_exception_flags(ieee_ex
& (~float_flag_invalid
)
1761 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1762 return (int64_t)a
< 0 ? q_min
: q_max
;
1765 if (q_val
< q_min
) {
1766 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1767 return (int32_t)q_min
;
1770 if (q_max
< q_val
) {
1771 float_raise(float_flag_overflow
| float_flag_inexact
, status
);
1772 return (int32_t)q_max
;
1775 return (int32_t)q_val
;
1778 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1780 float_status *status = &env->active_tc.msa_fp_status; \
1783 set_float_exception_flags(0, status); \
1785 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1787 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1789 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1790 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1792 if (get_enabled_exceptions(env, c)) { \
1793 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
1797 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1799 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1800 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1805 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1807 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1809 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1813 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1815 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1817 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1821 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1823 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1825 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1827 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1832 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1834 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1836 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1840 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1842 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1844 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1848 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1850 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1852 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1856 static inline void compare_af(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1857 wr_t
*pwt
, uint32_t df
, int quiet
,
1860 wr_t wx
, *pwx
= &wx
;
1863 clear_msacsr_cause(env
);
1867 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1868 MSA_FLOAT_AF(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
1872 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1873 MSA_FLOAT_AF(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
1880 check_msacsr_cause(env
, retaddr
);
1882 msa_move_v(pwd
, pwx
);
1885 static inline void compare_un(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1886 wr_t
*pwt
, uint32_t df
, int quiet
,
1889 wr_t wx
, *pwx
= &wx
;
1892 clear_msacsr_cause(env
);
1896 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1897 MSA_FLOAT_COND(pwx
->w
[i
], unordered
, pws
->w
[i
], pwt
->w
[i
], 32,
1902 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1903 MSA_FLOAT_COND(pwx
->d
[i
], unordered
, pws
->d
[i
], pwt
->d
[i
], 64,
1911 check_msacsr_cause(env
, retaddr
);
1913 msa_move_v(pwd
, pwx
);
1916 static inline void compare_eq(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1917 wr_t
*pwt
, uint32_t df
, int quiet
,
1920 wr_t wx
, *pwx
= &wx
;
1923 clear_msacsr_cause(env
);
1927 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1928 MSA_FLOAT_COND(pwx
->w
[i
], eq
, pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
1932 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1933 MSA_FLOAT_COND(pwx
->d
[i
], eq
, pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
1940 check_msacsr_cause(env
, retaddr
);
1942 msa_move_v(pwd
, pwx
);
1945 static inline void compare_ueq(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1946 wr_t
*pwt
, uint32_t df
, int quiet
,
1949 wr_t wx
, *pwx
= &wx
;
1952 clear_msacsr_cause(env
);
1956 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1957 MSA_FLOAT_UEQ(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
1961 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1962 MSA_FLOAT_UEQ(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
1969 check_msacsr_cause(env
, retaddr
);
1971 msa_move_v(pwd
, pwx
);
1974 static inline void compare_lt(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
1975 wr_t
*pwt
, uint32_t df
, int quiet
,
1978 wr_t wx
, *pwx
= &wx
;
1981 clear_msacsr_cause(env
);
1985 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
1986 MSA_FLOAT_COND(pwx
->w
[i
], lt
, pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
1990 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
1991 MSA_FLOAT_COND(pwx
->d
[i
], lt
, pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
1998 check_msacsr_cause(env
, retaddr
);
2000 msa_move_v(pwd
, pwx
);
2003 static inline void compare_ult(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2004 wr_t
*pwt
, uint32_t df
, int quiet
,
2007 wr_t wx
, *pwx
= &wx
;
2010 clear_msacsr_cause(env
);
2014 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2015 MSA_FLOAT_ULT(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2019 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2020 MSA_FLOAT_ULT(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2027 check_msacsr_cause(env
, retaddr
);
2029 msa_move_v(pwd
, pwx
);
2032 static inline void compare_le(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2033 wr_t
*pwt
, uint32_t df
, int quiet
,
2036 wr_t wx
, *pwx
= &wx
;
2039 clear_msacsr_cause(env
);
2043 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2044 MSA_FLOAT_COND(pwx
->w
[i
], le
, pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2048 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2049 MSA_FLOAT_COND(pwx
->d
[i
], le
, pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2056 check_msacsr_cause(env
, retaddr
);
2058 msa_move_v(pwd
, pwx
);
2061 static inline void compare_ule(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2062 wr_t
*pwt
, uint32_t df
, int quiet
,
2065 wr_t wx
, *pwx
= &wx
;
2068 clear_msacsr_cause(env
);
2072 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2073 MSA_FLOAT_ULE(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2077 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2078 MSA_FLOAT_ULE(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2085 check_msacsr_cause(env
, retaddr
);
2087 msa_move_v(pwd
, pwx
);
2090 static inline void compare_or(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2091 wr_t
*pwt
, uint32_t df
, int quiet
,
2094 wr_t wx
, *pwx
= &wx
;
2097 clear_msacsr_cause(env
);
2101 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2102 MSA_FLOAT_OR(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2106 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2107 MSA_FLOAT_OR(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2114 check_msacsr_cause(env
, retaddr
);
2116 msa_move_v(pwd
, pwx
);
2119 static inline void compare_une(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2120 wr_t
*pwt
, uint32_t df
, int quiet
,
2123 wr_t wx
, *pwx
= &wx
;
2126 clear_msacsr_cause(env
);
2130 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2131 MSA_FLOAT_UNE(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2135 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2136 MSA_FLOAT_UNE(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2143 check_msacsr_cause(env
, retaddr
);
2145 msa_move_v(pwd
, pwx
);
2148 static inline void compare_ne(CPUMIPSState
*env
, wr_t
*pwd
, wr_t
*pws
,
2149 wr_t
*pwt
, uint32_t df
, int quiet
,
2152 wr_t wx
, *pwx
= &wx
;
2155 clear_msacsr_cause(env
);
2159 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2160 MSA_FLOAT_NE(pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, quiet
);
2164 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2165 MSA_FLOAT_NE(pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, quiet
);
2172 check_msacsr_cause(env
, retaddr
);
2174 msa_move_v(pwd
, pwx
);
2177 void helper_msa_fcaf_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2178 uint32_t ws
, uint32_t wt
)
2180 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2181 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2182 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2183 compare_af(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2186 void helper_msa_fcun_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2187 uint32_t ws
, uint32_t wt
)
2189 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2190 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2191 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2192 compare_un(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2195 void helper_msa_fceq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2196 uint32_t ws
, uint32_t wt
)
2198 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2199 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2200 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2201 compare_eq(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2204 void helper_msa_fcueq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2205 uint32_t ws
, uint32_t wt
)
2207 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2208 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2209 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2210 compare_ueq(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2213 void helper_msa_fclt_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2214 uint32_t ws
, uint32_t wt
)
2216 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2217 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2218 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2219 compare_lt(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2222 void helper_msa_fcult_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2223 uint32_t ws
, uint32_t wt
)
2225 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2226 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2227 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2228 compare_ult(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2231 void helper_msa_fcle_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2232 uint32_t ws
, uint32_t wt
)
2234 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2235 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2236 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2237 compare_le(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2240 void helper_msa_fcule_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2241 uint32_t ws
, uint32_t wt
)
2243 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2244 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2245 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2246 compare_ule(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2249 void helper_msa_fsaf_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2250 uint32_t ws
, uint32_t wt
)
2252 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2253 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2254 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2255 compare_af(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2258 void helper_msa_fsun_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2259 uint32_t ws
, uint32_t wt
)
2261 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2262 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2263 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2264 compare_un(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2267 void helper_msa_fseq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2268 uint32_t ws
, uint32_t wt
)
2270 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2271 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2272 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2273 compare_eq(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2276 void helper_msa_fsueq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2277 uint32_t ws
, uint32_t wt
)
2279 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2280 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2281 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2282 compare_ueq(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2285 void helper_msa_fslt_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2286 uint32_t ws
, uint32_t wt
)
2288 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2289 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2290 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2291 compare_lt(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2294 void helper_msa_fsult_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2295 uint32_t ws
, uint32_t wt
)
2297 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2298 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2299 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2300 compare_ult(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2303 void helper_msa_fsle_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2304 uint32_t ws
, uint32_t wt
)
2306 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2307 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2308 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2309 compare_le(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2312 void helper_msa_fsule_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2313 uint32_t ws
, uint32_t wt
)
2315 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2316 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2317 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2318 compare_ule(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2321 void helper_msa_fcor_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2322 uint32_t ws
, uint32_t wt
)
2324 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2325 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2326 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2327 compare_or(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2330 void helper_msa_fcune_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2331 uint32_t ws
, uint32_t wt
)
2333 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2334 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2335 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2336 compare_une(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2339 void helper_msa_fcne_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2340 uint32_t ws
, uint32_t wt
)
2342 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2343 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2344 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2345 compare_ne(env
, pwd
, pws
, pwt
, df
, 1, GETPC());
2348 void helper_msa_fsor_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2349 uint32_t ws
, uint32_t wt
)
2351 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2352 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2353 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2354 compare_or(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2357 void helper_msa_fsune_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2358 uint32_t ws
, uint32_t wt
)
2360 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2361 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2362 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2363 compare_une(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2366 void helper_msa_fsne_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2367 uint32_t ws
, uint32_t wt
)
2369 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2370 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2371 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2372 compare_ne(env
, pwd
, pws
, pwt
, df
, 0, GETPC());
2375 #define float16_is_zero(ARG) 0
2376 #define float16_is_zero_or_denormal(ARG) 0
2378 #define IS_DENORMAL(ARG, BITS) \
2379 (!float ## BITS ## _is_zero(ARG) \
2380 && float ## BITS ## _is_zero_or_denormal(ARG))
2382 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2384 float_status *status = &env->active_tc.msa_fp_status; \
2387 set_float_exception_flags(0, status); \
2388 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2389 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2391 if (get_enabled_exceptions(env, c)) { \
2392 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2396 void helper_msa_fadd_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2397 uint32_t ws
, uint32_t wt
)
2399 wr_t wx
, *pwx
= &wx
;
2400 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2401 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2402 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2405 clear_msacsr_cause(env
);
2409 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2410 MSA_FLOAT_BINOP(pwx
->w
[i
], add
, pws
->w
[i
], pwt
->w
[i
], 32);
2414 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2415 MSA_FLOAT_BINOP(pwx
->d
[i
], add
, pws
->d
[i
], pwt
->d
[i
], 64);
2422 check_msacsr_cause(env
, GETPC());
2423 msa_move_v(pwd
, pwx
);
2426 void helper_msa_fsub_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2427 uint32_t ws
, uint32_t wt
)
2429 wr_t wx
, *pwx
= &wx
;
2430 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2431 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2432 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2435 clear_msacsr_cause(env
);
2439 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2440 MSA_FLOAT_BINOP(pwx
->w
[i
], sub
, pws
->w
[i
], pwt
->w
[i
], 32);
2444 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2445 MSA_FLOAT_BINOP(pwx
->d
[i
], sub
, pws
->d
[i
], pwt
->d
[i
], 64);
2452 check_msacsr_cause(env
, GETPC());
2453 msa_move_v(pwd
, pwx
);
2456 void helper_msa_fmul_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2457 uint32_t ws
, uint32_t wt
)
2459 wr_t wx
, *pwx
= &wx
;
2460 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2461 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2462 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2465 clear_msacsr_cause(env
);
2469 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2470 MSA_FLOAT_BINOP(pwx
->w
[i
], mul
, pws
->w
[i
], pwt
->w
[i
], 32);
2474 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2475 MSA_FLOAT_BINOP(pwx
->d
[i
], mul
, pws
->d
[i
], pwt
->d
[i
], 64);
2482 check_msacsr_cause(env
, GETPC());
2484 msa_move_v(pwd
, pwx
);
2487 void helper_msa_fdiv_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2488 uint32_t ws
, uint32_t wt
)
2490 wr_t wx
, *pwx
= &wx
;
2491 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2492 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2493 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2496 clear_msacsr_cause(env
);
2500 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2501 MSA_FLOAT_BINOP(pwx
->w
[i
], div
, pws
->w
[i
], pwt
->w
[i
], 32);
2505 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2506 MSA_FLOAT_BINOP(pwx
->d
[i
], div
, pws
->d
[i
], pwt
->d
[i
], 64);
2513 check_msacsr_cause(env
, GETPC());
2515 msa_move_v(pwd
, pwx
);
2518 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2520 float_status *status = &env->active_tc.msa_fp_status; \
2523 set_float_exception_flags(0, status); \
2524 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2525 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2527 if (get_enabled_exceptions(env, c)) { \
2528 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2532 void helper_msa_fmadd_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2533 uint32_t ws
, uint32_t wt
)
2535 wr_t wx
, *pwx
= &wx
;
2536 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2537 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2538 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2541 clear_msacsr_cause(env
);
2545 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2546 MSA_FLOAT_MULADD(pwx
->w
[i
], pwd
->w
[i
],
2547 pws
->w
[i
], pwt
->w
[i
], 0, 32);
2551 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2552 MSA_FLOAT_MULADD(pwx
->d
[i
], pwd
->d
[i
],
2553 pws
->d
[i
], pwt
->d
[i
], 0, 64);
2560 check_msacsr_cause(env
, GETPC());
2562 msa_move_v(pwd
, pwx
);
2565 void helper_msa_fmsub_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2566 uint32_t ws
, uint32_t wt
)
2568 wr_t wx
, *pwx
= &wx
;
2569 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2570 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2571 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2574 clear_msacsr_cause(env
);
2578 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2579 MSA_FLOAT_MULADD(pwx
->w
[i
], pwd
->w
[i
],
2580 pws
->w
[i
], pwt
->w
[i
],
2581 float_muladd_negate_product
, 32);
2585 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2586 MSA_FLOAT_MULADD(pwx
->d
[i
], pwd
->d
[i
],
2587 pws
->d
[i
], pwt
->d
[i
],
2588 float_muladd_negate_product
, 64);
2595 check_msacsr_cause(env
, GETPC());
2597 msa_move_v(pwd
, pwx
);
2600 void helper_msa_fexp2_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2601 uint32_t ws
, uint32_t wt
)
2603 wr_t wx
, *pwx
= &wx
;
2604 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2605 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2606 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2609 clear_msacsr_cause(env
);
2613 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2614 MSA_FLOAT_BINOP(pwx
->w
[i
], scalbn
, pws
->w
[i
],
2615 pwt
->w
[i
] > 0x200 ? 0x200 :
2616 pwt
->w
[i
] < -0x200 ? -0x200 : pwt
->w
[i
],
2621 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2622 MSA_FLOAT_BINOP(pwx
->d
[i
], scalbn
, pws
->d
[i
],
2623 pwt
->d
[i
] > 0x1000 ? 0x1000 :
2624 pwt
->d
[i
] < -0x1000 ? -0x1000 : pwt
->d
[i
],
2632 check_msacsr_cause(env
, GETPC());
2634 msa_move_v(pwd
, pwx
);
2637 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2639 float_status *status = &env->active_tc.msa_fp_status; \
2642 set_float_exception_flags(0, status); \
2643 DEST = float ## BITS ## _ ## OP(ARG, status); \
2644 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2646 if (get_enabled_exceptions(env, c)) { \
2647 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2651 void helper_msa_fexdo_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2652 uint32_t ws
, uint32_t wt
)
2654 wr_t wx
, *pwx
= &wx
;
2655 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2656 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2657 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2660 clear_msacsr_cause(env
);
2664 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2665 /* Half precision floats come in two formats: standard
2666 IEEE and "ARM" format. The latter gains extra exponent
2667 range by omitting the NaN/Inf encodings. */
2670 MSA_FLOAT_BINOP(Lh(pwx
, i
), from_float32
, pws
->w
[i
], ieee
, 16);
2671 MSA_FLOAT_BINOP(Rh(pwx
, i
), from_float32
, pwt
->w
[i
], ieee
, 16);
2675 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2676 MSA_FLOAT_UNOP(Lw(pwx
, i
), from_float64
, pws
->d
[i
], 32);
2677 MSA_FLOAT_UNOP(Rw(pwx
, i
), from_float64
, pwt
->d
[i
], 32);
2684 check_msacsr_cause(env
, GETPC());
2685 msa_move_v(pwd
, pwx
);
2688 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2690 float_status *status = &env->active_tc.msa_fp_status; \
2693 set_float_exception_flags(0, status); \
2694 DEST = float ## BITS ## _ ## OP(ARG, status); \
2695 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2697 if (get_enabled_exceptions(env, c)) { \
2698 DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
2702 void helper_msa_ftq_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2703 uint32_t ws
, uint32_t wt
)
2705 wr_t wx
, *pwx
= &wx
;
2706 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2707 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2708 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2711 clear_msacsr_cause(env
);
2715 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2716 MSA_FLOAT_UNOP_XD(Lh(pwx
, i
), to_q16
, pws
->w
[i
], 32, 16);
2717 MSA_FLOAT_UNOP_XD(Rh(pwx
, i
), to_q16
, pwt
->w
[i
], 32, 16);
2721 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2722 MSA_FLOAT_UNOP_XD(Lw(pwx
, i
), to_q32
, pws
->d
[i
], 64, 32);
2723 MSA_FLOAT_UNOP_XD(Rw(pwx
, i
), to_q32
, pwt
->d
[i
], 64, 32);
2730 check_msacsr_cause(env
, GETPC());
2732 msa_move_v(pwd
, pwx
);
2735 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
2736 !float ## BITS ## _is_any_nan(ARG1) \
2737 && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
2739 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2741 float_status *status = &env->active_tc.msa_fp_status; \
2744 set_float_exception_flags(0, status); \
2745 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2746 c = update_msacsr(env, 0, 0); \
2748 if (get_enabled_exceptions(env, c)) { \
2749 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2753 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
2755 uint## BITS ##_t S = _S, T = _T; \
2756 uint## BITS ##_t as, at, xs, xt, xd; \
2757 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
2760 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
2763 as = float## BITS ##_abs(S); \
2764 at = float## BITS ##_abs(T); \
2765 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2766 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2767 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2768 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2771 void helper_msa_fmin_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2772 uint32_t ws
, uint32_t wt
)
2774 float_status
*status
= &env
->active_tc
.msa_fp_status
;
2775 wr_t wx
, *pwx
= &wx
;
2776 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2777 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2778 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2781 clear_msacsr_cause(env
);
2785 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2786 if (NUMBER_QNAN_PAIR(pws
->w
[i
], pwt
->w
[i
], 32, status
)) {
2787 MSA_FLOAT_MAXOP(pwx
->w
[i
], min
, pws
->w
[i
], pws
->w
[i
], 32);
2788 } else if (NUMBER_QNAN_PAIR(pwt
->w
[i
], pws
->w
[i
], 32, status
)) {
2789 MSA_FLOAT_MAXOP(pwx
->w
[i
], min
, pwt
->w
[i
], pwt
->w
[i
], 32);
2791 MSA_FLOAT_MAXOP(pwx
->w
[i
], min
, pws
->w
[i
], pwt
->w
[i
], 32);
2796 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2797 if (NUMBER_QNAN_PAIR(pws
->d
[i
], pwt
->d
[i
], 64, status
)) {
2798 MSA_FLOAT_MAXOP(pwx
->d
[i
], min
, pws
->d
[i
], pws
->d
[i
], 64);
2799 } else if (NUMBER_QNAN_PAIR(pwt
->d
[i
], pws
->d
[i
], 64, status
)) {
2800 MSA_FLOAT_MAXOP(pwx
->d
[i
], min
, pwt
->d
[i
], pwt
->d
[i
], 64);
2802 MSA_FLOAT_MAXOP(pwx
->d
[i
], min
, pws
->d
[i
], pwt
->d
[i
], 64);
2810 check_msacsr_cause(env
, GETPC());
2812 msa_move_v(pwd
, pwx
);
2815 void helper_msa_fmin_a_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2816 uint32_t ws
, uint32_t wt
)
2818 float_status
*status
= &env
->active_tc
.msa_fp_status
;
2819 wr_t wx
, *pwx
= &wx
;
2820 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2821 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2822 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2825 clear_msacsr_cause(env
);
2829 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2830 FMAXMIN_A(min
, max
, pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, status
);
2834 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2835 FMAXMIN_A(min
, max
, pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, status
);
2842 check_msacsr_cause(env
, GETPC());
2844 msa_move_v(pwd
, pwx
);
2847 void helper_msa_fmax_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2848 uint32_t ws
, uint32_t wt
)
2850 float_status
*status
= &env
->active_tc
.msa_fp_status
;
2851 wr_t wx
, *pwx
= &wx
;
2852 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2853 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2854 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2857 clear_msacsr_cause(env
);
2861 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2862 if (NUMBER_QNAN_PAIR(pws
->w
[i
], pwt
->w
[i
], 32, status
)) {
2863 MSA_FLOAT_MAXOP(pwx
->w
[i
], max
, pws
->w
[i
], pws
->w
[i
], 32);
2864 } else if (NUMBER_QNAN_PAIR(pwt
->w
[i
], pws
->w
[i
], 32, status
)) {
2865 MSA_FLOAT_MAXOP(pwx
->w
[i
], max
, pwt
->w
[i
], pwt
->w
[i
], 32);
2867 MSA_FLOAT_MAXOP(pwx
->w
[i
], max
, pws
->w
[i
], pwt
->w
[i
], 32);
2872 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2873 if (NUMBER_QNAN_PAIR(pws
->d
[i
], pwt
->d
[i
], 64, status
)) {
2874 MSA_FLOAT_MAXOP(pwx
->d
[i
], max
, pws
->d
[i
], pws
->d
[i
], 64);
2875 } else if (NUMBER_QNAN_PAIR(pwt
->d
[i
], pws
->d
[i
], 64, status
)) {
2876 MSA_FLOAT_MAXOP(pwx
->d
[i
], max
, pwt
->d
[i
], pwt
->d
[i
], 64);
2878 MSA_FLOAT_MAXOP(pwx
->d
[i
], max
, pws
->d
[i
], pwt
->d
[i
], 64);
2886 check_msacsr_cause(env
, GETPC());
2888 msa_move_v(pwd
, pwx
);
2891 void helper_msa_fmax_a_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2892 uint32_t ws
, uint32_t wt
)
2894 float_status
*status
= &env
->active_tc
.msa_fp_status
;
2895 wr_t wx
, *pwx
= &wx
;
2896 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2897 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2898 wr_t
*pwt
= &(env
->active_fpu
.fpr
[wt
].wr
);
2901 clear_msacsr_cause(env
);
2905 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2906 FMAXMIN_A(max
, min
, pwx
->w
[i
], pws
->w
[i
], pwt
->w
[i
], 32, status
);
2910 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2911 FMAXMIN_A(max
, min
, pwx
->d
[i
], pws
->d
[i
], pwt
->d
[i
], 64, status
);
2918 check_msacsr_cause(env
, GETPC());
2920 msa_move_v(pwd
, pwx
);
2923 void helper_msa_fclass_df(CPUMIPSState
*env
, uint32_t df
,
2924 uint32_t wd
, uint32_t ws
)
2926 float_status
* status
= &env
->active_tc
.msa_fp_status
;
2928 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2929 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2930 if (df
== DF_WORD
) {
2931 pwd
->w
[0] = float_class_s(pws
->w
[0], status
);
2932 pwd
->w
[1] = float_class_s(pws
->w
[1], status
);
2933 pwd
->w
[2] = float_class_s(pws
->w
[2], status
);
2934 pwd
->w
[3] = float_class_s(pws
->w
[3], status
);
2936 pwd
->d
[0] = float_class_d(pws
->d
[0], status
);
2937 pwd
->d
[1] = float_class_d(pws
->d
[1], status
);
2941 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2943 float_status *status = &env->active_tc.msa_fp_status; \
2946 set_float_exception_flags(0, status); \
2947 DEST = float ## BITS ## _ ## OP(ARG, status); \
2948 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2950 if (get_enabled_exceptions(env, c)) { \
2951 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2952 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2957 void helper_msa_ftrunc_s_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2960 wr_t wx
, *pwx
= &wx
;
2961 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2962 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2965 clear_msacsr_cause(env
);
2969 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
2970 MSA_FLOAT_UNOP0(pwx
->w
[i
], to_int32_round_to_zero
, pws
->w
[i
], 32);
2974 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
2975 MSA_FLOAT_UNOP0(pwx
->d
[i
], to_int64_round_to_zero
, pws
->d
[i
], 64);
2982 check_msacsr_cause(env
, GETPC());
2984 msa_move_v(pwd
, pwx
);
2987 void helper_msa_ftrunc_u_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
2990 wr_t wx
, *pwx
= &wx
;
2991 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
2992 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
2995 clear_msacsr_cause(env
);
2999 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3000 MSA_FLOAT_UNOP0(pwx
->w
[i
], to_uint32_round_to_zero
, pws
->w
[i
], 32);
3004 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3005 MSA_FLOAT_UNOP0(pwx
->d
[i
], to_uint64_round_to_zero
, pws
->d
[i
], 64);
3012 check_msacsr_cause(env
, GETPC());
3014 msa_move_v(pwd
, pwx
);
3017 void helper_msa_fsqrt_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3020 wr_t wx
, *pwx
= &wx
;
3021 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3022 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3025 clear_msacsr_cause(env
);
3029 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3030 MSA_FLOAT_UNOP(pwx
->w
[i
], sqrt
, pws
->w
[i
], 32);
3034 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3035 MSA_FLOAT_UNOP(pwx
->d
[i
], sqrt
, pws
->d
[i
], 64);
3042 check_msacsr_cause(env
, GETPC());
3044 msa_move_v(pwd
, pwx
);
3047 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3049 float_status *status = &env->active_tc.msa_fp_status; \
3052 set_float_exception_flags(0, status); \
3053 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3054 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3055 float ## BITS ## _is_quiet_nan(DEST, status) ? \
3056 0 : RECIPROCAL_INEXACT, \
3057 IS_DENORMAL(DEST, BITS)); \
3059 if (get_enabled_exceptions(env, c)) { \
3060 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3064 void helper_msa_frsqrt_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3067 wr_t wx
, *pwx
= &wx
;
3068 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3069 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3072 clear_msacsr_cause(env
);
3076 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3077 MSA_FLOAT_RECIPROCAL(pwx
->w
[i
], float32_sqrt(pws
->w
[i
],
3078 &env
->active_tc
.msa_fp_status
), 32);
3082 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3083 MSA_FLOAT_RECIPROCAL(pwx
->d
[i
], float64_sqrt(pws
->d
[i
],
3084 &env
->active_tc
.msa_fp_status
), 64);
3091 check_msacsr_cause(env
, GETPC());
3093 msa_move_v(pwd
, pwx
);
3096 void helper_msa_frcp_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3099 wr_t wx
, *pwx
= &wx
;
3100 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3101 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3104 clear_msacsr_cause(env
);
3108 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3109 MSA_FLOAT_RECIPROCAL(pwx
->w
[i
], pws
->w
[i
], 32);
3113 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3114 MSA_FLOAT_RECIPROCAL(pwx
->d
[i
], pws
->d
[i
], 64);
3121 check_msacsr_cause(env
, GETPC());
3123 msa_move_v(pwd
, pwx
);
3126 void helper_msa_frint_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3129 wr_t wx
, *pwx
= &wx
;
3130 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3131 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3134 clear_msacsr_cause(env
);
3138 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3139 MSA_FLOAT_UNOP(pwx
->w
[i
], round_to_int
, pws
->w
[i
], 32);
3143 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3144 MSA_FLOAT_UNOP(pwx
->d
[i
], round_to_int
, pws
->d
[i
], 64);
3151 check_msacsr_cause(env
, GETPC());
3153 msa_move_v(pwd
, pwx
);
3156 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3158 float_status *status = &env->active_tc.msa_fp_status; \
3161 set_float_exception_flags(0, status); \
3162 set_float_rounding_mode(float_round_down, status); \
3163 DEST = float ## BITS ## _ ## log2(ARG, status); \
3164 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3165 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3166 MSACSR_RM_MASK) >> MSACSR_RM], \
3169 set_float_exception_flags(get_float_exception_flags(status) & \
3170 (~float_flag_inexact), \
3173 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3175 if (get_enabled_exceptions(env, c)) { \
3176 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3180 void helper_msa_flog2_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3183 wr_t wx
, *pwx
= &wx
;
3184 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3185 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3188 clear_msacsr_cause(env
);
3192 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3193 MSA_FLOAT_LOGB(pwx
->w
[i
], pws
->w
[i
], 32);
3197 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3198 MSA_FLOAT_LOGB(pwx
->d
[i
], pws
->d
[i
], 64);
3205 check_msacsr_cause(env
, GETPC());
3207 msa_move_v(pwd
, pwx
);
3210 void helper_msa_fexupl_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3213 wr_t wx
, *pwx
= &wx
;
3214 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3215 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3218 clear_msacsr_cause(env
);
3222 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3223 /* Half precision floats come in two formats: standard
3224 IEEE and "ARM" format. The latter gains extra exponent
3225 range by omitting the NaN/Inf encodings. */
3228 MSA_FLOAT_BINOP(pwx
->w
[i
], from_float16
, Lh(pws
, i
), ieee
, 32);
3232 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3233 MSA_FLOAT_UNOP(pwx
->d
[i
], from_float32
, Lw(pws
, i
), 64);
3240 check_msacsr_cause(env
, GETPC());
3241 msa_move_v(pwd
, pwx
);
3244 void helper_msa_fexupr_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3247 wr_t wx
, *pwx
= &wx
;
3248 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3249 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3252 clear_msacsr_cause(env
);
3256 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3257 /* Half precision floats come in two formats: standard
3258 IEEE and "ARM" format. The latter gains extra exponent
3259 range by omitting the NaN/Inf encodings. */
3262 MSA_FLOAT_BINOP(pwx
->w
[i
], from_float16
, Rh(pws
, i
), ieee
, 32);
3266 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3267 MSA_FLOAT_UNOP(pwx
->d
[i
], from_float32
, Rw(pws
, i
), 64);
3274 check_msacsr_cause(env
, GETPC());
3275 msa_move_v(pwd
, pwx
);
3278 void helper_msa_ffql_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3281 wr_t wx
, *pwx
= &wx
;
3282 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3283 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3288 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3289 MSA_FLOAT_UNOP(pwx
->w
[i
], from_q16
, Lh(pws
, i
), 32);
3293 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3294 MSA_FLOAT_UNOP(pwx
->d
[i
], from_q32
, Lw(pws
, i
), 64);
3301 msa_move_v(pwd
, pwx
);
3304 void helper_msa_ffqr_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3307 wr_t wx
, *pwx
= &wx
;
3308 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3309 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3314 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3315 MSA_FLOAT_UNOP(pwx
->w
[i
], from_q16
, Rh(pws
, i
), 32);
3319 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3320 MSA_FLOAT_UNOP(pwx
->d
[i
], from_q32
, Rw(pws
, i
), 64);
3327 msa_move_v(pwd
, pwx
);
3330 void helper_msa_ftint_s_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3333 wr_t wx
, *pwx
= &wx
;
3334 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3335 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3338 clear_msacsr_cause(env
);
3342 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3343 MSA_FLOAT_UNOP0(pwx
->w
[i
], to_int32
, pws
->w
[i
], 32);
3347 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3348 MSA_FLOAT_UNOP0(pwx
->d
[i
], to_int64
, pws
->d
[i
], 64);
3355 check_msacsr_cause(env
, GETPC());
3357 msa_move_v(pwd
, pwx
);
3360 void helper_msa_ftint_u_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3363 wr_t wx
, *pwx
= &wx
;
3364 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3365 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3368 clear_msacsr_cause(env
);
3372 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3373 MSA_FLOAT_UNOP0(pwx
->w
[i
], to_uint32
, pws
->w
[i
], 32);
3377 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3378 MSA_FLOAT_UNOP0(pwx
->d
[i
], to_uint64
, pws
->d
[i
], 64);
3385 check_msacsr_cause(env
, GETPC());
3387 msa_move_v(pwd
, pwx
);
3390 #define float32_from_int32 int32_to_float32
3391 #define float32_from_uint32 uint32_to_float32
3393 #define float64_from_int64 int64_to_float64
3394 #define float64_from_uint64 uint64_to_float64
3396 void helper_msa_ffint_s_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3399 wr_t wx
, *pwx
= &wx
;
3400 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3401 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3404 clear_msacsr_cause(env
);
3408 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3409 MSA_FLOAT_UNOP(pwx
->w
[i
], from_int32
, pws
->w
[i
], 32);
3413 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3414 MSA_FLOAT_UNOP(pwx
->d
[i
], from_int64
, pws
->d
[i
], 64);
3421 check_msacsr_cause(env
, GETPC());
3423 msa_move_v(pwd
, pwx
);
3426 void helper_msa_ffint_u_df(CPUMIPSState
*env
, uint32_t df
, uint32_t wd
,
3429 wr_t wx
, *pwx
= &wx
;
3430 wr_t
*pwd
= &(env
->active_fpu
.fpr
[wd
].wr
);
3431 wr_t
*pws
= &(env
->active_fpu
.fpr
[ws
].wr
);
3434 clear_msacsr_cause(env
);
3438 for (i
= 0; i
< DF_ELEMENTS(DF_WORD
); i
++) {
3439 MSA_FLOAT_UNOP(pwx
->w
[i
], from_uint32
, pws
->w
[i
], 32);
3443 for (i
= 0; i
< DF_ELEMENTS(DF_DOUBLE
); i
++) {
3444 MSA_FLOAT_UNOP(pwx
->d
[i
], from_uint64
, pws
->d
[i
], 64);
3451 check_msacsr_cause(env
, GETPC());
3453 msa_move_v(pwd
, pwx
);