hw/net/mcf_fec.c

   1 /*
   2  * ColdFire Fast Ethernet Controller emulation.
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  *
   6  * This code is licensed under the GPL
   7  */
   8 #include "qemu/osdep.h"
   9 #include "hw/hw.h"
  10 #include "net/net.h"
  11 #include "hw/m68k/mcf.h"
  12 #include "hw/m68k/mcf_fec.h"
  13 #include "hw/net/mii.h"
  14 #include "hw/sysbus.h"
  15 /* For crc32 */
  16 #include <zlib.h>
  17 #include "exec/address-spaces.h"
  18
  19 //#define DEBUG_FEC 1
  20
  21 #ifdef DEBUG_FEC
  22 #define DPRINTF(fmt, ...) \
  23 do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
  24 #else
  25 #define DPRINTF(fmt, ...) do {} while(0)
  26 #endif
  27
  28 #define FEC_MAX_DESC 1024
  29 #define FEC_MAX_FRAME_SIZE 2032
  30
  31 typedef struct {
  32     SysBusDevice parent_obj;
  33
  34     MemoryRegion iomem;
  35     qemu_irq irq[FEC_NUM_IRQ];
  36     NICState *nic;
  37     NICConf conf;
  38     uint32_t irq_state;
  39     uint32_t eir;
  40     uint32_t eimr;
  41     int rx_enabled;
  42     uint32_t rx_descriptor;
  43     uint32_t tx_descriptor;
  44     uint32_t ecr;
  45     uint32_t mmfr;
  46     uint32_t mscr;
  47     uint32_t rcr;
  48     uint32_t tcr;
  49     uint32_t tfwr;
  50     uint32_t rfsr;
  51     uint32_t erdsr;
  52     uint32_t etdsr;
  53     uint32_t emrbr;
  54 } mcf_fec_state;
  55
  56 #define FEC_INT_HB   0x80000000
  57 #define FEC_INT_BABR 0x40000000
  58 #define FEC_INT_BABT 0x20000000
  59 #define FEC_INT_GRA  0x10000000
  60 #define FEC_INT_TXF  0x08000000
  61 #define FEC_INT_TXB  0x04000000
  62 #define FEC_INT_RXF  0x02000000
  63 #define FEC_INT_RXB  0x01000000
  64 #define FEC_INT_MII  0x00800000
  65 #define FEC_INT_EB   0x00400000
  66 #define FEC_INT_LC   0x00200000
  67 #define FEC_INT_RL   0x00100000
  68 #define FEC_INT_UN   0x00080000
  69
  70 #define FEC_EN      2
  71 #define FEC_RESET   1
  72
  73 /* Map interrupt flags onto IRQ lines.  */
  74 static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = {
  75     FEC_INT_TXF,
  76     FEC_INT_TXB,
  77     FEC_INT_UN,
  78     FEC_INT_RL,
  79     FEC_INT_RXF,
  80     FEC_INT_RXB,
  81     FEC_INT_MII,
  82     FEC_INT_LC,
  83     FEC_INT_HB,
  84     FEC_INT_GRA,
  85     FEC_INT_EB,
  86     FEC_INT_BABT,
  87     FEC_INT_BABR
  88 };
  89
  90 /* Buffer Descriptor.  */
  91 typedef struct {
  92     uint16_t flags;
  93     uint16_t length;
  94     uint32_t data;
  95 } mcf_fec_bd;
  96
  97 #define FEC_BD_R    0x8000
  98 #define FEC_BD_E    0x8000
  99 #define FEC_BD_O1   0x4000
 100 #define FEC_BD_W    0x2000
 101 #define FEC_BD_O2   0x1000
 102 #define FEC_BD_L    0x0800
 103 #define FEC_BD_TC   0x0400
 104 #define FEC_BD_ABC  0x0200
 105 #define FEC_BD_M    0x0100
 106 #define FEC_BD_BC   0x0080
 107 #define FEC_BD_MC   0x0040
 108 #define FEC_BD_LG   0x0020
 109 #define FEC_BD_NO   0x0010
 110 #define FEC_BD_CR   0x0004
 111 #define FEC_BD_OV   0x0002
 112 #define FEC_BD_TR   0x0001
 113
 114 static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr)
 115 {
 116     cpu_physical_memory_read(addr, bd, sizeof(*bd));
 117     be16_to_cpus(&bd->flags);
 118     be16_to_cpus(&bd->length);
 119     be32_to_cpus(&bd->data);
 120 }
 121
 122 static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr)
 123 {
 124     mcf_fec_bd tmp;
 125     tmp.flags = cpu_to_be16(bd->flags);
 126     tmp.length = cpu_to_be16(bd->length);
 127     tmp.data = cpu_to_be32(bd->data);
 128     cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
 129 }
 130
 131 static void mcf_fec_update(mcf_fec_state *s)
 132 {
 133     uint32_t active;
 134     uint32_t changed;
 135     uint32_t mask;
 136     int i;
 137
 138     active = s->eir & s->eimr;
 139     changed = active ^s->irq_state;
 140     for (i = 0; i < FEC_NUM_IRQ; i++) {
 141         mask = mcf_fec_irq_map[i];
 142         if (changed & mask) {
 143             DPRINTF("IRQ %d = %d\n", i, (active & mask) != 0);
 144             qemu_set_irq(s->irq[i], (active & mask) != 0);
 145         }
 146     }
 147     s->irq_state = active;
 148 }
 149
 150 static void mcf_fec_do_tx(mcf_fec_state *s)
 151 {
 152     uint32_t addr;
 153     mcf_fec_bd bd;
 154     int frame_size;
 155     int len, descnt = 0;
 156     uint8_t frame[FEC_MAX_FRAME_SIZE];
 157     uint8_t *ptr;
 158
 159     DPRINTF("do_tx\n");
 160     ptr = frame;
 161     frame_size = 0;
 162     addr = s->tx_descriptor;
 163     while (descnt++ < FEC_MAX_DESC) {
 164         mcf_fec_read_bd(&bd, addr);
 165         DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
 166                 addr, bd.flags, bd.length, bd.data);
 167         if ((bd.flags & FEC_BD_R) == 0) {
 168             /* Run out of descriptors to transmit.  */
 169             break;
 170         }
 171         len = bd.length;
 172         if (frame_size + len > FEC_MAX_FRAME_SIZE) {
 173             len = FEC_MAX_FRAME_SIZE - frame_size;
 174             s->eir |= FEC_INT_BABT;
 175         }
 176         cpu_physical_memory_read(bd.data, ptr, len);
 177         ptr += len;
 178         frame_size += len;
 179         if (bd.flags & FEC_BD_L) {
 180             /* Last buffer in frame.  */
 181             DPRINTF("Sending packet\n");
 182             qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);
 183             ptr = frame;
 184             frame_size = 0;
 185             s->eir |= FEC_INT_TXF;
 186         }
 187         s->eir |= FEC_INT_TXB;
 188         bd.flags &= ~FEC_BD_R;
 189         /* Write back the modified descriptor.  */
 190         mcf_fec_write_bd(&bd, addr);
 191         /* Advance to the next descriptor.  */
 192         if ((bd.flags & FEC_BD_W) != 0) {
 193             addr = s->etdsr;
 194         } else {
 195             addr += 8;
 196         }
 197     }
 198     s->tx_descriptor = addr;
 199 }
 200
 201 static void mcf_fec_enable_rx(mcf_fec_state *s)
 202 {
 203     NetClientState *nc = qemu_get_queue(s->nic);
 204     mcf_fec_bd bd;
 205
 206     mcf_fec_read_bd(&bd, s->rx_descriptor);
 207     s->rx_enabled = ((bd.flags & FEC_BD_E) != 0);
 208     if (s->rx_enabled) {
 209         qemu_flush_queued_packets(nc);
 210     }
 211 }
 212
 213 static void mcf_fec_reset(DeviceState *dev)
 214 {
 215     mcf_fec_state *s = MCF_FEC_NET(dev);
 216
 217     s->eir = 0;
 218     s->eimr = 0;
 219     s->rx_enabled = 0;
 220     s->ecr = 0;
 221     s->mscr = 0;
 222     s->rcr = 0x05ee0001;
 223     s->tcr = 0;
 224     s->tfwr = 0;
 225     s->rfsr = 0x500;
 226 }
 227
 228 #define MMFR_WRITE_OP   (1 << 28)
 229 #define MMFR_READ_OP    (2 << 28)
 230 #define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
 231 #define MMFR_REGNUM(v)  (((v) >> 18) & 0x1f)
 232
 233 static uint64_t mcf_fec_read_mdio(mcf_fec_state *s)
 234 {
 235     uint64_t v;
 236
 237     if (s->mmfr & MMFR_WRITE_OP)
 238         return s->mmfr;
 239     if (MMFR_PHYADDR(s->mmfr) != 1)
 240         return s->mmfr |= 0xffff;
 241
 242     switch (MMFR_REGNUM(s->mmfr)) {
 243     case MII_BMCR:
 244         v = MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_FD;
 245         break;
 246     case MII_BMSR:
 247         v = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
 248             MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP |
 249             MII_BMSR_AUTONEG | MII_BMSR_LINK_ST;
 250         break;
 251     case MII_PHYID1:
 252         v = DP83848_PHYID1;
 253         break;
 254     case MII_PHYID2:
 255         v = DP83848_PHYID2;
 256         break;
 257     case MII_ANAR:
 258         v = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD |
 259             MII_ANAR_10 | MII_ANAR_CSMACD;
 260         break;
 261     case MII_ANLPAR:
 262         v = MII_ANLPAR_ACK | MII_ANLPAR_TXFD | MII_ANLPAR_TX |
 263             MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
 264         break;
 265     default:
 266         v = 0xffff;
 267         break;
 268     }
 269     s->mmfr = (s->mmfr & ~0xffff) | v;
 270     return s->mmfr;
 271 }
 272
 273 static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
 274                              unsigned size)
 275 {
 276     mcf_fec_state *s = (mcf_fec_state *)opaque;
 277     switch (addr & 0x3ff) {
 278     case 0x004: return s->eir;
 279     case 0x008: return s->eimr;
 280     case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
 281     case 0x014: return 0; /* TDAR */
 282     case 0x024: return s->ecr;
 283     case 0x040: return mcf_fec_read_mdio(s);
 284     case 0x044: return s->mscr;
 285     case 0x064: return 0; /* MIBC */
 286     case 0x084: return s->rcr;
 287     case 0x0c4: return s->tcr;
 288     case 0x0e4: /* PALR */
 289         return (s->conf.macaddr.a[0] << 24) | (s->conf.macaddr.a[1] << 16)
 290               | (s->conf.macaddr.a[2] << 8) | s->conf.macaddr.a[3];
 291         break;
 292     case 0x0e8: /* PAUR */
 293         return (s->conf.macaddr.a[4] << 24) | (s->conf.macaddr.a[5] << 16) | 0x8808;
 294     case 0x0ec: return 0x10000; /* OPD */
 295     case 0x118: return 0;
 296     case 0x11c: return 0;
 297     case 0x120: return 0;
 298     case 0x124: return 0;
 299     case 0x144: return s->tfwr;
 300     case 0x14c: return 0x600;
 301     case 0x150: return s->rfsr;
 302     case 0x180: return s->erdsr;
 303     case 0x184: return s->etdsr;
 304     case 0x188: return s->emrbr;
 305     default:
 306         hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
 307         return 0;
 308     }
 309 }
 310
 311 static void mcf_fec_write(void *opaque, hwaddr addr,
 312                           uint64_t value, unsigned size)
 313 {
 314     mcf_fec_state *s = (mcf_fec_state *)opaque;
 315     switch (addr & 0x3ff) {
 316     case 0x004:
 317         s->eir &= ~value;
 318         break;
 319     case 0x008:
 320         s->eimr = value;
 321         break;
 322     case 0x010: /* RDAR */
 323         if ((s->ecr & FEC_EN) && !s->rx_enabled) {
 324             DPRINTF("RX enable\n");
 325             mcf_fec_enable_rx(s);
 326         }
 327         break;
 328     case 0x014: /* TDAR */
 329         if (s->ecr & FEC_EN) {
 330             mcf_fec_do_tx(s);
 331         }
 332         break;
 333     case 0x024:
 334         s->ecr = value;
 335         if (value & FEC_RESET) {
 336             DPRINTF("Reset\n");
 337             mcf_fec_reset(opaque);
 338         }
 339         if ((s->ecr & FEC_EN) == 0) {
 340             s->rx_enabled = 0;
 341         }
 342         break;
 343     case 0x040:
 344         s->mmfr = value;
 345         s->eir |= FEC_INT_MII;
 346         break;
 347     case 0x044:
 348         s->mscr = value & 0xfe;
 349         break;
 350     case 0x064:
 351         /* TODO: Implement MIB.  */
 352         break;
 353     case 0x084:
 354         s->rcr = value & 0x07ff003f;
 355         /* TODO: Implement LOOP mode.  */
 356         break;
 357     case 0x0c4: /* TCR */
 358         /* We transmit immediately, so raise GRA immediately.  */
 359         s->tcr = value;
 360         if (value & 1)
 361             s->eir |= FEC_INT_GRA;
 362         break;
 363     case 0x0e4: /* PALR */
 364         s->conf.macaddr.a[0] = value >> 24;
 365         s->conf.macaddr.a[1] = value >> 16;
 366         s->conf.macaddr.a[2] = value >> 8;
 367         s->conf.macaddr.a[3] = value;
 368         break;
 369     case 0x0e8: /* PAUR */
 370         s->conf.macaddr.a[4] = value >> 24;
 371         s->conf.macaddr.a[5] = value >> 16;
 372         break;
 373     case 0x0ec:
 374         /* OPD */
 375         break;
 376     case 0x118:
 377     case 0x11c:
 378     case 0x120:
 379     case 0x124:
 380         /* TODO: implement MAC hash filtering.  */
 381         break;
 382     case 0x144:
 383         s->tfwr = value & 3;
 384         break;
 385     case 0x14c:
 386         /* FRBR writes ignored.  */
 387         break;
 388     case 0x150:
 389         s->rfsr = (value & 0x3fc) | 0x400;
 390         break;
 391     case 0x180:
 392         s->erdsr = value & ~3;
 393         s->rx_descriptor = s->erdsr;
 394         break;
 395     case 0x184:
 396         s->etdsr = value & ~3;
 397         s->tx_descriptor = s->etdsr;
 398         break;
 399     case 0x188:
 400         s->emrbr = value > 0 ? value & 0x7F0 : 0x7F0;
 401         break;
 402     default:
 403         hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
 404     }
 405     mcf_fec_update(s);
 406 }
 407
 408 static int mcf_fec_have_receive_space(mcf_fec_state *s, size_t want)
 409 {
 410     mcf_fec_bd bd;
 411     uint32_t addr;
 412
 413     /* Walk descriptor list to determine if we have enough buffer */
 414     addr = s->rx_descriptor;
 415     while (want > 0) {
 416         mcf_fec_read_bd(&bd, addr);
 417         if ((bd.flags & FEC_BD_E) == 0) {
 418             return 0;
 419         }
 420         if (want < s->emrbr) {
 421             return 1;
 422         }
 423         want -= s->emrbr;
 424         /* Advance to the next descriptor.  */
 425         if ((bd.flags & FEC_BD_W) != 0) {
 426             addr = s->erdsr;
 427         } else {
 428             addr += 8;
 429         }
 430     }
 431     return 0;
 432 }
 433
 434 static ssize_t mcf_fec_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 435 {
 436     mcf_fec_state *s = qemu_get_nic_opaque(nc);
 437     mcf_fec_bd bd;
 438     uint32_t flags = 0;
 439     uint32_t addr;
 440     uint32_t crc;
 441     uint32_t buf_addr;
 442     uint8_t *crc_ptr;
 443     unsigned int buf_len;
 444     size_t retsize;
 445
 446     DPRINTF("do_rx len %d\n", size);
 447     if (!s->rx_enabled) {
 448         return -1;
 449     }
 450     /* 4 bytes for the CRC.  */
 451     size += 4;
 452     crc = cpu_to_be32(crc32(~0, buf, size));
 453     crc_ptr = (uint8_t *)&crc;
 454     /* Huge frames are truncted.  */
 455     if (size > FEC_MAX_FRAME_SIZE) {
 456         size = FEC_MAX_FRAME_SIZE;
 457         flags |= FEC_BD_TR | FEC_BD_LG;
 458     }
 459     /* Frames larger than the user limit just set error flags.  */
 460     if (size > (s->rcr >> 16)) {
 461         flags |= FEC_BD_LG;
 462     }
 463     /* Check if we have enough space in current descriptors */
 464     if (!mcf_fec_have_receive_space(s, size)) {
 465         return 0;
 466     }
 467     addr = s->rx_descriptor;
 468     retsize = size;
 469     while (size > 0) {
 470         mcf_fec_read_bd(&bd, addr);
 471         buf_len = (size <= s->emrbr) ? size: s->emrbr;
 472         bd.length = buf_len;
 473         size -= buf_len;
 474         DPRINTF("rx_bd %x length %d\n", addr, bd.length);
 475         /* The last 4 bytes are the CRC.  */
 476         if (size < 4)
 477             buf_len += size - 4;
 478         buf_addr = bd.data;
 479         cpu_physical_memory_write(buf_addr, buf, buf_len);
 480         buf += buf_len;
 481         if (size < 4) {
 482             cpu_physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size);
 483             crc_ptr += 4 - size;
 484         }
 485         bd.flags &= ~FEC_BD_E;
 486         if (size == 0) {
 487             /* Last buffer in frame.  */
 488             bd.flags |= flags | FEC_BD_L;
 489             DPRINTF("rx frame flags %04x\n", bd.flags);
 490             s->eir |= FEC_INT_RXF;
 491         } else {
 492             s->eir |= FEC_INT_RXB;
 493         }
 494         mcf_fec_write_bd(&bd, addr);
 495         /* Advance to the next descriptor.  */
 496         if ((bd.flags & FEC_BD_W) != 0) {
 497             addr = s->erdsr;
 498         } else {
 499             addr += 8;
 500         }
 501     }
 502     s->rx_descriptor = addr;
 503     mcf_fec_enable_rx(s);
 504     mcf_fec_update(s);
 505     return retsize;
 506 }
 507
 508 static const MemoryRegionOps mcf_fec_ops = {
 509     .read = mcf_fec_read,
 510     .write = mcf_fec_write,
 511     .endianness = DEVICE_NATIVE_ENDIAN,
 512 };
 513
 514 static NetClientInfo net_mcf_fec_info = {
 515     .type = NET_CLIENT_DRIVER_NIC,
 516     .size = sizeof(NICState),
 517     .receive = mcf_fec_receive,
 518 };
 519
 520 static void mcf_fec_realize(DeviceState *dev, Error **errp)
 521 {
 522     mcf_fec_state *s = MCF_FEC_NET(dev);
 523
 524     s->nic = qemu_new_nic(&net_mcf_fec_info, &s->conf,
 525                           object_get_typename(OBJECT(dev)), dev->id, s);
 526     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 527 }
 528
 529 static void mcf_fec_instance_init(Object *obj)
 530 {
 531     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 532     mcf_fec_state *s = MCF_FEC_NET(obj);
 533     int i;
 534
 535     memory_region_init_io(&s->iomem, obj, &mcf_fec_ops, s, "fec", 0x400);
 536     sysbus_init_mmio(sbd, &s->iomem);
 537     for (i = 0; i < FEC_NUM_IRQ; i++) {
 538         sysbus_init_irq(sbd, &s->irq[i]);
 539     }
 540 }
 541
 542 static Property mcf_fec_properties[] = {
 543     DEFINE_NIC_PROPERTIES(mcf_fec_state, conf),
 544     DEFINE_PROP_END_OF_LIST(),
 545 };
 546
 547 static void mcf_fec_class_init(ObjectClass *oc, void *data)
 548 {
 549     DeviceClass *dc = DEVICE_CLASS(oc);
 550
 551     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 552     dc->realize = mcf_fec_realize;
 553     dc->desc = "MCF Fast Ethernet Controller network device";
 554     dc->reset = mcf_fec_reset;
 555     dc->props = mcf_fec_properties;
 556 }
 557
 558 static const TypeInfo mcf_fec_info = {
 559     .name          = TYPE_MCF_FEC_NET,
 560     .parent        = TYPE_SYS_BUS_DEVICE,
 561     .instance_size = sizeof(mcf_fec_state),
 562     .instance_init = mcf_fec_instance_init,
 563     .class_init    = mcf_fec_class_init,
 564 };
 565
 566 static void mcf_fec_register_types(void)
 567 {
 568     type_register_static(&mcf_fec_info);
 569 }
 570
 571 type_init(mcf_fec_register_types)