hw/intc/gicv3_internal.h

   1 /*
   2  * ARM GICv3 support - internal interfaces
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Copyright (c) 2015 Huawei.
   6  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   7  * Written by Peter Maydell
   8  * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation, either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #ifndef QEMU_ARM_GICV3_INTERNAL_H
  25 #define QEMU_ARM_GICV3_INTERNAL_H
  26
  27 #include "hw/intc/arm_gicv3_common.h"
  28
  29 /* Distributor registers, as offsets from the distributor base address */
  30 #define GICD_CTLR            0x0000
  31 #define GICD_TYPER           0x0004
  32 #define GICD_IIDR            0x0008
  33 #define GICD_STATUSR         0x0010
  34 #define GICD_SETSPI_NSR      0x0040
  35 #define GICD_CLRSPI_NSR      0x0048
  36 #define GICD_SETSPI_SR       0x0050
  37 #define GICD_CLRSPI_SR       0x0058
  38 #define GICD_SEIR            0x0068
  39 #define GICD_IGROUPR         0x0080
  40 #define GICD_ISENABLER       0x0100
  41 #define GICD_ICENABLER       0x0180
  42 #define GICD_ISPENDR         0x0200
  43 #define GICD_ICPENDR         0x0280
  44 #define GICD_ISACTIVER       0x0300
  45 #define GICD_ICACTIVER       0x0380
  46 #define GICD_IPRIORITYR      0x0400
  47 #define GICD_ITARGETSR       0x0800
  48 #define GICD_ICFGR           0x0C00
  49 #define GICD_IGRPMODR        0x0D00
  50 #define GICD_NSACR           0x0E00
  51 #define GICD_SGIR            0x0F00
  52 #define GICD_CPENDSGIR       0x0F10
  53 #define GICD_SPENDSGIR       0x0F20
  54 #define GICD_IROUTER         0x6000
  55 #define GICD_IDREGS          0xFFD0
  56
  57 /* GICD_CTLR fields  */
  58 #define GICD_CTLR_EN_GRP0           (1U << 0)
  59 #define GICD_CTLR_EN_GRP1NS         (1U << 1) /* GICv3 5.3.20 */
  60 #define GICD_CTLR_EN_GRP1S          (1U << 2)
  61 #define GICD_CTLR_EN_GRP1_ALL       (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S)
  62 /* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */
  63 #define GICD_CTLR_ARE               (1U << 4)
  64 #define GICD_CTLR_ARE_S             (1U << 4)
  65 #define GICD_CTLR_ARE_NS            (1U << 5)
  66 #define GICD_CTLR_DS                (1U << 6)
  67 #define GICD_CTLR_E1NWF             (1U << 7)
  68 #define GICD_CTLR_RWP               (1U << 31)
  69
  70 /*
  71  * Redistributor frame offsets from RD_base
  72  */
  73 #define GICR_SGI_OFFSET 0x10000
  74
  75 /*
  76  * Redistributor registers, offsets from RD_base
  77  */
  78 #define GICR_CTLR             0x0000
  79 #define GICR_IIDR             0x0004
  80 #define GICR_TYPER            0x0008
  81 #define GICR_STATUSR          0x0010
  82 #define GICR_WAKER            0x0014
  83 #define GICR_SETLPIR          0x0040
  84 #define GICR_CLRLPIR          0x0048
  85 #define GICR_PROPBASER        0x0070
  86 #define GICR_PENDBASER        0x0078
  87 #define GICR_INVLPIR          0x00A0
  88 #define GICR_INVALLR          0x00B0
  89 #define GICR_SYNCR            0x00C0
  90 #define GICR_IDREGS           0xFFD0
  91
  92 /* SGI and PPI Redistributor registers, offsets from RD_base */
  93 #define GICR_IGROUPR0         (GICR_SGI_OFFSET + 0x0080)
  94 #define GICR_ISENABLER0       (GICR_SGI_OFFSET + 0x0100)
  95 #define GICR_ICENABLER0       (GICR_SGI_OFFSET + 0x0180)
  96 #define GICR_ISPENDR0         (GICR_SGI_OFFSET + 0x0200)
  97 #define GICR_ICPENDR0         (GICR_SGI_OFFSET + 0x0280)
  98 #define GICR_ISACTIVER0       (GICR_SGI_OFFSET + 0x0300)
  99 #define GICR_ICACTIVER0       (GICR_SGI_OFFSET + 0x0380)
 100 #define GICR_IPRIORITYR       (GICR_SGI_OFFSET + 0x0400)
 101 #define GICR_ICFGR0           (GICR_SGI_OFFSET + 0x0C00)
 102 #define GICR_ICFGR1           (GICR_SGI_OFFSET + 0x0C04)
 103 #define GICR_IGRPMODR0        (GICR_SGI_OFFSET + 0x0D00)
 104 #define GICR_NSACR            (GICR_SGI_OFFSET + 0x0E00)
 105
 106 #define GICR_CTLR_ENABLE_LPIS        (1U << 0)
 107 #define GICR_CTLR_RWP                (1U << 3)
 108 #define GICR_CTLR_DPG0               (1U << 24)
 109 #define GICR_CTLR_DPG1NS             (1U << 25)
 110 #define GICR_CTLR_DPG1S              (1U << 26)
 111 #define GICR_CTLR_UWP                (1U << 31)
 112
 113 #define GICR_TYPER_PLPIS             (1U << 0)
 114 #define GICR_TYPER_VLPIS             (1U << 1)
 115 #define GICR_TYPER_DIRECTLPI         (1U << 3)
 116 #define GICR_TYPER_LAST              (1U << 4)
 117 #define GICR_TYPER_DPGS              (1U << 5)
 118 #define GICR_TYPER_PROCNUM           (0xFFFFU << 8)
 119 #define GICR_TYPER_COMMONLPIAFF      (0x3 << 24)
 120 #define GICR_TYPER_AFFINITYVALUE     (0xFFFFFFFFULL << 32)
 121
 122 #define GICR_WAKER_ProcessorSleep    (1U << 1)
 123 #define GICR_WAKER_ChildrenAsleep    (1U << 2)
 124
 125 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
 126 #define GICR_PROPBASER_ADDR_MASK               (0xfffffffffULL << 12)
 127 #define GICR_PROPBASER_SHAREABILITY_MASK       (3U << 10)
 128 #define GICR_PROPBASER_CACHEABILITY_MASK       (7U << 7)
 129 #define GICR_PROPBASER_IDBITS_MASK             (0x1f)
 130
 131 #define GICR_PENDBASER_PTZ                     (1ULL << 62)
 132 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
 133 #define GICR_PENDBASER_ADDR_MASK               (0xffffffffULL << 16)
 134 #define GICR_PENDBASER_SHAREABILITY_MASK       (3U << 10)
 135 #define GICR_PENDBASER_CACHEABILITY_MASK       (7U << 7)
 136
 137 #define ICC_CTLR_EL1_CBPR           (1U << 0)
 138 #define ICC_CTLR_EL1_EOIMODE        (1U << 1)
 139 #define ICC_CTLR_EL1_PMHE           (1U << 6)
 140 #define ICC_CTLR_EL1_PRIBITS_SHIFT 8
 141 #define ICC_CTLR_EL1_IDBITS_SHIFT 11
 142 #define ICC_CTLR_EL1_SEIS           (1U << 14)
 143 #define ICC_CTLR_EL1_A3V            (1U << 15)
 144
 145 #define ICC_PMR_PRIORITY_MASK    0xff
 146 #define ICC_BPR_BINARYPOINT_MASK 0x07
 147 #define ICC_IGRPEN_ENABLE        0x01
 148
 149 #define ICC_CTLR_EL3_CBPR_EL1S (1U << 0)
 150 #define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1)
 151 #define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2)
 152 #define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3)
 153 #define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4)
 154 #define ICC_CTLR_EL3_RM (1U << 5)
 155 #define ICC_CTLR_EL3_PMHE (1U << 6)
 156 #define ICC_CTLR_EL3_PRIBITS_SHIFT 8
 157 #define ICC_CTLR_EL3_IDBITS_SHIFT 11
 158 #define ICC_CTLR_EL3_SEIS (1U << 14)
 159 #define ICC_CTLR_EL3_A3V (1U << 15)
 160 #define ICC_CTLR_EL3_NDS (1U << 17)
 161
 162 #define ICH_VMCR_EL2_VENG0_SHIFT 0
 163 #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT)
 164 #define ICH_VMCR_EL2_VENG1_SHIFT 1
 165 #define ICH_VMCR_EL2_VENG1 (1U << ICH_VMCR_EL2_VENG1_SHIFT)
 166 #define ICH_VMCR_EL2_VACKCTL (1U << 2)
 167 #define ICH_VMCR_EL2_VFIQEN (1U << 3)
 168 #define ICH_VMCR_EL2_VCBPR_SHIFT 4
 169 #define ICH_VMCR_EL2_VCBPR (1U << ICH_VMCR_EL2_VCBPR_SHIFT)
 170 #define ICH_VMCR_EL2_VEOIM_SHIFT 9
 171 #define ICH_VMCR_EL2_VEOIM (1U << ICH_VMCR_EL2_VEOIM_SHIFT)
 172 #define ICH_VMCR_EL2_VBPR1_SHIFT 18
 173 #define ICH_VMCR_EL2_VBPR1_LENGTH 3
 174 #define ICH_VMCR_EL2_VBPR1_MASK (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT)
 175 #define ICH_VMCR_EL2_VBPR0_SHIFT 21
 176 #define ICH_VMCR_EL2_VBPR0_LENGTH 3
 177 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
 178 #define ICH_VMCR_EL2_VPMR_SHIFT 24
 179 #define ICH_VMCR_EL2_VPMR_LENGTH 8
 180 #define ICH_VMCR_EL2_VPMR_MASK (0xffU << ICH_VMCR_EL2_VPMR_SHIFT)
 181
 182 #define ICH_HCR_EL2_EN (1U << 0)
 183 #define ICH_HCR_EL2_UIE (1U << 1)
 184 #define ICH_HCR_EL2_LRENPIE (1U << 2)
 185 #define ICH_HCR_EL2_NPIE (1U << 3)
 186 #define ICH_HCR_EL2_VGRP0EIE (1U << 4)
 187 #define ICH_HCR_EL2_VGRP0DIE (1U << 5)
 188 #define ICH_HCR_EL2_VGRP1EIE (1U << 6)
 189 #define ICH_HCR_EL2_VGRP1DIE (1U << 7)
 190 #define ICH_HCR_EL2_TC (1U << 10)
 191 #define ICH_HCR_EL2_TALL0 (1U << 11)
 192 #define ICH_HCR_EL2_TALL1 (1U << 12)
 193 #define ICH_HCR_EL2_TSEI (1U << 13)
 194 #define ICH_HCR_EL2_TDIR (1U << 14)
 195 #define ICH_HCR_EL2_EOICOUNT_SHIFT 27
 196 #define ICH_HCR_EL2_EOICOUNT_LENGTH 5
 197 #define ICH_HCR_EL2_EOICOUNT_MASK (0x1fU << ICH_HCR_EL2_EOICOUNT_SHIFT)
 198
 199 #define ICH_LR_EL2_VINTID_SHIFT 0
 200 #define ICH_LR_EL2_VINTID_LENGTH 32
 201 #define ICH_LR_EL2_VINTID_MASK (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT)
 202 #define ICH_LR_EL2_PINTID_SHIFT 32
 203 #define ICH_LR_EL2_PINTID_LENGTH 10
 204 #define ICH_LR_EL2_PINTID_MASK (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT)
 205 /* Note that EOI shares with the top bit of the pINTID field */
 206 #define ICH_LR_EL2_EOI (1ULL << 41)
 207 #define ICH_LR_EL2_PRIORITY_SHIFT 48
 208 #define ICH_LR_EL2_PRIORITY_LENGTH 8
 209 #define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT)
 210 #define ICH_LR_EL2_GROUP (1ULL << 60)
 211 #define ICH_LR_EL2_HW (1ULL << 61)
 212 #define ICH_LR_EL2_STATE_SHIFT 62
 213 #define ICH_LR_EL2_STATE_LENGTH 2
 214 #define ICH_LR_EL2_STATE_MASK (3ULL << ICH_LR_EL2_STATE_SHIFT)
 215 /* values for the state field: */
 216 #define ICH_LR_EL2_STATE_INVALID 0
 217 #define ICH_LR_EL2_STATE_PENDING 1
 218 #define ICH_LR_EL2_STATE_ACTIVE 2
 219 #define ICH_LR_EL2_STATE_ACTIVE_PENDING 3
 220 #define ICH_LR_EL2_STATE_PENDING_BIT (1ULL << ICH_LR_EL2_STATE_SHIFT)
 221 #define ICH_LR_EL2_STATE_ACTIVE_BIT (2ULL << ICH_LR_EL2_STATE_SHIFT)
 222
 223 #define ICH_MISR_EL2_EOI (1U << 0)
 224 #define ICH_MISR_EL2_U (1U << 1)
 225 #define ICH_MISR_EL2_LRENP (1U << 2)
 226 #define ICH_MISR_EL2_NP (1U << 3)
 227 #define ICH_MISR_EL2_VGRP0E (1U << 4)
 228 #define ICH_MISR_EL2_VGRP0D (1U << 5)
 229 #define ICH_MISR_EL2_VGRP1E (1U << 6)
 230 #define ICH_MISR_EL2_VGRP1D (1U << 7)
 231
 232 #define ICH_VTR_EL2_LISTREGS_SHIFT 0
 233 #define ICH_VTR_EL2_TDS (1U << 19)
 234 #define ICH_VTR_EL2_NV4 (1U << 20)
 235 #define ICH_VTR_EL2_A3V (1U << 21)
 236 #define ICH_VTR_EL2_SEIS (1U << 22)
 237 #define ICH_VTR_EL2_IDBITS_SHIFT 23
 238 #define ICH_VTR_EL2_PREBITS_SHIFT 26
 239 #define ICH_VTR_EL2_PRIBITS_SHIFT 29
 240
 241 /* Special interrupt IDs */
 242 #define INTID_SECURE 1020
 243 #define INTID_NONSECURE 1021
 244 #define INTID_SPURIOUS 1023
 245
 246 /* Functions internal to the emulated GICv3 */
 247
 248 /**
 249  * gicv3_redist_update:
 250  * @cs: GICv3CPUState for this redistributor
 251  *
 252  * Recalculate the highest priority pending interrupt after a
 253  * change to redistributor state, and inform the CPU accordingly.
 254  */
 255 void gicv3_redist_update(GICv3CPUState *cs);
 256
 257 /**
 258  * gicv3_update:
 259  * @s: GICv3State
 260  * @start: first interrupt whose state changed
 261  * @len: length of the range of interrupts whose state changed
 262  *
 263  * Recalculate the highest priority pending interrupts after a
 264  * change to the distributor state affecting @len interrupts
 265  * starting at @start, and inform the CPUs accordingly.
 266  */
 267 void gicv3_update(GICv3State *s, int start, int len);
 268
 269 /**
 270  * gicv3_full_update_noirqset:
 271  * @s: GICv3State
 272  *
 273  * Recalculate the cached information about highest priority
 274  * pending interrupts, but don't inform the CPUs. This should be
 275  * called after an incoming migration has loaded new state.
 276  */
 277 void gicv3_full_update_noirqset(GICv3State *s);
 278
 279 /**
 280  * gicv3_full_update:
 281  * @s: GICv3State
 282  *
 283  * Recalculate the highest priority pending interrupts after
 284  * a change that could affect the status of all interrupts,
 285  * and inform the CPUs accordingly.
 286  */
 287 void gicv3_full_update(GICv3State *s);
 288 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
 289                             unsigned size, MemTxAttrs attrs);
 290 MemTxResult gicv3_dist_write(void *opaque, hwaddr addr, uint64_t data,
 291                              unsigned size, MemTxAttrs attrs);
 292 MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
 293                               unsigned size, MemTxAttrs attrs);
 294 MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
 295                                unsigned size, MemTxAttrs attrs);
 296 void gicv3_dist_set_irq(GICv3State *s, int irq, int level);
 297 void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level);
 298 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);
 299 void gicv3_init_cpuif(GICv3State *s);
 300
 301 /**
 302  * gicv3_cpuif_update:
 303  * @cs: GICv3CPUState for the CPU to update
 304  *
 305  * Recalculate whether to assert the IRQ or FIQ lines after a change
 306  * to the current highest priority pending interrupt, the CPU's
 307  * current running priority or the CPU's current exception level or
 308  * security state.
 309  */
 310 void gicv3_cpuif_update(GICv3CPUState *cs);
 311
 312 static inline uint32_t gicv3_iidr(void)
 313 {
 314     /* Return the Implementer Identification Register value
 315      * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR.
 316      *
 317      * We claim to be an ARM r0p0 with a zero ProductID.
 318      * This is the same as an r0p0 GIC-500.
 319      */
 320     return 0x43b;
 321 }
 322
 323 static inline uint32_t gicv3_idreg(int regoffset)
 324 {
 325     /* Return the value of the CoreSight ID register at the specified
 326      * offset from the first ID register (as found in the distributor
 327      * and redistributor register banks).
 328      * These values indicate an ARM implementation of a GICv3.
 329      */
 330     static const uint8_t gicd_ids[] = {
 331         0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1
 332     };
 333     return gicd_ids[regoffset / 4];
 334 }
 335
 336 /**
 337  * gicv3_irq_group:
 338  *
 339  * Return the group which this interrupt is configured as (GICV3_G0,
 340  * GICV3_G1 or GICV3_G1NS).
 341  */
 342 static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq)
 343 {
 344     bool grpbit, grpmodbit;
 345
 346     if (irq < GIC_INTERNAL) {
 347         grpbit = extract32(cs->gicr_igroupr0, irq, 1);
 348         grpmodbit = extract32(cs->gicr_igrpmodr0, irq, 1);
 349     } else {
 350         grpbit = gicv3_gicd_group_test(s, irq);
 351         grpmodbit = gicv3_gicd_grpmod_test(s, irq);
 352     }
 353     if (grpbit) {
 354         return GICV3_G1NS;
 355     }
 356     if (s->gicd_ctlr & GICD_CTLR_DS) {
 357         return GICV3_G0;
 358     }
 359     return grpmodbit ? GICV3_G1 : GICV3_G0;
 360 }
 361
 362 /**
 363  * gicv3_redist_affid:
 364  *
 365  * Return the 32-bit affinity ID of the CPU connected to this redistributor
 366  */
 367 static inline uint32_t gicv3_redist_affid(GICv3CPUState *cs)
 368 {
 369     return cs->gicr_typer >> 32;
 370 }
 371
 372 /**
 373  * gicv3_cache_target_cpustate:
 374  *
 375  * Update the cached CPU state corresponding to the target for this interrupt
 376  * (which is kept in s->gicd_irouter_target[]).
 377  */
 378 static inline void gicv3_cache_target_cpustate(GICv3State *s, int irq)
 379 {
 380     GICv3CPUState *cs = NULL;
 381     int i;
 382     uint32_t tgtaff = extract64(s->gicd_irouter[irq], 0, 24) |
 383         extract64(s->gicd_irouter[irq], 32, 8) << 24;
 384
 385     for (i = 0; i < s->num_cpu; i++) {
 386         if (s->cpu[i].gicr_typer >> 32 == tgtaff) {
 387             cs = &s->cpu[i];
 388             break;
 389         }
 390     }
 391
 392     s->gicd_irouter_target[irq] = cs;
 393 }
 394
 395 /**
 396  * gicv3_cache_all_target_cpustates:
 397  *
 398  * Populate the entire cache of CPU state pointers for interrupt targets
 399  * (eg after inbound migration or CPU reset)
 400  */
 401 static inline void gicv3_cache_all_target_cpustates(GICv3State *s)
 402 {
 403     int irq;
 404
 405     for (irq = GIC_INTERNAL; irq < GICV3_MAXIRQ; irq++) {
 406         gicv3_cache_target_cpustate(s, irq);
 407     }
 408 }
 409
 410 #endif /* QEMU_ARM_GICV3_INTERNAL_H */