hw/arm/stm32f205_soc.c

   1 /*
   2  * STM32F205 SoC
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "hw/arm/arm.h"
  29 #include "exec/address-spaces.h"
  30 #include "hw/arm/stm32f205_soc.h"
  31
  32 /* At the moment only Timer 2 to 5 are modelled */
  33 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
  34     0x40000800, 0x40000C00 };
  35 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
  36     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
  37 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
  38     0x40012200 };
  39 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
  40     0x40003C00 };
  41
  42 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
  43 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
  44 #define ADC_IRQ 18
  45 static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
  46
  47 static void stm32f205_soc_initfn(Object *obj)
  48 {
  49     STM32F205State *s = STM32F205_SOC(obj);
  50     int i;
  51
  52     object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
  53     qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
  54
  55     for (i = 0; i < STM_NUM_USARTS; i++) {
  56         object_initialize(&s->usart[i], sizeof(s->usart[i]),
  57                           TYPE_STM32F2XX_USART);
  58         qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
  59     }
  60
  61     for (i = 0; i < STM_NUM_TIMERS; i++) {
  62         object_initialize(&s->timer[i], sizeof(s->timer[i]),
  63                           TYPE_STM32F2XX_TIMER);
  64         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
  65     }
  66
  67     s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
  68
  69     for (i = 0; i < STM_NUM_ADCS; i++) {
  70         object_initialize(&s->adc[i], sizeof(s->adc[i]),
  71                           TYPE_STM32F2XX_ADC);
  72         qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
  73     }
  74
  75     for (i = 0; i < STM_NUM_SPIS; i++) {
  76         object_initialize(&s->spi[i], sizeof(s->spi[i]),
  77                           TYPE_STM32F2XX_SPI);
  78         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
  79     }
  80 }
  81
  82 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
  83 {
  84     STM32F205State *s = STM32F205_SOC(dev_soc);
  85     DeviceState *dev, *nvic;
  86     SysBusDevice *busdev;
  87     Error *err = NULL;
  88     int i;
  89
  90     MemoryRegion *system_memory = get_system_memory();
  91     MemoryRegion *sram = g_new(MemoryRegion, 1);
  92     MemoryRegion *flash = g_new(MemoryRegion, 1);
  93     MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
  94
  95     memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
  96                            &error_fatal);
  97     memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
  98                              flash, 0, FLASH_SIZE);
  99
 100     vmstate_register_ram_global(flash);
 101
 102     memory_region_set_readonly(flash, true);
 103     memory_region_set_readonly(flash_alias, true);
 104
 105     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
 106     memory_region_add_subregion(system_memory, 0, flash_alias);
 107
 108     memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
 109                            &error_fatal);
 110     vmstate_register_ram_global(sram);
 111     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 112
 113     nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
 114                        s->kernel_filename, s->cpu_model);
 115
 116     /* System configuration controller */
 117     dev = DEVICE(&s->syscfg);
 118     object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
 119     if (err != NULL) {
 120         error_propagate(errp, err);
 121         return;
 122     }
 123     busdev = SYS_BUS_DEVICE(dev);
 124     sysbus_mmio_map(busdev, 0, 0x40013800);
 125     sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
 126
 127     /* Attach UART (uses USART registers) and USART controllers */
 128     for (i = 0; i < STM_NUM_USARTS; i++) {
 129         dev = DEVICE(&(s->usart[i]));
 130         qdev_prop_set_chr(dev, "chardev",
 131                           i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL);
 132         object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
 133         if (err != NULL) {
 134             error_propagate(errp, err);
 135             return;
 136         }
 137         busdev = SYS_BUS_DEVICE(dev);
 138         sysbus_mmio_map(busdev, 0, usart_addr[i]);
 139         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
 140     }
 141
 142     /* Timer 2 to 5 */
 143     for (i = 0; i < STM_NUM_TIMERS; i++) {
 144         dev = DEVICE(&(s->timer[i]));
 145         qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
 146         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
 147         if (err != NULL) {
 148             error_propagate(errp, err);
 149             return;
 150         }
 151         busdev = SYS_BUS_DEVICE(dev);
 152         sysbus_mmio_map(busdev, 0, timer_addr[i]);
 153         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
 154     }
 155
 156     /* ADC 1 to 3 */
 157     object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
 158                             "num-lines", &err);
 159     object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
 160     if (err != NULL) {
 161         error_propagate(errp, err);
 162         return;
 163     }
 164     qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
 165                           qdev_get_gpio_in(nvic, ADC_IRQ));
 166
 167     for (i = 0; i < STM_NUM_ADCS; i++) {
 168         dev = DEVICE(&(s->adc[i]));
 169         object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
 170         if (err != NULL) {
 171             error_propagate(errp, err);
 172             return;
 173         }
 174         busdev = SYS_BUS_DEVICE(dev);
 175         sysbus_mmio_map(busdev, 0, adc_addr[i]);
 176         sysbus_connect_irq(busdev, 0,
 177                            qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
 178     }
 179
 180     /* SPI 1 and 2 */
 181     for (i = 0; i < STM_NUM_SPIS; i++) {
 182         dev = DEVICE(&(s->spi[i]));
 183         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 184         if (err != NULL) {
 185             error_propagate(errp, err);
 186             return;
 187         }
 188         busdev = SYS_BUS_DEVICE(dev);
 189         sysbus_mmio_map(busdev, 0, spi_addr[i]);
 190         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
 191     }
 192 }
 193
 194 static Property stm32f205_soc_properties[] = {
 195     DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
 196     DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
 197     DEFINE_PROP_END_OF_LIST(),
 198 };
 199
 200 static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
 201 {
 202     DeviceClass *dc = DEVICE_CLASS(klass);
 203
 204     dc->realize = stm32f205_soc_realize;
 205     dc->props = stm32f205_soc_properties;
 206 }
 207
 208 static const TypeInfo stm32f205_soc_info = {
 209     .name          = TYPE_STM32F205_SOC,
 210     .parent        = TYPE_SYS_BUS_DEVICE,
 211     .instance_size = sizeof(STM32F205State),
 212     .instance_init = stm32f205_soc_initfn,
 213     .class_init    = stm32f205_soc_class_init,
 214 };
 215
 216 static void stm32f205_soc_types(void)
 217 {
 218     type_register_static(&stm32f205_soc_info);
 219 }
 220
 221 type_init(stm32f205_soc_types)