hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "hw/sysbus.h"
  13 #include "hw/ssi/ssi.h"
  14 #include "hw/arm/arm.h"
  15 #include "hw/devices.h"
  16 #include "qemu/timer.h"
  17 #include "hw/i2c/i2c.h"
  18 #include "net/net.h"
  19 #include "hw/boards.h"
  20 #include "qemu/log.h"
  21 #include "exec/address-spaces.h"
  22 #include "sysemu/sysemu.h"
  23 #include "hw/char/pl011.h"
  24 #include "hw/misc/unimp.h"
  25
  26 #define GPIO_A 0
  27 #define GPIO_B 1
  28 #define GPIO_C 2
  29 #define GPIO_D 3
  30 #define GPIO_E 4
  31 #define GPIO_F 5
  32 #define GPIO_G 6
  33
  34 #define BP_OLED_I2C  0x01
  35 #define BP_OLED_SSI  0x02
  36 #define BP_GAMEPAD   0x04
  37
  38 #define NUM_IRQ_LINES 64
  39
  40 typedef const struct {
  41     const char *name;
  42     uint32_t did0;
  43     uint32_t did1;
  44     uint32_t dc0;
  45     uint32_t dc1;
  46     uint32_t dc2;
  47     uint32_t dc3;
  48     uint32_t dc4;
  49     uint32_t peripherals;
  50 } stellaris_board_info;
  51
  52 /* General purpose timer module.  */
  53
  54 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  55 #define STELLARIS_GPTM(obj) \
  56     OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
  57
  58 typedef struct gptm_state {
  59     SysBusDevice parent_obj;
  60
  61     MemoryRegion iomem;
  62     uint32_t config;
  63     uint32_t mode[2];
  64     uint32_t control;
  65     uint32_t state;
  66     uint32_t mask;
  67     uint32_t load[2];
  68     uint32_t match[2];
  69     uint32_t prescale[2];
  70     uint32_t match_prescale[2];
  71     uint32_t rtc;
  72     int64_t tick[2];
  73     struct gptm_state *opaque[2];
  74     QEMUTimer *timer[2];
  75     /* The timers have an alternate output used to trigger the ADC.  */
  76     qemu_irq trigger;
  77     qemu_irq irq;
  78 } gptm_state;
  79
  80 static void gptm_update_irq(gptm_state *s)
  81 {
  82     int level;
  83     level = (s->state & s->mask) != 0;
  84     qemu_set_irq(s->irq, level);
  85 }
  86
  87 static void gptm_stop(gptm_state *s, int n)
  88 {
  89     timer_del(s->timer[n]);
  90 }
  91
  92 static void gptm_reload(gptm_state *s, int n, int reset)
  93 {
  94     int64_t tick;
  95     if (reset)
  96         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  97     else
  98         tick = s->tick[n];
  99
 100     if (s->config == 0) {
 101         /* 32-bit CountDown.  */
 102         uint32_t count;
 103         count = s->load[0] | (s->load[1] << 16);
 104         tick += (int64_t)count * system_clock_scale;
 105     } else if (s->config == 1) {
 106         /* 32-bit RTC.  1Hz tick.  */
 107         tick += NANOSECONDS_PER_SECOND;
 108     } else if (s->mode[n] == 0xa) {
 109         /* PWM mode.  Not implemented.  */
 110     } else {
 111         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 112     }
 113     s->tick[n] = tick;
 114     timer_mod(s->timer[n], tick);
 115 }
 116
 117 static void gptm_tick(void *opaque)
 118 {
 119     gptm_state **p = (gptm_state **)opaque;
 120     gptm_state *s;
 121     int n;
 122
 123     s = *p;
 124     n = p - s->opaque;
 125     if (s->config == 0) {
 126         s->state |= 1;
 127         if ((s->control & 0x20)) {
 128             /* Output trigger.  */
 129             qemu_irq_pulse(s->trigger);
 130         }
 131         if (s->mode[0] & 1) {
 132             /* One-shot.  */
 133             s->control &= ~1;
 134         } else {
 135             /* Periodic.  */
 136             gptm_reload(s, 0, 0);
 137         }
 138     } else if (s->config == 1) {
 139         /* RTC.  */
 140         uint32_t match;
 141         s->rtc++;
 142         match = s->match[0] | (s->match[1] << 16);
 143         if (s->rtc > match)
 144             s->rtc = 0;
 145         if (s->rtc == 0) {
 146             s->state |= 8;
 147         }
 148         gptm_reload(s, 0, 0);
 149     } else if (s->mode[n] == 0xa) {
 150         /* PWM mode.  Not implemented.  */
 151     } else {
 152         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 153     }
 154     gptm_update_irq(s);
 155 }
 156
 157 static uint64_t gptm_read(void *opaque, hwaddr offset,
 158                           unsigned size)
 159 {
 160     gptm_state *s = (gptm_state *)opaque;
 161
 162     switch (offset) {
 163     case 0x00: /* CFG */
 164         return s->config;
 165     case 0x04: /* TAMR */
 166         return s->mode[0];
 167     case 0x08: /* TBMR */
 168         return s->mode[1];
 169     case 0x0c: /* CTL */
 170         return s->control;
 171     case 0x18: /* IMR */
 172         return s->mask;
 173     case 0x1c: /* RIS */
 174         return s->state;
 175     case 0x20: /* MIS */
 176         return s->state & s->mask;
 177     case 0x24: /* CR */
 178         return 0;
 179     case 0x28: /* TAILR */
 180         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 181     case 0x2c: /* TBILR */
 182         return s->load[1];
 183     case 0x30: /* TAMARCHR */
 184         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 185     case 0x34: /* TBMATCHR */
 186         return s->match[1];
 187     case 0x38: /* TAPR */
 188         return s->prescale[0];
 189     case 0x3c: /* TBPR */
 190         return s->prescale[1];
 191     case 0x40: /* TAPMR */
 192         return s->match_prescale[0];
 193     case 0x44: /* TBPMR */
 194         return s->match_prescale[1];
 195     case 0x48: /* TAR */
 196         if (s->config == 1) {
 197             return s->rtc;
 198         }
 199         qemu_log_mask(LOG_UNIMP,
 200                       "GPTM: read of TAR but timer read not supported");
 201         return 0;
 202     case 0x4c: /* TBR */
 203         qemu_log_mask(LOG_UNIMP,
 204                       "GPTM: read of TBR but timer read not supported");
 205         return 0;
 206     default:
 207         qemu_log_mask(LOG_GUEST_ERROR,
 208                       "GPTM: read at bad offset 0x%x\n", (int)offset);
 209         return 0;
 210     }
 211 }
 212
 213 static void gptm_write(void *opaque, hwaddr offset,
 214                        uint64_t value, unsigned size)
 215 {
 216     gptm_state *s = (gptm_state *)opaque;
 217     uint32_t oldval;
 218
 219     /* The timers should be disabled before changing the configuration.
 220        We take advantage of this and defer everything until the timer
 221        is enabled.  */
 222     switch (offset) {
 223     case 0x00: /* CFG */
 224         s->config = value;
 225         break;
 226     case 0x04: /* TAMR */
 227         s->mode[0] = value;
 228         break;
 229     case 0x08: /* TBMR */
 230         s->mode[1] = value;
 231         break;
 232     case 0x0c: /* CTL */
 233         oldval = s->control;
 234         s->control = value;
 235         /* TODO: Implement pause.  */
 236         if ((oldval ^ value) & 1) {
 237             if (value & 1) {
 238                 gptm_reload(s, 0, 1);
 239             } else {
 240                 gptm_stop(s, 0);
 241             }
 242         }
 243         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 244             if (value & 0x100) {
 245                 gptm_reload(s, 1, 1);
 246             } else {
 247                 gptm_stop(s, 1);
 248             }
 249         }
 250         break;
 251     case 0x18: /* IMR */
 252         s->mask = value & 0x77;
 253         gptm_update_irq(s);
 254         break;
 255     case 0x24: /* CR */
 256         s->state &= ~value;
 257         break;
 258     case 0x28: /* TAILR */
 259         s->load[0] = value & 0xffff;
 260         if (s->config < 4) {
 261             s->load[1] = value >> 16;
 262         }
 263         break;
 264     case 0x2c: /* TBILR */
 265         s->load[1] = value & 0xffff;
 266         break;
 267     case 0x30: /* TAMARCHR */
 268         s->match[0] = value & 0xffff;
 269         if (s->config < 4) {
 270             s->match[1] = value >> 16;
 271         }
 272         break;
 273     case 0x34: /* TBMATCHR */
 274         s->match[1] = value >> 16;
 275         break;
 276     case 0x38: /* TAPR */
 277         s->prescale[0] = value;
 278         break;
 279     case 0x3c: /* TBPR */
 280         s->prescale[1] = value;
 281         break;
 282     case 0x40: /* TAPMR */
 283         s->match_prescale[0] = value;
 284         break;
 285     case 0x44: /* TBPMR */
 286         s->match_prescale[0] = value;
 287         break;
 288     default:
 289         hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
 290     }
 291     gptm_update_irq(s);
 292 }
 293
 294 static const MemoryRegionOps gptm_ops = {
 295     .read = gptm_read,
 296     .write = gptm_write,
 297     .endianness = DEVICE_NATIVE_ENDIAN,
 298 };
 299
 300 static const VMStateDescription vmstate_stellaris_gptm = {
 301     .name = "stellaris_gptm",
 302     .version_id = 1,
 303     .minimum_version_id = 1,
 304     .fields = (VMStateField[]) {
 305         VMSTATE_UINT32(config, gptm_state),
 306         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 307         VMSTATE_UINT32(control, gptm_state),
 308         VMSTATE_UINT32(state, gptm_state),
 309         VMSTATE_UINT32(mask, gptm_state),
 310         VMSTATE_UNUSED(8),
 311         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 312         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 313         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 314         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 315         VMSTATE_UINT32(rtc, gptm_state),
 316         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 317         VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
 318         VMSTATE_END_OF_LIST()
 319     }
 320 };
 321
 322 static void stellaris_gptm_init(Object *obj)
 323 {
 324     DeviceState *dev = DEVICE(obj);
 325     gptm_state *s = STELLARIS_GPTM(obj);
 326     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 327
 328     sysbus_init_irq(sbd, &s->irq);
 329     qdev_init_gpio_out(dev, &s->trigger, 1);
 330
 331     memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
 332                           "gptm", 0x1000);
 333     sysbus_init_mmio(sbd, &s->iomem);
 334
 335     s->opaque[0] = s->opaque[1] = s;
 336     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 337     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 338 }
 339
 340
 341 /* System controller.  */
 342
 343 typedef struct {
 344     MemoryRegion iomem;
 345     uint32_t pborctl;
 346     uint32_t ldopctl;
 347     uint32_t int_status;
 348     uint32_t int_mask;
 349     uint32_t resc;
 350     uint32_t rcc;
 351     uint32_t rcc2;
 352     uint32_t rcgc[3];
 353     uint32_t scgc[3];
 354     uint32_t dcgc[3];
 355     uint32_t clkvclr;
 356     uint32_t ldoarst;
 357     uint32_t user0;
 358     uint32_t user1;
 359     qemu_irq irq;
 360     stellaris_board_info *board;
 361 } ssys_state;
 362
 363 static void ssys_update(ssys_state *s)
 364 {
 365   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 366 }
 367
 368 static uint32_t pllcfg_sandstorm[16] = {
 369     0x31c0, /* 1 Mhz */
 370     0x1ae0, /* 1.8432 Mhz */
 371     0x18c0, /* 2 Mhz */
 372     0xd573, /* 2.4576 Mhz */
 373     0x37a6, /* 3.57954 Mhz */
 374     0x1ae2, /* 3.6864 Mhz */
 375     0x0c40, /* 4 Mhz */
 376     0x98bc, /* 4.906 Mhz */
 377     0x935b, /* 4.9152 Mhz */
 378     0x09c0, /* 5 Mhz */
 379     0x4dee, /* 5.12 Mhz */
 380     0x0c41, /* 6 Mhz */
 381     0x75db, /* 6.144 Mhz */
 382     0x1ae6, /* 7.3728 Mhz */
 383     0x0600, /* 8 Mhz */
 384     0x585b /* 8.192 Mhz */
 385 };
 386
 387 static uint32_t pllcfg_fury[16] = {
 388     0x3200, /* 1 Mhz */
 389     0x1b20, /* 1.8432 Mhz */
 390     0x1900, /* 2 Mhz */
 391     0xf42b, /* 2.4576 Mhz */
 392     0x37e3, /* 3.57954 Mhz */
 393     0x1b21, /* 3.6864 Mhz */
 394     0x0c80, /* 4 Mhz */
 395     0x98ee, /* 4.906 Mhz */
 396     0xd5b4, /* 4.9152 Mhz */
 397     0x0a00, /* 5 Mhz */
 398     0x4e27, /* 5.12 Mhz */
 399     0x1902, /* 6 Mhz */
 400     0xec1c, /* 6.144 Mhz */
 401     0x1b23, /* 7.3728 Mhz */
 402     0x0640, /* 8 Mhz */
 403     0xb11c /* 8.192 Mhz */
 404 };
 405
 406 #define DID0_VER_MASK        0x70000000
 407 #define DID0_VER_0           0x00000000
 408 #define DID0_VER_1           0x10000000
 409
 410 #define DID0_CLASS_MASK      0x00FF0000
 411 #define DID0_CLASS_SANDSTORM 0x00000000
 412 #define DID0_CLASS_FURY      0x00010000
 413
 414 static int ssys_board_class(const ssys_state *s)
 415 {
 416     uint32_t did0 = s->board->did0;
 417     switch (did0 & DID0_VER_MASK) {
 418     case DID0_VER_0:
 419         return DID0_CLASS_SANDSTORM;
 420     case DID0_VER_1:
 421         switch (did0 & DID0_CLASS_MASK) {
 422         case DID0_CLASS_SANDSTORM:
 423         case DID0_CLASS_FURY:
 424             return did0 & DID0_CLASS_MASK;
 425         }
 426         /* for unknown classes, fall through */
 427     default:
 428         hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
 429     }
 430 }
 431
 432 static uint64_t ssys_read(void *opaque, hwaddr offset,
 433                           unsigned size)
 434 {
 435     ssys_state *s = (ssys_state *)opaque;
 436
 437     switch (offset) {
 438     case 0x000: /* DID0 */
 439         return s->board->did0;
 440     case 0x004: /* DID1 */
 441         return s->board->did1;
 442     case 0x008: /* DC0 */
 443         return s->board->dc0;
 444     case 0x010: /* DC1 */
 445         return s->board->dc1;
 446     case 0x014: /* DC2 */
 447         return s->board->dc2;
 448     case 0x018: /* DC3 */
 449         return s->board->dc3;
 450     case 0x01c: /* DC4 */
 451         return s->board->dc4;
 452     case 0x030: /* PBORCTL */
 453         return s->pborctl;
 454     case 0x034: /* LDOPCTL */
 455         return s->ldopctl;
 456     case 0x040: /* SRCR0 */
 457         return 0;
 458     case 0x044: /* SRCR1 */
 459         return 0;
 460     case 0x048: /* SRCR2 */
 461         return 0;
 462     case 0x050: /* RIS */
 463         return s->int_status;
 464     case 0x054: /* IMC */
 465         return s->int_mask;
 466     case 0x058: /* MISC */
 467         return s->int_status & s->int_mask;
 468     case 0x05c: /* RESC */
 469         return s->resc;
 470     case 0x060: /* RCC */
 471         return s->rcc;
 472     case 0x064: /* PLLCFG */
 473         {
 474             int xtal;
 475             xtal = (s->rcc >> 6) & 0xf;
 476             switch (ssys_board_class(s)) {
 477             case DID0_CLASS_FURY:
 478                 return pllcfg_fury[xtal];
 479             case DID0_CLASS_SANDSTORM:
 480                 return pllcfg_sandstorm[xtal];
 481             default:
 482                 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
 483                 return 0;
 484             }
 485         }
 486     case 0x070: /* RCC2 */
 487         return s->rcc2;
 488     case 0x100: /* RCGC0 */
 489         return s->rcgc[0];
 490     case 0x104: /* RCGC1 */
 491         return s->rcgc[1];
 492     case 0x108: /* RCGC2 */
 493         return s->rcgc[2];
 494     case 0x110: /* SCGC0 */
 495         return s->scgc[0];
 496     case 0x114: /* SCGC1 */
 497         return s->scgc[1];
 498     case 0x118: /* SCGC2 */
 499         return s->scgc[2];
 500     case 0x120: /* DCGC0 */
 501         return s->dcgc[0];
 502     case 0x124: /* DCGC1 */
 503         return s->dcgc[1];
 504     case 0x128: /* DCGC2 */
 505         return s->dcgc[2];
 506     case 0x150: /* CLKVCLR */
 507         return s->clkvclr;
 508     case 0x160: /* LDOARST */
 509         return s->ldoarst;
 510     case 0x1e0: /* USER0 */
 511         return s->user0;
 512     case 0x1e4: /* USER1 */
 513         return s->user1;
 514     default:
 515         hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
 516         return 0;
 517     }
 518 }
 519
 520 static bool ssys_use_rcc2(ssys_state *s)
 521 {
 522     return (s->rcc2 >> 31) & 0x1;
 523 }
 524
 525 /*
 526  * Caculate the sys. clock period in ms.
 527  */
 528 static void ssys_calculate_system_clock(ssys_state *s)
 529 {
 530     if (ssys_use_rcc2(s)) {
 531         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 532     } else {
 533         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 534     }
 535 }
 536
 537 static void ssys_write(void *opaque, hwaddr offset,
 538                        uint64_t value, unsigned size)
 539 {
 540     ssys_state *s = (ssys_state *)opaque;
 541
 542     switch (offset) {
 543     case 0x030: /* PBORCTL */
 544         s->pborctl = value & 0xffff;
 545         break;
 546     case 0x034: /* LDOPCTL */
 547         s->ldopctl = value & 0x1f;
 548         break;
 549     case 0x040: /* SRCR0 */
 550     case 0x044: /* SRCR1 */
 551     case 0x048: /* SRCR2 */
 552         fprintf(stderr, "Peripheral reset not implemented\n");
 553         break;
 554     case 0x054: /* IMC */
 555         s->int_mask = value & 0x7f;
 556         break;
 557     case 0x058: /* MISC */
 558         s->int_status &= ~value;
 559         break;
 560     case 0x05c: /* RESC */
 561         s->resc = value & 0x3f;
 562         break;
 563     case 0x060: /* RCC */
 564         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 565             /* PLL enable.  */
 566             s->int_status |= (1 << 6);
 567         }
 568         s->rcc = value;
 569         ssys_calculate_system_clock(s);
 570         break;
 571     case 0x070: /* RCC2 */
 572         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 573             break;
 574         }
 575
 576         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 577             /* PLL enable.  */
 578             s->int_status |= (1 << 6);
 579         }
 580         s->rcc2 = value;
 581         ssys_calculate_system_clock(s);
 582         break;
 583     case 0x100: /* RCGC0 */
 584         s->rcgc[0] = value;
 585         break;
 586     case 0x104: /* RCGC1 */
 587         s->rcgc[1] = value;
 588         break;
 589     case 0x108: /* RCGC2 */
 590         s->rcgc[2] = value;
 591         break;
 592     case 0x110: /* SCGC0 */
 593         s->scgc[0] = value;
 594         break;
 595     case 0x114: /* SCGC1 */
 596         s->scgc[1] = value;
 597         break;
 598     case 0x118: /* SCGC2 */
 599         s->scgc[2] = value;
 600         break;
 601     case 0x120: /* DCGC0 */
 602         s->dcgc[0] = value;
 603         break;
 604     case 0x124: /* DCGC1 */
 605         s->dcgc[1] = value;
 606         break;
 607     case 0x128: /* DCGC2 */
 608         s->dcgc[2] = value;
 609         break;
 610     case 0x150: /* CLKVCLR */
 611         s->clkvclr = value;
 612         break;
 613     case 0x160: /* LDOARST */
 614         s->ldoarst = value;
 615         break;
 616     default:
 617         hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
 618     }
 619     ssys_update(s);
 620 }
 621
 622 static const MemoryRegionOps ssys_ops = {
 623     .read = ssys_read,
 624     .write = ssys_write,
 625     .endianness = DEVICE_NATIVE_ENDIAN,
 626 };
 627
 628 static void ssys_reset(void *opaque)
 629 {
 630     ssys_state *s = (ssys_state *)opaque;
 631
 632     s->pborctl = 0x7ffd;
 633     s->rcc = 0x078e3ac0;
 634
 635     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 636         s->rcc2 = 0;
 637     } else {
 638         s->rcc2 = 0x07802810;
 639     }
 640     s->rcgc[0] = 1;
 641     s->scgc[0] = 1;
 642     s->dcgc[0] = 1;
 643     ssys_calculate_system_clock(s);
 644 }
 645
 646 static int stellaris_sys_post_load(void *opaque, int version_id)
 647 {
 648     ssys_state *s = opaque;
 649
 650     ssys_calculate_system_clock(s);
 651
 652     return 0;
 653 }
 654
 655 static const VMStateDescription vmstate_stellaris_sys = {
 656     .name = "stellaris_sys",
 657     .version_id = 2,
 658     .minimum_version_id = 1,
 659     .post_load = stellaris_sys_post_load,
 660     .fields = (VMStateField[]) {
 661         VMSTATE_UINT32(pborctl, ssys_state),
 662         VMSTATE_UINT32(ldopctl, ssys_state),
 663         VMSTATE_UINT32(int_mask, ssys_state),
 664         VMSTATE_UINT32(int_status, ssys_state),
 665         VMSTATE_UINT32(resc, ssys_state),
 666         VMSTATE_UINT32(rcc, ssys_state),
 667         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 668         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 669         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 670         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 671         VMSTATE_UINT32(clkvclr, ssys_state),
 672         VMSTATE_UINT32(ldoarst, ssys_state),
 673         VMSTATE_END_OF_LIST()
 674     }
 675 };
 676
 677 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 678                               stellaris_board_info * board,
 679                               uint8_t *macaddr)
 680 {
 681     ssys_state *s;
 682
 683     s = g_new0(ssys_state, 1);
 684     s->irq = irq;
 685     s->board = board;
 686     /* Most devices come preprogrammed with a MAC address in the user data. */
 687     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 688     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 689
 690     memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
 691     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 692     ssys_reset(s);
 693     vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
 694     return 0;
 695 }
 696
 697
 698 /* I2C controller.  */
 699
 700 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 701 #define STELLARIS_I2C(obj) \
 702     OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
 703
 704 typedef struct {
 705     SysBusDevice parent_obj;
 706
 707     I2CBus *bus;
 708     qemu_irq irq;
 709     MemoryRegion iomem;
 710     uint32_t msa;
 711     uint32_t mcs;
 712     uint32_t mdr;
 713     uint32_t mtpr;
 714     uint32_t mimr;
 715     uint32_t mris;
 716     uint32_t mcr;
 717 } stellaris_i2c_state;
 718
 719 #define STELLARIS_I2C_MCS_BUSY    0x01
 720 #define STELLARIS_I2C_MCS_ERROR   0x02
 721 #define STELLARIS_I2C_MCS_ADRACK  0x04
 722 #define STELLARIS_I2C_MCS_DATACK  0x08
 723 #define STELLARIS_I2C_MCS_ARBLST  0x10
 724 #define STELLARIS_I2C_MCS_IDLE    0x20
 725 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 726
 727 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 728                                    unsigned size)
 729 {
 730     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 731
 732     switch (offset) {
 733     case 0x00: /* MSA */
 734         return s->msa;
 735     case 0x04: /* MCS */
 736         /* We don't emulate timing, so the controller is never busy.  */
 737         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 738     case 0x08: /* MDR */
 739         return s->mdr;
 740     case 0x0c: /* MTPR */
 741         return s->mtpr;
 742     case 0x10: /* MIMR */
 743         return s->mimr;
 744     case 0x14: /* MRIS */
 745         return s->mris;
 746     case 0x18: /* MMIS */
 747         return s->mris & s->mimr;
 748     case 0x20: /* MCR */
 749         return s->mcr;
 750     default:
 751         hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
 752         return 0;
 753     }
 754 }
 755
 756 static void stellaris_i2c_update(stellaris_i2c_state *s)
 757 {
 758     int level;
 759
 760     level = (s->mris & s->mimr) != 0;
 761     qemu_set_irq(s->irq, level);
 762 }
 763
 764 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 765                                 uint64_t value, unsigned size)
 766 {
 767     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 768
 769     switch (offset) {
 770     case 0x00: /* MSA */
 771         s->msa = value & 0xff;
 772         break;
 773     case 0x04: /* MCS */
 774         if ((s->mcr & 0x10) == 0) {
 775             /* Disabled.  Do nothing.  */
 776             break;
 777         }
 778         /* Grab the bus if this is starting a transfer.  */
 779         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 780             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 781                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 782             } else {
 783                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 784                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 785             }
 786         }
 787         /* If we don't have the bus then indicate an error.  */
 788         if (!i2c_bus_busy(s->bus)
 789                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 790             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 791             break;
 792         }
 793         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 794         if (value & 1) {
 795             /* Transfer a byte.  */
 796             /* TODO: Handle errors.  */
 797             if (s->msa & 1) {
 798                 /* Recv */
 799                 s->mdr = i2c_recv(s->bus) & 0xff;
 800             } else {
 801                 /* Send */
 802                 i2c_send(s->bus, s->mdr);
 803             }
 804             /* Raise an interrupt.  */
 805             s->mris |= 1;
 806         }
 807         if (value & 4) {
 808             /* Finish transfer.  */
 809             i2c_end_transfer(s->bus);
 810             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 811         }
 812         break;
 813     case 0x08: /* MDR */
 814         s->mdr = value & 0xff;
 815         break;
 816     case 0x0c: /* MTPR */
 817         s->mtpr = value & 0xff;
 818         break;
 819     case 0x10: /* MIMR */
 820         s->mimr = 1;
 821         break;
 822     case 0x1c: /* MICR */
 823         s->mris &= ~value;
 824         break;
 825     case 0x20: /* MCR */
 826         if (value & 1)
 827             hw_error(
 828                       "stellaris_i2c_write: Loopback not implemented\n");
 829         if (value & 0x20)
 830             hw_error(
 831                       "stellaris_i2c_write: Slave mode not implemented\n");
 832         s->mcr = value & 0x31;
 833         break;
 834     default:
 835         hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
 836                   (int)offset);
 837     }
 838     stellaris_i2c_update(s);
 839 }
 840
 841 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 842 {
 843     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 844         i2c_end_transfer(s->bus);
 845
 846     s->msa = 0;
 847     s->mcs = 0;
 848     s->mdr = 0;
 849     s->mtpr = 1;
 850     s->mimr = 0;
 851     s->mris = 0;
 852     s->mcr = 0;
 853     stellaris_i2c_update(s);
 854 }
 855
 856 static const MemoryRegionOps stellaris_i2c_ops = {
 857     .read = stellaris_i2c_read,
 858     .write = stellaris_i2c_write,
 859     .endianness = DEVICE_NATIVE_ENDIAN,
 860 };
 861
 862 static const VMStateDescription vmstate_stellaris_i2c = {
 863     .name = "stellaris_i2c",
 864     .version_id = 1,
 865     .minimum_version_id = 1,
 866     .fields = (VMStateField[]) {
 867         VMSTATE_UINT32(msa, stellaris_i2c_state),
 868         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 869         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 870         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 871         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 872         VMSTATE_UINT32(mris, stellaris_i2c_state),
 873         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 874         VMSTATE_END_OF_LIST()
 875     }
 876 };
 877
 878 static void stellaris_i2c_init(Object *obj)
 879 {
 880     DeviceState *dev = DEVICE(obj);
 881     stellaris_i2c_state *s = STELLARIS_I2C(obj);
 882     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 883     I2CBus *bus;
 884
 885     sysbus_init_irq(sbd, &s->irq);
 886     bus = i2c_init_bus(dev, "i2c");
 887     s->bus = bus;
 888
 889     memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
 890                           "i2c", 0x1000);
 891     sysbus_init_mmio(sbd, &s->iomem);
 892     /* ??? For now we only implement the master interface.  */
 893     stellaris_i2c_reset(s);
 894 }
 895
 896 /* Analogue to Digital Converter.  This is only partially implemented,
 897    enough for applications that use a combined ADC and timer tick.  */
 898
 899 #define STELLARIS_ADC_EM_CONTROLLER 0
 900 #define STELLARIS_ADC_EM_COMP       1
 901 #define STELLARIS_ADC_EM_EXTERNAL   4
 902 #define STELLARIS_ADC_EM_TIMER      5
 903 #define STELLARIS_ADC_EM_PWM0       6
 904 #define STELLARIS_ADC_EM_PWM1       7
 905 #define STELLARIS_ADC_EM_PWM2       8
 906
 907 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 908 #define STELLARIS_ADC_FIFO_FULL     0x1000
 909
 910 #define TYPE_STELLARIS_ADC "stellaris-adc"
 911 #define STELLARIS_ADC(obj) \
 912     OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
 913
 914 typedef struct StellarisADCState {
 915     SysBusDevice parent_obj;
 916
 917     MemoryRegion iomem;
 918     uint32_t actss;
 919     uint32_t ris;
 920     uint32_t im;
 921     uint32_t emux;
 922     uint32_t ostat;
 923     uint32_t ustat;
 924     uint32_t sspri;
 925     uint32_t sac;
 926     struct {
 927         uint32_t state;
 928         uint32_t data[16];
 929     } fifo[4];
 930     uint32_t ssmux[4];
 931     uint32_t ssctl[4];
 932     uint32_t noise;
 933     qemu_irq irq[4];
 934 } stellaris_adc_state;
 935
 936 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 937 {
 938     int tail;
 939
 940     tail = s->fifo[n].state & 0xf;
 941     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 942         s->ustat |= 1 << n;
 943     } else {
 944         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 945         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 946         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 947             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 948     }
 949     return s->fifo[n].data[tail];
 950 }
 951
 952 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 953                                      uint32_t value)
 954 {
 955     int head;
 956
 957     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 958        FIFO fir each sequencer.  */
 959     head = (s->fifo[n].state >> 4) & 0xf;
 960     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 961         s->ostat |= 1 << n;
 962         return;
 963     }
 964     s->fifo[n].data[head] = value;
 965     head = (head + 1) & 0xf;
 966     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 967     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 968     if ((s->fifo[n].state & 0xf) == head)
 969         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 970 }
 971
 972 static void stellaris_adc_update(stellaris_adc_state *s)
 973 {
 974     int level;
 975     int n;
 976
 977     for (n = 0; n < 4; n++) {
 978         level = (s->ris & s->im & (1 << n)) != 0;
 979         qemu_set_irq(s->irq[n], level);
 980     }
 981 }
 982
 983 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 984 {
 985     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
 986     int n;
 987
 988     for (n = 0; n < 4; n++) {
 989         if ((s->actss & (1 << n)) == 0) {
 990             continue;
 991         }
 992
 993         if (((s->emux >> (n * 4)) & 0xff) != 5) {
 994             continue;
 995         }
 996
 997         /* Some applications use the ADC as a random number source, so introduce
 998            some variation into the signal.  */
 999         s->noise = s->noise * 314159 + 1;
1000         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
1001         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1002         s->ris |= (1 << n);
1003         stellaris_adc_update(s);
1004     }
1005 }
1006
1007 static void stellaris_adc_reset(stellaris_adc_state *s)
1008 {
1009     int n;
1010
1011     for (n = 0; n < 4; n++) {
1012         s->ssmux[n] = 0;
1013         s->ssctl[n] = 0;
1014         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1015     }
1016 }
1017
1018 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1019                                    unsigned size)
1020 {
1021     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1022
1023     /* TODO: Implement this.  */
1024     if (offset >= 0x40 && offset < 0xc0) {
1025         int n;
1026         n = (offset - 0x40) >> 5;
1027         switch (offset & 0x1f) {
1028         case 0x00: /* SSMUX */
1029             return s->ssmux[n];
1030         case 0x04: /* SSCTL */
1031             return s->ssctl[n];
1032         case 0x08: /* SSFIFO */
1033             return stellaris_adc_fifo_read(s, n);
1034         case 0x0c: /* SSFSTAT */
1035             return s->fifo[n].state;
1036         default:
1037             break;
1038         }
1039     }
1040     switch (offset) {
1041     case 0x00: /* ACTSS */
1042         return s->actss;
1043     case 0x04: /* RIS */
1044         return s->ris;
1045     case 0x08: /* IM */
1046         return s->im;
1047     case 0x0c: /* ISC */
1048         return s->ris & s->im;
1049     case 0x10: /* OSTAT */
1050         return s->ostat;
1051     case 0x14: /* EMUX */
1052         return s->emux;
1053     case 0x18: /* USTAT */
1054         return s->ustat;
1055     case 0x20: /* SSPRI */
1056         return s->sspri;
1057     case 0x30: /* SAC */
1058         return s->sac;
1059     default:
1060         hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1061                   (int)offset);
1062         return 0;
1063     }
1064 }
1065
1066 static void stellaris_adc_write(void *opaque, hwaddr offset,
1067                                 uint64_t value, unsigned size)
1068 {
1069     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1070
1071     /* TODO: Implement this.  */
1072     if (offset >= 0x40 && offset < 0xc0) {
1073         int n;
1074         n = (offset - 0x40) >> 5;
1075         switch (offset & 0x1f) {
1076         case 0x00: /* SSMUX */
1077             s->ssmux[n] = value & 0x33333333;
1078             return;
1079         case 0x04: /* SSCTL */
1080             if (value != 6) {
1081                 hw_error("ADC: Unimplemented sequence %" PRIx64 "\n",
1082                           value);
1083             }
1084             s->ssctl[n] = value;
1085             return;
1086         default:
1087             break;
1088         }
1089     }
1090     switch (offset) {
1091     case 0x00: /* ACTSS */
1092         s->actss = value & 0xf;
1093         break;
1094     case 0x08: /* IM */
1095         s->im = value;
1096         break;
1097     case 0x0c: /* ISC */
1098         s->ris &= ~value;
1099         break;
1100     case 0x10: /* OSTAT */
1101         s->ostat &= ~value;
1102         break;
1103     case 0x14: /* EMUX */
1104         s->emux = value;
1105         break;
1106     case 0x18: /* USTAT */
1107         s->ustat &= ~value;
1108         break;
1109     case 0x20: /* SSPRI */
1110         s->sspri = value;
1111         break;
1112     case 0x28: /* PSSI */
1113         hw_error("Not implemented:  ADC sample initiate\n");
1114         break;
1115     case 0x30: /* SAC */
1116         s->sac = value;
1117         break;
1118     default:
1119         hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
1120     }
1121     stellaris_adc_update(s);
1122 }
1123
1124 static const MemoryRegionOps stellaris_adc_ops = {
1125     .read = stellaris_adc_read,
1126     .write = stellaris_adc_write,
1127     .endianness = DEVICE_NATIVE_ENDIAN,
1128 };
1129
1130 static const VMStateDescription vmstate_stellaris_adc = {
1131     .name = "stellaris_adc",
1132     .version_id = 1,
1133     .minimum_version_id = 1,
1134     .fields = (VMStateField[]) {
1135         VMSTATE_UINT32(actss, stellaris_adc_state),
1136         VMSTATE_UINT32(ris, stellaris_adc_state),
1137         VMSTATE_UINT32(im, stellaris_adc_state),
1138         VMSTATE_UINT32(emux, stellaris_adc_state),
1139         VMSTATE_UINT32(ostat, stellaris_adc_state),
1140         VMSTATE_UINT32(ustat, stellaris_adc_state),
1141         VMSTATE_UINT32(sspri, stellaris_adc_state),
1142         VMSTATE_UINT32(sac, stellaris_adc_state),
1143         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1144         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1145         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1146         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1147         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1148         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1149         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1150         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1151         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1152         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1153         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1154         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1155         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1156         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1157         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1158         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1159         VMSTATE_UINT32(noise, stellaris_adc_state),
1160         VMSTATE_END_OF_LIST()
1161     }
1162 };
1163
1164 static void stellaris_adc_init(Object *obj)
1165 {
1166     DeviceState *dev = DEVICE(obj);
1167     stellaris_adc_state *s = STELLARIS_ADC(obj);
1168     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1169     int n;
1170
1171     for (n = 0; n < 4; n++) {
1172         sysbus_init_irq(sbd, &s->irq[n]);
1173     }
1174
1175     memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1176                           "adc", 0x1000);
1177     sysbus_init_mmio(sbd, &s->iomem);
1178     stellaris_adc_reset(s);
1179     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1180 }
1181
1182 static
1183 void do_sys_reset(void *opaque, int n, int level)
1184 {
1185     if (level) {
1186         qemu_system_reset_request();
1187     }
1188 }
1189
1190 /* Board init.  */
1191 static stellaris_board_info stellaris_boards[] = {
1192   { "LM3S811EVB",
1193     0,
1194     0x0032000e,
1195     0x001f001f, /* dc0 */
1196     0x001132bf,
1197     0x01071013,
1198     0x3f0f01ff,
1199     0x0000001f,
1200     BP_OLED_I2C
1201   },
1202   { "LM3S6965EVB",
1203     0x10010002,
1204     0x1073402e,
1205     0x00ff007f, /* dc0 */
1206     0x001133ff,
1207     0x030f5317,
1208     0x0f0f87ff,
1209     0x5000007f,
1210     BP_OLED_SSI | BP_GAMEPAD
1211   }
1212 };
1213
1214 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1215                            stellaris_board_info *board)
1216 {
1217     static const int uart_irq[] = {5, 6, 33, 34};
1218     static const int timer_irq[] = {19, 21, 23, 35};
1219     static const uint32_t gpio_addr[7] =
1220       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1221         0x40024000, 0x40025000, 0x40026000};
1222     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1223
1224     /* Memory map of SoC devices, from
1225      * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1226      * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1227      *
1228      * 40000000 wdtimer (unimplemented)
1229      * 40002000 i2c (unimplemented)
1230      * 40004000 GPIO
1231      * 40005000 GPIO
1232      * 40006000 GPIO
1233      * 40007000 GPIO
1234      * 40008000 SSI
1235      * 4000c000 UART
1236      * 4000d000 UART
1237      * 4000e000 UART
1238      * 40020000 i2c
1239      * 40021000 i2c (unimplemented)
1240      * 40024000 GPIO
1241      * 40025000 GPIO
1242      * 40026000 GPIO
1243      * 40028000 PWM (unimplemented)
1244      * 4002c000 QEI (unimplemented)
1245      * 4002d000 QEI (unimplemented)
1246      * 40030000 gptimer
1247      * 40031000 gptimer
1248      * 40032000 gptimer
1249      * 40033000 gptimer
1250      * 40038000 ADC
1251      * 4003c000 analogue comparator (unimplemented)
1252      * 40048000 ethernet
1253      * 400fc000 hibernation module (unimplemented)
1254      * 400fd000 flash memory control (unimplemented)
1255      * 400fe000 system control
1256      */
1257
1258     DeviceState *gpio_dev[7], *nvic;
1259     qemu_irq gpio_in[7][8];
1260     qemu_irq gpio_out[7][8];
1261     qemu_irq adc;
1262     int sram_size;
1263     int flash_size;
1264     I2CBus *i2c;
1265     DeviceState *dev;
1266     int i;
1267     int j;
1268
1269     MemoryRegion *sram = g_new(MemoryRegion, 1);
1270     MemoryRegion *flash = g_new(MemoryRegion, 1);
1271     MemoryRegion *system_memory = get_system_memory();
1272
1273     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1274     sram_size = ((board->dc0 >> 18) + 1) * 1024;
1275
1276     /* Flash programming is done via the SCU, so pretend it is ROM.  */
1277     memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
1278                            &error_fatal);
1279     vmstate_register_ram_global(flash);
1280     memory_region_set_readonly(flash, true);
1281     memory_region_add_subregion(system_memory, 0, flash);
1282
1283     memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1284                            &error_fatal);
1285     vmstate_register_ram_global(sram);
1286     memory_region_add_subregion(system_memory, 0x20000000, sram);
1287
1288     nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
1289                       kernel_filename, cpu_model);
1290
1291     qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
1292                                 qemu_allocate_irq(&do_sys_reset, NULL, 0));
1293
1294     if (board->dc1 & (1 << 16)) {
1295         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1296                                     qdev_get_gpio_in(nvic, 14),
1297                                     qdev_get_gpio_in(nvic, 15),
1298                                     qdev_get_gpio_in(nvic, 16),
1299                                     qdev_get_gpio_in(nvic, 17),
1300                                     NULL);
1301         adc = qdev_get_gpio_in(dev, 0);
1302     } else {
1303         adc = NULL;
1304     }
1305     for (i = 0; i < 4; i++) {
1306         if (board->dc2 & (0x10000 << i)) {
1307             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1308                                        0x40030000 + i * 0x1000,
1309                                        qdev_get_gpio_in(nvic, timer_irq[i]));
1310             /* TODO: This is incorrect, but we get away with it because
1311                the ADC output is only ever pulsed.  */
1312             qdev_connect_gpio_out(dev, 0, adc);
1313         }
1314     }
1315
1316     stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1317                        board, nd_table[0].macaddr.a);
1318
1319     for (i = 0; i < 7; i++) {
1320         if (board->dc4 & (1 << i)) {
1321             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1322                                                qdev_get_gpio_in(nvic,
1323                                                                 gpio_irq[i]));
1324             for (j = 0; j < 8; j++) {
1325                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1326                 gpio_out[i][j] = NULL;
1327             }
1328         }
1329     }
1330
1331     if (board->dc2 & (1 << 12)) {
1332         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1333                                    qdev_get_gpio_in(nvic, 8));
1334         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1335         if (board->peripherals & BP_OLED_I2C) {
1336             i2c_create_slave(i2c, "ssd0303", 0x3d);
1337         }
1338     }
1339
1340     for (i = 0; i < 4; i++) {
1341         if (board->dc2 & (1 << i)) {
1342             pl011_luminary_create(0x4000c000 + i * 0x1000,
1343                                   qdev_get_gpio_in(nvic, uart_irq[i]),
1344                                   serial_hds[i]);
1345         }
1346     }
1347     if (board->dc2 & (1 << 4)) {
1348         dev = sysbus_create_simple("pl022", 0x40008000,
1349                                    qdev_get_gpio_in(nvic, 7));
1350         if (board->peripherals & BP_OLED_SSI) {
1351             void *bus;
1352             DeviceState *sddev;
1353             DeviceState *ssddev;
1354
1355             /* Some boards have both an OLED controller and SD card connected to
1356              * the same SSI port, with the SD card chip select connected to a
1357              * GPIO pin.  Technically the OLED chip select is connected to the
1358              * SSI Fss pin.  We do not bother emulating that as both devices
1359              * should never be selected simultaneously, and our OLED controller
1360              * ignores stray 0xff commands that occur when deselecting the SD
1361              * card.
1362              */
1363             bus = qdev_get_child_bus(dev, "ssi");
1364
1365             sddev = ssi_create_slave(bus, "ssi-sd");
1366             ssddev = ssi_create_slave(bus, "ssd0323");
1367             gpio_out[GPIO_D][0] = qemu_irq_split(
1368                     qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1369                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1370             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1371
1372             /* Make sure the select pin is high.  */
1373             qemu_irq_raise(gpio_out[GPIO_D][0]);
1374         }
1375     }
1376     if (board->dc4 & (1 << 28)) {
1377         DeviceState *enet;
1378
1379         qemu_check_nic_model(&nd_table[0], "stellaris");
1380
1381         enet = qdev_create(NULL, "stellaris_enet");
1382         qdev_set_nic_properties(enet, &nd_table[0]);
1383         qdev_init_nofail(enet);
1384         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1385         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1386     }
1387     if (board->peripherals & BP_GAMEPAD) {
1388         qemu_irq gpad_irq[5];
1389         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1390
1391         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1392         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1393         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1394         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1395         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1396
1397         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1398     }
1399     for (i = 0; i < 7; i++) {
1400         if (board->dc4 & (1 << i)) {
1401             for (j = 0; j < 8; j++) {
1402                 if (gpio_out[i][j]) {
1403                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1404                 }
1405             }
1406         }
1407     }
1408
1409     /* Add dummy regions for the devices we don't implement yet,
1410      * so guest accesses don't cause unlogged crashes.
1411      */
1412     create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
1413     create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1414     create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1415     create_unimplemented_device("PWM", 0x40028000, 0x1000);
1416     create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1417     create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1418     create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1419     create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1420     create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1421 }
1422
1423 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1424 static void lm3s811evb_init(MachineState *machine)
1425 {
1426     const char *cpu_model = machine->cpu_model;
1427     const char *kernel_filename = machine->kernel_filename;
1428     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
1429 }
1430
1431 static void lm3s6965evb_init(MachineState *machine)
1432 {
1433     const char *cpu_model = machine->cpu_model;
1434     const char *kernel_filename = machine->kernel_filename;
1435     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
1436 }
1437
1438 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1439 {
1440     MachineClass *mc = MACHINE_CLASS(oc);
1441
1442     mc->desc = "Stellaris LM3S811EVB";
1443     mc->init = lm3s811evb_init;
1444 }
1445
1446 static const TypeInfo lm3s811evb_type = {
1447     .name = MACHINE_TYPE_NAME("lm3s811evb"),
1448     .parent = TYPE_MACHINE,
1449     .class_init = lm3s811evb_class_init,
1450 };
1451
1452 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1453 {
1454     MachineClass *mc = MACHINE_CLASS(oc);
1455
1456     mc->desc = "Stellaris LM3S6965EVB";
1457     mc->init = lm3s6965evb_init;
1458 }
1459
1460 static const TypeInfo lm3s6965evb_type = {
1461     .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1462     .parent = TYPE_MACHINE,
1463     .class_init = lm3s6965evb_class_init,
1464 };
1465
1466 static void stellaris_machine_init(void)
1467 {
1468     type_register_static(&lm3s811evb_type);
1469     type_register_static(&lm3s6965evb_type);
1470 }
1471
1472 type_init(stellaris_machine_init)
1473
1474 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1475 {
1476     DeviceClass *dc = DEVICE_CLASS(klass);
1477
1478     dc->vmsd = &vmstate_stellaris_i2c;
1479 }
1480
1481 static const TypeInfo stellaris_i2c_info = {
1482     .name          = TYPE_STELLARIS_I2C,
1483     .parent        = TYPE_SYS_BUS_DEVICE,
1484     .instance_size = sizeof(stellaris_i2c_state),
1485     .instance_init = stellaris_i2c_init,
1486     .class_init    = stellaris_i2c_class_init,
1487 };
1488
1489 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1490 {
1491     DeviceClass *dc = DEVICE_CLASS(klass);
1492
1493     dc->vmsd = &vmstate_stellaris_gptm;
1494 }
1495
1496 static const TypeInfo stellaris_gptm_info = {
1497     .name          = TYPE_STELLARIS_GPTM,
1498     .parent        = TYPE_SYS_BUS_DEVICE,
1499     .instance_size = sizeof(gptm_state),
1500     .instance_init = stellaris_gptm_init,
1501     .class_init    = stellaris_gptm_class_init,
1502 };
1503
1504 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1505 {
1506     DeviceClass *dc = DEVICE_CLASS(klass);
1507
1508     dc->vmsd = &vmstate_stellaris_adc;
1509 }
1510
1511 static const TypeInfo stellaris_adc_info = {
1512     .name          = TYPE_STELLARIS_ADC,
1513     .parent        = TYPE_SYS_BUS_DEVICE,
1514     .instance_size = sizeof(stellaris_adc_state),
1515     .instance_init = stellaris_adc_init,
1516     .class_init    = stellaris_adc_class_init,
1517 };
1518
1519 static void stellaris_register_types(void)
1520 {
1521     type_register_static(&stellaris_i2c_info);
1522     type_register_static(&stellaris_gptm_info);
1523     type_register_static(&stellaris_adc_info);
1524 }
1525
1526 type_init(stellaris_register_types)