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disas/i386.c: disassemble pclmulqdq instruction
[qemu/ar7.git] / hw / sparc / sun4m.c
blob31beb328858a4377af1ba485a741785746b6fd8f
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/sysbus.h"
25 #include "qemu/timer.h"
26 #include "hw/sparc/sun4m.h"
27 #include "hw/timer/m48t59.h"
28 #include "hw/sparc/sparc32_dma.h"
29 #include "hw/block/fdc.h"
30 #include "sysemu/sysemu.h"
31 #include "net/net.h"
32 #include "hw/boards.h"
33 #include "hw/sparc/firmware_abi.h"
34 #include "hw/scsi/esp.h"
35 #include "hw/i386/pc.h"
36 #include "hw/isa/isa.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/char/escc.h"
39 #include "hw/empty_slot.h"
40 #include "hw/qdev-addr.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "sysemu/blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
92 hwaddr serial_base, fd_base;
93 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
94 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 hwaddr bpp_base, dbri_base, sx_base;
96 struct {
97 hwaddr reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 hwaddr ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
112 hwaddr counter_base, nvram_base, ms_kb_base;
113 hwaddr serial_base;
114 hwaddr espdma_base, esp_base;
115 hwaddr ledma_base, le_base;
116 hwaddr tcx_base;
117 hwaddr sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123 };
124
125 struct sun4c_hwdef {
126 hwaddr iommu_base, slavio_base;
127 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
128 hwaddr serial_base, fd_base;
129 hwaddr idreg_base, dma_base, esp_base, le_base;
130 hwaddr tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void sun4m_pic_info(Monitor *mon, const QDict *qdict)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void sun4m_irq_info(Monitor *mon, const QDict *qdict)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUSPARCState *env)
232 {
233 CPUState *cs;
234
235 if (env->pil_in && (env->interrupt_index == 0 ||
236 (env->interrupt_index & ~15) == TT_EXTINT)) {
237 unsigned int i;
238
239 for (i = 15; i > 0; i--) {
240 if (env->pil_in & (1 << i)) {
241 int old_interrupt = env->interrupt_index;
242
243 env->interrupt_index = TT_EXTINT | i;
244 if (old_interrupt != env->interrupt_index) {
245 cs = CPU(sparc_env_get_cpu(env));
246 trace_sun4m_cpu_interrupt(i);
247 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
248 }
249 break;
250 }
251 }
252 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
253 cs = CPU(sparc_env_get_cpu(env));
254 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
255 env->interrupt_index = 0;
256 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
257 }
258 }
259
260 static void cpu_kick_irq(SPARCCPU *cpu)
261 {
262 CPUSPARCState *env = &cpu->env;
263 CPUState *cs = CPU(cpu);
264
265 cs->halted = 0;
266 cpu_check_irqs(env);
267 qemu_cpu_kick(cs);
268 }
269
270 static void cpu_set_irq(void *opaque, int irq, int level)
271 {
272 SPARCCPU *cpu = opaque;
273 CPUSPARCState *env = &cpu->env;
274
275 if (level) {
276 trace_sun4m_cpu_set_irq_raise(irq);
277 env->pil_in |= 1 << irq;
278 cpu_kick_irq(cpu);
279 } else {
280 trace_sun4m_cpu_set_irq_lower(irq);
281 env->pil_in &= ~(1 << irq);
282 cpu_check_irqs(env);
283 }
284 }
285
286 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
287 {
288 }
289
290 static void main_cpu_reset(void *opaque)
291 {
292 SPARCCPU *cpu = opaque;
293 CPUState *cs = CPU(cpu);
294
295 cpu_reset(cs);
296 cs->halted = 0;
297 }
298
299 static void secondary_cpu_reset(void *opaque)
300 {
301 SPARCCPU *cpu = opaque;
302 CPUState *cs = CPU(cpu);
303
304 cpu_reset(cs);
305 cs->halted = 1;
306 }
307
308 static void cpu_halt_signal(void *opaque, int irq, int level)
309 {
310 if (level && cpu_single_env) {
311 cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)),
312 CPU_INTERRUPT_HALT);
313 }
314 }
315
316 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
317 {
318 return addr - 0xf0000000ULL;
319 }
320
321 static unsigned long sun4m_load_kernel(const char *kernel_filename,
322 const char *initrd_filename,
323 ram_addr_t RAM_size)
324 {
325 int linux_boot;
326 unsigned int i;
327 long initrd_size, kernel_size;
328 uint8_t *ptr;
329
330 linux_boot = (kernel_filename != NULL);
331
332 kernel_size = 0;
333 if (linux_boot) {
334 int bswap_needed;
335
336 #ifdef BSWAP_NEEDED
337 bswap_needed = 1;
338 #else
339 bswap_needed = 0;
340 #endif
341 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
342 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
343 if (kernel_size < 0)
344 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
345 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
346 TARGET_PAGE_SIZE);
347 if (kernel_size < 0)
348 kernel_size = load_image_targphys(kernel_filename,
349 KERNEL_LOAD_ADDR,
350 RAM_size - KERNEL_LOAD_ADDR);
351 if (kernel_size < 0) {
352 fprintf(stderr, "qemu: could not load kernel '%s'\n",
353 kernel_filename);
354 exit(1);
355 }
356
357 /* load initrd */
358 initrd_size = 0;
359 if (initrd_filename) {
360 initrd_size = load_image_targphys(initrd_filename,
361 INITRD_LOAD_ADDR,
362 RAM_size - INITRD_LOAD_ADDR);
363 if (initrd_size < 0) {
364 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
365 initrd_filename);
366 exit(1);
367 }
368 }
369 if (initrd_size > 0) {
370 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
371 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
372 if (ldl_p(ptr) == 0x48647253) { // HdrS
373 stl_p(ptr + 16, INITRD_LOAD_ADDR);
374 stl_p(ptr + 20, initrd_size);
375 break;
376 }
377 }
378 }
379 }
380 return kernel_size;
381 }
382
383 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
384 {
385 DeviceState *dev;
386 SysBusDevice *s;
387
388 dev = qdev_create(NULL, "iommu");
389 qdev_prop_set_uint32(dev, "version", version);
390 qdev_init_nofail(dev);
391 s = SYS_BUS_DEVICE(dev);
392 sysbus_connect_irq(s, 0, irq);
393 sysbus_mmio_map(s, 0, addr);
394
395 return s;
396 }
397
398 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
399 void *iommu, qemu_irq *dev_irq, int is_ledma)
400 {
401 DeviceState *dev;
402 SysBusDevice *s;
403
404 dev = qdev_create(NULL, "sparc32_dma");
405 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
406 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
407 qdev_init_nofail(dev);
408 s = SYS_BUS_DEVICE(dev);
409 sysbus_connect_irq(s, 0, parent_irq);
410 *dev_irq = qdev_get_gpio_in(dev, 0);
411 sysbus_mmio_map(s, 0, daddr);
412
413 return s;
414 }
415
416 static void lance_init(NICInfo *nd, hwaddr leaddr,
417 void *dma_opaque, qemu_irq irq)
418 {
419 DeviceState *dev;
420 SysBusDevice *s;
421 qemu_irq reset;
422
423 qemu_check_nic_model(&nd_table[0], "lance");
424
425 dev = qdev_create(NULL, "lance");
426 qdev_set_nic_properties(dev, nd);
427 qdev_prop_set_ptr(dev, "dma", dma_opaque);
428 qdev_init_nofail(dev);
429 s = SYS_BUS_DEVICE(dev);
430 sysbus_mmio_map(s, 0, leaddr);
431 sysbus_connect_irq(s, 0, irq);
432 reset = qdev_get_gpio_in(dev, 0);
433 qdev_connect_gpio_out(dma_opaque, 0, reset);
434 }
435
436 static DeviceState *slavio_intctl_init(hwaddr addr,
437 hwaddr addrg,
438 qemu_irq **parent_irq)
439 {
440 DeviceState *dev;
441 SysBusDevice *s;
442 unsigned int i, j;
443
444 dev = qdev_create(NULL, "slavio_intctl");
445 qdev_init_nofail(dev);
446
447 s = SYS_BUS_DEVICE(dev);
448
449 for (i = 0; i < MAX_CPUS; i++) {
450 for (j = 0; j < MAX_PILS; j++) {
451 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
452 }
453 }
454 sysbus_mmio_map(s, 0, addrg);
455 for (i = 0; i < MAX_CPUS; i++) {
456 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
457 }
458
459 return dev;
460 }
461
462 #define SYS_TIMER_OFFSET 0x10000ULL
463 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
464
465 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
466 qemu_irq *cpu_irqs, unsigned int num_cpus)
467 {
468 DeviceState *dev;
469 SysBusDevice *s;
470 unsigned int i;
471
472 dev = qdev_create(NULL, "slavio_timer");
473 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
474 qdev_init_nofail(dev);
475 s = SYS_BUS_DEVICE(dev);
476 sysbus_connect_irq(s, 0, master_irq);
477 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
478
479 for (i = 0; i < MAX_CPUS; i++) {
480 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
481 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
482 }
483 }
484
485 static qemu_irq slavio_system_powerdown;
486
487 static void slavio_powerdown_req(Notifier *n, void *opaque)
488 {
489 qemu_irq_raise(slavio_system_powerdown);
490 }
491
492 static Notifier slavio_system_powerdown_notifier = {
493 .notify = slavio_powerdown_req
494 };
495
496 #define MISC_LEDS 0x01600000
497 #define MISC_CFG 0x01800000
498 #define MISC_DIAG 0x01a00000
499 #define MISC_MDM 0x01b00000
500 #define MISC_SYS 0x01f00000
501
502 static void slavio_misc_init(hwaddr base,
503 hwaddr aux1_base,
504 hwaddr aux2_base, qemu_irq irq,
505 qemu_irq fdc_tc)
506 {
507 DeviceState *dev;
508 SysBusDevice *s;
509
510 dev = qdev_create(NULL, "slavio_misc");
511 qdev_init_nofail(dev);
512 s = SYS_BUS_DEVICE(dev);
513 if (base) {
514 /* 8 bit registers */
515 /* Slavio control */
516 sysbus_mmio_map(s, 0, base + MISC_CFG);
517 /* Diagnostics */
518 sysbus_mmio_map(s, 1, base + MISC_DIAG);
519 /* Modem control */
520 sysbus_mmio_map(s, 2, base + MISC_MDM);
521 /* 16 bit registers */
522 /* ss600mp diag LEDs */
523 sysbus_mmio_map(s, 3, base + MISC_LEDS);
524 /* 32 bit registers */
525 /* System control */
526 sysbus_mmio_map(s, 4, base + MISC_SYS);
527 }
528 if (aux1_base) {
529 /* AUX 1 (Misc System Functions) */
530 sysbus_mmio_map(s, 5, aux1_base);
531 }
532 if (aux2_base) {
533 /* AUX 2 (Software Powerdown Control) */
534 sysbus_mmio_map(s, 6, aux2_base);
535 }
536 sysbus_connect_irq(s, 0, irq);
537 sysbus_connect_irq(s, 1, fdc_tc);
538 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
539 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
540 }
541
542 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
543 {
544 DeviceState *dev;
545 SysBusDevice *s;
546
547 dev = qdev_create(NULL, "eccmemctl");
548 qdev_prop_set_uint32(dev, "version", version);
549 qdev_init_nofail(dev);
550 s = SYS_BUS_DEVICE(dev);
551 sysbus_connect_irq(s, 0, irq);
552 sysbus_mmio_map(s, 0, base);
553 if (version == 0) { // SS-600MP only
554 sysbus_mmio_map(s, 1, base + 0x1000);
555 }
556 }
557
558 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
559 {
560 DeviceState *dev;
561 SysBusDevice *s;
562
563 dev = qdev_create(NULL, "apc");
564 qdev_init_nofail(dev);
565 s = SYS_BUS_DEVICE(dev);
566 /* Power management (APC) XXX: not a Slavio device */
567 sysbus_mmio_map(s, 0, power_base);
568 sysbus_connect_irq(s, 0, cpu_halt);
569 }
570
571 static void tcx_init(hwaddr addr, int vram_size, int width,
572 int height, int depth)
573 {
574 DeviceState *dev;
575 SysBusDevice *s;
576
577 dev = qdev_create(NULL, "SUNW,tcx");
578 qdev_prop_set_uint32(dev, "vram_size", vram_size);
579 qdev_prop_set_uint16(dev, "width", width);
580 qdev_prop_set_uint16(dev, "height", height);
581 qdev_prop_set_uint16(dev, "depth", depth);
582 qdev_init_nofail(dev);
583 s = SYS_BUS_DEVICE(dev);
584 /* 8-bit plane */
585 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
586 /* DAC */
587 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
588 /* TEC (dummy) */
589 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
590 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
591 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
592 if (depth == 24) {
593 /* 24-bit plane */
594 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
595 /* Control plane */
596 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
597 } else {
598 /* THC 8 bit (dummy) */
599 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
600 }
601 }
602
603 /* NCR89C100/MACIO Internal ID register */
604 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
605
606 static void idreg_init(hwaddr addr)
607 {
608 DeviceState *dev;
609 SysBusDevice *s;
610
611 dev = qdev_create(NULL, "macio_idreg");
612 qdev_init_nofail(dev);
613 s = SYS_BUS_DEVICE(dev);
614
615 sysbus_mmio_map(s, 0, addr);
616 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
617 }
618
619 typedef struct IDRegState {
620 SysBusDevice busdev;
621 MemoryRegion mem;
622 } IDRegState;
623
624 static int idreg_init1(SysBusDevice *dev)
625 {
626 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
627
628 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
629 vmstate_register_ram_global(&s->mem);
630 memory_region_set_readonly(&s->mem, true);
631 sysbus_init_mmio(dev, &s->mem);
632 return 0;
633 }
634
635 static void idreg_class_init(ObjectClass *klass, void *data)
636 {
637 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
638
639 k->init = idreg_init1;
640 }
641
642 static const TypeInfo idreg_info = {
643 .name = "macio_idreg",
644 .parent = TYPE_SYS_BUS_DEVICE,
645 .instance_size = sizeof(IDRegState),
646 .class_init = idreg_class_init,
647 };
648
649 typedef struct AFXState {
650 SysBusDevice busdev;
651 MemoryRegion mem;
652 } AFXState;
653
654 /* SS-5 TCX AFX register */
655 static void afx_init(hwaddr addr)
656 {
657 DeviceState *dev;
658 SysBusDevice *s;
659
660 dev = qdev_create(NULL, "tcx_afx");
661 qdev_init_nofail(dev);
662 s = SYS_BUS_DEVICE(dev);
663
664 sysbus_mmio_map(s, 0, addr);
665 }
666
667 static int afx_init1(SysBusDevice *dev)
668 {
669 AFXState *s = FROM_SYSBUS(AFXState, dev);
670
671 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
672 vmstate_register_ram_global(&s->mem);
673 sysbus_init_mmio(dev, &s->mem);
674 return 0;
675 }
676
677 static void afx_class_init(ObjectClass *klass, void *data)
678 {
679 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
680
681 k->init = afx_init1;
682 }
683
684 static const TypeInfo afx_info = {
685 .name = "tcx_afx",
686 .parent = TYPE_SYS_BUS_DEVICE,
687 .instance_size = sizeof(AFXState),
688 .class_init = afx_class_init,
689 };
690
691 typedef struct PROMState {
692 SysBusDevice busdev;
693 MemoryRegion prom;
694 } PROMState;
695
696 /* Boot PROM (OpenBIOS) */
697 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
698 {
699 hwaddr *base_addr = (hwaddr *)opaque;
700 return addr + *base_addr - PROM_VADDR;
701 }
702
703 static void prom_init(hwaddr addr, const char *bios_name)
704 {
705 DeviceState *dev;
706 SysBusDevice *s;
707 char *filename;
708 int ret;
709
710 dev = qdev_create(NULL, "openprom");
711 qdev_init_nofail(dev);
712 s = SYS_BUS_DEVICE(dev);
713
714 sysbus_mmio_map(s, 0, addr);
715
716 /* load boot prom */
717 if (bios_name == NULL) {
718 bios_name = PROM_FILENAME;
719 }
720 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
721 if (filename) {
722 ret = load_elf(filename, translate_prom_address, &addr, NULL,
723 NULL, NULL, 1, ELF_MACHINE, 0);
724 if (ret < 0 || ret > PROM_SIZE_MAX) {
725 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
726 }
727 g_free(filename);
728 } else {
729 ret = -1;
730 }
731 if (ret < 0 || ret > PROM_SIZE_MAX) {
732 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
733 exit(1);
734 }
735 }
736
737 static int prom_init1(SysBusDevice *dev)
738 {
739 PROMState *s = FROM_SYSBUS(PROMState, dev);
740
741 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
742 vmstate_register_ram_global(&s->prom);
743 memory_region_set_readonly(&s->prom, true);
744 sysbus_init_mmio(dev, &s->prom);
745 return 0;
746 }
747
748 static Property prom_properties[] = {
749 {/* end of property list */},
750 };
751
752 static void prom_class_init(ObjectClass *klass, void *data)
753 {
754 DeviceClass *dc = DEVICE_CLASS(klass);
755 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
756
757 k->init = prom_init1;
758 dc->props = prom_properties;
759 }
760
761 static const TypeInfo prom_info = {
762 .name = "openprom",
763 .parent = TYPE_SYS_BUS_DEVICE,
764 .instance_size = sizeof(PROMState),
765 .class_init = prom_class_init,
766 };
767
768 typedef struct RamDevice
769 {
770 SysBusDevice busdev;
771 MemoryRegion ram;
772 uint64_t size;
773 } RamDevice;
774
775 /* System RAM */
776 static int ram_init1(SysBusDevice *dev)
777 {
778 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
779
780 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
781 vmstate_register_ram_global(&d->ram);
782 sysbus_init_mmio(dev, &d->ram);
783 return 0;
784 }
785
786 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
787 uint64_t max_mem)
788 {
789 DeviceState *dev;
790 SysBusDevice *s;
791 RamDevice *d;
792
793 /* allocate RAM */
794 if ((uint64_t)RAM_size > max_mem) {
795 fprintf(stderr,
796 "qemu: Too much memory for this machine: %d, maximum %d\n",
797 (unsigned int)(RAM_size / (1024 * 1024)),
798 (unsigned int)(max_mem / (1024 * 1024)));
799 exit(1);
800 }
801 dev = qdev_create(NULL, "memory");
802 s = SYS_BUS_DEVICE(dev);
803
804 d = FROM_SYSBUS(RamDevice, s);
805 d->size = RAM_size;
806 qdev_init_nofail(dev);
807
808 sysbus_mmio_map(s, 0, addr);
809 }
810
811 static Property ram_properties[] = {
812 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
813 DEFINE_PROP_END_OF_LIST(),
814 };
815
816 static void ram_class_init(ObjectClass *klass, void *data)
817 {
818 DeviceClass *dc = DEVICE_CLASS(klass);
819 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
820
821 k->init = ram_init1;
822 dc->props = ram_properties;
823 }
824
825 static const TypeInfo ram_info = {
826 .name = "memory",
827 .parent = TYPE_SYS_BUS_DEVICE,
828 .instance_size = sizeof(RamDevice),
829 .class_init = ram_class_init,
830 };
831
832 static void cpu_devinit(const char *cpu_model, unsigned int id,
833 uint64_t prom_addr, qemu_irq **cpu_irqs)
834 {
835 CPUState *cs;
836 SPARCCPU *cpu;
837 CPUSPARCState *env;
838
839 cpu = cpu_sparc_init(cpu_model);
840 if (cpu == NULL) {
841 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
842 exit(1);
843 }
844 env = &cpu->env;
845
846 cpu_sparc_set_id(env, id);
847 if (id == 0) {
848 qemu_register_reset(main_cpu_reset, cpu);
849 } else {
850 qemu_register_reset(secondary_cpu_reset, cpu);
851 cs = CPU(cpu);
852 cs->halted = 1;
853 }
854 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
855 env->prom_addr = prom_addr;
856 }
857
858 static void dummy_fdc_tc(void *opaque, int irq, int level)
859 {
860 }
861
862 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
863 const char *boot_device,
864 const char *kernel_filename,
865 const char *kernel_cmdline,
866 const char *initrd_filename, const char *cpu_model)
867 {
868 unsigned int i;
869 void *iommu, *espdma, *ledma, *nvram;
870 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
871 espdma_irq, ledma_irq;
872 qemu_irq esp_reset, dma_enable;
873 qemu_irq fdc_tc;
874 qemu_irq *cpu_halt;
875 unsigned long kernel_size;
876 DriveInfo *fd[MAX_FD];
877 void *fw_cfg;
878 unsigned int num_vsimms;
879
880 /* init CPUs */
881 if (!cpu_model)
882 cpu_model = hwdef->default_cpu_model;
883
884 for(i = 0; i < smp_cpus; i++) {
885 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
886 }
887
888 for (i = smp_cpus; i < MAX_CPUS; i++)
889 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
890
891
892 /* set up devices */
893 ram_init(0, RAM_size, hwdef->max_mem);
894 /* models without ECC don't trap when missing ram is accessed */
895 if (!hwdef->ecc_base) {
896 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
897 }
898
899 prom_init(hwdef->slavio_base, bios_name);
900
901 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
902 hwdef->intctl_base + 0x10000ULL,
903 cpu_irqs);
904
905 for (i = 0; i < 32; i++) {
906 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
907 }
908 for (i = 0; i < MAX_CPUS; i++) {
909 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
910 }
911
912 if (hwdef->idreg_base) {
913 idreg_init(hwdef->idreg_base);
914 }
915
916 if (hwdef->afx_base) {
917 afx_init(hwdef->afx_base);
918 }
919
920 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
921 slavio_irq[30]);
922
923 if (hwdef->iommu_pad_base) {
924 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
925 Software shouldn't use aliased addresses, neither should it crash
926 when does. Using empty_slot instead of aliasing can help with
927 debugging such accesses */
928 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
929 }
930
931 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
932 iommu, &espdma_irq, 0);
933
934 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
935 slavio_irq[16], iommu, &ledma_irq, 1);
936
937 if (graphic_depth != 8 && graphic_depth != 24) {
938 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
939 exit (1);
940 }
941 num_vsimms = 0;
942 if (num_vsimms == 0) {
943 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
944 graphic_depth);
945 }
946
947 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
948 /* vsimm registers probed by OBP */
949 if (hwdef->vsimm[i].reg_base) {
950 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
951 }
952 }
953
954 if (hwdef->sx_base) {
955 empty_slot_init(hwdef->sx_base, 0x2000);
956 }
957
958 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
959
960 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
961
962 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
963
964 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
965 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
966 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
967 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
968 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
969 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
970
971 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
972 if (hwdef->apc_base) {
973 apc_init(hwdef->apc_base, cpu_halt[0]);
974 }
975
976 if (hwdef->fd_base) {
977 /* there is zero or one floppy drive */
978 memset(fd, 0, sizeof(fd));
979 fd[0] = drive_get(IF_FLOPPY, 0, 0);
980 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
981 &fdc_tc);
982 } else {
983 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
984 }
985
986 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
987 slavio_irq[30], fdc_tc);
988
989 if (drive_get_max_bus(IF_SCSI) > 0) {
990 fprintf(stderr, "qemu: too many SCSI bus\n");
991 exit(1);
992 }
993
994 esp_init(hwdef->esp_base, 2,
995 espdma_memory_read, espdma_memory_write,
996 espdma, espdma_irq, &esp_reset, &dma_enable);
997
998 qdev_connect_gpio_out(espdma, 0, esp_reset);
999 qdev_connect_gpio_out(espdma, 1, dma_enable);
1000
1001 if (hwdef->cs_base) {
1002 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1003 slavio_irq[5]);
1004 }
1005
1006 if (hwdef->dbri_base) {
1007 /* ISDN chip with attached CS4215 audio codec */
1008 /* prom space */
1009 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1010 /* reg space */
1011 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1012 }
1013
1014 if (hwdef->bpp_base) {
1015 /* parallel port */
1016 empty_slot_init(hwdef->bpp_base, 0x20);
1017 }
1018
1019 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1020 RAM_size);
1021
1022 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1023 boot_device, RAM_size, kernel_size, graphic_width,
1024 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1025 "Sun4m");
1026
1027 if (hwdef->ecc_base)
1028 ecc_init(hwdef->ecc_base, slavio_irq[28],
1029 hwdef->ecc_version);
1030
1031 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1032 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1033 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1034 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1035 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1036 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1037 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1038 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1039 if (kernel_cmdline) {
1040 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1041 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1042 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1043 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1044 strlen(kernel_cmdline) + 1);
1045 } else {
1046 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1047 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1048 }
1049 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1050 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1051 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1052 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1053 }
1054
1055 enum {
1056 ss2_id = 0,
1057 ss5_id = 32,
1058 vger_id,
1059 lx_id,
1060 ss4_id,
1061 scls_id,
1062 sbook_id,
1063 ss10_id = 64,
1064 ss20_id,
1065 ss600mp_id,
1066 ss1000_id = 96,
1067 ss2000_id,
1068 };
1069
1070 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1071 /* SS-5 */
1072 {
1073 .iommu_base = 0x10000000,
1074 .iommu_pad_base = 0x10004000,
1075 .iommu_pad_len = 0x0fffb000,
1076 .tcx_base = 0x50000000,
1077 .cs_base = 0x6c000000,
1078 .slavio_base = 0x70000000,
1079 .ms_kb_base = 0x71000000,
1080 .serial_base = 0x71100000,
1081 .nvram_base = 0x71200000,
1082 .fd_base = 0x71400000,
1083 .counter_base = 0x71d00000,
1084 .intctl_base = 0x71e00000,
1085 .idreg_base = 0x78000000,
1086 .dma_base = 0x78400000,
1087 .esp_base = 0x78800000,
1088 .le_base = 0x78c00000,
1089 .apc_base = 0x6a000000,
1090 .afx_base = 0x6e000000,
1091 .aux1_base = 0x71900000,
1092 .aux2_base = 0x71910000,
1093 .nvram_machine_id = 0x80,
1094 .machine_id = ss5_id,
1095 .iommu_version = 0x05000000,
1096 .max_mem = 0x10000000,
1097 .default_cpu_model = "Fujitsu MB86904",
1098 },
1099 /* SS-10 */
1100 {
1101 .iommu_base = 0xfe0000000ULL,
1102 .tcx_base = 0xe20000000ULL,
1103 .slavio_base = 0xff0000000ULL,
1104 .ms_kb_base = 0xff1000000ULL,
1105 .serial_base = 0xff1100000ULL,
1106 .nvram_base = 0xff1200000ULL,
1107 .fd_base = 0xff1700000ULL,
1108 .counter_base = 0xff1300000ULL,
1109 .intctl_base = 0xff1400000ULL,
1110 .idreg_base = 0xef0000000ULL,
1111 .dma_base = 0xef0400000ULL,
1112 .esp_base = 0xef0800000ULL,
1113 .le_base = 0xef0c00000ULL,
1114 .apc_base = 0xefa000000ULL, // XXX should not exist
1115 .aux1_base = 0xff1800000ULL,
1116 .aux2_base = 0xff1a01000ULL,
1117 .ecc_base = 0xf00000000ULL,
1118 .ecc_version = 0x10000000, // version 0, implementation 1
1119 .nvram_machine_id = 0x72,
1120 .machine_id = ss10_id,
1121 .iommu_version = 0x03000000,
1122 .max_mem = 0xf00000000ULL,
1123 .default_cpu_model = "TI SuperSparc II",
1124 },
1125 /* SS-600MP */
1126 {
1127 .iommu_base = 0xfe0000000ULL,
1128 .tcx_base = 0xe20000000ULL,
1129 .slavio_base = 0xff0000000ULL,
1130 .ms_kb_base = 0xff1000000ULL,
1131 .serial_base = 0xff1100000ULL,
1132 .nvram_base = 0xff1200000ULL,
1133 .counter_base = 0xff1300000ULL,
1134 .intctl_base = 0xff1400000ULL,
1135 .dma_base = 0xef0081000ULL,
1136 .esp_base = 0xef0080000ULL,
1137 .le_base = 0xef0060000ULL,
1138 .apc_base = 0xefa000000ULL, // XXX should not exist
1139 .aux1_base = 0xff1800000ULL,
1140 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1141 .ecc_base = 0xf00000000ULL,
1142 .ecc_version = 0x00000000, // version 0, implementation 0
1143 .nvram_machine_id = 0x71,
1144 .machine_id = ss600mp_id,
1145 .iommu_version = 0x01000000,
1146 .max_mem = 0xf00000000ULL,
1147 .default_cpu_model = "TI SuperSparc II",
1148 },
1149 /* SS-20 */
1150 {
1151 .iommu_base = 0xfe0000000ULL,
1152 .tcx_base = 0xe20000000ULL,
1153 .slavio_base = 0xff0000000ULL,
1154 .ms_kb_base = 0xff1000000ULL,
1155 .serial_base = 0xff1100000ULL,
1156 .nvram_base = 0xff1200000ULL,
1157 .fd_base = 0xff1700000ULL,
1158 .counter_base = 0xff1300000ULL,
1159 .intctl_base = 0xff1400000ULL,
1160 .idreg_base = 0xef0000000ULL,
1161 .dma_base = 0xef0400000ULL,
1162 .esp_base = 0xef0800000ULL,
1163 .le_base = 0xef0c00000ULL,
1164 .bpp_base = 0xef4800000ULL,
1165 .apc_base = 0xefa000000ULL, // XXX should not exist
1166 .aux1_base = 0xff1800000ULL,
1167 .aux2_base = 0xff1a01000ULL,
1168 .dbri_base = 0xee0000000ULL,
1169 .sx_base = 0xf80000000ULL,
1170 .vsimm = {
1171 {
1172 .reg_base = 0x9c000000ULL,
1173 .vram_base = 0xfc000000ULL
1174 }, {
1175 .reg_base = 0x90000000ULL,
1176 .vram_base = 0xf0000000ULL
1177 }, {
1178 .reg_base = 0x94000000ULL
1179 }, {
1180 .reg_base = 0x98000000ULL
1181 }
1182 },
1183 .ecc_base = 0xf00000000ULL,
1184 .ecc_version = 0x20000000, // version 0, implementation 2
1185 .nvram_machine_id = 0x72,
1186 .machine_id = ss20_id,
1187 .iommu_version = 0x13000000,
1188 .max_mem = 0xf00000000ULL,
1189 .default_cpu_model = "TI SuperSparc II",
1190 },
1191 /* Voyager */
1192 {
1193 .iommu_base = 0x10000000,
1194 .tcx_base = 0x50000000,
1195 .slavio_base = 0x70000000,
1196 .ms_kb_base = 0x71000000,
1197 .serial_base = 0x71100000,
1198 .nvram_base = 0x71200000,
1199 .fd_base = 0x71400000,
1200 .counter_base = 0x71d00000,
1201 .intctl_base = 0x71e00000,
1202 .idreg_base = 0x78000000,
1203 .dma_base = 0x78400000,
1204 .esp_base = 0x78800000,
1205 .le_base = 0x78c00000,
1206 .apc_base = 0x71300000, // pmc
1207 .aux1_base = 0x71900000,
1208 .aux2_base = 0x71910000,
1209 .nvram_machine_id = 0x80,
1210 .machine_id = vger_id,
1211 .iommu_version = 0x05000000,
1212 .max_mem = 0x10000000,
1213 .default_cpu_model = "Fujitsu MB86904",
1214 },
1215 /* LX */
1216 {
1217 .iommu_base = 0x10000000,
1218 .iommu_pad_base = 0x10004000,
1219 .iommu_pad_len = 0x0fffb000,
1220 .tcx_base = 0x50000000,
1221 .slavio_base = 0x70000000,
1222 .ms_kb_base = 0x71000000,
1223 .serial_base = 0x71100000,
1224 .nvram_base = 0x71200000,
1225 .fd_base = 0x71400000,
1226 .counter_base = 0x71d00000,
1227 .intctl_base = 0x71e00000,
1228 .idreg_base = 0x78000000,
1229 .dma_base = 0x78400000,
1230 .esp_base = 0x78800000,
1231 .le_base = 0x78c00000,
1232 .aux1_base = 0x71900000,
1233 .aux2_base = 0x71910000,
1234 .nvram_machine_id = 0x80,
1235 .machine_id = lx_id,
1236 .iommu_version = 0x04000000,
1237 .max_mem = 0x10000000,
1238 .default_cpu_model = "TI MicroSparc I",
1239 },
1240 /* SS-4 */
1241 {
1242 .iommu_base = 0x10000000,
1243 .tcx_base = 0x50000000,
1244 .cs_base = 0x6c000000,
1245 .slavio_base = 0x70000000,
1246 .ms_kb_base = 0x71000000,
1247 .serial_base = 0x71100000,
1248 .nvram_base = 0x71200000,
1249 .fd_base = 0x71400000,
1250 .counter_base = 0x71d00000,
1251 .intctl_base = 0x71e00000,
1252 .idreg_base = 0x78000000,
1253 .dma_base = 0x78400000,
1254 .esp_base = 0x78800000,
1255 .le_base = 0x78c00000,
1256 .apc_base = 0x6a000000,
1257 .aux1_base = 0x71900000,
1258 .aux2_base = 0x71910000,
1259 .nvram_machine_id = 0x80,
1260 .machine_id = ss4_id,
1261 .iommu_version = 0x05000000,
1262 .max_mem = 0x10000000,
1263 .default_cpu_model = "Fujitsu MB86904",
1264 },
1265 /* SPARCClassic */
1266 {
1267 .iommu_base = 0x10000000,
1268 .tcx_base = 0x50000000,
1269 .slavio_base = 0x70000000,
1270 .ms_kb_base = 0x71000000,
1271 .serial_base = 0x71100000,
1272 .nvram_base = 0x71200000,
1273 .fd_base = 0x71400000,
1274 .counter_base = 0x71d00000,
1275 .intctl_base = 0x71e00000,
1276 .idreg_base = 0x78000000,
1277 .dma_base = 0x78400000,
1278 .esp_base = 0x78800000,
1279 .le_base = 0x78c00000,
1280 .apc_base = 0x6a000000,
1281 .aux1_base = 0x71900000,
1282 .aux2_base = 0x71910000,
1283 .nvram_machine_id = 0x80,
1284 .machine_id = scls_id,
1285 .iommu_version = 0x05000000,
1286 .max_mem = 0x10000000,
1287 .default_cpu_model = "TI MicroSparc I",
1288 },
1289 /* SPARCbook */
1290 {
1291 .iommu_base = 0x10000000,
1292 .tcx_base = 0x50000000, // XXX
1293 .slavio_base = 0x70000000,
1294 .ms_kb_base = 0x71000000,
1295 .serial_base = 0x71100000,
1296 .nvram_base = 0x71200000,
1297 .fd_base = 0x71400000,
1298 .counter_base = 0x71d00000,
1299 .intctl_base = 0x71e00000,
1300 .idreg_base = 0x78000000,
1301 .dma_base = 0x78400000,
1302 .esp_base = 0x78800000,
1303 .le_base = 0x78c00000,
1304 .apc_base = 0x6a000000,
1305 .aux1_base = 0x71900000,
1306 .aux2_base = 0x71910000,
1307 .nvram_machine_id = 0x80,
1308 .machine_id = sbook_id,
1309 .iommu_version = 0x05000000,
1310 .max_mem = 0x10000000,
1311 .default_cpu_model = "TI MicroSparc I",
1312 },
1313 };
1314
1315 /* SPARCstation 5 hardware initialisation */
1316 static void ss5_init(QEMUMachineInitArgs *args)
1317 {
1318 ram_addr_t RAM_size = args->ram_size;
1319 const char *cpu_model = args->cpu_model;
1320 const char *kernel_filename = args->kernel_filename;
1321 const char *kernel_cmdline = args->kernel_cmdline;
1322 const char *initrd_filename = args->initrd_filename;
1323 const char *boot_device = args->boot_device;
1324 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1325 kernel_cmdline, initrd_filename, cpu_model);
1326 }
1327
1328 /* SPARCstation 10 hardware initialisation */
1329 static void ss10_init(QEMUMachineInitArgs *args)
1330 {
1331 ram_addr_t RAM_size = args->ram_size;
1332 const char *cpu_model = args->cpu_model;
1333 const char *kernel_filename = args->kernel_filename;
1334 const char *kernel_cmdline = args->kernel_cmdline;
1335 const char *initrd_filename = args->initrd_filename;
1336 const char *boot_device = args->boot_device;
1337 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1338 kernel_cmdline, initrd_filename, cpu_model);
1339 }
1340
1341 /* SPARCserver 600MP hardware initialisation */
1342 static void ss600mp_init(QEMUMachineInitArgs *args)
1343 {
1344 ram_addr_t RAM_size = args->ram_size;
1345 const char *cpu_model = args->cpu_model;
1346 const char *kernel_filename = args->kernel_filename;
1347 const char *kernel_cmdline = args->kernel_cmdline;
1348 const char *initrd_filename = args->initrd_filename;
1349 const char *boot_device = args->boot_device;
1350 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1351 kernel_cmdline, initrd_filename, cpu_model);
1352 }
1353
1354 /* SPARCstation 20 hardware initialisation */
1355 static void ss20_init(QEMUMachineInitArgs *args)
1356 {
1357 ram_addr_t RAM_size = args->ram_size;
1358 const char *cpu_model = args->cpu_model;
1359 const char *kernel_filename = args->kernel_filename;
1360 const char *kernel_cmdline = args->kernel_cmdline;
1361 const char *initrd_filename = args->initrd_filename;
1362 const char *boot_device = args->boot_device;
1363 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1364 kernel_cmdline, initrd_filename, cpu_model);
1365 }
1366
1367 /* SPARCstation Voyager hardware initialisation */
1368 static void vger_init(QEMUMachineInitArgs *args)
1369 {
1370 ram_addr_t RAM_size = args->ram_size;
1371 const char *cpu_model = args->cpu_model;
1372 const char *kernel_filename = args->kernel_filename;
1373 const char *kernel_cmdline = args->kernel_cmdline;
1374 const char *initrd_filename = args->initrd_filename;
1375 const char *boot_device = args->boot_device;
1376 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1377 kernel_cmdline, initrd_filename, cpu_model);
1378 }
1379
1380 /* SPARCstation LX hardware initialisation */
1381 static void ss_lx_init(QEMUMachineInitArgs *args)
1382 {
1383 ram_addr_t RAM_size = args->ram_size;
1384 const char *cpu_model = args->cpu_model;
1385 const char *kernel_filename = args->kernel_filename;
1386 const char *kernel_cmdline = args->kernel_cmdline;
1387 const char *initrd_filename = args->initrd_filename;
1388 const char *boot_device = args->boot_device;
1389 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1390 kernel_cmdline, initrd_filename, cpu_model);
1391 }
1392
1393 /* SPARCstation 4 hardware initialisation */
1394 static void ss4_init(QEMUMachineInitArgs *args)
1395 {
1396 ram_addr_t RAM_size = args->ram_size;
1397 const char *cpu_model = args->cpu_model;
1398 const char *kernel_filename = args->kernel_filename;
1399 const char *kernel_cmdline = args->kernel_cmdline;
1400 const char *initrd_filename = args->initrd_filename;
1401 const char *boot_device = args->boot_device;
1402 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1403 kernel_cmdline, initrd_filename, cpu_model);
1404 }
1405
1406 /* SPARCClassic hardware initialisation */
1407 static void scls_init(QEMUMachineInitArgs *args)
1408 {
1409 ram_addr_t RAM_size = args->ram_size;
1410 const char *cpu_model = args->cpu_model;
1411 const char *kernel_filename = args->kernel_filename;
1412 const char *kernel_cmdline = args->kernel_cmdline;
1413 const char *initrd_filename = args->initrd_filename;
1414 const char *boot_device = args->boot_device;
1415 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1416 kernel_cmdline, initrd_filename, cpu_model);
1417 }
1418
1419 /* SPARCbook hardware initialisation */
1420 static void sbook_init(QEMUMachineInitArgs *args)
1421 {
1422 ram_addr_t RAM_size = args->ram_size;
1423 const char *cpu_model = args->cpu_model;
1424 const char *kernel_filename = args->kernel_filename;
1425 const char *kernel_cmdline = args->kernel_cmdline;
1426 const char *initrd_filename = args->initrd_filename;
1427 const char *boot_device = args->boot_device;
1428 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1429 kernel_cmdline, initrd_filename, cpu_model);
1430 }
1431
1432 static QEMUMachine ss5_machine = {
1433 .name = "SS-5",
1434 .desc = "Sun4m platform, SPARCstation 5",
1435 .init = ss5_init,
1436 .block_default_type = IF_SCSI,
1437 .is_default = 1,
1438 DEFAULT_MACHINE_OPTIONS,
1439 };
1440
1441 static QEMUMachine ss10_machine = {
1442 .name = "SS-10",
1443 .desc = "Sun4m platform, SPARCstation 10",
1444 .init = ss10_init,
1445 .block_default_type = IF_SCSI,
1446 .max_cpus = 4,
1447 DEFAULT_MACHINE_OPTIONS,
1448 };
1449
1450 static QEMUMachine ss600mp_machine = {
1451 .name = "SS-600MP",
1452 .desc = "Sun4m platform, SPARCserver 600MP",
1453 .init = ss600mp_init,
1454 .block_default_type = IF_SCSI,
1455 .max_cpus = 4,
1456 DEFAULT_MACHINE_OPTIONS,
1457 };
1458
1459 static QEMUMachine ss20_machine = {
1460 .name = "SS-20",
1461 .desc = "Sun4m platform, SPARCstation 20",
1462 .init = ss20_init,
1463 .block_default_type = IF_SCSI,
1464 .max_cpus = 4,
1465 DEFAULT_MACHINE_OPTIONS,
1466 };
1467
1468 static QEMUMachine voyager_machine = {
1469 .name = "Voyager",
1470 .desc = "Sun4m platform, SPARCstation Voyager",
1471 .init = vger_init,
1472 .block_default_type = IF_SCSI,
1473 DEFAULT_MACHINE_OPTIONS,
1474 };
1475
1476 static QEMUMachine ss_lx_machine = {
1477 .name = "LX",
1478 .desc = "Sun4m platform, SPARCstation LX",
1479 .init = ss_lx_init,
1480 .block_default_type = IF_SCSI,
1481 DEFAULT_MACHINE_OPTIONS,
1482 };
1483
1484 static QEMUMachine ss4_machine = {
1485 .name = "SS-4",
1486 .desc = "Sun4m platform, SPARCstation 4",
1487 .init = ss4_init,
1488 .block_default_type = IF_SCSI,
1489 DEFAULT_MACHINE_OPTIONS,
1490 };
1491
1492 static QEMUMachine scls_machine = {
1493 .name = "SPARCClassic",
1494 .desc = "Sun4m platform, SPARCClassic",
1495 .init = scls_init,
1496 .block_default_type = IF_SCSI,
1497 DEFAULT_MACHINE_OPTIONS,
1498 };
1499
1500 static QEMUMachine sbook_machine = {
1501 .name = "SPARCbook",
1502 .desc = "Sun4m platform, SPARCbook",
1503 .init = sbook_init,
1504 .block_default_type = IF_SCSI,
1505 DEFAULT_MACHINE_OPTIONS,
1506 };
1507
1508 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1509 /* SS-1000 */
1510 {
1511 .iounit_bases = {
1512 0xfe0200000ULL,
1513 0xfe1200000ULL,
1514 0xfe2200000ULL,
1515 0xfe3200000ULL,
1516 -1,
1517 },
1518 .tcx_base = 0x820000000ULL,
1519 .slavio_base = 0xf00000000ULL,
1520 .ms_kb_base = 0xf00240000ULL,
1521 .serial_base = 0xf00200000ULL,
1522 .nvram_base = 0xf00280000ULL,
1523 .counter_base = 0xf00300000ULL,
1524 .espdma_base = 0x800081000ULL,
1525 .esp_base = 0x800080000ULL,
1526 .ledma_base = 0x800040000ULL,
1527 .le_base = 0x800060000ULL,
1528 .sbi_base = 0xf02800000ULL,
1529 .nvram_machine_id = 0x80,
1530 .machine_id = ss1000_id,
1531 .iounit_version = 0x03000000,
1532 .max_mem = 0xf00000000ULL,
1533 .default_cpu_model = "TI SuperSparc II",
1534 },
1535 /* SS-2000 */
1536 {
1537 .iounit_bases = {
1538 0xfe0200000ULL,
1539 0xfe1200000ULL,
1540 0xfe2200000ULL,
1541 0xfe3200000ULL,
1542 0xfe4200000ULL,
1543 },
1544 .tcx_base = 0x820000000ULL,
1545 .slavio_base = 0xf00000000ULL,
1546 .ms_kb_base = 0xf00240000ULL,
1547 .serial_base = 0xf00200000ULL,
1548 .nvram_base = 0xf00280000ULL,
1549 .counter_base = 0xf00300000ULL,
1550 .espdma_base = 0x800081000ULL,
1551 .esp_base = 0x800080000ULL,
1552 .ledma_base = 0x800040000ULL,
1553 .le_base = 0x800060000ULL,
1554 .sbi_base = 0xf02800000ULL,
1555 .nvram_machine_id = 0x80,
1556 .machine_id = ss2000_id,
1557 .iounit_version = 0x03000000,
1558 .max_mem = 0xf00000000ULL,
1559 .default_cpu_model = "TI SuperSparc II",
1560 },
1561 };
1562
1563 static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
1564 {
1565 DeviceState *dev;
1566 SysBusDevice *s;
1567 unsigned int i;
1568
1569 dev = qdev_create(NULL, "sbi");
1570 qdev_init_nofail(dev);
1571
1572 s = SYS_BUS_DEVICE(dev);
1573
1574 for (i = 0; i < MAX_CPUS; i++) {
1575 sysbus_connect_irq(s, i, *parent_irq[i]);
1576 }
1577
1578 sysbus_mmio_map(s, 0, addr);
1579
1580 return dev;
1581 }
1582
1583 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1584 const char *boot_device,
1585 const char *kernel_filename,
1586 const char *kernel_cmdline,
1587 const char *initrd_filename, const char *cpu_model)
1588 {
1589 unsigned int i;
1590 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1591 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1592 espdma_irq, ledma_irq;
1593 qemu_irq esp_reset, dma_enable;
1594 unsigned long kernel_size;
1595 void *fw_cfg;
1596 DeviceState *dev;
1597
1598 /* init CPUs */
1599 if (!cpu_model)
1600 cpu_model = hwdef->default_cpu_model;
1601
1602 for(i = 0; i < smp_cpus; i++) {
1603 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1604 }
1605
1606 for (i = smp_cpus; i < MAX_CPUS; i++)
1607 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1608
1609 /* set up devices */
1610 ram_init(0, RAM_size, hwdef->max_mem);
1611
1612 prom_init(hwdef->slavio_base, bios_name);
1613
1614 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1615
1616 for (i = 0; i < 32; i++) {
1617 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1618 }
1619 for (i = 0; i < MAX_CPUS; i++) {
1620 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1621 }
1622
1623 for (i = 0; i < MAX_IOUNITS; i++)
1624 if (hwdef->iounit_bases[i] != (hwaddr)-1)
1625 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1626 hwdef->iounit_version,
1627 sbi_irq[0]);
1628
1629 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1630 iounits[0], &espdma_irq, 0);
1631
1632 /* should be lebuffer instead */
1633 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1634 iounits[0], &ledma_irq, 0);
1635
1636 if (graphic_depth != 8 && graphic_depth != 24) {
1637 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1638 exit (1);
1639 }
1640 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1641 graphic_depth);
1642
1643 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1644
1645 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1646
1647 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1648
1649 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1650 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1651 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1652 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1653 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1654 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1655
1656 if (drive_get_max_bus(IF_SCSI) > 0) {
1657 fprintf(stderr, "qemu: too many SCSI bus\n");
1658 exit(1);
1659 }
1660
1661 esp_init(hwdef->esp_base, 2,
1662 espdma_memory_read, espdma_memory_write,
1663 espdma, espdma_irq, &esp_reset, &dma_enable);
1664
1665 qdev_connect_gpio_out(espdma, 0, esp_reset);
1666 qdev_connect_gpio_out(espdma, 1, dma_enable);
1667
1668 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1669 RAM_size);
1670
1671 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1672 boot_device, RAM_size, kernel_size, graphic_width,
1673 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1674 "Sun4d");
1675
1676 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1677 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1678 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1679 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1680 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1681 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1682 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1683 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1684 if (kernel_cmdline) {
1685 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1686 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1687 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1688 } else {
1689 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1690 }
1691 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1692 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1693 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1694 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1695 }
1696
1697 /* SPARCserver 1000 hardware initialisation */
1698 static void ss1000_init(QEMUMachineInitArgs *args)
1699 {
1700 ram_addr_t RAM_size = args->ram_size;
1701 const char *cpu_model = args->cpu_model;
1702 const char *kernel_filename = args->kernel_filename;
1703 const char *kernel_cmdline = args->kernel_cmdline;
1704 const char *initrd_filename = args->initrd_filename;
1705 const char *boot_device = args->boot_device;
1706 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1707 kernel_cmdline, initrd_filename, cpu_model);
1708 }
1709
1710 /* SPARCcenter 2000 hardware initialisation */
1711 static void ss2000_init(QEMUMachineInitArgs *args)
1712 {
1713 ram_addr_t RAM_size = args->ram_size;
1714 const char *cpu_model = args->cpu_model;
1715 const char *kernel_filename = args->kernel_filename;
1716 const char *kernel_cmdline = args->kernel_cmdline;
1717 const char *initrd_filename = args->initrd_filename;
1718 const char *boot_device = args->boot_device;
1719 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1720 kernel_cmdline, initrd_filename, cpu_model);
1721 }
1722
1723 static QEMUMachine ss1000_machine = {
1724 .name = "SS-1000",
1725 .desc = "Sun4d platform, SPARCserver 1000",
1726 .init = ss1000_init,
1727 .block_default_type = IF_SCSI,
1728 .max_cpus = 8,
1729 DEFAULT_MACHINE_OPTIONS,
1730 };
1731
1732 static QEMUMachine ss2000_machine = {
1733 .name = "SS-2000",
1734 .desc = "Sun4d platform, SPARCcenter 2000",
1735 .init = ss2000_init,
1736 .block_default_type = IF_SCSI,
1737 .max_cpus = 20,
1738 DEFAULT_MACHINE_OPTIONS,
1739 };
1740
1741 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1742 /* SS-2 */
1743 {
1744 .iommu_base = 0xf8000000,
1745 .tcx_base = 0xfe000000,
1746 .slavio_base = 0xf6000000,
1747 .intctl_base = 0xf5000000,
1748 .counter_base = 0xf3000000,
1749 .ms_kb_base = 0xf0000000,
1750 .serial_base = 0xf1000000,
1751 .nvram_base = 0xf2000000,
1752 .fd_base = 0xf7200000,
1753 .dma_base = 0xf8400000,
1754 .esp_base = 0xf8800000,
1755 .le_base = 0xf8c00000,
1756 .aux1_base = 0xf7400003,
1757 .nvram_machine_id = 0x55,
1758 .machine_id = ss2_id,
1759 .max_mem = 0x10000000,
1760 .default_cpu_model = "Cypress CY7C601",
1761 },
1762 };
1763
1764 static DeviceState *sun4c_intctl_init(hwaddr addr,
1765 qemu_irq *parent_irq)
1766 {
1767 DeviceState *dev;
1768 SysBusDevice *s;
1769 unsigned int i;
1770
1771 dev = qdev_create(NULL, "sun4c_intctl");
1772 qdev_init_nofail(dev);
1773
1774 s = SYS_BUS_DEVICE(dev);
1775
1776 for (i = 0; i < MAX_PILS; i++) {
1777 sysbus_connect_irq(s, i, parent_irq[i]);
1778 }
1779 sysbus_mmio_map(s, 0, addr);
1780
1781 return dev;
1782 }
1783
1784 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1785 const char *boot_device,
1786 const char *kernel_filename,
1787 const char *kernel_cmdline,
1788 const char *initrd_filename, const char *cpu_model)
1789 {
1790 void *iommu, *espdma, *ledma, *nvram;
1791 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1792 qemu_irq esp_reset, dma_enable;
1793 qemu_irq fdc_tc;
1794 unsigned long kernel_size;
1795 DriveInfo *fd[MAX_FD];
1796 void *fw_cfg;
1797 DeviceState *dev;
1798 unsigned int i;
1799
1800 /* init CPU */
1801 if (!cpu_model)
1802 cpu_model = hwdef->default_cpu_model;
1803
1804 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1805
1806 /* set up devices */
1807 ram_init(0, RAM_size, hwdef->max_mem);
1808
1809 prom_init(hwdef->slavio_base, bios_name);
1810
1811 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1812
1813 for (i = 0; i < 8; i++) {
1814 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1815 }
1816
1817 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1818 slavio_irq[1]);
1819
1820 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1821 iommu, &espdma_irq, 0);
1822
1823 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1824 slavio_irq[3], iommu, &ledma_irq, 1);
1825
1826 if (graphic_depth != 8 && graphic_depth != 24) {
1827 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1828 exit (1);
1829 }
1830 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1831 graphic_depth);
1832
1833 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1834
1835 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1836
1837 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1838 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1839 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1840 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1841 escc_init(hwdef->serial_base, slavio_irq[1],
1842 slavio_irq[1], serial_hds[0], serial_hds[1],
1843 ESCC_CLOCK, 1);
1844
1845 if (hwdef->fd_base != (hwaddr)-1) {
1846 /* there is zero or one floppy drive */
1847 memset(fd, 0, sizeof(fd));
1848 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1849 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1850 &fdc_tc);
1851 } else {
1852 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1853 }
1854
1855 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1856
1857 if (drive_get_max_bus(IF_SCSI) > 0) {
1858 fprintf(stderr, "qemu: too many SCSI bus\n");
1859 exit(1);
1860 }
1861
1862 esp_init(hwdef->esp_base, 2,
1863 espdma_memory_read, espdma_memory_write,
1864 espdma, espdma_irq, &esp_reset, &dma_enable);
1865
1866 qdev_connect_gpio_out(espdma, 0, esp_reset);
1867 qdev_connect_gpio_out(espdma, 1, dma_enable);
1868
1869 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1870 RAM_size);
1871
1872 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1873 boot_device, RAM_size, kernel_size, graphic_width,
1874 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1875 "Sun4c");
1876
1877 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1878 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1879 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1880 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1881 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1882 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1883 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1884 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1885 if (kernel_cmdline) {
1886 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1887 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1888 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1889 } else {
1890 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1891 }
1892 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1893 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1894 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1895 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1896 }
1897
1898 /* SPARCstation 2 hardware initialisation */
1899 static void ss2_init(QEMUMachineInitArgs *args)
1900 {
1901 ram_addr_t RAM_size = args->ram_size;
1902 const char *cpu_model = args->cpu_model;
1903 const char *kernel_filename = args->kernel_filename;
1904 const char *kernel_cmdline = args->kernel_cmdline;
1905 const char *initrd_filename = args->initrd_filename;
1906 const char *boot_device = args->boot_device;
1907 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1908 kernel_cmdline, initrd_filename, cpu_model);
1909 }
1910
1911 static QEMUMachine ss2_machine = {
1912 .name = "SS-2",
1913 .desc = "Sun4c platform, SPARCstation 2",
1914 .init = ss2_init,
1915 .block_default_type = IF_SCSI,
1916 DEFAULT_MACHINE_OPTIONS,
1917 };
1918
1919 static void sun4m_register_types(void)
1920 {
1921 type_register_static(&idreg_info);
1922 type_register_static(&afx_info);
1923 type_register_static(&prom_info);
1924 type_register_static(&ram_info);
1925 }
1926
1927 static void ss2_machine_init(void)
1928 {
1929 qemu_register_machine(&ss5_machine);
1930 qemu_register_machine(&ss10_machine);
1931 qemu_register_machine(&ss600mp_machine);
1932 qemu_register_machine(&ss20_machine);
1933 qemu_register_machine(&voyager_machine);
1934 qemu_register_machine(&ss_lx_machine);
1935 qemu_register_machine(&ss4_machine);
1936 qemu_register_machine(&scls_machine);
1937 qemu_register_machine(&sbook_machine);
1938 qemu_register_machine(&ss1000_machine);
1939 qemu_register_machine(&ss2000_machine);
1940 qemu_register_machine(&ss2_machine);
1941 }
1942
1943 type_init(sun4m_register_types)
1944 machine_init(ss2_machine_init);
AR7 emulation for QEMU