target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7
   8 #define CPUArchState struct CPUMIPSState
   9
  10 #include "qemu-common.h"
  11 #include "mips-defs.h"
  12 #include "exec/cpu-defs.h"
  13 #include "fpu/softfloat.h"
  14
  15 struct CPUMIPSState;
  16
  17 typedef struct r4k_tlb_t r4k_tlb_t;
  18 struct r4k_tlb_t {
  19     target_ulong VPN;
  20     uint32_t PageMask;
  21     uint8_t ASID;
  22     unsigned int G:1;
  23     unsigned int C0:3;
  24     unsigned int C1:3;
  25     unsigned int V0:1;
  26     unsigned int V1:1;
  27     unsigned int D0:1;
  28     unsigned int D1:1;
  29     unsigned int XI0:1;
  30     unsigned int XI1:1;
  31     unsigned int RI0:1;
  32     unsigned int RI1:1;
  33     unsigned int EHINV:1;
  34     uint64_t PFN[2];
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  39 struct CPUMIPSTLBContext {
  40     uint32_t nb_tlb;
  41     uint32_t tlb_in_use;
  42     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  43     void (*helper_tlbwi)(struct CPUMIPSState *env);
  44     void (*helper_tlbwr)(struct CPUMIPSState *env);
  45     void (*helper_tlbp)(struct CPUMIPSState *env);
  46     void (*helper_tlbr)(struct CPUMIPSState *env);
  47     void (*helper_tlbinv)(struct CPUMIPSState *env);
  48     void (*helper_tlbinvf)(struct CPUMIPSState *env);
  49     union {
  50         struct {
  51             r4k_tlb_t tlb[MIPS_TLB_MAX];
  52         } r4k;
  53     } mmu;
  54 };
  55 #endif
  56
  57 /* MSA Context */
  58 #define MSA_WRLEN (128)
  59
  60 enum CPUMIPSMSADataFormat {
  61     DF_BYTE = 0,
  62     DF_HALF,
  63     DF_WORD,
  64     DF_DOUBLE
  65 };
  66
  67 typedef union wr_t wr_t;
  68 union wr_t {
  69     int8_t  b[MSA_WRLEN/8];
  70     int16_t h[MSA_WRLEN/16];
  71     int32_t w[MSA_WRLEN/32];
  72     int64_t d[MSA_WRLEN/64];
  73 };
  74
  75 typedef union fpr_t fpr_t;
  76 union fpr_t {
  77     float64  fd;   /* ieee double precision */
  78     float32  fs[2];/* ieee single precision */
  79     uint64_t d;    /* binary double fixed-point */
  80     uint32_t w[2]; /* binary single fixed-point */
  81 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  82     wr_t     wr;   /* vector data */
  83 };
  84 /* define FP_ENDIAN_IDX to access the same location
  85  * in the fpr_t union regardless of the host endianness
  86  */
  87 #if defined(HOST_WORDS_BIGENDIAN)
  88 #  define FP_ENDIAN_IDX 1
  89 #else
  90 #  define FP_ENDIAN_IDX 0
  91 #endif
  92
  93 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  94 struct CPUMIPSFPUContext {
  95     /* Floating point registers */
  96     fpr_t fpr[32];
  97     float_status fp_status;
  98     /* fpu implementation/revision register (fir) */
  99     uint32_t fcr0;
 100 #define FCR0_FREP 29
 101 #define FCR0_UFRP 28
 102 #define FCR0_F64 22
 103 #define FCR0_L 21
 104 #define FCR0_W 20
 105 #define FCR0_3D 19
 106 #define FCR0_PS 18
 107 #define FCR0_D 17
 108 #define FCR0_S 16
 109 #define FCR0_PRID 8
 110 #define FCR0_REV 0
 111     /* fcsr */
 112     uint32_t fcr31;
 113 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 114 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 115 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 116 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 117 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 118 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
 119 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
 120 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
 121 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
 122 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
 123 #define FP_INEXACT        1
 124 #define FP_UNDERFLOW      2
 125 #define FP_OVERFLOW       4
 126 #define FP_DIV0           8
 127 #define FP_INVALID        16
 128 #define FP_UNIMPLEMENTED  32
 129 };
 130
 131 #define NB_MMU_MODES 3
 132 #define TARGET_INSN_START_EXTRA_WORDS 2
 133
 134 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 135 struct CPUMIPSMVPContext {
 136     int32_t CP0_MVPControl;
 137 #define CP0MVPCo_CPA    3
 138 #define CP0MVPCo_STLB   2
 139 #define CP0MVPCo_VPC    1
 140 #define CP0MVPCo_EVP    0
 141     int32_t CP0_MVPConf0;
 142 #define CP0MVPC0_M      31
 143 #define CP0MVPC0_TLBS   29
 144 #define CP0MVPC0_GS     28
 145 #define CP0MVPC0_PCP    27
 146 #define CP0MVPC0_PTLBE  16
 147 #define CP0MVPC0_TCA    15
 148 #define CP0MVPC0_PVPE   10
 149 #define CP0MVPC0_PTC    0
 150     int32_t CP0_MVPConf1;
 151 #define CP0MVPC1_CIM    31
 152 #define CP0MVPC1_CIF    30
 153 #define CP0MVPC1_PCX    20
 154 #define CP0MVPC1_PCP2   10
 155 #define CP0MVPC1_PCP1   0
 156 };
 157
 158 typedef struct mips_def_t mips_def_t;
 159
 160 #define MIPS_SHADOW_SET_MAX 16
 161 #define MIPS_TC_MAX 5
 162 #define MIPS_FPU_MAX 1
 163 #define MIPS_DSP_ACC 4
 164 #define MIPS_KSCRATCH_NUM 6
 165
 166 typedef struct TCState TCState;
 167 struct TCState {
 168     target_ulong gpr[32];
 169     target_ulong PC;
 170     target_ulong HI[MIPS_DSP_ACC];
 171     target_ulong LO[MIPS_DSP_ACC];
 172     target_ulong ACX[MIPS_DSP_ACC];
 173     target_ulong DSPControl;
 174     int32_t CP0_TCStatus;
 175 #define CP0TCSt_TCU3    31
 176 #define CP0TCSt_TCU2    30
 177 #define CP0TCSt_TCU1    29
 178 #define CP0TCSt_TCU0    28
 179 #define CP0TCSt_TMX     27
 180 #define CP0TCSt_RNST    23
 181 #define CP0TCSt_TDS     21
 182 #define CP0TCSt_DT      20
 183 #define CP0TCSt_DA      15
 184 #define CP0TCSt_A       13
 185 #define CP0TCSt_TKSU    11
 186 #define CP0TCSt_IXMT    10
 187 #define CP0TCSt_TASID   0
 188     int32_t CP0_TCBind;
 189 #define CP0TCBd_CurTC   21
 190 #define CP0TCBd_TBE     17
 191 #define CP0TCBd_CurVPE  0
 192     target_ulong CP0_TCHalt;
 193     target_ulong CP0_TCContext;
 194     target_ulong CP0_TCSchedule;
 195     target_ulong CP0_TCScheFBack;
 196     int32_t CP0_Debug_tcstatus;
 197     target_ulong CP0_UserLocal;
 198
 199     int32_t msacsr;
 200
 201 #define MSACSR_FS       24
 202 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 203 #define MSACSR_NX       18
 204 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 205 #define MSACSR_CEF      2
 206 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 207 #define MSACSR_RM       0
 208 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 209 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 210         MSACSR_FS_MASK)
 211
 212     float_status msa_fp_status;
 213 };
 214
 215 typedef struct CPUMIPSState CPUMIPSState;
 216 struct CPUMIPSState {
 217     TCState active_tc;
 218     CPUMIPSFPUContext active_fpu;
 219
 220     uint32_t current_tc;
 221     uint32_t current_fpu;
 222
 223     uint32_t SEGBITS;
 224     uint32_t PABITS;
 225 #if defined(TARGET_MIPS64)
 226 # define PABITS_BASE 36
 227 #else
 228 # define PABITS_BASE 32
 229 #endif
 230     target_ulong SEGMask;
 231     uint64_t PAMask;
 232 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 233
 234     int32_t msair;
 235 #define MSAIR_ProcID    8
 236 #define MSAIR_Rev       0
 237
 238     int32_t CP0_Index;
 239     /* CP0_MVP* are per MVP registers. */
 240     int32_t CP0_Random;
 241     int32_t CP0_VPEControl;
 242 #define CP0VPECo_YSI    21
 243 #define CP0VPECo_GSI    20
 244 #define CP0VPECo_EXCPT  16
 245 #define CP0VPECo_TE     15
 246 #define CP0VPECo_TargTC 0
 247     int32_t CP0_VPEConf0;
 248 #define CP0VPEC0_M      31
 249 #define CP0VPEC0_XTC    21
 250 #define CP0VPEC0_TCS    19
 251 #define CP0VPEC0_SCS    18
 252 #define CP0VPEC0_DSC    17
 253 #define CP0VPEC0_ICS    16
 254 #define CP0VPEC0_MVP    1
 255 #define CP0VPEC0_VPA    0
 256     int32_t CP0_VPEConf1;
 257 #define CP0VPEC1_NCX    20
 258 #define CP0VPEC1_NCP2   10
 259 #define CP0VPEC1_NCP1   0
 260     target_ulong CP0_YQMask;
 261     target_ulong CP0_VPESchedule;
 262     target_ulong CP0_VPEScheFBack;
 263     int32_t CP0_VPEOpt;
 264 #define CP0VPEOpt_IWX7  15
 265 #define CP0VPEOpt_IWX6  14
 266 #define CP0VPEOpt_IWX5  13
 267 #define CP0VPEOpt_IWX4  12
 268 #define CP0VPEOpt_IWX3  11
 269 #define CP0VPEOpt_IWX2  10
 270 #define CP0VPEOpt_IWX1  9
 271 #define CP0VPEOpt_IWX0  8
 272 #define CP0VPEOpt_DWX7  7
 273 #define CP0VPEOpt_DWX6  6
 274 #define CP0VPEOpt_DWX5  5
 275 #define CP0VPEOpt_DWX4  4
 276 #define CP0VPEOpt_DWX3  3
 277 #define CP0VPEOpt_DWX2  2
 278 #define CP0VPEOpt_DWX1  1
 279 #define CP0VPEOpt_DWX0  0
 280     uint64_t CP0_EntryLo0;
 281     uint64_t CP0_EntryLo1;
 282 #if defined(TARGET_MIPS64)
 283 # define CP0EnLo_RI 63
 284 # define CP0EnLo_XI 62
 285 #else
 286 # define CP0EnLo_RI 31
 287 # define CP0EnLo_XI 30
 288 #endif
 289     target_ulong CP0_Context;
 290     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 291     int32_t CP0_PageMask;
 292     int32_t CP0_PageGrain_rw_bitmask;
 293     int32_t CP0_PageGrain;
 294 #define CP0PG_RIE 31
 295 #define CP0PG_XIE 30
 296 #define CP0PG_ELPA 29
 297 #define CP0PG_IEC 27
 298     int32_t CP0_Wired;
 299     int32_t CP0_SRSConf0_rw_bitmask;
 300     int32_t CP0_SRSConf0;
 301 #define CP0SRSC0_M      31
 302 #define CP0SRSC0_SRS3   20
 303 #define CP0SRSC0_SRS2   10
 304 #define CP0SRSC0_SRS1   0
 305     int32_t CP0_SRSConf1_rw_bitmask;
 306     int32_t CP0_SRSConf1;
 307 #define CP0SRSC1_M      31
 308 #define CP0SRSC1_SRS6   20
 309 #define CP0SRSC1_SRS5   10
 310 #define CP0SRSC1_SRS4   0
 311     int32_t CP0_SRSConf2_rw_bitmask;
 312     int32_t CP0_SRSConf2;
 313 #define CP0SRSC2_M      31
 314 #define CP0SRSC2_SRS9   20
 315 #define CP0SRSC2_SRS8   10
 316 #define CP0SRSC2_SRS7   0
 317     int32_t CP0_SRSConf3_rw_bitmask;
 318     int32_t CP0_SRSConf3;
 319 #define CP0SRSC3_M      31
 320 #define CP0SRSC3_SRS12  20
 321 #define CP0SRSC3_SRS11  10
 322 #define CP0SRSC3_SRS10  0
 323     int32_t CP0_SRSConf4_rw_bitmask;
 324     int32_t CP0_SRSConf4;
 325 #define CP0SRSC4_SRS15  20
 326 #define CP0SRSC4_SRS14  10
 327 #define CP0SRSC4_SRS13  0
 328     int32_t CP0_HWREna;
 329     target_ulong CP0_BadVAddr;
 330     uint32_t CP0_BadInstr;
 331     uint32_t CP0_BadInstrP;
 332     int32_t CP0_Count;
 333     target_ulong CP0_EntryHi;
 334 #define CP0EnHi_EHINV 10
 335     int32_t CP0_Compare;
 336     int32_t CP0_Status;
 337 #define CP0St_CU3   31
 338 #define CP0St_CU2   30
 339 #define CP0St_CU1   29
 340 #define CP0St_CU0   28
 341 #define CP0St_RP    27
 342 #define CP0St_FR    26
 343 #define CP0St_RE    25
 344 #define CP0St_MX    24
 345 #define CP0St_PX    23
 346 #define CP0St_BEV   22
 347 #define CP0St_TS    21
 348 #define CP0St_SR    20
 349 #define CP0St_NMI   19
 350 #define CP0St_IM    8
 351 #define CP0St_KX    7
 352 #define CP0St_SX    6
 353 #define CP0St_UX    5
 354 #define CP0St_KSU   3
 355 #define CP0St_ERL   2
 356 #define CP0St_EXL   1
 357 #define CP0St_IE    0
 358     int32_t CP0_IntCtl;
 359 #define CP0IntCtl_IPTI 29
 360 #define CP0IntCtl_IPPCI 26
 361 #define CP0IntCtl_VS 5
 362     int32_t CP0_SRSCtl;
 363 #define CP0SRSCtl_HSS 26
 364 #define CP0SRSCtl_EICSS 18
 365 #define CP0SRSCtl_ESS 12
 366 #define CP0SRSCtl_PSS 6
 367 #define CP0SRSCtl_CSS 0
 368     int32_t CP0_SRSMap;
 369 #define CP0SRSMap_SSV7 28
 370 #define CP0SRSMap_SSV6 24
 371 #define CP0SRSMap_SSV5 20
 372 #define CP0SRSMap_SSV4 16
 373 #define CP0SRSMap_SSV3 12
 374 #define CP0SRSMap_SSV2 8
 375 #define CP0SRSMap_SSV1 4
 376 #define CP0SRSMap_SSV0 0
 377     int32_t CP0_Cause;
 378 #define CP0Ca_BD   31
 379 #define CP0Ca_TI   30
 380 #define CP0Ca_CE   28
 381 #define CP0Ca_DC   27
 382 #define CP0Ca_PCI  26
 383 #define CP0Ca_IV   23
 384 #define CP0Ca_WP   22
 385 #define CP0Ca_IP    8
 386 #define CP0Ca_IP_mask 0x0000FF00
 387 #define CP0Ca_EC    2
 388     target_ulong CP0_EPC;
 389     int32_t CP0_PRid;
 390     int32_t CP0_EBase;
 391     int32_t CP0_Config0;
 392 #define CP0C0_M    31
 393 #define CP0C0_K23  28
 394 #define CP0C0_KU   25
 395 #define CP0C0_MDU  20
 396 #define CP0C0_MM   18
 397 #define CP0C0_BM   16
 398 #define CP0C0_BE   15
 399 #define CP0C0_AT   13
 400 #define CP0C0_AR   10
 401 #define CP0C0_MT   7
 402 #define CP0C0_VI   3
 403 #define CP0C0_K0   0
 404     int32_t CP0_Config1;
 405 #define CP0C1_M    31
 406 #define CP0C1_MMU  25
 407 #define CP0C1_IS   22
 408 #define CP0C1_IL   19
 409 #define CP0C1_IA   16
 410 #define CP0C1_DS   13
 411 #define CP0C1_DL   10
 412 #define CP0C1_DA   7
 413 #define CP0C1_C2   6
 414 #define CP0C1_MD   5
 415 #define CP0C1_PC   4
 416 #define CP0C1_WR   3
 417 #define CP0C1_CA   2
 418 #define CP0C1_EP   1
 419 #define CP0C1_FP   0
 420     int32_t CP0_Config2;
 421 #define CP0C2_M    31
 422 #define CP0C2_TU   28
 423 #define CP0C2_TS   24
 424 #define CP0C2_TL   20
 425 #define CP0C2_TA   16
 426 #define CP0C2_SU   12
 427 #define CP0C2_SS   8
 428 #define CP0C2_SL   4
 429 #define CP0C2_SA   0
 430     int32_t CP0_Config3;
 431 #define CP0C3_M    31
 432 #define CP0C3_BPG  30
 433 #define CP0C3_CMCGR 29
 434 #define CP0C3_MSAP  28
 435 #define CP0C3_BP 27
 436 #define CP0C3_BI 26
 437 #define CP0C3_IPLW 21
 438 #define CP0C3_MMAR 18
 439 #define CP0C3_MCU  17
 440 #define CP0C3_ISA_ON_EXC 16
 441 #define CP0C3_ISA  14
 442 #define CP0C3_ULRI 13
 443 #define CP0C3_RXI  12
 444 #define CP0C3_DSP2P 11
 445 #define CP0C3_DSPP 10
 446 #define CP0C3_LPA  7
 447 #define CP0C3_VEIC 6
 448 #define CP0C3_VInt 5
 449 #define CP0C3_SP   4
 450 #define CP0C3_CDMM 3
 451 #define CP0C3_MT   2
 452 #define CP0C3_SM   1
 453 #define CP0C3_TL   0
 454     int32_t CP0_Config4;
 455     int32_t CP0_Config4_rw_bitmask;
 456 #define CP0C4_M    31
 457 #define CP0C4_IE   29
 458 #define CP0C4_KScrExist 16
 459 #define CP0C4_MMUExtDef 14
 460 #define CP0C4_FTLBPageSize 8
 461 #define CP0C4_FTLBWays 4
 462 #define CP0C4_FTLBSets 0
 463 #define CP0C4_MMUSizeExt 0
 464     int32_t CP0_Config5;
 465     int32_t CP0_Config5_rw_bitmask;
 466 #define CP0C5_M          31
 467 #define CP0C5_K          30
 468 #define CP0C5_CV         29
 469 #define CP0C5_EVA        28
 470 #define CP0C5_MSAEn      27
 471 #define CP0C5_XNP        13
 472 #define CP0C5_UFE        9
 473 #define CP0C5_FRE        8
 474 #define CP0C5_SBRI       6
 475 #define CP0C5_MVH        5
 476 #define CP0C5_LLB        4
 477 #define CP0C5_UFR        2
 478 #define CP0C5_NFExists   0
 479     int32_t CP0_Config6;
 480     int32_t CP0_Config7;
 481     /* XXX: Maybe make LLAddr per-TC? */
 482     uint64_t lladdr;
 483     target_ulong llval;
 484     target_ulong llnewval;
 485     target_ulong llreg;
 486     uint64_t CP0_LLAddr_rw_bitmask;
 487     int CP0_LLAddr_shift;
 488     target_ulong CP0_WatchLo[8];
 489     int32_t CP0_WatchHi[8];
 490     target_ulong CP0_XContext;
 491     int32_t CP0_Framemask;
 492     int32_t CP0_Debug;
 493 #define CP0DB_DBD  31
 494 #define CP0DB_DM   30
 495 #define CP0DB_LSNM 28
 496 #define CP0DB_Doze 27
 497 #define CP0DB_Halt 26
 498 #define CP0DB_CNT  25
 499 #define CP0DB_IBEP 24
 500 #define CP0DB_DBEP 21
 501 #define CP0DB_IEXI 20
 502 #define CP0DB_VER  15
 503 #define CP0DB_DEC  10
 504 #define CP0DB_SSt  8
 505 #define CP0DB_DINT 5
 506 #define CP0DB_DIB  4
 507 #define CP0DB_DDBS 3
 508 #define CP0DB_DDBL 2
 509 #define CP0DB_DBp  1
 510 #define CP0DB_DSS  0
 511     target_ulong CP0_DEPC;
 512     int32_t CP0_Performance0;
 513     uint64_t CP0_TagLo;
 514     int32_t CP0_DataLo;
 515     int32_t CP0_TagHi;
 516     int32_t CP0_DataHi;
 517     target_ulong CP0_ErrorEPC;
 518     int32_t CP0_DESAVE;
 519     /* We waste some space so we can handle shadow registers like TCs. */
 520     TCState tcs[MIPS_SHADOW_SET_MAX];
 521     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 522     /* QEMU */
 523     int error_code;
 524 #define EXCP_TLB_NOMATCH   0x1
 525 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 526     uint32_t hflags;    /* CPU State */
 527     /* TMASK defines different execution modes */
 528 #define MIPS_HFLAG_TMASK  0x75807FF
 529 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 530     /* The KSU flags must be the lowest bits in hflags. The flag order
 531        must be the same as defined for CP0 Status. This allows to use
 532        the bits as the value of mmu_idx. */
 533 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 534 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 535 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 536 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 537 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 538 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 539 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 540 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 541 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 542     /* True if the MIPS IV COP1X instructions can be used.  This also
 543        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 544        and RSQRT.D.  */
 545 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 546 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 547 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 548 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 549 #define MIPS_HFLAG_M16_SHIFT 10
 550     /* If translation is interrupted between the branch instruction and
 551      * the delay slot, record what type of branch it is so that we can
 552      * resume translation properly.  It might be possible to reduce
 553      * this from three bits to two.  */
 554 #define MIPS_HFLAG_BMASK_BASE  0x803800
 555 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 556 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 557 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 558 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 559     /* Extra flags about the current pending branch.  */
 560 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 561 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 562 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 563 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 564 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 565 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 566 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 567     /* MIPS DSP resources access. */
 568 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 569 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
 570     /* Extra flag about HWREna register. */
 571 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 572 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 573 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 574 #define MIPS_HFLAG_MSA   0x1000000
 575 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
 576 #define MIPS_HFLAG_ELPA  0x4000000
 577     target_ulong btarget;        /* Jump / branch target               */
 578     target_ulong bcond;          /* Branch condition (if needed)       */
 579
 580     int SYNCI_Step; /* Address step size for SYNCI */
 581     int CCRes; /* Cycle count resolution/divisor */
 582     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 583     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 584     int insn_flags; /* Supported instruction set */
 585
 586     CPU_COMMON
 587
 588     /* Fields from here on are preserved across CPU reset. */
 589     CPUMIPSMVPContext *mvp;
 590 #if !defined(CONFIG_USER_ONLY)
 591     CPUMIPSTLBContext *tlb;
 592 #endif
 593
 594     const mips_def_t *cpu_model;
 595     void *irq[8];
 596     QEMUTimer *timer; /* Internal timer */
 597 };
 598
 599 #include "cpu-qom.h"
 600
 601 #if !defined(CONFIG_USER_ONLY)
 602 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 603                         target_ulong address, int rw, int access_type);
 604 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 605                            target_ulong address, int rw, int access_type);
 606 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 607                      target_ulong address, int rw, int access_type);
 608 void r4k_helper_tlbwi(CPUMIPSState *env);
 609 void r4k_helper_tlbwr(CPUMIPSState *env);
 610 void r4k_helper_tlbp(CPUMIPSState *env);
 611 void r4k_helper_tlbr(CPUMIPSState *env);
 612 void r4k_helper_tlbinv(CPUMIPSState *env);
 613 void r4k_helper_tlbinvf(CPUMIPSState *env);
 614
 615 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 616                                 bool is_write, bool is_exec, int unused,
 617                                 unsigned size);
 618 #endif
 619
 620 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 621
 622 #define cpu_exec cpu_mips_exec
 623 #define cpu_signal_handler cpu_mips_signal_handler
 624 #define cpu_list mips_cpu_list
 625
 626 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 627 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 628
 629 /* MMU modes definitions. We carefully match the indices with our
 630    hflags layout. */
 631 #define MMU_MODE0_SUFFIX _kernel
 632 #define MMU_MODE1_SUFFIX _super
 633 #define MMU_MODE2_SUFFIX _user
 634 #define MMU_USER_IDX 2
 635 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 636 {
 637     return env->hflags & MIPS_HFLAG_KSU;
 638 }
 639
 640 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 641 {
 642     return (env->CP0_Status & (1 << CP0St_IE)) &&
 643         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 644         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 645         !(env->hflags & MIPS_HFLAG_DM) &&
 646         /* Note that the TCStatus IXMT field is initialized to zero,
 647            and only MT capable cores can set it to one. So we don't
 648            need to check for MT capabilities here.  */
 649         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 650 }
 651
 652 /* Check if there is pending and not masked out interrupt */
 653 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 654 {
 655     int32_t pending;
 656     int32_t status;
 657     bool r;
 658
 659     pending = env->CP0_Cause & CP0Ca_IP_mask;
 660     status = env->CP0_Status & CP0Ca_IP_mask;
 661
 662     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 663         /* A MIPS configured with a vectorizing external interrupt controller
 664            will feed a vector into the Cause pending lines. The core treats
 665            the status lines as a vector level, not as indiviual masks.  */
 666         r = pending > status;
 667     } else {
 668         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 669            treats the pending lines as individual interrupt lines, the status
 670            lines are individual masks.  */
 671         r = (pending & status) != 0;
 672     }
 673     return r;
 674 }
 675
 676 #include "exec/cpu-all.h"
 677
 678 /* Memory access type :
 679  * may be needed for precise access rights control and precise exceptions.
 680  */
 681 enum {
 682     /* 1 bit to define user level / supervisor access */
 683     ACCESS_USER  = 0x00,
 684     ACCESS_SUPER = 0x01,
 685     /* 1 bit to indicate direction */
 686     ACCESS_STORE = 0x02,
 687     /* Type of instruction that generated the access */
 688     ACCESS_CODE  = 0x10, /* Code fetch access                */
 689     ACCESS_INT   = 0x20, /* Integer load/store access        */
 690     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 691 };
 692
 693 /* Exceptions */
 694 enum {
 695     EXCP_NONE          = -1,
 696     EXCP_RESET         = 0,
 697     EXCP_SRESET,
 698     EXCP_DSS,
 699     EXCP_DINT,
 700     EXCP_DDBL,
 701     EXCP_DDBS,
 702     EXCP_NMI,
 703     EXCP_MCHECK,
 704     EXCP_EXT_INTERRUPT, /* 8 */
 705     EXCP_DFWATCH,
 706     EXCP_DIB,
 707     EXCP_IWATCH,
 708     EXCP_AdEL,
 709     EXCP_AdES,
 710     EXCP_TLBF,
 711     EXCP_IBE,
 712     EXCP_DBp, /* 16 */
 713     EXCP_SYSCALL,
 714     EXCP_BREAK,
 715     EXCP_CpU,
 716     EXCP_RI,
 717     EXCP_OVERFLOW,
 718     EXCP_TRAP,
 719     EXCP_FPE,
 720     EXCP_DWATCH, /* 24 */
 721     EXCP_LTLBL,
 722     EXCP_TLBL,
 723     EXCP_TLBS,
 724     EXCP_DBE,
 725     EXCP_THREAD,
 726     EXCP_MDMX,
 727     EXCP_C2E,
 728     EXCP_CACHE, /* 32 */
 729     EXCP_DSPDIS,
 730     EXCP_MSADIS,
 731     EXCP_MSAFPE,
 732     EXCP_TLBXI,
 733     EXCP_TLBRI,
 734
 735     EXCP_LAST = EXCP_TLBRI,
 736 };
 737 /* Dummy exception for conditional stores.  */
 738 #define EXCP_SC 0x100
 739
 740 /*
 741  * This is an interrnally generated WAKE request line.
 742  * It is driven by the CPU itself. Raised when the MT
 743  * block wants to wake a VPE from an inactive state and
 744  * cleared when VPE goes from active to inactive.
 745  */
 746 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 747
 748 int cpu_mips_exec(CPUState *cpu);
 749 void mips_tcg_init(void);
 750 MIPSCPU *cpu_mips_init(const char *cpu_model);
 751 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 752
 753 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
 754
 755 /* TODO QOM'ify CPU reset and remove */
 756 void cpu_state_reset(CPUMIPSState *s);
 757
 758 /* mips_timer.c */
 759 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 760 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 761 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 762 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 763 void cpu_mips_start_count(CPUMIPSState *env);
 764 void cpu_mips_stop_count(CPUMIPSState *env);
 765
 766 /* mips_int.c */
 767 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 768
 769 /* helper.c */
 770 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 771                               int mmu_idx);
 772 #if !defined(CONFIG_USER_ONLY)
 773 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 774 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 775                                                int rw);
 776 #endif
 777 target_ulong exception_resume_pc (CPUMIPSState *env);
 778
 779 /* op_helper.c */
 780 extern unsigned int ieee_rm[];
 781 int ieee_ex_to_mips(int xcpt);
 782
 783 static inline void restore_rounding_mode(CPUMIPSState *env)
 784 {
 785     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 786                             &env->active_fpu.fp_status);
 787 }
 788
 789 static inline void restore_flush_mode(CPUMIPSState *env)
 790 {
 791     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
 792                       &env->active_fpu.fp_status);
 793 }
 794
 795 static inline void restore_fp_status(CPUMIPSState *env)
 796 {
 797     restore_rounding_mode(env);
 798     restore_flush_mode(env);
 799 }
 800
 801 static inline void restore_msa_fp_status(CPUMIPSState *env)
 802 {
 803     float_status *status = &env->active_tc.msa_fp_status;
 804     int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
 805     bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
 806
 807     set_float_rounding_mode(ieee_rm[rounding_mode], status);
 808     set_flush_to_zero(flush_to_zero, status);
 809     set_flush_inputs_to_zero(flush_to_zero, status);
 810 }
 811
 812 static inline void restore_pamask(CPUMIPSState *env)
 813 {
 814     if (env->hflags & MIPS_HFLAG_ELPA) {
 815         env->PAMask = (1ULL << env->PABITS) - 1;
 816     } else {
 817         env->PAMask = PAMASK_BASE;
 818     }
 819 }
 820
 821 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 822                                         target_ulong *cs_base, int *flags)
 823 {
 824     *pc = env->active_tc.PC;
 825     *cs_base = 0;
 826     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 827                             MIPS_HFLAG_HWRENA_ULR);
 828 }
 829
 830 static inline int mips_vpe_active(CPUMIPSState *env)
 831 {
 832     int active = 1;
 833
 834     /* Check that the VPE is enabled.  */
 835     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 836         active = 0;
 837     }
 838     /* Check that the VPE is activated.  */
 839     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 840         active = 0;
 841     }
 842
 843     /* Now verify that there are active thread contexts in the VPE.
 844
 845        This assumes the CPU model will internally reschedule threads
 846        if the active one goes to sleep. If there are no threads available
 847        the active one will be in a sleeping state, and we can turn off
 848        the entire VPE.  */
 849     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 850         /* TC is not activated.  */
 851         active = 0;
 852     }
 853     if (env->active_tc.CP0_TCHalt & 1) {
 854         /* TC is in halt state.  */
 855         active = 0;
 856     }
 857
 858     return active;
 859 }
 860
 861 #include "exec/exec-all.h"
 862
 863 static inline void compute_hflags(CPUMIPSState *env)
 864 {
 865     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 866                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 867                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 868                      MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
 869                      MIPS_HFLAG_ELPA);
 870     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 871         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 872         !(env->hflags & MIPS_HFLAG_DM)) {
 873         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 874     }
 875 #if defined(TARGET_MIPS64)
 876     if ((env->insn_flags & ISA_MIPS3) &&
 877         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 878          (env->CP0_Status & (1 << CP0St_PX)) ||
 879          (env->CP0_Status & (1 << CP0St_UX)))) {
 880         env->hflags |= MIPS_HFLAG_64;
 881     }
 882
 883     if (!(env->insn_flags & ISA_MIPS3)) {
 884         env->hflags |= MIPS_HFLAG_AWRAP;
 885     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 886                !(env->CP0_Status & (1 << CP0St_UX))) {
 887         env->hflags |= MIPS_HFLAG_AWRAP;
 888     } else if (env->insn_flags & ISA_MIPS64R6) {
 889         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 890         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 891              !(env->CP0_Status & (1 << CP0St_SX))) ||
 892             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 893              !(env->CP0_Status & (1 << CP0St_KX)))) {
 894             env->hflags |= MIPS_HFLAG_AWRAP;
 895         }
 896     }
 897 #endif
 898     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 899          !(env->insn_flags & ISA_MIPS32R6)) ||
 900         !(env->hflags & MIPS_HFLAG_KSU)) {
 901         env->hflags |= MIPS_HFLAG_CP0;
 902     }
 903     if (env->CP0_Status & (1 << CP0St_CU1)) {
 904         env->hflags |= MIPS_HFLAG_FPU;
 905     }
 906     if (env->CP0_Status & (1 << CP0St_FR)) {
 907         env->hflags |= MIPS_HFLAG_F64;
 908     }
 909     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 910         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 911         env->hflags |= MIPS_HFLAG_SBRI;
 912     }
 913     if (env->insn_flags & ASE_DSPR2) {
 914         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 915            so enable to access DSPR2 resources. */
 916         if (env->CP0_Status & (1 << CP0St_MX)) {
 917             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 918         }
 919
 920     } else if (env->insn_flags & ASE_DSP) {
 921         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 922            so enable to access DSP resources. */
 923         if (env->CP0_Status & (1 << CP0St_MX)) {
 924             env->hflags |= MIPS_HFLAG_DSP;
 925         }
 926
 927     }
 928     if (env->insn_flags & ISA_MIPS32R2) {
 929         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 930             env->hflags |= MIPS_HFLAG_COP1X;
 931         }
 932     } else if (env->insn_flags & ISA_MIPS32) {
 933         if (env->hflags & MIPS_HFLAG_64) {
 934             env->hflags |= MIPS_HFLAG_COP1X;
 935         }
 936     } else if (env->insn_flags & ISA_MIPS4) {
 937         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 938            and disable the MIPS IV extensions to the MIPS III ISA.
 939            Some other MIPS IV CPUs ignore the bit, so the check here
 940            would be too restrictive for them.  */
 941         if (env->CP0_Status & (1U << CP0St_CU3)) {
 942             env->hflags |= MIPS_HFLAG_COP1X;
 943         }
 944     }
 945     if (env->insn_flags & ASE_MSA) {
 946         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 947             env->hflags |= MIPS_HFLAG_MSA;
 948         }
 949     }
 950     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 951         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 952             env->hflags |= MIPS_HFLAG_FRE;
 953         }
 954     }
 955     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 956         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 957             env->hflags |= MIPS_HFLAG_ELPA;
 958         }
 959     }
 960 }
 961
 962 #ifndef CONFIG_USER_ONLY
 963 static inline void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
 964 {
 965     MIPSCPU *cpu = mips_env_get_cpu(env);
 966
 967     /* Flush qemu's TLB and discard all shadowed entries.  */
 968     tlb_flush(CPU(cpu), flush_global);
 969     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 970 }
 971
 972 /* Called for updates to CP0_Status.  */
 973 static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 974 {
 975     int32_t tcstatus, *tcst;
 976     uint32_t v = cpu->CP0_Status;
 977     uint32_t cu, mx, asid, ksu;
 978     uint32_t mask = ((1 << CP0TCSt_TCU3)
 979                        | (1 << CP0TCSt_TCU2)
 980                        | (1 << CP0TCSt_TCU1)
 981                        | (1 << CP0TCSt_TCU0)
 982                        | (1 << CP0TCSt_TMX)
 983                        | (3 << CP0TCSt_TKSU)
 984                        | (0xff << CP0TCSt_TASID));
 985
 986     cu = (v >> CP0St_CU0) & 0xf;
 987     mx = (v >> CP0St_MX) & 0x1;
 988     ksu = (v >> CP0St_KSU) & 0x3;
 989     asid = env->CP0_EntryHi & 0xff;
 990
 991     tcstatus = cu << CP0TCSt_TCU0;
 992     tcstatus |= mx << CP0TCSt_TMX;
 993     tcstatus |= ksu << CP0TCSt_TKSU;
 994     tcstatus |= asid;
 995
 996     if (tc == cpu->current_tc) {
 997         tcst = &cpu->active_tc.CP0_TCStatus;
 998     } else {
 999         tcst = &cpu->tcs[tc].CP0_TCStatus;
1000     }
1001
1002     *tcst &= ~mask;
1003     *tcst |= tcstatus;
1004     compute_hflags(cpu);
1005 }
1006
1007 static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
1008 {
1009     uint32_t mask = env->CP0_Status_rw_bitmask;
1010     target_ulong old = env->CP0_Status;
1011
1012     if (env->insn_flags & ISA_MIPS32R6) {
1013         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
1014 #if defined(TARGET_MIPS64)
1015         uint32_t ksux = (1 << CP0St_KX) & val;
1016         ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
1017         ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
1018         val = (val & ~(7 << CP0St_UX)) | ksux;
1019 #endif
1020         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
1021             mask &= ~(3 << CP0St_KSU);
1022         }
1023         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
1024     }
1025
1026     env->CP0_Status = (old & ~mask) | (val & mask);
1027 #if defined(TARGET_MIPS64)
1028     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
1029         /* Access to at least one of the 64-bit segments has been disabled */
1030         cpu_mips_tlb_flush(env, 1);
1031     }
1032 #endif
1033     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1034         sync_c0_status(env, env, env->current_tc);
1035     } else {
1036         compute_hflags(env);
1037     }
1038 }
1039
1040 static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
1041 {
1042     uint32_t mask = 0x00C00300;
1043     uint32_t old = env->CP0_Cause;
1044     int i;
1045
1046     if (env->insn_flags & ISA_MIPS32R2) {
1047         mask |= 1 << CP0Ca_DC;
1048     }
1049     if (env->insn_flags & ISA_MIPS32R6) {
1050         mask &= ~((1 << CP0Ca_WP) & val);
1051     }
1052
1053     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
1054
1055     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1056         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
1057             cpu_mips_stop_count(env);
1058         } else {
1059             cpu_mips_start_count(env);
1060         }
1061     }
1062
1063     /* Set/reset software interrupts */
1064     for (i = 0 ; i < 2 ; i++) {
1065         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1066             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
1067         }
1068     }
1069 }
1070 #endif
1071
1072 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
1073                                                         uint32_t exception,
1074                                                         int error_code,
1075                                                         uintptr_t pc)
1076 {
1077     CPUState *cs = CPU(mips_env_get_cpu(env));
1078
1079     if (exception < EXCP_SC) {
1080         qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
1081                       __func__, exception, error_code);
1082     }
1083     cs->exception_index = exception;
1084     env->error_code = error_code;
1085
1086     cpu_loop_exit_restore(cs, pc);
1087 }
1088
1089 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
1090                                                     uint32_t exception,
1091                                                     uintptr_t pc)
1092 {
1093     do_raise_exception_err(env, exception, 0, pc);
1094 }
1095
1096 #endif /* !defined (__MIPS_CPU_H__) */