hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers
[qemu/ar7.git] / linux-user / aarch64 / target_syscall.h
blob76f6c3391d338421641dac895ed0a8b06bea1f49
1 #ifndef AARCH64_TARGET_SYSCALL_H
2 #define AARCH64_TARGET_SYSCALL_H
4 struct target_pt_regs {
5 uint64_t regs[31];
6 uint64_t sp;
7 uint64_t pc;
8 uint64_t pstate;
9 };
11 #if defined(TARGET_WORDS_BIGENDIAN)
12 #define UNAME_MACHINE "aarch64_be"
13 #else
14 #define UNAME_MACHINE "aarch64"
15 #endif
16 #define UNAME_MINIMUM_RELEASE "3.8.0"
17 #define TARGET_CLONE_BACKWARDS
18 #define TARGET_MINSIGSTKSZ 2048
19 #define TARGET_MCL_CURRENT 1
20 #define TARGET_MCL_FUTURE 2
21 #define TARGET_MCL_ONFAULT 4
23 #define TARGET_PR_SVE_SET_VL 50
24 #define TARGET_PR_SVE_GET_VL 51
26 #define TARGET_PR_PAC_RESET_KEYS 54
27 # define TARGET_PR_PAC_APIAKEY (1 << 0)
28 # define TARGET_PR_PAC_APIBKEY (1 << 1)
29 # define TARGET_PR_PAC_APDAKEY (1 << 2)
30 # define TARGET_PR_PAC_APDBKEY (1 << 3)
31 # define TARGET_PR_PAC_APGAKEY (1 << 4)
33 #define TARGET_PR_SET_TAGGED_ADDR_CTRL 55
34 #define TARGET_PR_GET_TAGGED_ADDR_CTRL 56
35 # define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0)
36 /* MTE tag check fault modes */
37 # define TARGET_PR_MTE_TCF_SHIFT 1
38 # define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT)
39 # define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT)
40 # define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT)
41 # define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT)
42 /* MTE tag inclusion mask */
43 # define TARGET_PR_MTE_TAG_SHIFT 3
44 # define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT)
46 #endif /* AARCH64_TARGET_SYSCALL_H */