hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 /* debug PIC */
  31 //#define DEBUG_PIC
  32
  33 #ifdef DEBUG_PIC
  34 #define DPRINTF(fmt, ...)                                       \
  35     do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 //#define DEBUG_IRQ_LATENCY
  41 //#define DEBUG_IRQ_COUNT
  42
  43 typedef struct PicState {
  44     uint8_t last_irr; /* edge detection */
  45     uint8_t irr; /* interrupt request register */
  46     uint8_t imr; /* interrupt mask register */
  47     uint8_t isr; /* interrupt service register */
  48     uint8_t priority_add; /* highest irq priority */
  49     uint8_t irq_base;
  50     uint8_t read_reg_select;
  51     uint8_t poll;
  52     uint8_t special_mask;
  53     uint8_t init_state;
  54     uint8_t auto_eoi;
  55     uint8_t rotate_on_auto_eoi;
  56     uint8_t special_fully_nested_mode;
  57     uint8_t init4; /* true if 4 byte init */
  58     uint8_t single_mode; /* true if slave pic is not initialized */
  59     uint8_t elcr; /* PIIX edge/trigger selection*/
  60     uint8_t elcr_mask;
  61     qemu_irq int_out;
  62     PicState2 *pics_state;
  63     MemoryRegion base_io;
  64     MemoryRegion elcr_io;
  65 } PicState;
  66
  67 struct PicState2 {
  68     /* 0 is master pic, 1 is slave pic */
  69     /* XXX: better separation between the two pics */
  70     PicState pics[2];
  71     void *irq_request_opaque;
  72 };
  73
  74 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  75 static int irq_level[16];
  76 #endif
  77 #ifdef DEBUG_IRQ_COUNT
  78 static uint64_t irq_count[16];
  79 #endif
  80 PicState2 *isa_pic;
  81
  82 /* return the highest priority found in mask (highest = smallest
  83    number). Return 8 if no irq */
  84 static int get_priority(PicState *s, int mask)
  85 {
  86     int priority;
  87     if (mask == 0)
  88         return 8;
  89     priority = 0;
  90     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  91         priority++;
  92     return priority;
  93 }
  94
  95 /* return the pic wanted interrupt. return -1 if none */
  96 static int pic_get_irq(PicState *s)
  97 {
  98     int mask, cur_priority, priority;
  99
 100     mask = s->irr & ~s->imr;
 101     priority = get_priority(s, mask);
 102     if (priority == 8)
 103         return -1;
 104     /* compute current priority. If special fully nested mode on the
 105        master, the IRQ coming from the slave is not taken into account
 106        for the priority computation. */
 107     mask = s->isr;
 108     if (s->special_mask)
 109         mask &= ~s->imr;
 110     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 111         mask &= ~(1 << 2);
 112     cur_priority = get_priority(s, mask);
 113     if (priority < cur_priority) {
 114         /* higher priority found: an irq should be generated */
 115         return (priority + s->priority_add) & 7;
 116     } else {
 117         return -1;
 118     }
 119 }
 120
 121 /* Update INT output. Must be called every time the output may have changed. */
 122 static void pic_update_irq(PicState *s)
 123 {
 124     int irq;
 125
 126     irq = pic_get_irq(s);
 127     if (irq >= 0) {
 128         DPRINTF("pic%d: imr=%x irr=%x padd=%d\n",
 129                 s == &s->pics_state->pics[0] ? 0 : 1, s->imr, s->irr,
 130                 s->priority_add);
 131         qemu_irq_raise(s->int_out);
 132     } else {
 133         qemu_irq_lower(s->int_out);
 134     }
 135 }
 136
 137 /* set irq level. If an edge is detected, then the IRR is set to 1 */
 138 static void pic_set_irq1(PicState *s, int irq, int level)
 139 {
 140     int mask;
 141     mask = 1 << irq;
 142     if (s->elcr & mask) {
 143         /* level triggered */
 144         if (level) {
 145             s->irr |= mask;
 146             s->last_irr |= mask;
 147         } else {
 148             s->irr &= ~mask;
 149             s->last_irr &= ~mask;
 150         }
 151     } else {
 152         /* edge triggered */
 153         if (level) {
 154             if ((s->last_irr & mask) == 0) {
 155                 s->irr |= mask;
 156             }
 157             s->last_irr |= mask;
 158         } else {
 159             s->last_irr &= ~mask;
 160         }
 161     }
 162     pic_update_irq(s);
 163 }
 164
 165 #ifdef DEBUG_IRQ_LATENCY
 166 int64_t irq_time[16];
 167 #endif
 168
 169 static void i8259_set_irq(void *opaque, int irq, int level)
 170 {
 171     PicState2 *s = opaque;
 172
 173 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 174     if (level != irq_level[irq]) {
 175         DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
 176         irq_level[irq] = level;
 177 #ifdef DEBUG_IRQ_COUNT
 178         if (level == 1)
 179             irq_count[irq]++;
 180 #endif
 181     }
 182 #endif
 183 #ifdef DEBUG_IRQ_LATENCY
 184     if (level) {
 185         irq_time[irq] = qemu_get_clock_ns(vm_clock);
 186     }
 187 #endif
 188     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 189 }
 190
 191 /* acknowledge interrupt 'irq' */
 192 static void pic_intack(PicState *s, int irq)
 193 {
 194     if (s->auto_eoi) {
 195         if (s->rotate_on_auto_eoi)
 196             s->priority_add = (irq + 1) & 7;
 197     } else {
 198         s->isr |= (1 << irq);
 199     }
 200     /* We don't clear a level sensitive interrupt here */
 201     if (!(s->elcr & (1 << irq)))
 202         s->irr &= ~(1 << irq);
 203     pic_update_irq(s);
 204 }
 205
 206 int pic_read_irq(PicState2 *s)
 207 {
 208     int irq, irq2, intno;
 209
 210     irq = pic_get_irq(&s->pics[0]);
 211     if (irq >= 0) {
 212         if (irq == 2) {
 213             irq2 = pic_get_irq(&s->pics[1]);
 214             if (irq2 >= 0) {
 215                 pic_intack(&s->pics[1], irq2);
 216             } else {
 217                 /* spurious IRQ on slave controller */
 218                 irq2 = 7;
 219             }
 220             intno = s->pics[1].irq_base + irq2;
 221         } else {
 222             intno = s->pics[0].irq_base + irq;
 223         }
 224         pic_intack(&s->pics[0], irq);
 225     } else {
 226         /* spurious IRQ on host controller */
 227         irq = 7;
 228         intno = s->pics[0].irq_base + irq;
 229     }
 230
 231 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
 232     if (irq == 2) {
 233         irq = irq2 + 8;
 234     }
 235 #endif
 236 #ifdef DEBUG_IRQ_LATENCY
 237     printf("IRQ%d latency=%0.3fus\n",
 238            irq,
 239            (double)(qemu_get_clock_ns(vm_clock) -
 240                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 241 #endif
 242     DPRINTF("pic_interrupt: irq=%d\n", irq);
 243     return intno;
 244 }
 245
 246 static void pic_init_reset(PicState *s)
 247 {
 248     s->last_irr = 0;
 249     s->irr = 0;
 250     s->imr = 0;
 251     s->isr = 0;
 252     s->priority_add = 0;
 253     s->irq_base = 0;
 254     s->read_reg_select = 0;
 255     s->poll = 0;
 256     s->special_mask = 0;
 257     s->init_state = 0;
 258     s->auto_eoi = 0;
 259     s->rotate_on_auto_eoi = 0;
 260     s->special_fully_nested_mode = 0;
 261     s->init4 = 0;
 262     s->single_mode = 0;
 263     /* Note: ELCR is not reset */
 264     pic_update_irq(s);
 265 }
 266
 267 static void pic_reset(void *opaque)
 268 {
 269     PicState *s = opaque;
 270
 271     pic_init_reset(s);
 272     s->elcr = 0;
 273 }
 274
 275 static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
 276                              uint64_t val64, unsigned size)
 277 {
 278     PicState *s = opaque;
 279     uint32_t addr = addr64;
 280     uint32_t val = val64;
 281     int priority, cmd, irq;
 282
 283     DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
 284     if (addr == 0) {
 285         if (val & 0x10) {
 286             pic_init_reset(s);
 287             s->init_state = 1;
 288             s->init4 = val & 1;
 289             s->single_mode = val & 2;
 290             if (val & 0x08)
 291                 hw_error("level sensitive irq not supported");
 292         } else if (val & 0x08) {
 293             if (val & 0x04)
 294                 s->poll = 1;
 295             if (val & 0x02)
 296                 s->read_reg_select = val & 1;
 297             if (val & 0x40)
 298                 s->special_mask = (val >> 5) & 1;
 299         } else {
 300             cmd = val >> 5;
 301             switch(cmd) {
 302             case 0:
 303             case 4:
 304                 s->rotate_on_auto_eoi = cmd >> 2;
 305                 break;
 306             case 1: /* end of interrupt */
 307             case 5:
 308                 priority = get_priority(s, s->isr);
 309                 if (priority != 8) {
 310                     irq = (priority + s->priority_add) & 7;
 311                     s->isr &= ~(1 << irq);
 312                     if (cmd == 5)
 313                         s->priority_add = (irq + 1) & 7;
 314                     pic_update_irq(s);
 315                 }
 316                 break;
 317             case 3:
 318                 irq = val & 7;
 319                 s->isr &= ~(1 << irq);
 320                 pic_update_irq(s);
 321                 break;
 322             case 6:
 323                 s->priority_add = (val + 1) & 7;
 324                 pic_update_irq(s);
 325                 break;
 326             case 7:
 327                 irq = val & 7;
 328                 s->isr &= ~(1 << irq);
 329                 s->priority_add = (irq + 1) & 7;
 330                 pic_update_irq(s);
 331                 break;
 332             default:
 333                 /* no operation */
 334                 break;
 335             }
 336         }
 337     } else {
 338         switch(s->init_state) {
 339         case 0:
 340             /* normal mode */
 341             s->imr = val;
 342             pic_update_irq(s);
 343             break;
 344         case 1:
 345             s->irq_base = val & 0xf8;
 346             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 347             break;
 348         case 2:
 349             if (s->init4) {
 350                 s->init_state = 3;
 351             } else {
 352                 s->init_state = 0;
 353             }
 354             break;
 355         case 3:
 356             s->special_fully_nested_mode = (val >> 4) & 1;
 357             s->auto_eoi = (val >> 1) & 1;
 358             s->init_state = 0;
 359             break;
 360         }
 361     }
 362 }
 363
 364 static uint32_t pic_poll_read(PicState *s)
 365 {
 366     int ret;
 367
 368     ret = pic_get_irq(s);
 369     if (ret >= 0) {
 370         bool slave = (s == &isa_pic->pics[1]);
 371
 372         if (slave) {
 373             s->pics_state->pics[0].isr &= ~(1 << 2);
 374             s->pics_state->pics[0].irr &= ~(1 << 2);
 375         }
 376         s->irr &= ~(1 << ret);
 377         s->isr &= ~(1 << ret);
 378         if (slave || ret != 2) {
 379             pic_update_irq(s);
 380         }
 381     } else {
 382         ret = 0x07;
 383     }
 384
 385     return ret;
 386 }
 387
 388 static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1,
 389                                 unsigned size)
 390 {
 391     PicState *s = opaque;
 392     unsigned int addr = addr1;
 393     int ret;
 394
 395     if (s->poll) {
 396         ret = pic_get_irq(s);
 397         if (ret >= 0) {
 398             pic_intack(s, ret);
 399             ret |= 0x80;
 400         } else {
 401             ret = 0;
 402         }
 403         s->poll = 0;
 404     } else {
 405         if (addr == 0) {
 406             if (s->read_reg_select)
 407                 ret = s->isr;
 408             else
 409                 ret = s->irr;
 410         } else {
 411             ret = s->imr;
 412         }
 413     }
 414     DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
 415     return ret;
 416 }
 417
 418 /* memory mapped interrupt status */
 419 /* XXX: may be the same than pic_read_irq() */
 420 uint32_t pic_intack_read(PicState2 *s)
 421 {
 422     int ret;
 423
 424     ret = pic_poll_read(&s->pics[0]);
 425     if (ret == 2)
 426         ret = pic_poll_read(&s->pics[1]) + 8;
 427     /* Prepare for ISR read */
 428     s->pics[0].read_reg_select = 1;
 429
 430     return ret;
 431 }
 432
 433 int pic_get_output(PicState2 *s)
 434 {
 435     return (pic_get_irq(&s->pics[0]) >= 0);
 436 }
 437
 438 static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
 439                               uint64_t val, unsigned size)
 440 {
 441     PicState *s = opaque;
 442     s->elcr = val & s->elcr_mask;
 443 }
 444
 445 static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
 446                                  unsigned size)
 447 {
 448     PicState *s = opaque;
 449     return s->elcr;
 450 }
 451
 452 static const VMStateDescription vmstate_pic = {
 453     .name = "i8259",
 454     .version_id = 1,
 455     .minimum_version_id = 1,
 456     .minimum_version_id_old = 1,
 457     .fields      = (VMStateField []) {
 458         VMSTATE_UINT8(last_irr, PicState),
 459         VMSTATE_UINT8(irr, PicState),
 460         VMSTATE_UINT8(imr, PicState),
 461         VMSTATE_UINT8(isr, PicState),
 462         VMSTATE_UINT8(priority_add, PicState),
 463         VMSTATE_UINT8(irq_base, PicState),
 464         VMSTATE_UINT8(read_reg_select, PicState),
 465         VMSTATE_UINT8(poll, PicState),
 466         VMSTATE_UINT8(special_mask, PicState),
 467         VMSTATE_UINT8(init_state, PicState),
 468         VMSTATE_UINT8(auto_eoi, PicState),
 469         VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
 470         VMSTATE_UINT8(special_fully_nested_mode, PicState),
 471         VMSTATE_UINT8(init4, PicState),
 472         VMSTATE_UINT8(single_mode, PicState),
 473         VMSTATE_UINT8(elcr, PicState),
 474         VMSTATE_END_OF_LIST()
 475     }
 476 };
 477
 478 static const MemoryRegionOps pic_base_ioport_ops = {
 479     .read = pic_ioport_read,
 480     .write = pic_ioport_write,
 481     .impl = {
 482         .min_access_size = 1,
 483         .max_access_size = 1,
 484     },
 485 };
 486
 487 static const MemoryRegionOps pic_elcr_ioport_ops = {
 488     .read = elcr_ioport_read,
 489     .write = elcr_ioport_write,
 490     .impl = {
 491         .min_access_size = 1,
 492         .max_access_size = 1,
 493     },
 494 };
 495
 496 /* XXX: add generic master/slave system */
 497 static void pic_init(int io_addr, int elcr_addr, PicState *s, qemu_irq int_out)
 498 {
 499     s->int_out = int_out;
 500
 501     memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
 502     memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
 503
 504     isa_register_ioport(NULL, &s->base_io, io_addr);
 505     if (elcr_addr >= 0) {
 506         isa_register_ioport(NULL, &s->elcr_io, elcr_addr);
 507     }
 508
 509     vmstate_register(NULL, io_addr, &vmstate_pic, s);
 510     qemu_register_reset(pic_reset, s);
 511 }
 512
 513 void pic_info(Monitor *mon)
 514 {
 515     int i;
 516     PicState *s;
 517
 518     if (!isa_pic)
 519         return;
 520
 521     for(i=0;i<2;i++) {
 522         s = &isa_pic->pics[i];
 523         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 524                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 525                        i, s->irr, s->imr, s->isr, s->priority_add,
 526                        s->irq_base, s->read_reg_select, s->elcr,
 527                        s->special_fully_nested_mode);
 528     }
 529 }
 530
 531 void irq_info(Monitor *mon)
 532 {
 533 #ifndef DEBUG_IRQ_COUNT
 534     monitor_printf(mon, "irq statistic code not compiled.\n");
 535 #else
 536     int i;
 537     int64_t count;
 538
 539     monitor_printf(mon, "IRQ statistics:\n");
 540     for (i = 0; i < 16; i++) {
 541         count = irq_count[i];
 542         if (count > 0)
 543             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 544     }
 545 #endif
 546 }
 547
 548 qemu_irq *i8259_init(qemu_irq parent_irq)
 549 {
 550     qemu_irq *irqs;
 551     PicState2 *s;
 552
 553     s = g_malloc0(sizeof(PicState2));
 554     irqs = qemu_allocate_irqs(i8259_set_irq, s, 16);
 555     pic_init(0x20, 0x4d0, &s->pics[0], parent_irq);
 556     pic_init(0xa0, 0x4d1, &s->pics[1], irqs[2]);
 557     s->pics[0].elcr_mask = 0xf8;
 558     s->pics[1].elcr_mask = 0xde;
 559     s->pics[0].pics_state = s;
 560     s->pics[1].pics_state = s;
 561     isa_pic = s;
 562     return irqs;
 563 }