2 * TI OMAP processors GPIO emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "hw/arm/omap.h"
23 #include "hw/sysbus.h"
38 #define TYPE_OMAP1_GPIO "omap-gpio"
39 #define OMAP1_GPIO(obj) \
40 OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
43 SysBusDevice parent_obj
;
48 struct omap_gpio_s omap1
;
51 /* General-Purpose I/O of OMAP1 */
52 static void omap_gpio_set(void *opaque
, int line
, int level
)
54 struct omap_gpio_s
*s
= &((struct omap_gpif_s
*) opaque
)->omap1
;
55 uint16_t prev
= s
->inputs
;
58 s
->inputs
|= 1 << line
;
60 s
->inputs
&= ~(1 << line
);
62 if (((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) &
63 (1 << line
) & s
->dir
& ~s
->mask
) {
65 qemu_irq_raise(s
->irq
);
69 static uint64_t omap_gpio_read(void *opaque
, hwaddr addr
,
72 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
73 int offset
= addr
& OMAP_MPUI_REG_MASK
;
76 return omap_badwidth_read16(opaque
, addr
);
80 case 0x00: /* DATA_INPUT */
81 return s
->inputs
& s
->pins
;
83 case 0x04: /* DATA_OUTPUT */
86 case 0x08: /* DIRECTION_CONTROL */
89 case 0x0c: /* INTERRUPT_CONTROL */
92 case 0x10: /* INTERRUPT_MASK */
95 case 0x14: /* INTERRUPT_STATUS */
98 case 0x18: /* PIN_CONTROL (not in OMAP310) */
107 static void omap_gpio_write(void *opaque
, hwaddr addr
,
108 uint64_t value
, unsigned size
)
110 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
111 int offset
= addr
& OMAP_MPUI_REG_MASK
;
116 omap_badwidth_write16(opaque
, addr
, value
);
121 case 0x00: /* DATA_INPUT */
125 case 0x04: /* DATA_OUTPUT */
126 diff
= (s
->outputs
^ value
) & ~s
->dir
;
128 while ((ln
= ffs(diff
))) {
131 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
136 case 0x08: /* DIRECTION_CONTROL */
137 diff
= s
->outputs
& (s
->dir
^ value
);
140 value
= s
->outputs
& ~s
->dir
;
141 while ((ln
= ffs(diff
))) {
144 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
149 case 0x0c: /* INTERRUPT_CONTROL */
153 case 0x10: /* INTERRUPT_MASK */
157 case 0x14: /* INTERRUPT_STATUS */
160 qemu_irq_lower(s
->irq
);
163 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
174 /* *Some* sources say the memory region is 32-bit. */
175 static const MemoryRegionOps omap_gpio_ops
= {
176 .read
= omap_gpio_read
,
177 .write
= omap_gpio_write
,
178 .endianness
= DEVICE_NATIVE_ENDIAN
,
181 static void omap_gpio_reset(struct omap_gpio_s
*s
)
192 struct omap2_gpio_s
{
212 #define TYPE_OMAP2_GPIO "omap2-gpio"
213 #define OMAP2_GPIO(obj) \
214 OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
216 struct omap2_gpif_s
{
217 SysBusDevice parent_obj
;
224 struct omap2_gpio_s
*modules
;
230 /* General-Purpose Interface of OMAP2/3 */
231 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s
*s
,
234 qemu_set_irq(s
->irq
[line
], s
->ints
[line
] & s
->mask
[line
]);
237 static void omap2_gpio_module_wake(struct omap2_gpio_s
*s
, int line
)
239 if (!(s
->config
[0] & (1 << 2))) /* ENAWAKEUP */
241 if (!(s
->config
[0] & (3 << 3))) /* Force Idle */
243 if (!(s
->wumask
& (1 << line
)))
246 qemu_irq_raise(s
->wkup
);
249 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s
*s
,
256 while ((ln
= ffs(diff
))) {
258 qemu_set_irq(s
->handler
[ln
], (s
->outputs
>> ln
) & 1);
263 static void omap2_gpio_module_level_update(struct omap2_gpio_s
*s
, int line
)
265 s
->ints
[line
] |= s
->dir
&
266 ((s
->inputs
& s
->level
[1]) | (~s
->inputs
& s
->level
[0]));
267 omap2_gpio_module_int_update(s
, line
);
270 static inline void omap2_gpio_module_int(struct omap2_gpio_s
*s
, int line
)
272 s
->ints
[0] |= 1 << line
;
273 omap2_gpio_module_int_update(s
, 0);
274 s
->ints
[1] |= 1 << line
;
275 omap2_gpio_module_int_update(s
, 1);
276 omap2_gpio_module_wake(s
, line
);
279 static void omap2_gpio_set(void *opaque
, int line
, int level
)
281 struct omap2_gpif_s
*p
= opaque
;
282 struct omap2_gpio_s
*s
= &p
->modules
[line
>> 5];
286 if (s
->dir
& (1 << line
) & ((~s
->inputs
& s
->edge
[0]) | s
->level
[1]))
287 omap2_gpio_module_int(s
, line
);
288 s
->inputs
|= 1 << line
;
290 if (s
->dir
& (1 << line
) & ((s
->inputs
& s
->edge
[1]) | s
->level
[0]))
291 omap2_gpio_module_int(s
, line
);
292 s
->inputs
&= ~(1 << line
);
296 static void omap2_gpio_module_reset(struct omap2_gpio_s
*s
)
314 static uint32_t omap2_gpio_module_read(void *opaque
, hwaddr addr
)
316 struct omap2_gpio_s
*s
= (struct omap2_gpio_s
*) opaque
;
319 case 0x00: /* GPIO_REVISION */
322 case 0x10: /* GPIO_SYSCONFIG */
325 case 0x14: /* GPIO_SYSSTATUS */
328 case 0x18: /* GPIO_IRQSTATUS1 */
331 case 0x1c: /* GPIO_IRQENABLE1 */
332 case 0x60: /* GPIO_CLEARIRQENABLE1 */
333 case 0x64: /* GPIO_SETIRQENABLE1 */
336 case 0x20: /* GPIO_WAKEUPENABLE */
337 case 0x80: /* GPIO_CLEARWKUENA */
338 case 0x84: /* GPIO_SETWKUENA */
341 case 0x28: /* GPIO_IRQSTATUS2 */
344 case 0x2c: /* GPIO_IRQENABLE2 */
345 case 0x70: /* GPIO_CLEARIRQENABLE2 */
346 case 0x74: /* GPIO_SETIREQNEABLE2 */
349 case 0x30: /* GPIO_CTRL */
352 case 0x34: /* GPIO_OE */
355 case 0x38: /* GPIO_DATAIN */
358 case 0x3c: /* GPIO_DATAOUT */
359 case 0x90: /* GPIO_CLEARDATAOUT */
360 case 0x94: /* GPIO_SETDATAOUT */
363 case 0x40: /* GPIO_LEVELDETECT0 */
366 case 0x44: /* GPIO_LEVELDETECT1 */
369 case 0x48: /* GPIO_RISINGDETECT */
372 case 0x4c: /* GPIO_FALLINGDETECT */
375 case 0x50: /* GPIO_DEBOUNCENABLE */
378 case 0x54: /* GPIO_DEBOUNCINGTIME */
386 static void omap2_gpio_module_write(void *opaque
, hwaddr addr
,
389 struct omap2_gpio_s
*s
= (struct omap2_gpio_s
*) opaque
;
394 case 0x00: /* GPIO_REVISION */
395 case 0x14: /* GPIO_SYSSTATUS */
396 case 0x38: /* GPIO_DATAIN */
400 case 0x10: /* GPIO_SYSCONFIG */
401 if (((value
>> 3) & 3) == 3)
402 fprintf(stderr
, "%s: bad IDLEMODE value\n", __FUNCTION__
);
404 omap2_gpio_module_reset(s
);
405 s
->config
[0] = value
& 0x1d;
408 case 0x18: /* GPIO_IRQSTATUS1 */
409 if (s
->ints
[0] & value
) {
410 s
->ints
[0] &= ~value
;
411 omap2_gpio_module_level_update(s
, 0);
415 case 0x1c: /* GPIO_IRQENABLE1 */
417 omap2_gpio_module_int_update(s
, 0);
420 case 0x20: /* GPIO_WAKEUPENABLE */
424 case 0x28: /* GPIO_IRQSTATUS2 */
425 if (s
->ints
[1] & value
) {
426 s
->ints
[1] &= ~value
;
427 omap2_gpio_module_level_update(s
, 1);
431 case 0x2c: /* GPIO_IRQENABLE2 */
433 omap2_gpio_module_int_update(s
, 1);
436 case 0x30: /* GPIO_CTRL */
437 s
->config
[1] = value
& 7;
440 case 0x34: /* GPIO_OE */
441 diff
= s
->outputs
& (s
->dir
^ value
);
444 value
= s
->outputs
& ~s
->dir
;
445 while ((ln
= ffs(diff
))) {
446 diff
&= ~(1 <<-- ln
);
447 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
450 omap2_gpio_module_level_update(s
, 0);
451 omap2_gpio_module_level_update(s
, 1);
454 case 0x3c: /* GPIO_DATAOUT */
455 omap2_gpio_module_out_update(s
, s
->outputs
^ value
);
458 case 0x40: /* GPIO_LEVELDETECT0 */
460 omap2_gpio_module_level_update(s
, 0);
461 omap2_gpio_module_level_update(s
, 1);
464 case 0x44: /* GPIO_LEVELDETECT1 */
466 omap2_gpio_module_level_update(s
, 0);
467 omap2_gpio_module_level_update(s
, 1);
470 case 0x48: /* GPIO_RISINGDETECT */
474 case 0x4c: /* GPIO_FALLINGDETECT */
478 case 0x50: /* GPIO_DEBOUNCENABLE */
482 case 0x54: /* GPIO_DEBOUNCINGTIME */
486 case 0x60: /* GPIO_CLEARIRQENABLE1 */
487 s
->mask
[0] &= ~value
;
488 omap2_gpio_module_int_update(s
, 0);
491 case 0x64: /* GPIO_SETIRQENABLE1 */
493 omap2_gpio_module_int_update(s
, 0);
496 case 0x70: /* GPIO_CLEARIRQENABLE2 */
497 s
->mask
[1] &= ~value
;
498 omap2_gpio_module_int_update(s
, 1);
501 case 0x74: /* GPIO_SETIREQNEABLE2 */
503 omap2_gpio_module_int_update(s
, 1);
506 case 0x80: /* GPIO_CLEARWKUENA */
510 case 0x84: /* GPIO_SETWKUENA */
514 case 0x90: /* GPIO_CLEARDATAOUT */
515 omap2_gpio_module_out_update(s
, s
->outputs
& value
);
518 case 0x94: /* GPIO_SETDATAOUT */
519 omap2_gpio_module_out_update(s
, ~s
->outputs
& value
);
528 static uint32_t omap2_gpio_module_readp(void *opaque
, hwaddr addr
)
530 return omap2_gpio_module_read(opaque
, addr
& ~3) >> ((addr
& 3) << 3);
533 static void omap2_gpio_module_writep(void *opaque
, hwaddr addr
,
537 uint32_t mask
= 0xffff;
540 case 0x00: /* GPIO_REVISION */
541 case 0x14: /* GPIO_SYSSTATUS */
542 case 0x38: /* GPIO_DATAIN */
546 case 0x10: /* GPIO_SYSCONFIG */
547 case 0x1c: /* GPIO_IRQENABLE1 */
548 case 0x20: /* GPIO_WAKEUPENABLE */
549 case 0x2c: /* GPIO_IRQENABLE2 */
550 case 0x30: /* GPIO_CTRL */
551 case 0x34: /* GPIO_OE */
552 case 0x3c: /* GPIO_DATAOUT */
553 case 0x40: /* GPIO_LEVELDETECT0 */
554 case 0x44: /* GPIO_LEVELDETECT1 */
555 case 0x48: /* GPIO_RISINGDETECT */
556 case 0x4c: /* GPIO_FALLINGDETECT */
557 case 0x50: /* GPIO_DEBOUNCENABLE */
558 case 0x54: /* GPIO_DEBOUNCINGTIME */
559 cur
= omap2_gpio_module_read(opaque
, addr
& ~3) &
560 ~(mask
<< ((addr
& 3) << 3));
563 case 0x18: /* GPIO_IRQSTATUS1 */
564 case 0x28: /* GPIO_IRQSTATUS2 */
565 case 0x60: /* GPIO_CLEARIRQENABLE1 */
566 case 0x64: /* GPIO_SETIRQENABLE1 */
567 case 0x70: /* GPIO_CLEARIRQENABLE2 */
568 case 0x74: /* GPIO_SETIREQNEABLE2 */
569 case 0x80: /* GPIO_CLEARWKUENA */
570 case 0x84: /* GPIO_SETWKUENA */
571 case 0x90: /* GPIO_CLEARDATAOUT */
572 case 0x94: /* GPIO_SETDATAOUT */
573 value
<<= (addr
& 3) << 3;
574 omap2_gpio_module_write(opaque
, addr
, cur
| value
);
583 static const MemoryRegionOps omap2_gpio_module_ops
= {
586 omap2_gpio_module_readp
,
587 omap2_gpio_module_readp
,
588 omap2_gpio_module_read
,
591 omap2_gpio_module_writep
,
592 omap2_gpio_module_writep
,
593 omap2_gpio_module_write
,
596 .endianness
= DEVICE_NATIVE_ENDIAN
,
599 static void omap_gpif_reset(DeviceState
*dev
)
601 struct omap_gpif_s
*s
= OMAP1_GPIO(dev
);
603 omap_gpio_reset(&s
->omap1
);
606 static void omap2_gpif_reset(DeviceState
*dev
)
608 struct omap2_gpif_s
*s
= OMAP2_GPIO(dev
);
611 for (i
= 0; i
< s
->modulecount
; i
++) {
612 omap2_gpio_module_reset(&s
->modules
[i
]);
618 static uint64_t omap2_gpif_top_read(void *opaque
, hwaddr addr
,
621 struct omap2_gpif_s
*s
= (struct omap2_gpif_s
*) opaque
;
624 case 0x00: /* IPGENERICOCPSPL_REVISION */
627 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
630 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
633 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
636 case 0x40: /* IPGENERICOCPSPL_GPO */
639 case 0x50: /* IPGENERICOCPSPL_GPI */
647 static void omap2_gpif_top_write(void *opaque
, hwaddr addr
,
648 uint64_t value
, unsigned size
)
650 struct omap2_gpif_s
*s
= (struct omap2_gpif_s
*) opaque
;
653 case 0x00: /* IPGENERICOCPSPL_REVISION */
654 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
655 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
656 case 0x50: /* IPGENERICOCPSPL_GPI */
660 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
661 if (value
& (1 << 1)) /* SOFTRESET */
662 omap2_gpif_reset(DEVICE(s
));
663 s
->autoidle
= value
& 1;
666 case 0x40: /* IPGENERICOCPSPL_GPO */
676 static const MemoryRegionOps omap2_gpif_top_ops
= {
677 .read
= omap2_gpif_top_read
,
678 .write
= omap2_gpif_top_write
,
679 .endianness
= DEVICE_NATIVE_ENDIAN
,
682 static int omap_gpio_init(SysBusDevice
*sbd
)
684 DeviceState
*dev
= DEVICE(sbd
);
685 struct omap_gpif_s
*s
= OMAP1_GPIO(dev
);
688 hw_error("omap-gpio: clk not connected\n");
690 qdev_init_gpio_in(dev
, omap_gpio_set
, 16);
691 qdev_init_gpio_out(dev
, s
->omap1
.handler
, 16);
692 sysbus_init_irq(sbd
, &s
->omap1
.irq
);
693 memory_region_init_io(&s
->iomem
, OBJECT(s
), &omap_gpio_ops
, &s
->omap1
,
694 "omap.gpio", 0x1000);
695 sysbus_init_mmio(sbd
, &s
->iomem
);
699 static int omap2_gpio_init(SysBusDevice
*sbd
)
701 DeviceState
*dev
= DEVICE(sbd
);
702 struct omap2_gpif_s
*s
= OMAP2_GPIO(dev
);
706 hw_error("omap2-gpio: iclk not connected\n");
708 if (s
->mpu_model
< omap3430
) {
709 s
->modulecount
= (s
->mpu_model
< omap2430
) ? 4 : 5;
710 memory_region_init_io(&s
->iomem
, OBJECT(s
), &omap2_gpif_top_ops
, s
,
711 "omap2.gpio", 0x1000);
712 sysbus_init_mmio(sbd
, &s
->iomem
);
716 s
->modules
= g_malloc0(s
->modulecount
* sizeof(struct omap2_gpio_s
));
717 s
->handler
= g_malloc0(s
->modulecount
* 32 * sizeof(qemu_irq
));
718 qdev_init_gpio_in(dev
, omap2_gpio_set
, s
->modulecount
* 32);
719 qdev_init_gpio_out(dev
, s
->handler
, s
->modulecount
* 32);
720 for (i
= 0; i
< s
->modulecount
; i
++) {
721 struct omap2_gpio_s
*m
= &s
->modules
[i
];
723 hw_error("omap2-gpio: fclk%d not connected\n", i
);
725 m
->revision
= (s
->mpu_model
< omap3430
) ? 0x18 : 0x25;
726 m
->handler
= &s
->handler
[i
* 32];
727 sysbus_init_irq(sbd
, &m
->irq
[0]); /* mpu irq */
728 sysbus_init_irq(sbd
, &m
->irq
[1]); /* dsp irq */
729 sysbus_init_irq(sbd
, &m
->wkup
);
730 memory_region_init_io(&m
->iomem
, OBJECT(s
), &omap2_gpio_module_ops
, m
,
731 "omap.gpio-module", 0x1000);
732 sysbus_init_mmio(sbd
, &m
->iomem
);
737 /* Using qdev pointer properties for the clocks is not ideal.
738 * qdev should support a generic means of defining a 'port' with
739 * an arbitrary interface for connecting two devices. Then we
740 * could reframe the omap clock API in terms of clock ports,
741 * and get some type safety. For now the best qdev provides is
742 * passing an arbitrary pointer.
743 * (It's not possible to pass in the string which is the clock
744 * name, because this device does not have the necessary information
745 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
749 static Property omap_gpio_properties
[] = {
750 DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s
, mpu_model
, 0),
751 DEFINE_PROP_PTR("clk", struct omap_gpif_s
, clk
),
752 DEFINE_PROP_END_OF_LIST(),
755 static void omap_gpio_class_init(ObjectClass
*klass
, void *data
)
757 DeviceClass
*dc
= DEVICE_CLASS(klass
);
758 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
760 k
->init
= omap_gpio_init
;
761 dc
->reset
= omap_gpif_reset
;
762 dc
->props
= omap_gpio_properties
;
763 /* Reason: pointer property "clk" */
764 dc
->cannot_instantiate_with_device_add_yet
= true;
767 static const TypeInfo omap_gpio_info
= {
768 .name
= TYPE_OMAP1_GPIO
,
769 .parent
= TYPE_SYS_BUS_DEVICE
,
770 .instance_size
= sizeof(struct omap_gpif_s
),
771 .class_init
= omap_gpio_class_init
,
774 static Property omap2_gpio_properties
[] = {
775 DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s
, mpu_model
, 0),
776 DEFINE_PROP_PTR("iclk", struct omap2_gpif_s
, iclk
),
777 DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s
, fclk
[0]),
778 DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s
, fclk
[1]),
779 DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s
, fclk
[2]),
780 DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s
, fclk
[3]),
781 DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s
, fclk
[4]),
782 DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s
, fclk
[5]),
783 DEFINE_PROP_END_OF_LIST(),
786 static void omap2_gpio_class_init(ObjectClass
*klass
, void *data
)
788 DeviceClass
*dc
= DEVICE_CLASS(klass
);
789 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
791 k
->init
= omap2_gpio_init
;
792 dc
->reset
= omap2_gpif_reset
;
793 dc
->props
= omap2_gpio_properties
;
794 /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */
795 dc
->cannot_instantiate_with_device_add_yet
= true;
798 static const TypeInfo omap2_gpio_info
= {
799 .name
= TYPE_OMAP2_GPIO
,
800 .parent
= TYPE_SYS_BUS_DEVICE
,
801 .instance_size
= sizeof(struct omap2_gpif_s
),
802 .class_init
= omap2_gpio_class_init
,
805 static void omap_gpio_register_types(void)
807 type_register_static(&omap_gpio_info
);
808 type_register_static(&omap2_gpio_info
);
811 type_init(omap_gpio_register_types
)