2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 static const TypeInfo spapr_intc_info
= {
27 .name
= TYPE_SPAPR_INTC
,
28 .parent
= TYPE_INTERFACE
,
29 .class_size
= sizeof(SpaprInterruptControllerClass
),
32 static void spapr_irq_msi_init(SpaprMachineState
*spapr
)
34 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
35 /* Legacy mode doesn't use this allocator */
39 spapr
->irq_map_nr
= spapr_irq_nr_msis(spapr
);
40 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
43 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
49 * The 'align_mask' parameter of bitmap_find_next_zero_area()
50 * should be one less than a power of 2; 0 means no
51 * alignment. Adapt the 'align' value of the former allocator
52 * to fit the requirements of bitmap_find_next_zero_area()
56 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
58 if (irq
== spapr
->irq_map_nr
) {
59 error_setg(errp
, "can't find a free %d-IRQ block", num
);
63 bitmap_set(spapr
->irq_map
, irq
, num
);
65 return irq
+ SPAPR_IRQ_MSI
;
68 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
70 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
73 int spapr_irq_init_kvm(int (*fn
)(SpaprInterruptController
*, Error
**),
74 SpaprInterruptController
*intc
,
77 MachineState
*machine
= MACHINE(qdev_get_machine());
78 Error
*local_err
= NULL
;
80 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
81 if (fn(intc
, &local_err
) < 0) {
82 if (machine_kernel_irqchip_required(machine
)) {
83 error_prepend(&local_err
,
84 "kernel_irqchip requested but unavailable: ");
85 error_propagate(errp
, local_err
);
90 * We failed to initialize the KVM device, fallback to
93 error_prepend(&local_err
,
94 "kernel_irqchip allowed but unavailable: ");
95 error_append_hint(&local_err
,
96 "Falling back to kernel-irqchip=off\n");
97 warn_report_err(local_err
);
108 SpaprIrq spapr_irq_xics
= {
109 .nr_xirqs
= SPAPR_NR_XIRQS
,
118 SpaprIrq spapr_irq_xive
= {
119 .nr_xirqs
= SPAPR_NR_XIRQS
,
125 * Dual XIVE and XICS IRQ backend.
127 * Both interrupt mode, XIVE and XICS, objects are created but the
128 * machine starts in legacy interrupt mode (XICS). It can be changed
129 * by the CAS negotiation process and, in that case, the new mode is
130 * activated after an extra machine reset.
134 * Define values in sync with the XIVE and XICS backend
136 SpaprIrq spapr_irq_dual
= {
137 .nr_xirqs
= SPAPR_NR_XIRQS
,
143 static int spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
145 MachineState
*machine
= MACHINE(spapr
);
148 * Sanity checks on non-P9 machines. On these, XIVE is not
149 * advertised, see spapr_dt_ov5_platform_support()
151 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
152 0, spapr
->max_compat_pvr
)) {
154 * If the 'dual' interrupt mode is selected, force XICS as CAS
155 * negotiation is useless.
157 if (spapr
->irq
== &spapr_irq_dual
) {
158 spapr
->irq
= &spapr_irq_xics
;
163 * Non-P9 machines using only XIVE is a bogus setup. We have two
164 * scenarios to take into account because of the compat mode:
166 * 1. POWER7/8 machines should fail to init later on when creating
167 * the XIVE interrupt presenters because a POWER9 exception
170 * 2. POWER9 machines using the POWER8 compat mode won't fail and
171 * will let the OS boot with a partial XIVE setup : DT
172 * properties but no hcalls.
174 * To cover both and not confuse the OS, add an early failure in
177 if (spapr
->irq
== &spapr_irq_xive
) {
178 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
184 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
185 * re-created. Detect that early to avoid QEMU to exit later when the
189 spapr
->irq
== &spapr_irq_dual
&&
190 machine_kernel_irqchip_required(machine
) &&
191 xics_kvm_has_broken_disconnect(spapr
)) {
192 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
200 * sPAPR IRQ frontend routines for devices
202 #define ALL_INTCS(spapr_) \
203 { SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), }
205 int spapr_irq_cpu_intc_create(SpaprMachineState
*spapr
,
206 PowerPCCPU
*cpu
, Error
**errp
)
208 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
212 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
213 SpaprInterruptController
*intc
= intcs
[i
];
215 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
216 rc
= sicc
->cpu_intc_create(intc
, cpu
, errp
);
226 static void spapr_set_irq(void *opaque
, int irq
, int level
)
228 SpaprMachineState
*spapr
= SPAPR_MACHINE(opaque
);
229 SpaprInterruptControllerClass
*sicc
230 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
232 sicc
->set_irq(spapr
->active_intc
, irq
, level
);
235 void spapr_irq_print_info(SpaprMachineState
*spapr
, Monitor
*mon
)
237 SpaprInterruptControllerClass
*sicc
238 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
240 sicc
->print_info(spapr
->active_intc
, mon
);
243 void spapr_irq_dt(SpaprMachineState
*spapr
, uint32_t nr_servers
,
244 void *fdt
, uint32_t phandle
)
246 SpaprInterruptControllerClass
*sicc
247 = SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
249 sicc
->dt(spapr
->active_intc
, nr_servers
, fdt
, phandle
);
252 uint32_t spapr_irq_nr_msis(SpaprMachineState
*spapr
)
254 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
255 return spapr
->irq
->nr_xirqs
;
257 return SPAPR_XIRQ_BASE
+ spapr
->irq
->nr_xirqs
- SPAPR_IRQ_MSI
;
261 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
263 MachineState
*machine
= MACHINE(spapr
);
265 if (machine_kernel_irqchip_split(machine
)) {
266 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
270 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
272 "kernel_irqchip requested but only available with KVM");
276 if (spapr_irq_check(spapr
, errp
) < 0) {
280 /* Initialize the MSI IRQ allocator. */
281 spapr_irq_msi_init(spapr
);
283 if (spapr
->irq
->xics
) {
284 Error
*local_err
= NULL
;
287 obj
= object_new(TYPE_ICS_SPAPR
);
288 object_property_add_child(OBJECT(spapr
), "ics", obj
, &local_err
);
290 error_propagate(errp
, local_err
);
294 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
297 error_propagate(errp
, local_err
);
301 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
, "nr-irqs",
304 error_propagate(errp
, local_err
);
308 object_property_set_bool(obj
, true, "realized", &local_err
);
310 error_propagate(errp
, local_err
);
314 spapr
->ics
= ICS_SPAPR(obj
);
317 if (spapr
->irq
->xive
) {
318 uint32_t nr_servers
= spapr_max_server_number(spapr
);
322 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
323 qdev_prop_set_uint32(dev
, "nr-irqs",
324 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
326 * 8 XIVE END structures per CPU. One for each available
329 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
330 qdev_init_nofail(dev
);
332 spapr
->xive
= SPAPR_XIVE(dev
);
334 /* Enable the CPU IPIs */
335 for (i
= 0; i
< nr_servers
; ++i
) {
336 SpaprInterruptControllerClass
*sicc
337 = SPAPR_INTC_GET_CLASS(spapr
->xive
);
339 if (sicc
->claim_irq(SPAPR_INTC(spapr
->xive
), SPAPR_IRQ_IPI
+ i
,
345 spapr_xive_hcall_init(spapr
);
348 spapr
->qirqs
= qemu_allocate_irqs(spapr_set_irq
, spapr
,
349 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
352 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
354 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
358 assert(irq
>= SPAPR_XIRQ_BASE
);
359 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
361 for (i
= 0; i
< ARRAY_SIZE(intcs
); i
++) {
362 SpaprInterruptController
*intc
= intcs
[i
];
364 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_GET_CLASS(intc
);
365 rc
= sicc
->claim_irq(intc
, irq
, lsi
, errp
);
375 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
377 SpaprInterruptController
*intcs
[] = ALL_INTCS(spapr
);
380 assert(irq
>= SPAPR_XIRQ_BASE
);
381 assert((irq
+ num
) <= (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
383 for (i
= irq
; i
< (irq
+ num
); i
++) {
384 for (j
= 0; j
< ARRAY_SIZE(intcs
); j
++) {
385 SpaprInterruptController
*intc
= intcs
[j
];
388 SpaprInterruptControllerClass
*sicc
389 = SPAPR_INTC_GET_CLASS(intc
);
390 sicc
->free_irq(intc
, i
);
396 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
399 * This interface is basically for VIO and PHB devices to find the
400 * right qemu_irq to manipulate, so we only allow access to the
401 * external irqs for now. Currently anything which needs to
402 * access the IPIs most naturally gets there via the guest side
403 * interfaces, we can change this if we need to in future.
405 assert(irq
>= SPAPR_XIRQ_BASE
);
406 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
409 assert(ics_valid_irq(spapr
->ics
, irq
));
412 assert(irq
< spapr
->xive
->nr_irqs
);
413 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
416 return spapr
->qirqs
[irq
];
419 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
421 SpaprInterruptControllerClass
*sicc
;
423 spapr_irq_update_active_intc(spapr
);
424 sicc
= SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
425 return sicc
->post_load(spapr
->active_intc
, version_id
);
428 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
430 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
432 spapr_irq_update_active_intc(spapr
);
435 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
437 const char *nodename
= "interrupt-controller";
440 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
442 error_setg(errp
, "Can't find node \"%s\": %s",
443 nodename
, fdt_strerror(offset
));
447 phandle
= fdt_get_phandle(fdt
, offset
);
449 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
456 static void set_active_intc(SpaprMachineState
*spapr
,
457 SpaprInterruptController
*new_intc
)
459 SpaprInterruptControllerClass
*sicc
;
463 if (new_intc
== spapr
->active_intc
) {
468 if (spapr
->active_intc
) {
469 sicc
= SPAPR_INTC_GET_CLASS(spapr
->active_intc
);
470 if (sicc
->deactivate
) {
471 sicc
->deactivate(spapr
->active_intc
);
475 sicc
= SPAPR_INTC_GET_CLASS(new_intc
);
476 if (sicc
->activate
) {
477 sicc
->activate(new_intc
, &error_fatal
);
480 spapr
->active_intc
= new_intc
;
483 void spapr_irq_update_active_intc(SpaprMachineState
*spapr
)
485 SpaprInterruptController
*new_intc
;
489 * XXX before we run CAS, ov5_cas is initialized empty, which
490 * indicates XICS, even if we have ic-mode=xive. TODO: clean
491 * up the CAS path so that we have a clearer way of handling
494 new_intc
= SPAPR_INTC(spapr
->xive
);
495 } else if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
496 new_intc
= SPAPR_INTC(spapr
->xive
);
498 new_intc
= SPAPR_INTC(spapr
->ics
);
501 set_active_intc(spapr
, new_intc
);
505 * XICS legacy routines - to deprecate one day
508 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
512 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
513 if (num
> (ics
->nr_irqs
- first
)) {
516 for (i
= first
; i
< first
+ num
; ++i
) {
517 if (!ics_irq_free(ics
, i
)) {
521 if (i
== (first
+ num
)) {
529 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
531 ICSState
*ics
= spapr
->ics
;
537 * MSIMesage::data is used for storing VIRQ so
538 * it has to be aligned to num to support multiple
539 * MSI vectors. MSI-X is not affected by this.
540 * The hint is used for the first IRQ, the rest should
541 * be allocated continuously.
544 assert((num
== 1) || (num
== 2) || (num
== 4) ||
545 (num
== 8) || (num
== 16) || (num
== 32));
546 first
= ics_find_free_block(ics
, num
, num
);
548 first
= ics_find_free_block(ics
, num
, 1);
552 error_setg(errp
, "can't find a free %d-IRQ block", num
);
556 return first
+ ics
->offset
;
559 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
561 SpaprIrq spapr_irq_xics_legacy
= {
562 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
567 static void spapr_irq_register_types(void)
569 type_register_static(&spapr_intc_info
);
572 type_init(spapr_irq_register_types
)