target-lm32/cpu.c

   1 /*
   2  * QEMU LatticeMico32 CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23
  24
  25 static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
  26 {
  27     LM32CPU *cpu = LM32_CPU(cs);
  28
  29     cpu->env.pc = value;
  30 }
  31
  32 /* CPUClass::reset() */
  33 static void lm32_cpu_reset(CPUState *s)
  34 {
  35     LM32CPU *cpu = LM32_CPU(s);
  36     LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
  37     CPULM32State *env = &cpu->env;
  38
  39     lcc->parent_reset(s);
  40
  41     /* reset cpu state */
  42     memset(env, 0, offsetof(CPULM32State, breakpoints));
  43
  44     tlb_flush(env, 1);
  45 }
  46
  47 static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
  48 {
  49     LM32CPU *cpu = LM32_CPU(dev);
  50     LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
  51
  52     cpu_reset(CPU(cpu));
  53
  54     lcc->parent_realize(dev, errp);
  55 }
  56
  57 static void lm32_cpu_initfn(Object *obj)
  58 {
  59     CPUState *cs = CPU(obj);
  60     LM32CPU *cpu = LM32_CPU(obj);
  61     CPULM32State *env = &cpu->env;
  62     static bool tcg_initialized;
  63
  64     cs->env_ptr = env;
  65     cpu_exec_init(env);
  66
  67     env->flags = 0;
  68
  69     if (tcg_enabled() && !tcg_initialized) {
  70         tcg_initialized = true;
  71         lm32_translate_init();
  72     }
  73 }
  74
  75 static void lm32_cpu_class_init(ObjectClass *oc, void *data)
  76 {
  77     LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
  78     CPUClass *cc = CPU_CLASS(oc);
  79     DeviceClass *dc = DEVICE_CLASS(oc);
  80
  81     lcc->parent_realize = dc->realize;
  82     dc->realize = lm32_cpu_realizefn;
  83
  84     lcc->parent_reset = cc->reset;
  85     cc->reset = lm32_cpu_reset;
  86
  87     cc->do_interrupt = lm32_cpu_do_interrupt;
  88     cc->dump_state = lm32_cpu_dump_state;
  89     cc->set_pc = lm32_cpu_set_pc;
  90     cc->gdb_read_register = lm32_cpu_gdb_read_register;
  91     cc->gdb_write_register = lm32_cpu_gdb_write_register;
  92 #ifndef CONFIG_USER_ONLY
  93     cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
  94     cc->vmsd = &vmstate_lm32_cpu;
  95 #endif
  96     cc->gdb_num_core_regs = 32 + 7;
  97 }
  98
  99 static const TypeInfo lm32_cpu_type_info = {
 100     .name = TYPE_LM32_CPU,
 101     .parent = TYPE_CPU,
 102     .instance_size = sizeof(LM32CPU),
 103     .instance_init = lm32_cpu_initfn,
 104     .abstract = false,
 105     .class_size = sizeof(LM32CPUClass),
 106     .class_init = lm32_cpu_class_init,
 107 };
 108
 109 static void lm32_cpu_register_types(void)
 110 {
 111     type_register_static(&lm32_cpu_type_info);
 112 }
 113
 114 type_init(lm32_cpu_register_types)