2 * User emulator execution
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "disas/disas.h"
23 #include "qemu/bitops.h"
36 #include <sys/ucontext.h>
39 //#define DEBUG_SIGNAL
41 static void exception_action(CPUState
*cpu
)
43 #if defined(TARGET_I386)
44 X86CPU
*x86_cpu
= X86_CPU(cpu
);
45 CPUX86State
*env1
= &x86_cpu
->env
;
47 raise_exception_err(env1
, cpu
->exception_index
, env1
->error_code
);
53 /* exit the current TB from a signal handler. The host registers are
54 restored in a state compatible with the CPU emulator
56 void cpu_resume_from_signal(CPUState
*cpu
, void *puc
)
59 struct ucontext
*uc
= puc
;
60 #elif defined(__OpenBSD__)
61 struct sigcontext
*uc
= puc
;
65 /* XXX: use siglongjmp ? */
68 sigprocmask(SIG_SETMASK
, (sigset_t
*)&uc
->uc_sigmask
, NULL
);
70 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
72 #elif defined(__OpenBSD__)
73 sigprocmask(SIG_SETMASK
, &uc
->sc_mask
, NULL
);
76 cpu
->exception_index
= -1;
77 siglongjmp(cpu
->jmp_env
, 1);
80 /* 'pc' is the host PC at which the exception was raised. 'address' is
81 the effective address of the memory exception. 'is_write' is 1 if a
82 write caused the exception and otherwise 0'. 'old_set' is the
83 signal set which should be restored */
84 static inline int handle_cpu_signal(uintptr_t pc
, void *ptr
,
85 int is_write
, sigset_t
*old_set
,
88 uintptr_t address
= (uintptr_t)ptr
;
93 #if defined(DEBUG_SIGNAL)
94 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
95 pc
, address
, is_write
, *(unsigned long *)old_set
);
97 /* XXX: locking issue */
98 if (is_write
&& h2g_valid(address
)
99 && page_unprotect(h2g(address
), pc
, puc
)) {
103 /* Convert forcefully to guest address space, invalid addresses
104 are still valid segv ones */
105 address
= h2g_nocheck(address
);
108 cc
= CPU_GET_CLASS(cpu
);
109 /* see if it is an MMU fault */
110 g_assert(cc
->handle_mmu_fault
);
111 ret
= cc
->handle_mmu_fault(cpu
, address
, is_write
, MMU_USER_IDX
);
113 return 0; /* not an MMU fault */
116 return 1; /* the MMU fault was handled without causing real CPU fault */
118 /* now we have a real cpu fault */
119 cpu_restore_state(cpu
, pc
);
121 /* we restore the process signal mask as the sigreturn should
122 do it (XXX: use sigsetjmp) */
123 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
124 exception_action(cpu
);
126 /* never comes here */
130 #if defined(__i386__)
132 #if defined(__APPLE__)
133 #include <sys/ucontext.h>
135 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
136 #define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
137 #define ERROR_sig(context) ((context)->uc_mcontext->es.err)
138 #define MASK_sig(context) ((context)->uc_sigmask)
139 #elif defined(__NetBSD__)
140 #include <ucontext.h>
142 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
143 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
144 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
145 #define MASK_sig(context) ((context)->uc_sigmask)
146 #elif defined(__FreeBSD__) || defined(__DragonFly__)
147 #include <ucontext.h>
149 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
150 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
151 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
152 #define MASK_sig(context) ((context)->uc_sigmask)
153 #elif defined(__OpenBSD__)
154 #define EIP_sig(context) ((context)->sc_eip)
155 #define TRAP_sig(context) ((context)->sc_trapno)
156 #define ERROR_sig(context) ((context)->sc_err)
157 #define MASK_sig(context) ((context)->sc_mask)
159 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
160 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
161 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
162 #define MASK_sig(context) ((context)->uc_sigmask)
165 int cpu_signal_handler(int host_signum
, void *pinfo
,
168 siginfo_t
*info
= pinfo
;
169 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
170 ucontext_t
*uc
= puc
;
171 #elif defined(__OpenBSD__)
172 struct sigcontext
*uc
= puc
;
174 struct ucontext
*uc
= puc
;
183 #define REG_TRAPNO TRAPNO
186 trapno
= TRAP_sig(uc
);
187 return handle_cpu_signal(pc
, info
->si_addr
,
189 (ERROR_sig(uc
) >> 1) & 1 : 0,
193 #elif defined(__x86_64__)
196 #define PC_sig(context) _UC_MACHINE_PC(context)
197 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
198 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
199 #define MASK_sig(context) ((context)->uc_sigmask)
200 #elif defined(__OpenBSD__)
201 #define PC_sig(context) ((context)->sc_rip)
202 #define TRAP_sig(context) ((context)->sc_trapno)
203 #define ERROR_sig(context) ((context)->sc_err)
204 #define MASK_sig(context) ((context)->sc_mask)
205 #elif defined(__FreeBSD__) || defined(__DragonFly__)
206 #include <ucontext.h>
208 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
209 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
210 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
211 #define MASK_sig(context) ((context)->uc_sigmask)
213 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
214 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
215 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
216 #define MASK_sig(context) ((context)->uc_sigmask)
219 int cpu_signal_handler(int host_signum
, void *pinfo
,
222 siginfo_t
*info
= pinfo
;
224 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
225 ucontext_t
*uc
= puc
;
226 #elif defined(__OpenBSD__)
227 struct sigcontext
*uc
= puc
;
229 struct ucontext
*uc
= puc
;
233 return handle_cpu_signal(pc
, info
->si_addr
,
234 TRAP_sig(uc
) == 0xe ?
235 (ERROR_sig(uc
) >> 1) & 1 : 0,
239 #elif defined(_ARCH_PPC)
241 /***********************************************************************
242 * signal context platform-specific definitions
246 /* All Registers access - only for local access */
247 #define REG_sig(reg_name, context) \
248 ((context)->uc_mcontext.regs->reg_name)
249 /* Gpr Registers access */
250 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
251 /* Program counter */
252 #define IAR_sig(context) REG_sig(nip, context)
253 /* Machine State Register (Supervisor) */
254 #define MSR_sig(context) REG_sig(msr, context)
256 #define CTR_sig(context) REG_sig(ctr, context)
257 /* User's integer exception register */
258 #define XER_sig(context) REG_sig(xer, context)
260 #define LR_sig(context) REG_sig(link, context)
261 /* Condition register */
262 #define CR_sig(context) REG_sig(ccr, context)
264 /* Float Registers access */
265 #define FLOAT_sig(reg_num, context) \
266 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
267 #define FPSCR_sig(context) \
268 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
269 /* Exception Registers access */
270 #define DAR_sig(context) REG_sig(dar, context)
271 #define DSISR_sig(context) REG_sig(dsisr, context)
272 #define TRAP_sig(context) REG_sig(trap, context)
275 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
276 #include <ucontext.h>
277 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
278 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
279 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
280 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
281 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
282 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
283 /* Exception Registers access */
284 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
285 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
286 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
287 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
290 #include <sys/ucontext.h>
291 typedef struct ucontext SIGCONTEXT
;
292 /* All Registers access - only for local access */
293 #define REG_sig(reg_name, context) \
294 ((context)->uc_mcontext->ss.reg_name)
295 #define FLOATREG_sig(reg_name, context) \
296 ((context)->uc_mcontext->fs.reg_name)
297 #define EXCEPREG_sig(reg_name, context) \
298 ((context)->uc_mcontext->es.reg_name)
299 #define VECREG_sig(reg_name, context) \
300 ((context)->uc_mcontext->vs.reg_name)
301 /* Gpr Registers access */
302 #define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
303 /* Program counter */
304 #define IAR_sig(context) REG_sig(srr0, context)
305 /* Machine State Register (Supervisor) */
306 #define MSR_sig(context) REG_sig(srr1, context)
307 #define CTR_sig(context) REG_sig(ctr, context)
309 #define XER_sig(context) REG_sig(xer, context)
310 /* User's integer exception register */
311 #define LR_sig(context) REG_sig(lr, context)
312 /* Condition register */
313 #define CR_sig(context) REG_sig(cr, context)
314 /* Float Registers access */
315 #define FLOAT_sig(reg_num, context) \
316 FLOATREG_sig(fpregs[reg_num], context)
317 #define FPSCR_sig(context) \
318 ((double)FLOATREG_sig(fpscr, context))
319 /* Exception Registers access */
320 /* Fault registers for coredump */
321 #define DAR_sig(context) EXCEPREG_sig(dar, context)
322 #define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
323 /* number of powerpc exception taken */
324 #define TRAP_sig(context) EXCEPREG_sig(exception, context)
325 #endif /* __APPLE__ */
327 int cpu_signal_handler(int host_signum
, void *pinfo
,
330 siginfo_t
*info
= pinfo
;
331 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
332 ucontext_t
*uc
= puc
;
334 struct ucontext
*uc
= puc
;
343 if (DSISR_sig(uc
) & 0x00800000) {
347 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000)) {
351 return handle_cpu_signal(pc
, info
->si_addr
, is_write
, &uc
->uc_sigmask
, puc
);
354 #elif defined(__alpha__)
356 int cpu_signal_handler(int host_signum
, void *pinfo
,
359 siginfo_t
*info
= pinfo
;
360 struct ucontext
*uc
= puc
;
361 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
365 /* XXX: need kernel patch to get write flag faster */
366 switch (insn
>> 26) {
369 case 0x0f: /* stq_u */
376 case 0x2e: /* stl_c */
377 case 0x2f: /* stq_c */
381 return handle_cpu_signal(pc
, info
->si_addr
, is_write
, &uc
->uc_sigmask
, puc
);
383 #elif defined(__sparc__)
385 int cpu_signal_handler(int host_signum
, void *pinfo
,
388 siginfo_t
*info
= pinfo
;
391 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
392 uint32_t *regs
= (uint32_t *)(info
+ 1);
393 void *sigmask
= (regs
+ 20);
394 /* XXX: is there a standard glibc define ? */
395 uintptr_t pc
= regs
[1];
398 struct sigcontext
*sc
= puc
;
399 uintptr_t pc
= sc
->sigc_regs
.tpc
;
400 void *sigmask
= (void *)sc
->sigc_mask
;
401 #elif defined(__OpenBSD__)
402 struct sigcontext
*uc
= puc
;
403 uintptr_t pc
= uc
->sc_pc
;
404 void *sigmask
= (void *)(long)uc
->sc_mask
;
408 /* XXX: need kernel patch to get write flag faster */
410 insn
= *(uint32_t *)pc
;
411 if ((insn
>> 30) == 3) {
412 switch ((insn
>> 19) & 0x3f) {
414 case 0x15: /* stba */
416 case 0x16: /* stha */
420 case 0x17: /* stda */
422 case 0x1e: /* stxa */
424 case 0x34: /* stfa */
425 case 0x27: /* stdf */
426 case 0x37: /* stdfa */
427 case 0x26: /* stqf */
428 case 0x36: /* stqfa */
429 case 0x25: /* stfsr */
430 case 0x3c: /* casa */
431 case 0x3e: /* casxa */
436 return handle_cpu_signal(pc
, info
->si_addr
, is_write
, sigmask
, NULL
);
439 #elif defined(__arm__)
441 int cpu_signal_handler(int host_signum
, void *pinfo
,
444 siginfo_t
*info
= pinfo
;
445 struct ucontext
*uc
= puc
;
449 #if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
450 pc
= uc
->uc_mcontext
.gregs
[R15
];
452 pc
= uc
->uc_mcontext
.arm_pc
;
455 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
456 * later processor; on v5 we will always report this as a read).
458 is_write
= extract32(uc
->uc_mcontext
.error_code
, 11, 1);
459 return handle_cpu_signal(pc
, info
->si_addr
, is_write
, &uc
->uc_sigmask
, puc
);
462 #elif defined(__aarch64__)
464 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
466 siginfo_t
*info
= pinfo
;
467 struct ucontext
*uc
= puc
;
468 uintptr_t pc
= uc
->uc_mcontext
.pc
;
469 uint32_t insn
= *(uint32_t *)pc
;
472 /* XXX: need kernel patch to get write flag faster. */
473 is_write
= ( (insn
& 0xbfff0000) == 0x0c000000 /* C3.3.1 */
474 || (insn
& 0xbfe00000) == 0x0c800000 /* C3.3.2 */
475 || (insn
& 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
476 || (insn
& 0xbfc00000) == 0x0d800000 /* C3.3.4 */
477 || (insn
& 0x3f400000) == 0x08000000 /* C3.3.6 */
478 || (insn
& 0x3bc00000) == 0x39000000 /* C3.3.13 */
479 || (insn
& 0x3fc00000) == 0x3d800000 /* ... 128bit */
480 /* Ingore bits 10, 11 & 21, controlling indexing. */
481 || (insn
& 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
482 || (insn
& 0x3fe00000) == 0x3c800000 /* ... 128bit */
483 /* Ignore bits 23 & 24, controlling indexing. */
484 || (insn
& 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
486 return handle_cpu_signal(pc
, (uintptr_t)info
->si_addr
,
487 is_write
, &uc
->uc_sigmask
, puc
);
490 #elif defined(__mc68000)
492 int cpu_signal_handler(int host_signum
, void *pinfo
,
495 siginfo_t
*info
= pinfo
;
496 struct ucontext
*uc
= puc
;
500 pc
= uc
->uc_mcontext
.gregs
[16];
501 /* XXX: compute is_write */
503 return handle_cpu_signal(pc
, info
->si_addr
, is_write
, &uc
->uc_sigmask
, puc
);
506 #elif defined(__ia64)
509 /* This ought to be in <bits/siginfo.h>... */
510 # define __ISR_VALID 1
513 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
515 siginfo_t
*info
= pinfo
;
516 struct ucontext
*uc
= puc
;
520 ip
= uc
->uc_mcontext
.sc_ip
;
521 switch (host_signum
) {
527 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
)) {
528 /* ISR.W (write-access) is bit 33: */
529 is_write
= (info
->si_isr
>> 33) & 1;
536 return handle_cpu_signal(ip
, info
->si_addr
, is_write
,
537 (sigset_t
*)&uc
->uc_sigmask
, puc
);
540 #elif defined(__s390__)
542 int cpu_signal_handler(int host_signum
, void *pinfo
,
545 siginfo_t
*info
= pinfo
;
546 struct ucontext
*uc
= puc
;
551 pc
= uc
->uc_mcontext
.psw
.addr
;
553 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
554 of the normal 2 arguments. The 3rd argument contains the "int_code"
555 from the hardware which does in fact contain the is_write value.
556 The rt signal handler, as far as I can tell, does not give this value
557 at all. Not that we could get to it from here even if it were. */
558 /* ??? This is not even close to complete, since it ignores all
559 of the read-modify-write instructions. */
560 pinsn
= (uint16_t *)pc
;
561 switch (pinsn
[0] >> 8) {
567 case 0xc4: /* RIL format insns */
568 switch (pinsn
[0] & 0xf) {
570 case 0xb: /* STGRL */
571 case 0x7: /* STHRL */
575 case 0xe3: /* RXY format insns */
576 switch (pinsn
[2] & 0xff) {
579 case 0x72: /* STCY */
580 case 0x70: /* STHY */
581 case 0x8e: /* STPQ */
582 case 0x3f: /* STRVH */
583 case 0x3e: /* STRV */
584 case 0x2f: /* STRVG */
589 return handle_cpu_signal(pc
, info
->si_addr
, is_write
, &uc
->uc_sigmask
, puc
);
592 #elif defined(__mips__)
594 int cpu_signal_handler(int host_signum
, void *pinfo
,
597 siginfo_t
*info
= pinfo
;
598 struct ucontext
*uc
= puc
;
599 greg_t pc
= uc
->uc_mcontext
.pc
;
602 /* XXX: compute is_write */
604 return handle_cpu_signal(pc
, info
->si_addr
, is_write
, &uc
->uc_sigmask
, puc
);
607 #elif defined(__hppa__)
609 int cpu_signal_handler(int host_signum
, void *pinfo
,
612 siginfo_t
*info
= pinfo
;
613 struct ucontext
*uc
= puc
;
614 uintptr_t pc
= uc
->uc_mcontext
.sc_iaoq
[0];
615 uint32_t insn
= *(uint32_t *)pc
;
618 /* XXX: need kernel patch to get write flag faster. */
619 switch (insn
>> 26) {
623 case 0x1b: /* STWM */
627 case 0x09: /* CSTWX, FSTWX, FSTWS */
628 case 0x0b: /* CSTDX, FSTDX, FSTDS */
629 /* Distinguish from coprocessor load ... */
630 is_write
= (insn
>> 9) & 1;
634 switch ((insn
>> 6) & 15) {
638 case 0xe: /* STWAS */
639 case 0xc: /* STBYS */
645 return handle_cpu_signal(pc
, info
->si_addr
, is_write
, &uc
->uc_sigmask
, puc
);
650 #error host CPU specific signal handler needed