target-sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "helper.h"
  22
  23 #ifndef CONFIG_USER_ONLY
  24 #include "exec/softmmu_exec.h"
  25
  26 #define MMUSUFFIX _mmu
  27
  28 #define SHIFT 0
  29 #include "exec/softmmu_template.h"
  30
  31 #define SHIFT 1
  32 #include "exec/softmmu_template.h"
  33
  34 #define SHIFT 2
  35 #include "exec/softmmu_template.h"
  36
  37 #define SHIFT 3
  38 #include "exec/softmmu_template.h"
  39
  40 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  41               uintptr_t retaddr)
  42 {
  43     int ret;
  44
  45     ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  46     if (ret) {
  47         /* now we have a real cpu fault */
  48         if (retaddr) {
  49             cpu_restore_state(cs, retaddr);
  50         }
  51         cpu_loop_exit(cs);
  52     }
  53 }
  54
  55 #endif
  56
  57 #ifdef CONFIG_USER_ONLY
  58 void QEMU_NORETURN helper_ldtlb(CPUSH4State *env)
  59 #else
  60 void helper_ldtlb(CPUSH4State *env)
  61 #endif
  62 {
  63 #ifdef CONFIG_USER_ONLY
  64     SuperHCPU *cpu = sh_env_get_cpu(env);
  65
  66     /* XXXXX */
  67     cpu_abort(CPU(cpu), "Unhandled ldtlb");
  68 #else
  69     cpu_load_tlb(env);
  70 #endif
  71 }
  72
  73 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
  74                                                  uintptr_t retaddr)
  75 {
  76     CPUState *cs = CPU(sh_env_get_cpu(env));
  77
  78     cs->exception_index = index;
  79     if (retaddr) {
  80         cpu_restore_state(cs, retaddr);
  81     }
  82     cpu_loop_exit(cs);
  83 }
  84
  85 void QEMU_NORETURN helper_raise_illegal_instruction(CPUSH4State *env)
  86 {
  87     raise_exception(env, 0x180, 0);
  88 }
  89
  90 void QEMU_NORETURN helper_raise_slot_illegal_instruction(CPUSH4State *env)
  91 {
  92     raise_exception(env, 0x1a0, 0);
  93 }
  94
  95 void QEMU_NORETURN helper_raise_fpu_disable(CPUSH4State *env)
  96 {
  97     raise_exception(env, 0x800, 0);
  98 }
  99
 100 void QEMU_NORETURN helper_raise_slot_fpu_disable(CPUSH4State *env)
 101 {
 102     raise_exception(env, 0x820, 0);
 103 }
 104
 105 void QEMU_NORETURN helper_debug(CPUSH4State *env)
 106 {
 107     raise_exception(env, EXCP_DEBUG, 0);
 108 }
 109
 110 void QEMU_NORETURN helper_sleep(CPUSH4State *env)
 111 {
 112     CPUState *cs = CPU(sh_env_get_cpu(env));
 113
 114     cs->halted = 1;
 115     env->in_sleep = 1;
 116     raise_exception(env, EXCP_HLT, 0);
 117 }
 118
 119 void QEMU_NORETURN helper_trapa(CPUSH4State *env, uint32_t tra)
 120 {
 121     env->tra = tra << 2;
 122     raise_exception(env, 0x160, 0);
 123 }
 124
 125 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 126 {
 127     if (cpu_sh4_is_cached (env, address))
 128     {
 129         memory_content *r = malloc (sizeof(memory_content));
 130         r->address = address;
 131         r->value = value;
 132         r->next = NULL;
 133
 134         *(env->movcal_backup_tail) = r;
 135         env->movcal_backup_tail = &(r->next);
 136     }
 137 }
 138
 139 void helper_discard_movcal_backup(CPUSH4State *env)
 140 {
 141     memory_content *current = env->movcal_backup;
 142
 143     while(current)
 144     {
 145         memory_content *next = current->next;
 146         free (current);
 147         env->movcal_backup = current = next;
 148         if (current == NULL)
 149             env->movcal_backup_tail = &(env->movcal_backup);
 150     }
 151 }
 152
 153 void helper_ocbi(CPUSH4State *env, uint32_t address)
 154 {
 155     memory_content **current = &(env->movcal_backup);
 156     while (*current)
 157     {
 158         uint32_t a = (*current)->address;
 159         if ((a & ~0x1F) == (address & ~0x1F))
 160         {
 161             memory_content *next = (*current)->next;
 162             cpu_stl_data(env, a, (*current)->value);
 163
 164             if (next == NULL)
 165             {
 166                 env->movcal_backup_tail = current;
 167             }
 168
 169             free (*current);
 170             *current = next;
 171             break;
 172         }
 173     }
 174 }
 175
 176 #define T (env->sr & SR_T)
 177 #define Q (env->sr & SR_Q ? 1 : 0)
 178 #define M (env->sr & SR_M ? 1 : 0)
 179 #define SETT env->sr |= SR_T
 180 #define CLRT env->sr &= ~SR_T
 181 #define SETQ env->sr |= SR_Q
 182 #define CLRQ env->sr &= ~SR_Q
 183 #define SETM env->sr |= SR_M
 184 #define CLRM env->sr &= ~SR_M
 185
 186 uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 187 {
 188     uint32_t tmp0, tmp2;
 189     uint8_t old_q, tmp1 = 0xff;
 190
 191     //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
 192     old_q = Q;
 193     if ((0x80000000 & arg1) != 0)
 194         SETQ;
 195     else
 196         CLRQ;
 197     tmp2 = arg0;
 198     arg1 <<= 1;
 199     arg1 |= T;
 200     switch (old_q) {
 201     case 0:
 202         switch (M) {
 203         case 0:
 204             tmp0 = arg1;
 205             arg1 -= tmp2;
 206             tmp1 = arg1 > tmp0;
 207             switch (Q) {
 208             case 0:
 209                 if (tmp1)
 210                     SETQ;
 211                 else
 212                     CLRQ;
 213                 break;
 214             case 1:
 215                 if (tmp1 == 0)
 216                     SETQ;
 217                 else
 218                     CLRQ;
 219                 break;
 220             }
 221             break;
 222         case 1:
 223             tmp0 = arg1;
 224             arg1 += tmp2;
 225             tmp1 = arg1 < tmp0;
 226             switch (Q) {
 227             case 0:
 228                 if (tmp1 == 0)
 229                     SETQ;
 230                 else
 231                     CLRQ;
 232                 break;
 233             case 1:
 234                 if (tmp1)
 235                     SETQ;
 236                 else
 237                     CLRQ;
 238                 break;
 239             }
 240             break;
 241         }
 242         break;
 243     case 1:
 244         switch (M) {
 245         case 0:
 246             tmp0 = arg1;
 247             arg1 += tmp2;
 248             tmp1 = arg1 < tmp0;
 249             switch (Q) {
 250             case 0:
 251                 if (tmp1)
 252                     SETQ;
 253                 else
 254                     CLRQ;
 255                 break;
 256             case 1:
 257                 if (tmp1 == 0)
 258                     SETQ;
 259                 else
 260                     CLRQ;
 261                 break;
 262             }
 263             break;
 264         case 1:
 265             tmp0 = arg1;
 266             arg1 -= tmp2;
 267             tmp1 = arg1 > tmp0;
 268             switch (Q) {
 269             case 0:
 270                 if (tmp1 == 0)
 271                     SETQ;
 272                 else
 273                     CLRQ;
 274                 break;
 275             case 1:
 276                 if (tmp1)
 277                     SETQ;
 278                 else
 279                     CLRQ;
 280                 break;
 281             }
 282             break;
 283         }
 284         break;
 285     }
 286     if (Q == M)
 287         SETT;
 288     else
 289         CLRT;
 290     //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
 291     return arg1;
 292 }
 293
 294 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 295 {
 296     int64_t res;
 297
 298     res = ((uint64_t) env->mach << 32) | env->macl;
 299     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 300     env->mach = (res >> 32) & 0xffffffff;
 301     env->macl = res & 0xffffffff;
 302     if (env->sr & SR_S) {
 303         if (res < 0)
 304             env->mach |= 0xffff0000;
 305         else
 306             env->mach &= 0x00007fff;
 307     }
 308 }
 309
 310 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 311 {
 312     int64_t res;
 313
 314     res = ((uint64_t) env->mach << 32) | env->macl;
 315     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 316     env->mach = (res >> 32) & 0xffffffff;
 317     env->macl = res & 0xffffffff;
 318     if (env->sr & SR_S) {
 319         if (res < -0x80000000) {
 320             env->mach = 1;
 321             env->macl = 0x80000000;
 322         } else if (res > 0x000000007fffffff) {
 323             env->mach = 1;
 324             env->macl = 0x7fffffff;
 325         }
 326     }
 327 }
 328
 329 static inline void set_t(CPUSH4State *env)
 330 {
 331     env->sr |= SR_T;
 332 }
 333
 334 static inline void clr_t(CPUSH4State *env)
 335 {
 336     env->sr &= ~SR_T;
 337 }
 338
 339 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 340 {
 341     env->fpscr = val & FPSCR_MASK;
 342     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 343         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 344     } else {
 345         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 346     }
 347     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 348 }
 349
 350 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 351 {
 352     int xcpt, cause, enable;
 353
 354     xcpt = get_float_exception_flags(&env->fp_status);
 355
 356     /* Clear the flag entries */
 357     env->fpscr &= ~FPSCR_FLAG_MASK;
 358
 359     if (unlikely(xcpt)) {
 360         if (xcpt & float_flag_invalid) {
 361             env->fpscr |= FPSCR_FLAG_V;
 362         }
 363         if (xcpt & float_flag_divbyzero) {
 364             env->fpscr |= FPSCR_FLAG_Z;
 365         }
 366         if (xcpt & float_flag_overflow) {
 367             env->fpscr |= FPSCR_FLAG_O;
 368         }
 369         if (xcpt & float_flag_underflow) {
 370             env->fpscr |= FPSCR_FLAG_U;
 371         }
 372         if (xcpt & float_flag_inexact) {
 373             env->fpscr |= FPSCR_FLAG_I;
 374         }
 375
 376         /* Accumulate in cause entries */
 377         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 378                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 379
 380         /* Generate an exception if enabled */
 381         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 382         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 383         if (cause & enable) {
 384             raise_exception(env, 0x120, retaddr);
 385         }
 386     }
 387 }
 388
 389 float32 helper_fabs_FT(float32 t0)
 390 {
 391     return float32_abs(t0);
 392 }
 393
 394 float64 helper_fabs_DT(float64 t0)
 395 {
 396     return float64_abs(t0);
 397 }
 398
 399 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 400 {
 401     set_float_exception_flags(0, &env->fp_status);
 402     t0 = float32_add(t0, t1, &env->fp_status);
 403     update_fpscr(env, GETPC());
 404     return t0;
 405 }
 406
 407 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 408 {
 409     set_float_exception_flags(0, &env->fp_status);
 410     t0 = float64_add(t0, t1, &env->fp_status);
 411     update_fpscr(env, GETPC());
 412     return t0;
 413 }
 414
 415 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 416 {
 417     int relation;
 418
 419     set_float_exception_flags(0, &env->fp_status);
 420     relation = float32_compare(t0, t1, &env->fp_status);
 421     if (unlikely(relation == float_relation_unordered)) {
 422         update_fpscr(env, GETPC());
 423     } else if (relation == float_relation_equal) {
 424         set_t(env);
 425     } else {
 426         clr_t(env);
 427     }
 428 }
 429
 430 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 431 {
 432     int relation;
 433
 434     set_float_exception_flags(0, &env->fp_status);
 435     relation = float64_compare(t0, t1, &env->fp_status);
 436     if (unlikely(relation == float_relation_unordered)) {
 437         update_fpscr(env, GETPC());
 438     } else if (relation == float_relation_equal) {
 439         set_t(env);
 440     } else {
 441         clr_t(env);
 442     }
 443 }
 444
 445 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 446 {
 447     int relation;
 448
 449     set_float_exception_flags(0, &env->fp_status);
 450     relation = float32_compare(t0, t1, &env->fp_status);
 451     if (unlikely(relation == float_relation_unordered)) {
 452         update_fpscr(env, GETPC());
 453     } else if (relation == float_relation_greater) {
 454         set_t(env);
 455     } else {
 456         clr_t(env);
 457     }
 458 }
 459
 460 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 461 {
 462     int relation;
 463
 464     set_float_exception_flags(0, &env->fp_status);
 465     relation = float64_compare(t0, t1, &env->fp_status);
 466     if (unlikely(relation == float_relation_unordered)) {
 467         update_fpscr(env, GETPC());
 468     } else if (relation == float_relation_greater) {
 469         set_t(env);
 470     } else {
 471         clr_t(env);
 472     }
 473 }
 474
 475 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 476 {
 477     float64 ret;
 478     set_float_exception_flags(0, &env->fp_status);
 479     ret = float32_to_float64(t0, &env->fp_status);
 480     update_fpscr(env, GETPC());
 481     return ret;
 482 }
 483
 484 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 485 {
 486     float32 ret;
 487     set_float_exception_flags(0, &env->fp_status);
 488     ret = float64_to_float32(t0, &env->fp_status);
 489     update_fpscr(env, GETPC());
 490     return ret;
 491 }
 492
 493 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 494 {
 495     set_float_exception_flags(0, &env->fp_status);
 496     t0 = float32_div(t0, t1, &env->fp_status);
 497     update_fpscr(env, GETPC());
 498     return t0;
 499 }
 500
 501 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 502 {
 503     set_float_exception_flags(0, &env->fp_status);
 504     t0 = float64_div(t0, t1, &env->fp_status);
 505     update_fpscr(env, GETPC());
 506     return t0;
 507 }
 508
 509 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 510 {
 511     float32 ret;
 512     set_float_exception_flags(0, &env->fp_status);
 513     ret = int32_to_float32(t0, &env->fp_status);
 514     update_fpscr(env, GETPC());
 515     return ret;
 516 }
 517
 518 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 519 {
 520     float64 ret;
 521     set_float_exception_flags(0, &env->fp_status);
 522     ret = int32_to_float64(t0, &env->fp_status);
 523     update_fpscr(env, GETPC());
 524     return ret;
 525 }
 526
 527 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 528 {
 529     set_float_exception_flags(0, &env->fp_status);
 530     t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
 531     update_fpscr(env, GETPC());
 532     return t0;
 533 }
 534
 535 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 536 {
 537     set_float_exception_flags(0, &env->fp_status);
 538     t0 = float32_mul(t0, t1, &env->fp_status);
 539     update_fpscr(env, GETPC());
 540     return t0;
 541 }
 542
 543 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 544 {
 545     set_float_exception_flags(0, &env->fp_status);
 546     t0 = float64_mul(t0, t1, &env->fp_status);
 547     update_fpscr(env, GETPC());
 548     return t0;
 549 }
 550
 551 float32 helper_fneg_T(float32 t0)
 552 {
 553     return float32_chs(t0);
 554 }
 555
 556 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 557 {
 558     set_float_exception_flags(0, &env->fp_status);
 559     t0 = float32_sqrt(t0, &env->fp_status);
 560     update_fpscr(env, GETPC());
 561     return t0;
 562 }
 563
 564 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 565 {
 566     set_float_exception_flags(0, &env->fp_status);
 567     t0 = float64_sqrt(t0, &env->fp_status);
 568     update_fpscr(env, GETPC());
 569     return t0;
 570 }
 571
 572 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 573 {
 574     set_float_exception_flags(0, &env->fp_status);
 575     t0 = float32_sub(t0, t1, &env->fp_status);
 576     update_fpscr(env, GETPC());
 577     return t0;
 578 }
 579
 580 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 581 {
 582     set_float_exception_flags(0, &env->fp_status);
 583     t0 = float64_sub(t0, t1, &env->fp_status);
 584     update_fpscr(env, GETPC());
 585     return t0;
 586 }
 587
 588 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 589 {
 590     uint32_t ret;
 591     set_float_exception_flags(0, &env->fp_status);
 592     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 593     update_fpscr(env, GETPC());
 594     return ret;
 595 }
 596
 597 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 598 {
 599     uint32_t ret;
 600     set_float_exception_flags(0, &env->fp_status);
 601     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 602     update_fpscr(env, GETPC());
 603     return ret;
 604 }
 605
 606 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 607 {
 608     int bank, i;
 609     float32 r, p;
 610
 611     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 612     r = float32_zero;
 613     set_float_exception_flags(0, &env->fp_status);
 614
 615     for (i = 0 ; i < 4 ; i++) {
 616         p = float32_mul(env->fregs[bank + m + i],
 617                         env->fregs[bank + n + i],
 618                         &env->fp_status);
 619         r = float32_add(r, p, &env->fp_status);
 620     }
 621     update_fpscr(env, GETPC());
 622
 623     env->fregs[bank + n + 3] = r;
 624 }
 625
 626 void helper_ftrv(CPUSH4State *env, uint32_t n)
 627 {
 628     int bank_matrix, bank_vector;
 629     int i, j;
 630     float32 r[4];
 631     float32 p;
 632
 633     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 634     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 635     set_float_exception_flags(0, &env->fp_status);
 636     for (i = 0 ; i < 4 ; i++) {
 637         r[i] = float32_zero;
 638         for (j = 0 ; j < 4 ; j++) {
 639             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 640                             env->fregs[bank_vector + j],
 641                             &env->fp_status);
 642             r[i] = float32_add(r[i], p, &env->fp_status);
 643         }
 644     }
 645     update_fpscr(env, GETPC());
 646
 647     for (i = 0 ; i < 4 ; i++) {
 648         env->fregs[bank_vector + i] = r[i];
 649     }
 650 }