hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "pci_host.h"
  33 #include "usb-ohci.h"
  34 #include "ppc.h"
  35 #include "boards.h"
  36 #include "qemu-log.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "mc146818rtc.h"
  40 #include "blockdev.h"
  41 #include "exec-memory.h"
  42
  43 //#define HARD_DEBUG_PPC_IO
  44 //#define DEBUG_PPC_IO
  45
  46 /* SMP is not enabled, for now */
  47 #define MAX_CPUS 1
  48
  49 #define MAX_IDE_BUS 2
  50
  51 #define BIOS_SIZE (1024 * 1024)
  52 #define BIOS_FILENAME "ppc_rom.bin"
  53 #define KERNEL_LOAD_ADDR 0x01000000
  54 #define INITRD_LOAD_ADDR 0x01800000
  55
  56 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  57 #define DEBUG_PPC_IO
  58 #endif
  59
  60 #if defined (HARD_DEBUG_PPC_IO)
  61 #define PPC_IO_DPRINTF(fmt, ...)                         \
  62 do {                                                     \
  63     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  64         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  65     } else {                                             \
  66         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  67     }                                                    \
  68 } while (0)
  69 #elif defined (DEBUG_PPC_IO)
  70 #define PPC_IO_DPRINTF(fmt, ...) \
  71 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  72 #else
  73 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  74 #endif
  75
  76 /* Constants for devices init */
  77 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  78 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  79 static const int ide_irq[2] = { 13, 13 };
  80
  81 #define NE2000_NB_MAX 6
  82
  83 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  84 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  85
  86 /* ISA IO ports bridge */
  87 #define PPC_IO_BASE 0x80000000
  88
  89 /* PCI intack register */
  90 /* Read-only register (?) */
  91 static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
  92                               uint64_t value, unsigned size)
  93 {
  94 #if 0
  95     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr,
  96            value);
  97 #endif
  98 }
  99
 100 static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr,
 101                                 unsigned size)
 102 {
 103     uint32_t retval = 0;
 104
 105     if ((addr & 0xf) == 0)
 106         retval = pic_read_irq(isa_pic);
 107 #if 0
 108     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 109            retval);
 110 #endif
 111
 112     return retval;
 113 }
 114
 115 static const MemoryRegionOps PPC_intack_ops = {
 116     .read = PPC_intack_read,
 117     .write = PPC_intack_write,
 118     .endianness = DEVICE_LITTLE_ENDIAN,
 119 };
 120
 121 /* PowerPC control and status registers */
 122 #if 0 // Not used
 123 static struct {
 124     /* IDs */
 125     uint32_t veni_devi;
 126     uint32_t revi;
 127     /* Control and status */
 128     uint32_t gcsr;
 129     uint32_t xcfr;
 130     uint32_t ct32;
 131     uint32_t mcsr;
 132     /* General purpose registers */
 133     uint32_t gprg[6];
 134     /* Exceptions */
 135     uint32_t feen;
 136     uint32_t fest;
 137     uint32_t fema;
 138     uint32_t fecl;
 139     uint32_t eeen;
 140     uint32_t eest;
 141     uint32_t eecl;
 142     uint32_t eeint;
 143     uint32_t eemck0;
 144     uint32_t eemck1;
 145     /* Error diagnostic */
 146 } XCSR;
 147
 148 static void PPC_XCSR_writeb (void *opaque,
 149                              target_phys_addr_t addr, uint32_t value)
 150 {
 151     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 152            value);
 153 }
 154
 155 static void PPC_XCSR_writew (void *opaque,
 156                              target_phys_addr_t addr, uint32_t value)
 157 {
 158     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 159            value);
 160 }
 161
 162 static void PPC_XCSR_writel (void *opaque,
 163                              target_phys_addr_t addr, uint32_t value)
 164 {
 165     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 166            value);
 167 }
 168
 169 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 170 {
 171     uint32_t retval = 0;
 172
 173     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 174            retval);
 175
 176     return retval;
 177 }
 178
 179 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 180 {
 181     uint32_t retval = 0;
 182
 183     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 184            retval);
 185
 186     return retval;
 187 }
 188
 189 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 190 {
 191     uint32_t retval = 0;
 192
 193     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 194            retval);
 195
 196     return retval;
 197 }
 198
 199 static const MemoryRegionOps PPC_XCSR_ops = {
 200     .old_mmio = {
 201         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 202         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 203     },
 204     .endianness = DEVICE_LITTLE_ENDIAN,
 205 };
 206
 207 #endif
 208
 209 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 210 typedef struct sysctrl_t {
 211     qemu_irq reset_irq;
 212     M48t59State *nvram;
 213     uint8_t state;
 214     uint8_t syscontrol;
 215     uint8_t fake_io[2];
 216     int contiguous_map;
 217     int endian;
 218 } sysctrl_t;
 219
 220 enum {
 221     STATE_HARDFILE = 0x01,
 222 };
 223
 224 static sysctrl_t *sysctrl;
 225
 226 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 227 {
 228     sysctrl_t *sysctrl = opaque;
 229
 230     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 231                    val);
 232     sysctrl->fake_io[addr - 0x0398] = val;
 233 }
 234
 235 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 236 {
 237     sysctrl_t *sysctrl = opaque;
 238
 239     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 240                    sysctrl->fake_io[addr - 0x0398]);
 241     return sysctrl->fake_io[addr - 0x0398];
 242 }
 243
 244 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 245 {
 246     sysctrl_t *sysctrl = opaque;
 247
 248     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 249                    addr - PPC_IO_BASE, val);
 250     switch (addr) {
 251     case 0x0092:
 252         /* Special port 92 */
 253         /* Check soft reset asked */
 254         if (val & 0x01) {
 255             qemu_irq_raise(sysctrl->reset_irq);
 256         } else {
 257             qemu_irq_lower(sysctrl->reset_irq);
 258         }
 259         /* Check LE mode */
 260         if (val & 0x02) {
 261             sysctrl->endian = 1;
 262         } else {
 263             sysctrl->endian = 0;
 264         }
 265         break;
 266     case 0x0800:
 267         /* Motorola CPU configuration register : read-only */
 268         break;
 269     case 0x0802:
 270         /* Motorola base module feature register : read-only */
 271         break;
 272     case 0x0803:
 273         /* Motorola base module status register : read-only */
 274         break;
 275     case 0x0808:
 276         /* Hardfile light register */
 277         if (val & 1)
 278             sysctrl->state |= STATE_HARDFILE;
 279         else
 280             sysctrl->state &= ~STATE_HARDFILE;
 281         break;
 282     case 0x0810:
 283         /* Password protect 1 register */
 284         if (sysctrl->nvram != NULL)
 285             m48t59_toggle_lock(sysctrl->nvram, 1);
 286         break;
 287     case 0x0812:
 288         /* Password protect 2 register */
 289         if (sysctrl->nvram != NULL)
 290             m48t59_toggle_lock(sysctrl->nvram, 2);
 291         break;
 292     case 0x0814:
 293         /* L2 invalidate register */
 294         //        tlb_flush(first_cpu, 1);
 295         break;
 296     case 0x081C:
 297         /* system control register */
 298         sysctrl->syscontrol = val & 0x0F;
 299         break;
 300     case 0x0850:
 301         /* I/O map type register */
 302         sysctrl->contiguous_map = val & 0x01;
 303         break;
 304     default:
 305         printf("ERROR: unaffected IO port write: %04" PRIx32
 306                " => %02" PRIx32"\n", addr, val);
 307         break;
 308     }
 309 }
 310
 311 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 312 {
 313     sysctrl_t *sysctrl = opaque;
 314     uint32_t retval = 0xFF;
 315
 316     switch (addr) {
 317     case 0x0092:
 318         /* Special port 92 */
 319         retval = 0x00;
 320         break;
 321     case 0x0800:
 322         /* Motorola CPU configuration register */
 323         retval = 0xEF; /* MPC750 */
 324         break;
 325     case 0x0802:
 326         /* Motorola Base module feature register */
 327         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 328         break;
 329     case 0x0803:
 330         /* Motorola base module status register */
 331         retval = 0xE0; /* Standard MPC750 */
 332         break;
 333     case 0x080C:
 334         /* Equipment present register:
 335          *  no L2 cache
 336          *  no upgrade processor
 337          *  no cards in PCI slots
 338          *  SCSI fuse is bad
 339          */
 340         retval = 0x3C;
 341         break;
 342     case 0x0810:
 343         /* Motorola base module extended feature register */
 344         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 345         break;
 346     case 0x0814:
 347         /* L2 invalidate: don't care */
 348         break;
 349     case 0x0818:
 350         /* Keylock */
 351         retval = 0x00;
 352         break;
 353     case 0x081C:
 354         /* system control register
 355          * 7 - 6 / 1 - 0: L2 cache enable
 356          */
 357         retval = sysctrl->syscontrol;
 358         break;
 359     case 0x0823:
 360         /* */
 361         retval = 0x03; /* no L2 cache */
 362         break;
 363     case 0x0850:
 364         /* I/O map type register */
 365         retval = sysctrl->contiguous_map;
 366         break;
 367     default:
 368         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 369         break;
 370     }
 371     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 372                    addr - PPC_IO_BASE, retval);
 373
 374     return retval;
 375 }
 376
 377 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 378                                                  target_phys_addr_t addr)
 379 {
 380     if (sysctrl->contiguous_map == 0) {
 381         /* 64 KB contiguous space for IOs */
 382         addr &= 0xFFFF;
 383     } else {
 384         /* 8 MB non-contiguous space for IOs */
 385         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 386     }
 387
 388     return addr;
 389 }
 390
 391 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 392                                 uint32_t value)
 393 {
 394     sysctrl_t *sysctrl = opaque;
 395
 396     addr = prep_IO_address(sysctrl, addr);
 397     cpu_outb(addr, value);
 398 }
 399
 400 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 401 {
 402     sysctrl_t *sysctrl = opaque;
 403     uint32_t ret;
 404
 405     addr = prep_IO_address(sysctrl, addr);
 406     ret = cpu_inb(addr);
 407
 408     return ret;
 409 }
 410
 411 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 412                                 uint32_t value)
 413 {
 414     sysctrl_t *sysctrl = opaque;
 415
 416     addr = prep_IO_address(sysctrl, addr);
 417     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 418     cpu_outw(addr, value);
 419 }
 420
 421 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 422 {
 423     sysctrl_t *sysctrl = opaque;
 424     uint32_t ret;
 425
 426     addr = prep_IO_address(sysctrl, addr);
 427     ret = cpu_inw(addr);
 428     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 429
 430     return ret;
 431 }
 432
 433 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 434                                 uint32_t value)
 435 {
 436     sysctrl_t *sysctrl = opaque;
 437
 438     addr = prep_IO_address(sysctrl, addr);
 439     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 440     cpu_outl(addr, value);
 441 }
 442
 443 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 444 {
 445     sysctrl_t *sysctrl = opaque;
 446     uint32_t ret;
 447
 448     addr = prep_IO_address(sysctrl, addr);
 449     ret = cpu_inl(addr);
 450     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 451
 452     return ret;
 453 }
 454
 455 static const MemoryRegionOps PPC_prep_io_ops = {
 456     .old_mmio = {
 457         .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
 458         .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
 459     },
 460     .endianness = DEVICE_LITTLE_ENDIAN,
 461 };
 462
 463 #define NVRAM_SIZE        0x2000
 464
 465 static void cpu_request_exit(void *opaque, int irq, int level)
 466 {
 467     CPUState *env = cpu_single_env;
 468
 469     if (env && level) {
 470         cpu_exit(env);
 471     }
 472 }
 473
 474 /* PowerPC PREP hardware initialisation */
 475 static void ppc_prep_init (ram_addr_t ram_size,
 476                            const char *boot_device,
 477                            const char *kernel_filename,
 478                            const char *kernel_cmdline,
 479                            const char *initrd_filename,
 480                            const char *cpu_model)
 481 {
 482     MemoryRegion *sysmem = get_system_memory();
 483     CPUState *env = NULL;
 484     char *filename;
 485     nvram_t nvram;
 486     M48t59State *m48t59;
 487     MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
 488     MemoryRegion *intack = g_new(MemoryRegion, 1);
 489 #if 0
 490     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 491 #endif
 492     int linux_boot, i, nb_nics1, bios_size;
 493     MemoryRegion *ram = g_new(MemoryRegion, 1);
 494     MemoryRegion *bios = g_new(MemoryRegion, 1);
 495     uint32_t kernel_base, initrd_base;
 496     long kernel_size, initrd_size;
 497     DeviceState *dev;
 498     SysBusDevice *sys;
 499     PCIHostState *pcihost;
 500     PCIBus *pci_bus;
 501     PCIDevice *pci;
 502     ISABus *isa_bus;
 503     qemu_irq *cpu_exit_irq;
 504     int ppc_boot_device;
 505     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 506     DriveInfo *fd[MAX_FD];
 507
 508     sysctrl = g_malloc0(sizeof(sysctrl_t));
 509
 510     linux_boot = (kernel_filename != NULL);
 511
 512     /* init CPUs */
 513     if (cpu_model == NULL)
 514         cpu_model = "602";
 515     for (i = 0; i < smp_cpus; i++) {
 516         env = cpu_init(cpu_model);
 517         if (!env) {
 518             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 519             exit(1);
 520         }
 521         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 522             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 523             cpu_ppc_tb_init(env, 7812500UL);
 524         } else {
 525             /* Set time-base frequency to 100 Mhz */
 526             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 527         }
 528         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 529     }
 530
 531     /* allocate RAM */
 532     memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
 533     vmstate_register_ram_global(ram);
 534     memory_region_add_subregion(sysmem, 0, ram);
 535
 536     /* allocate and load BIOS */
 537     memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
 538     memory_region_set_readonly(bios, true);
 539     memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios);
 540     vmstate_register_ram_global(bios);
 541     if (bios_name == NULL)
 542         bios_name = BIOS_FILENAME;
 543     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 544     if (filename) {
 545         bios_size = get_image_size(filename);
 546     } else {
 547         bios_size = -1;
 548     }
 549     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 550         target_phys_addr_t bios_addr;
 551         bios_size = (bios_size + 0xfff) & ~0xfff;
 552         bios_addr = (uint32_t)(-bios_size);
 553         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 554     }
 555     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 556         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 557     }
 558     if (filename) {
 559         g_free(filename);
 560     }
 561
 562     if (linux_boot) {
 563         kernel_base = KERNEL_LOAD_ADDR;
 564         /* now we can load the kernel */
 565         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 566                                           ram_size - kernel_base);
 567         if (kernel_size < 0) {
 568             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 569             exit(1);
 570         }
 571         /* load initrd */
 572         if (initrd_filename) {
 573             initrd_base = INITRD_LOAD_ADDR;
 574             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 575                                               ram_size - initrd_base);
 576             if (initrd_size < 0) {
 577                 hw_error("qemu: could not load initial ram disk '%s'\n",
 578                           initrd_filename);
 579             }
 580         } else {
 581             initrd_base = 0;
 582             initrd_size = 0;
 583         }
 584         ppc_boot_device = 'm';
 585     } else {
 586         kernel_base = 0;
 587         kernel_size = 0;
 588         initrd_base = 0;
 589         initrd_size = 0;
 590         ppc_boot_device = '\0';
 591         /* For now, OHW cannot boot from the network. */
 592         for (i = 0; boot_device[i] != '\0'; i++) {
 593             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 594                 ppc_boot_device = boot_device[i];
 595                 break;
 596             }
 597         }
 598         if (ppc_boot_device == '\0') {
 599             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 600             exit(1);
 601         }
 602     }
 603
 604     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 605         hw_error("Only 6xx bus is supported on PREP machine\n");
 606     }
 607
 608     dev = qdev_create(NULL, "raven-pcihost");
 609     sys = sysbus_from_qdev(dev);
 610     pcihost = DO_UPCAST(PCIHostState, busdev, sys);
 611     pcihost->address_space = get_system_memory();
 612     qdev_init_nofail(dev);
 613     qdev_property_add_child(qdev_get_root(), "raven", dev, NULL);
 614     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 615     if (pci_bus == NULL) {
 616         fprintf(stderr, "Couldn't create PCI host controller.\n");
 617         exit(1);
 618     }
 619
 620     /* PCI -> ISA bridge */
 621     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 622     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 623     qdev_connect_gpio_out(&pci->qdev, 0,
 624                           first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 625     qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
 626     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 627     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 628     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 629     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 630     isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
 631
 632     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 633     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
 634                           "ppc-io", 0x00800000);
 635     memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
 636
 637     /* init basic PC hardware */
 638     pci_vga_init(pci_bus);
 639
 640     if (serial_hds[0])
 641         serial_isa_init(isa_bus, 0, serial_hds[0]);
 642     nb_nics1 = nb_nics;
 643     if (nb_nics1 > NE2000_NB_MAX)
 644         nb_nics1 = NE2000_NB_MAX;
 645     for(i = 0; i < nb_nics1; i++) {
 646         if (nd_table[i].model == NULL) {
 647             nd_table[i].model = g_strdup("ne2k_isa");
 648         }
 649         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 650             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 651                             &nd_table[i]);
 652         } else {
 653             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 654         }
 655     }
 656
 657     ide_drive_get(hd, MAX_IDE_BUS);
 658     for(i = 0; i < MAX_IDE_BUS; i++) {
 659         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 660                      hd[2 * i],
 661                      hd[2 * i + 1]);
 662     }
 663     isa_create_simple(isa_bus, "i8042");
 664
 665     //    SB16_init();
 666
 667     for(i = 0; i < MAX_FD; i++) {
 668         fd[i] = drive_get(IF_FLOPPY, 0, i);
 669     }
 670     fdctrl_init_isa(isa_bus, fd);
 671
 672     /* Register fake IO ports for PREP */
 673     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 674     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 675     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 676     /* System control ports */
 677     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 678     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 679     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 680     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 681     /* PCI intack location */
 682     memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4);
 683     memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack);
 684     /* PowerPC control and status register group */
 685 #if 0
 686     memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 687     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 688 #endif
 689
 690     if (usb_enabled) {
 691         usb_ohci_init_pci(pci_bus, -1);
 692     }
 693
 694     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 695     if (m48t59 == NULL)
 696         return;
 697     sysctrl->nvram = m48t59;
 698
 699     /* Initialise NVRAM */
 700     nvram.opaque = m48t59;
 701     nvram.read_fn = &m48t59_read;
 702     nvram.write_fn = &m48t59_write;
 703     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 704                          kernel_base, kernel_size,
 705                          kernel_cmdline,
 706                          initrd_base, initrd_size,
 707                          /* XXX: need an option to load a NVRAM image */
 708                          0,
 709                          graphic_width, graphic_height, graphic_depth);
 710
 711     /* Special port to get debug messages from Open-Firmware */
 712     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 713 }
 714
 715 static QEMUMachine prep_machine = {
 716     .name = "prep",
 717     .desc = "PowerPC PREP platform",
 718     .init = ppc_prep_init,
 719     .max_cpus = MAX_CPUS,
 720 };
 721
 722 static void prep_machine_init(void)
 723 {
 724     qemu_register_machine(&prep_machine);
 725 }
 726
 727 machine_init(prep_machine_init);