include/hw/ssi/ibex_spi_host.h

   1
   2 /*
   3  * QEMU model of the Ibex SPI Controller
   4  * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/
   5  *
   6  * Copyright (C) 2022 Western Digital
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #ifndef IBEX_SPI_HOST_H
  28 #define IBEX_SPI_HOST_H
  29
  30 #include "hw/sysbus.h"
  31 #include "hw/hw.h"
  32 #include "hw/ssi/ssi.h"
  33 #include "qemu/fifo8.h"
  34 #include "qom/object.h"
  35 #include "qemu/timer.h"
  36
  37 #define TYPE_IBEX_SPI_HOST "ibex-spi"
  38 #define IBEX_SPI_HOST(obj) \
  39     OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST)
  40
  41 /* SPI Registers */
  42 #define IBEX_SPI_HOST_INTR_STATE         (0x00 / 4)  /* rw1c */
  43 #define IBEX_SPI_HOST_INTR_ENABLE        (0x04 / 4)  /* rw */
  44 #define IBEX_SPI_HOST_INTR_TEST          (0x08 / 4)  /* wo */
  45 #define IBEX_SPI_HOST_ALERT_TEST         (0x0c / 4)  /* wo */
  46 #define IBEX_SPI_HOST_CONTROL            (0x10 / 4)  /* rw */
  47 #define IBEX_SPI_HOST_STATUS             (0x14 / 4)  /* ro */
  48 #define IBEX_SPI_HOST_CONFIGOPTS         (0x18 / 4)  /* rw */
  49 #define IBEX_SPI_HOST_CSID               (0x1c / 4)  /* rw */
  50 #define IBEX_SPI_HOST_COMMAND            (0x20 / 4)  /* wo */
  51 /* RX/TX Modelled by FIFO */
  52 #define IBEX_SPI_HOST_RXDATA             (0x24 / 4)
  53 #define IBEX_SPI_HOST_TXDATA             (0x28 / 4)
  54
  55 #define IBEX_SPI_HOST_ERROR_ENABLE       (0x2c / 4)  /* rw */
  56 #define IBEX_SPI_HOST_ERROR_STATUS       (0x30 / 4)  /* rw1c */
  57 #define IBEX_SPI_HOST_EVENT_ENABLE       (0x34 / 4)  /* rw */
  58
  59 /* FIFO Len in Bytes */
  60 #define IBEX_SPI_HOST_TXFIFO_LEN         288
  61 #define IBEX_SPI_HOST_RXFIFO_LEN         256
  62
  63 /*  Max Register (Based on addr) */
  64 #define IBEX_SPI_HOST_MAX_REGS           (IBEX_SPI_HOST_EVENT_ENABLE + 1)
  65
  66 /* MISC */
  67 #define TX_INTERRUPT_TRIGGER_DELAY_NS    100
  68 #define BIDIRECTIONAL_TRANSFER           3
  69
  70 typedef struct {
  71     /* <private> */
  72     SysBusDevice parent_obj;
  73
  74     /* <public> */
  75     MemoryRegion mmio;
  76     uint32_t regs[IBEX_SPI_HOST_MAX_REGS];
  77     /* Multi-reg that sets config opts per CS */
  78     uint32_t *config_opts;
  79     Fifo8 rx_fifo;
  80     Fifo8 tx_fifo;
  81     QEMUTimer *fifo_trigger_handle;
  82
  83     qemu_irq event;
  84     qemu_irq host_err;
  85     uint32_t num_cs;
  86     qemu_irq *cs_lines;
  87     SSIBus *ssi;
  88
  89     /* Used to track the init status, for replicating TXDATA ghost writes */
  90     bool init_status;
  91 } IbexSPIHostState;
  92
  93 #endif