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tcg/mips: Remove retranslation code
[qemu/ar7.git] / tcg / mips / tcg-target.inc.c
blobe21cb1ae2862a946aa98cf5ded78d2c760794820
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #ifdef HOST_WORDS_BIGENDIAN
28 # define MIPS_BE 1
29 #else
30 # define MIPS_BE 0
31 #endif
32
33 #if TCG_TARGET_REG_BITS == 32
34 # define LO_OFF (MIPS_BE * 4)
35 # define HI_OFF (4 - LO_OFF)
36 #else
37 /* To assert at compile-time that these values are never used
38 for TCG_TARGET_REG_BITS == 64. */
39 int link_error(void);
40 # define LO_OFF link_error()
41 # define HI_OFF link_error()
42 #endif
43
44 #ifdef CONFIG_DEBUG_TCG
45 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "zero",
47 "at",
48 "v0",
49 "v1",
50 "a0",
51 "a1",
52 "a2",
53 "a3",
54 "t0",
55 "t1",
56 "t2",
57 "t3",
58 "t4",
59 "t5",
60 "t6",
61 "t7",
62 "s0",
63 "s1",
64 "s2",
65 "s3",
66 "s4",
67 "s5",
68 "s6",
69 "s7",
70 "t8",
71 "t9",
72 "k0",
73 "k1",
74 "gp",
75 "sp",
76 "s8",
77 "ra",
78 };
79 #endif
80
81 #define TCG_TMP0 TCG_REG_AT
82 #define TCG_TMP1 TCG_REG_T9
83 #define TCG_TMP2 TCG_REG_T8
84 #define TCG_TMP3 TCG_REG_T7
85
86 #ifndef CONFIG_SOFTMMU
87 #define TCG_GUEST_BASE_REG TCG_REG_S1
88 #endif
89
90 /* check if we really need so many registers :P */
91 static const int tcg_target_reg_alloc_order[] = {
92 /* Call saved registers. */
93 TCG_REG_S0,
94 TCG_REG_S1,
95 TCG_REG_S2,
96 TCG_REG_S3,
97 TCG_REG_S4,
98 TCG_REG_S5,
99 TCG_REG_S6,
100 TCG_REG_S7,
101 TCG_REG_S8,
102
103 /* Call clobbered registers. */
104 TCG_REG_T4,
105 TCG_REG_T5,
106 TCG_REG_T6,
107 TCG_REG_T7,
108 TCG_REG_T8,
109 TCG_REG_T9,
110 TCG_REG_V1,
111 TCG_REG_V0,
112
113 /* Argument registers, opposite order of allocation. */
114 TCG_REG_T3,
115 TCG_REG_T2,
116 TCG_REG_T1,
117 TCG_REG_T0,
118 TCG_REG_A3,
119 TCG_REG_A2,
120 TCG_REG_A1,
121 TCG_REG_A0,
122 };
123
124 static const TCGReg tcg_target_call_iarg_regs[] = {
125 TCG_REG_A0,
126 TCG_REG_A1,
127 TCG_REG_A2,
128 TCG_REG_A3,
129 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
130 TCG_REG_T0,
131 TCG_REG_T1,
132 TCG_REG_T2,
133 TCG_REG_T3,
134 #endif
135 };
136
137 static const TCGReg tcg_target_call_oarg_regs[2] = {
138 TCG_REG_V0,
139 TCG_REG_V1
140 };
141
142 static tcg_insn_unit *tb_ret_addr;
143 static tcg_insn_unit *bswap32_addr;
144 static tcg_insn_unit *bswap32u_addr;
145 static tcg_insn_unit *bswap64_addr;
146
147 static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
148 {
149 /* Let the compiler perform the right-shift as part of the arithmetic. */
150 ptrdiff_t disp = target - (pc + 1);
151 tcg_debug_assert(disp == (int16_t)disp);
152 return disp & 0xffff;
153 }
154
155 static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
156 {
157 *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
158 }
159
160 static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
161 {
162 tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
163 return ((uintptr_t)target >> 2) & 0x3ffffff;
164 }
165
166 static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
167 {
168 *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target));
169 }
170
171 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
172 intptr_t value, intptr_t addend)
173 {
174 tcg_debug_assert(type == R_MIPS_PC16);
175 tcg_debug_assert(addend == 0);
176 reloc_pc16(code_ptr, (tcg_insn_unit *)value);
177 }
178
179 #define TCG_CT_CONST_ZERO 0x100
180 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
181 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
182 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
183 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
184 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
185
186 static inline bool is_p2m1(tcg_target_long val)
187 {
188 return val && ((val + 1) & val) == 0;
189 }
190
191 /* parse target specific constraints */
192 static const char *target_parse_constraint(TCGArgConstraint *ct,
193 const char *ct_str, TCGType type)
194 {
195 switch(*ct_str++) {
196 case 'r':
197 ct->ct |= TCG_CT_REG;
198 ct->u.regs = 0xffffffff;
199 break;
200 case 'L': /* qemu_ld input arg constraint */
201 ct->ct |= TCG_CT_REG;
202 ct->u.regs = 0xffffffff;
203 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
204 #if defined(CONFIG_SOFTMMU)
205 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
206 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
207 }
208 #endif
209 break;
210 case 'S': /* qemu_st constraint */
211 ct->ct |= TCG_CT_REG;
212 ct->u.regs = 0xffffffff;
213 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
214 #if defined(CONFIG_SOFTMMU)
215 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
216 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
217 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
218 } else {
219 tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
220 }
221 #endif
222 break;
223 case 'I':
224 ct->ct |= TCG_CT_CONST_U16;
225 break;
226 case 'J':
227 ct->ct |= TCG_CT_CONST_S16;
228 break;
229 case 'K':
230 ct->ct |= TCG_CT_CONST_P2M1;
231 break;
232 case 'N':
233 ct->ct |= TCG_CT_CONST_N16;
234 break;
235 case 'W':
236 ct->ct |= TCG_CT_CONST_WSZ;
237 break;
238 case 'Z':
239 /* We are cheating a bit here, using the fact that the register
240 ZERO is also the register number 0. Hence there is no need
241 to check for const_args in each instruction. */
242 ct->ct |= TCG_CT_CONST_ZERO;
243 break;
244 default:
245 return NULL;
246 }
247 return ct_str;
248 }
249
250 /* test if a constant matches the constraint */
251 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
252 const TCGArgConstraint *arg_ct)
253 {
254 int ct;
255 ct = arg_ct->ct;
256 if (ct & TCG_CT_CONST) {
257 return 1;
258 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
259 return 1;
260 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
261 return 1;
262 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
263 return 1;
264 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
265 return 1;
266 } else if ((ct & TCG_CT_CONST_P2M1)
267 && use_mips32r2_instructions && is_p2m1(val)) {
268 return 1;
269 } else if ((ct & TCG_CT_CONST_WSZ)
270 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
271 return 1;
272 }
273 return 0;
274 }
275
276 /* instruction opcodes */
277 typedef enum {
278 OPC_J = 002 << 26,
279 OPC_JAL = 003 << 26,
280 OPC_BEQ = 004 << 26,
281 OPC_BNE = 005 << 26,
282 OPC_BLEZ = 006 << 26,
283 OPC_BGTZ = 007 << 26,
284 OPC_ADDIU = 011 << 26,
285 OPC_SLTI = 012 << 26,
286 OPC_SLTIU = 013 << 26,
287 OPC_ANDI = 014 << 26,
288 OPC_ORI = 015 << 26,
289 OPC_XORI = 016 << 26,
290 OPC_LUI = 017 << 26,
291 OPC_DADDIU = 031 << 26,
292 OPC_LB = 040 << 26,
293 OPC_LH = 041 << 26,
294 OPC_LW = 043 << 26,
295 OPC_LBU = 044 << 26,
296 OPC_LHU = 045 << 26,
297 OPC_LWU = 047 << 26,
298 OPC_SB = 050 << 26,
299 OPC_SH = 051 << 26,
300 OPC_SW = 053 << 26,
301 OPC_LD = 067 << 26,
302 OPC_SD = 077 << 26,
303
304 OPC_SPECIAL = 000 << 26,
305 OPC_SLL = OPC_SPECIAL | 000,
306 OPC_SRL = OPC_SPECIAL | 002,
307 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
308 OPC_SRA = OPC_SPECIAL | 003,
309 OPC_SLLV = OPC_SPECIAL | 004,
310 OPC_SRLV = OPC_SPECIAL | 006,
311 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
312 OPC_SRAV = OPC_SPECIAL | 007,
313 OPC_JR_R5 = OPC_SPECIAL | 010,
314 OPC_JALR = OPC_SPECIAL | 011,
315 OPC_MOVZ = OPC_SPECIAL | 012,
316 OPC_MOVN = OPC_SPECIAL | 013,
317 OPC_SYNC = OPC_SPECIAL | 017,
318 OPC_MFHI = OPC_SPECIAL | 020,
319 OPC_MFLO = OPC_SPECIAL | 022,
320 OPC_DSLLV = OPC_SPECIAL | 024,
321 OPC_DSRLV = OPC_SPECIAL | 026,
322 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
323 OPC_DSRAV = OPC_SPECIAL | 027,
324 OPC_MULT = OPC_SPECIAL | 030,
325 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
326 OPC_MUH = OPC_SPECIAL | 030 | 0300,
327 OPC_MULTU = OPC_SPECIAL | 031,
328 OPC_MULU = OPC_SPECIAL | 031 | 0200,
329 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
330 OPC_DIV = OPC_SPECIAL | 032,
331 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
332 OPC_MOD = OPC_SPECIAL | 032 | 0300,
333 OPC_DIVU = OPC_SPECIAL | 033,
334 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
335 OPC_MODU = OPC_SPECIAL | 033 | 0300,
336 OPC_DMULT = OPC_SPECIAL | 034,
337 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
338 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
339 OPC_DMULTU = OPC_SPECIAL | 035,
340 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
341 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
342 OPC_DDIV = OPC_SPECIAL | 036,
343 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
344 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
345 OPC_DDIVU = OPC_SPECIAL | 037,
346 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
347 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
348 OPC_ADDU = OPC_SPECIAL | 041,
349 OPC_SUBU = OPC_SPECIAL | 043,
350 OPC_AND = OPC_SPECIAL | 044,
351 OPC_OR = OPC_SPECIAL | 045,
352 OPC_XOR = OPC_SPECIAL | 046,
353 OPC_NOR = OPC_SPECIAL | 047,
354 OPC_SLT = OPC_SPECIAL | 052,
355 OPC_SLTU = OPC_SPECIAL | 053,
356 OPC_DADDU = OPC_SPECIAL | 055,
357 OPC_DSUBU = OPC_SPECIAL | 057,
358 OPC_SELEQZ = OPC_SPECIAL | 065,
359 OPC_SELNEZ = OPC_SPECIAL | 067,
360 OPC_DSLL = OPC_SPECIAL | 070,
361 OPC_DSRL = OPC_SPECIAL | 072,
362 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
363 OPC_DSRA = OPC_SPECIAL | 073,
364 OPC_DSLL32 = OPC_SPECIAL | 074,
365 OPC_DSRL32 = OPC_SPECIAL | 076,
366 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
367 OPC_DSRA32 = OPC_SPECIAL | 077,
368 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
369 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
370
371 OPC_REGIMM = 001 << 26,
372 OPC_BLTZ = OPC_REGIMM | (000 << 16),
373 OPC_BGEZ = OPC_REGIMM | (001 << 16),
374
375 OPC_SPECIAL2 = 034 << 26,
376 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
377 OPC_CLZ = OPC_SPECIAL2 | 040,
378 OPC_DCLZ = OPC_SPECIAL2 | 044,
379
380 OPC_SPECIAL3 = 037 << 26,
381 OPC_EXT = OPC_SPECIAL3 | 000,
382 OPC_DEXTM = OPC_SPECIAL3 | 001,
383 OPC_DEXTU = OPC_SPECIAL3 | 002,
384 OPC_DEXT = OPC_SPECIAL3 | 003,
385 OPC_INS = OPC_SPECIAL3 | 004,
386 OPC_DINSM = OPC_SPECIAL3 | 005,
387 OPC_DINSU = OPC_SPECIAL3 | 006,
388 OPC_DINS = OPC_SPECIAL3 | 007,
389 OPC_WSBH = OPC_SPECIAL3 | 00240,
390 OPC_DSBH = OPC_SPECIAL3 | 00244,
391 OPC_DSHD = OPC_SPECIAL3 | 00544,
392 OPC_SEB = OPC_SPECIAL3 | 02040,
393 OPC_SEH = OPC_SPECIAL3 | 03040,
394
395 /* MIPS r6 doesn't have JR, JALR should be used instead */
396 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
397
398 /*
399 * MIPS r6 replaces MUL with an alternative encoding which is
400 * backwards-compatible at the assembly level.
401 */
402 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
403
404 /* MIPS r6 introduced names for weaker variants of SYNC. These are
405 backward compatible to previous architecture revisions. */
406 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 5,
407 OPC_SYNC_MB = OPC_SYNC | 0x10 << 5,
408 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 5,
409 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 5,
410 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 5,
411
412 /* Aliases for convenience. */
413 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
414 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
415 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
416 ? OPC_SRL : OPC_DSRL,
417 } MIPSInsn;
418
419 /*
420 * Type reg
421 */
422 static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
423 TCGReg rd, TCGReg rs, TCGReg rt)
424 {
425 int32_t inst;
426
427 inst = opc;
428 inst |= (rs & 0x1F) << 21;
429 inst |= (rt & 0x1F) << 16;
430 inst |= (rd & 0x1F) << 11;
431 tcg_out32(s, inst);
432 }
433
434 /*
435 * Type immediate
436 */
437 static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
438 TCGReg rt, TCGReg rs, TCGArg imm)
439 {
440 int32_t inst;
441
442 inst = opc;
443 inst |= (rs & 0x1F) << 21;
444 inst |= (rt & 0x1F) << 16;
445 inst |= (imm & 0xffff);
446 tcg_out32(s, inst);
447 }
448
449 /*
450 * Type bitfield
451 */
452 static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
453 TCGReg rs, int msb, int lsb)
454 {
455 int32_t inst;
456
457 inst = opc;
458 inst |= (rs & 0x1F) << 21;
459 inst |= (rt & 0x1F) << 16;
460 inst |= (msb & 0x1F) << 11;
461 inst |= (lsb & 0x1F) << 6;
462 tcg_out32(s, inst);
463 }
464
465 static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
466 MIPSInsn oph, TCGReg rt, TCGReg rs,
467 int msb, int lsb)
468 {
469 if (lsb >= 32) {
470 opc = oph;
471 msb -= 32;
472 lsb -= 32;
473 } else if (msb >= 32) {
474 opc = opm;
475 msb -= 32;
476 }
477 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
478 }
479
480 /*
481 * Type branch
482 */
483 static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
484 TCGReg rt, TCGReg rs)
485 {
486 tcg_out_opc_imm(s, opc, rt, rs, 0);
487 }
488
489 /*
490 * Type sa
491 */
492 static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
493 TCGReg rd, TCGReg rt, TCGArg sa)
494 {
495 int32_t inst;
496
497 inst = opc;
498 inst |= (rt & 0x1F) << 16;
499 inst |= (rd & 0x1F) << 11;
500 inst |= (sa & 0x1F) << 6;
501 tcg_out32(s, inst);
502
503 }
504
505 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
506 TCGReg rd, TCGReg rt, TCGArg sa)
507 {
508 int32_t inst;
509
510 inst = (sa & 32 ? opc2 : opc1);
511 inst |= (rt & 0x1F) << 16;
512 inst |= (rd & 0x1F) << 11;
513 inst |= (sa & 0x1F) << 6;
514 tcg_out32(s, inst);
515 }
516
517 /*
518 * Type jump.
519 * Returns true if the branch was in range and the insn was emitted.
520 */
521 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
522 {
523 uintptr_t dest = (uintptr_t)target;
524 uintptr_t from = (uintptr_t)s->code_ptr + 4;
525 int32_t inst;
526
527 /* The pc-region branch happens within the 256MB region of
528 the delay slot (thus the +4). */
529 if ((from ^ dest) & -(1 << 28)) {
530 return false;
531 }
532 tcg_debug_assert((dest & 3) == 0);
533
534 inst = opc;
535 inst |= (dest >> 2) & 0x3ffffff;
536 tcg_out32(s, inst);
537 return true;
538 }
539
540 static inline void tcg_out_nop(TCGContext *s)
541 {
542 tcg_out32(s, 0);
543 }
544
545 static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
546 {
547 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
548 }
549
550 static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
551 {
552 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
553 }
554
555 static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
556 {
557 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
558 }
559
560 static inline void tcg_out_mov(TCGContext *s, TCGType type,
561 TCGReg ret, TCGReg arg)
562 {
563 /* Simple reg-reg move, optimising out the 'do nothing' case */
564 if (ret != arg) {
565 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
566 }
567 }
568
569 static void tcg_out_movi(TCGContext *s, TCGType type,
570 TCGReg ret, tcg_target_long arg)
571 {
572 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
573 arg = (int32_t)arg;
574 }
575 if (arg == (int16_t)arg) {
576 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
577 return;
578 }
579 if (arg == (uint16_t)arg) {
580 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
581 return;
582 }
583 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
584 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
585 } else {
586 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
587 if (arg & 0xffff0000ull) {
588 tcg_out_dsll(s, ret, ret, 16);
589 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
590 tcg_out_dsll(s, ret, ret, 16);
591 } else {
592 tcg_out_dsll(s, ret, ret, 32);
593 }
594 }
595 if (arg & 0xffff) {
596 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
597 }
598 }
599
600 static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
601 {
602 if (use_mips32r2_instructions) {
603 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
604 } else {
605 /* ret and arg can't be register at */
606 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
607 tcg_abort();
608 }
609
610 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
611 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
612 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
613 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
614 }
615 }
616
617 static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
618 {
619 if (use_mips32r2_instructions) {
620 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
621 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
622 } else {
623 /* ret and arg can't be register at */
624 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
625 tcg_abort();
626 }
627
628 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
629 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
630 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
631 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
632 }
633 }
634
635 static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub)
636 {
637 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
638 tcg_debug_assert(ok);
639 }
640
641 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
642 {
643 if (use_mips32r2_instructions) {
644 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
645 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
646 } else {
647 tcg_out_bswap_subr(s, bswap32_addr);
648 /* delay slot -- never omit the insn, like tcg_out_mov might. */
649 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
650 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
651 }
652 }
653
654 static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
655 {
656 if (use_mips32r2_instructions) {
657 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
658 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
659 tcg_out_dsrl(s, ret, ret, 32);
660 } else {
661 tcg_out_bswap_subr(s, bswap32u_addr);
662 /* delay slot -- never omit the insn, like tcg_out_mov might. */
663 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
664 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
665 }
666 }
667
668 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
669 {
670 if (use_mips32r2_instructions) {
671 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
672 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
673 } else {
674 tcg_out_bswap_subr(s, bswap64_addr);
675 /* delay slot -- never omit the insn, like tcg_out_mov might. */
676 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
677 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
678 }
679 }
680
681 static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
682 {
683 if (use_mips32r2_instructions) {
684 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
685 } else {
686 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
687 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
688 }
689 }
690
691 static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
692 {
693 if (use_mips32r2_instructions) {
694 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
695 } else {
696 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
697 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
698 }
699 }
700
701 static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
702 {
703 if (use_mips32r2_instructions) {
704 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
705 } else {
706 tcg_out_dsll(s, ret, arg, 32);
707 tcg_out_dsrl(s, ret, ret, 32);
708 }
709 }
710
711 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
712 TCGReg addr, intptr_t ofs)
713 {
714 int16_t lo = ofs;
715 if (ofs != lo) {
716 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
717 if (addr != TCG_REG_ZERO) {
718 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
719 }
720 addr = TCG_TMP0;
721 }
722 tcg_out_opc_imm(s, opc, data, addr, lo);
723 }
724
725 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
726 TCGReg arg1, intptr_t arg2)
727 {
728 MIPSInsn opc = OPC_LD;
729 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
730 opc = OPC_LW;
731 }
732 tcg_out_ldst(s, opc, arg, arg1, arg2);
733 }
734
735 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
736 TCGReg arg1, intptr_t arg2)
737 {
738 MIPSInsn opc = OPC_SD;
739 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
740 opc = OPC_SW;
741 }
742 tcg_out_ldst(s, opc, arg, arg1, arg2);
743 }
744
745 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
746 TCGReg base, intptr_t ofs)
747 {
748 if (val == 0) {
749 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
750 return true;
751 }
752 return false;
753 }
754
755 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
756 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
757 bool cbh, bool is_sub)
758 {
759 TCGReg th = TCG_TMP1;
760
761 /* If we have a negative constant such that negating it would
762 make the high part zero, we can (usually) eliminate one insn. */
763 if (cbl && cbh && bh == -1 && bl != 0) {
764 bl = -bl;
765 bh = 0;
766 is_sub = !is_sub;
767 }
768
769 /* By operating on the high part first, we get to use the final
770 carry operation to move back from the temporary. */
771 if (!cbh) {
772 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
773 } else if (bh != 0 || ah == rl) {
774 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
775 } else {
776 th = ah;
777 }
778
779 /* Note that tcg optimization should eliminate the bl == 0 case. */
780 if (is_sub) {
781 if (cbl) {
782 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
783 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
784 } else {
785 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
786 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
787 }
788 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
789 } else {
790 if (cbl) {
791 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
792 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
793 } else if (rl == al && rl == bl) {
794 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, 31);
795 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
796 } else {
797 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
798 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
799 }
800 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
801 }
802 }
803
804 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
805 #define MIPS_CMP_INV 1
806 #define MIPS_CMP_SWAP 2
807
808 static const uint8_t mips_cmp_map[16] = {
809 [TCG_COND_LT] = 0,
810 [TCG_COND_LTU] = 0,
811 [TCG_COND_GE] = MIPS_CMP_INV,
812 [TCG_COND_GEU] = MIPS_CMP_INV,
813 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
814 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
815 [TCG_COND_GT] = MIPS_CMP_SWAP,
816 [TCG_COND_GTU] = MIPS_CMP_SWAP,
817 };
818
819 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
820 TCGReg arg1, TCGReg arg2)
821 {
822 MIPSInsn s_opc = OPC_SLTU;
823 int cmp_map;
824
825 switch (cond) {
826 case TCG_COND_EQ:
827 if (arg2 != 0) {
828 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
829 arg1 = ret;
830 }
831 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
832 break;
833
834 case TCG_COND_NE:
835 if (arg2 != 0) {
836 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
837 arg1 = ret;
838 }
839 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
840 break;
841
842 case TCG_COND_LT:
843 case TCG_COND_GE:
844 case TCG_COND_LE:
845 case TCG_COND_GT:
846 s_opc = OPC_SLT;
847 /* FALLTHRU */
848
849 case TCG_COND_LTU:
850 case TCG_COND_GEU:
851 case TCG_COND_LEU:
852 case TCG_COND_GTU:
853 cmp_map = mips_cmp_map[cond];
854 if (cmp_map & MIPS_CMP_SWAP) {
855 TCGReg t = arg1;
856 arg1 = arg2;
857 arg2 = t;
858 }
859 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
860 if (cmp_map & MIPS_CMP_INV) {
861 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
862 }
863 break;
864
865 default:
866 tcg_abort();
867 break;
868 }
869 }
870
871 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
872 TCGReg arg2, TCGLabel *l)
873 {
874 static const MIPSInsn b_zero[16] = {
875 [TCG_COND_LT] = OPC_BLTZ,
876 [TCG_COND_GT] = OPC_BGTZ,
877 [TCG_COND_LE] = OPC_BLEZ,
878 [TCG_COND_GE] = OPC_BGEZ,
879 };
880
881 MIPSInsn s_opc = OPC_SLTU;
882 MIPSInsn b_opc;
883 int cmp_map;
884
885 switch (cond) {
886 case TCG_COND_EQ:
887 b_opc = OPC_BEQ;
888 break;
889 case TCG_COND_NE:
890 b_opc = OPC_BNE;
891 break;
892
893 case TCG_COND_LT:
894 case TCG_COND_GT:
895 case TCG_COND_LE:
896 case TCG_COND_GE:
897 if (arg2 == 0) {
898 b_opc = b_zero[cond];
899 arg2 = arg1;
900 arg1 = 0;
901 break;
902 }
903 s_opc = OPC_SLT;
904 /* FALLTHRU */
905
906 case TCG_COND_LTU:
907 case TCG_COND_GTU:
908 case TCG_COND_LEU:
909 case TCG_COND_GEU:
910 cmp_map = mips_cmp_map[cond];
911 if (cmp_map & MIPS_CMP_SWAP) {
912 TCGReg t = arg1;
913 arg1 = arg2;
914 arg2 = t;
915 }
916 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
917 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
918 arg1 = TCG_TMP0;
919 arg2 = TCG_REG_ZERO;
920 break;
921
922 default:
923 tcg_abort();
924 break;
925 }
926
927 tcg_out_opc_br(s, b_opc, arg1, arg2);
928 if (l->has_value) {
929 reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
930 } else {
931 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
932 }
933 tcg_out_nop(s);
934 }
935
936 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
937 TCGReg al, TCGReg ah,
938 TCGReg bl, TCGReg bh)
939 {
940 /* Merge highpart comparison into AH. */
941 if (bh != 0) {
942 if (ah != 0) {
943 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
944 ah = tmp0;
945 } else {
946 ah = bh;
947 }
948 }
949 /* Merge lowpart comparison into AL. */
950 if (bl != 0) {
951 if (al != 0) {
952 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
953 al = tmp1;
954 } else {
955 al = bl;
956 }
957 }
958 /* Merge high and low part comparisons into AL. */
959 if (ah != 0) {
960 if (al != 0) {
961 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
962 al = tmp0;
963 } else {
964 al = ah;
965 }
966 }
967 return al;
968 }
969
970 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
971 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
972 {
973 TCGReg tmp0 = TCG_TMP0;
974 TCGReg tmp1 = ret;
975
976 tcg_debug_assert(ret != TCG_TMP0);
977 if (ret == ah || ret == bh) {
978 tcg_debug_assert(ret != TCG_TMP1);
979 tmp1 = TCG_TMP1;
980 }
981
982 switch (cond) {
983 case TCG_COND_EQ:
984 case TCG_COND_NE:
985 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
986 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
987 break;
988
989 default:
990 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
991 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
992 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
993 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
994 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
995 break;
996 }
997 }
998
999 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
1000 TCGReg bl, TCGReg bh, TCGLabel *l)
1001 {
1002 TCGCond b_cond = TCG_COND_NE;
1003 TCGReg tmp = TCG_TMP1;
1004
1005 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
1006 With setcond, we emit between 3 and 10 insns and only 1 branch,
1007 which ought to get better branch prediction. */
1008 switch (cond) {
1009 case TCG_COND_EQ:
1010 case TCG_COND_NE:
1011 b_cond = cond;
1012 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
1013 break;
1014
1015 default:
1016 /* Minimize code size by preferring a compare not requiring INV. */
1017 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1018 cond = tcg_invert_cond(cond);
1019 b_cond = TCG_COND_EQ;
1020 }
1021 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
1022 break;
1023 }
1024
1025 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
1026 }
1027
1028 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
1029 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
1030 {
1031 bool eqz = false;
1032
1033 /* If one of the values is zero, put it last to match SEL*Z instructions */
1034 if (use_mips32r6_instructions && v1 == 0) {
1035 v1 = v2;
1036 v2 = 0;
1037 cond = tcg_invert_cond(cond);
1038 }
1039
1040 switch (cond) {
1041 case TCG_COND_EQ:
1042 eqz = true;
1043 /* FALLTHRU */
1044 case TCG_COND_NE:
1045 if (c2 != 0) {
1046 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
1047 c1 = TCG_TMP0;
1048 }
1049 break;
1050
1051 default:
1052 /* Minimize code size by preferring a compare not requiring INV. */
1053 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1054 cond = tcg_invert_cond(cond);
1055 eqz = true;
1056 }
1057 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1058 c1 = TCG_TMP0;
1059 break;
1060 }
1061
1062 if (use_mips32r6_instructions) {
1063 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1064 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1065
1066 if (v2 != 0) {
1067 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1068 }
1069 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1070 if (v2 != 0) {
1071 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1072 }
1073 } else {
1074 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1075
1076 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1077
1078 /* This should be guaranteed via constraints */
1079 tcg_debug_assert(v2 == ret);
1080 }
1081 }
1082
1083 static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
1084 {
1085 /* Note that the ABI requires the called function's address to be
1086 loaded into T9, even if a direct branch is in range. */
1087 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1088
1089 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1090 if (tail) {
1091 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1092 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1093 }
1094 } else {
1095 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1096 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1097 }
1098 }
1099 }
1100
1101 static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
1102 {
1103 tcg_out_call_int(s, arg, false);
1104 tcg_out_nop(s);
1105 }
1106
1107 #if defined(CONFIG_SOFTMMU)
1108 #include "tcg-ldst.inc.c"
1109
1110 static void * const qemu_ld_helpers[16] = {
1111 [MO_UB] = helper_ret_ldub_mmu,
1112 [MO_SB] = helper_ret_ldsb_mmu,
1113 [MO_LEUW] = helper_le_lduw_mmu,
1114 [MO_LESW] = helper_le_ldsw_mmu,
1115 [MO_LEUL] = helper_le_ldul_mmu,
1116 [MO_LEQ] = helper_le_ldq_mmu,
1117 [MO_BEUW] = helper_be_lduw_mmu,
1118 [MO_BESW] = helper_be_ldsw_mmu,
1119 [MO_BEUL] = helper_be_ldul_mmu,
1120 [MO_BEQ] = helper_be_ldq_mmu,
1121 #if TCG_TARGET_REG_BITS == 64
1122 [MO_LESL] = helper_le_ldsl_mmu,
1123 [MO_BESL] = helper_be_ldsl_mmu,
1124 #endif
1125 };
1126
1127 static void * const qemu_st_helpers[16] = {
1128 [MO_UB] = helper_ret_stb_mmu,
1129 [MO_LEUW] = helper_le_stw_mmu,
1130 [MO_LEUL] = helper_le_stl_mmu,
1131 [MO_LEQ] = helper_le_stq_mmu,
1132 [MO_BEUW] = helper_be_stw_mmu,
1133 [MO_BEUL] = helper_be_stl_mmu,
1134 [MO_BEQ] = helper_be_stq_mmu,
1135 };
1136
1137 /* Helper routines for marshalling helper function arguments into
1138 * the correct registers and stack.
1139 * I is where we want to put this argument, and is updated and returned
1140 * for the next call. ARG is the argument itself.
1141 *
1142 * We provide routines for arguments which are: immediate, 32 bit
1143 * value in register, 16 and 8 bit values in register (which must be zero
1144 * extended before use) and 64 bit value in a lo:hi register pair.
1145 */
1146
1147 static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
1148 {
1149 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1150 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1151 } else {
1152 /* For N32 and N64, the initial offset is different. But there
1153 we also have 8 argument register so we don't run out here. */
1154 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1155 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1156 }
1157 return i + 1;
1158 }
1159
1160 static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1161 {
1162 TCGReg tmp = TCG_TMP0;
1163 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1164 tmp = tcg_target_call_iarg_regs[i];
1165 }
1166 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
1167 return tcg_out_call_iarg_reg(s, i, tmp);
1168 }
1169
1170 static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1171 {
1172 TCGReg tmp = TCG_TMP0;
1173 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1174 tmp = tcg_target_call_iarg_regs[i];
1175 }
1176 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1177 return tcg_out_call_iarg_reg(s, i, tmp);
1178 }
1179
1180 static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1181 {
1182 TCGReg tmp = TCG_TMP0;
1183 if (arg == 0) {
1184 tmp = TCG_REG_ZERO;
1185 } else {
1186 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1187 tmp = tcg_target_call_iarg_regs[i];
1188 }
1189 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
1190 }
1191 return tcg_out_call_iarg_reg(s, i, tmp);
1192 }
1193
1194 static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1195 {
1196 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1197 i = (i + 1) & ~1;
1198 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1199 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1200 return i;
1201 }
1202
1203 /* Perform the tlb comparison operation. The complete host address is
1204 placed in BASE. Clobbers TMP0, TMP1, TMP2, A0. */
1205 static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
1206 TCGReg addrh, TCGMemOpIdx oi,
1207 tcg_insn_unit *label_ptr[2], bool is_load)
1208 {
1209 TCGMemOp opc = get_memop(oi);
1210 unsigned s_bits = opc & MO_SIZE;
1211 unsigned a_bits = get_alignment_bits(opc);
1212 target_ulong mask;
1213 int mem_index = get_mmuidx(oi);
1214 int cmp_off
1215 = (is_load
1216 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1217 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1218 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1219
1220 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_REG_A0, addrl,
1221 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1222 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_A0, TCG_REG_A0,
1223 (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
1224 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, TCG_REG_A0, TCG_AREG0);
1225
1226 /* Compensate for very large offsets. */
1227 while (add_off >= 0x8000) {
1228 /* Most target env are smaller than 32k, but a few are larger than 64k,
1229 * so handle an arbitrarily large offset.
1230 */
1231 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, TCG_REG_A0, 0x7ff0);
1232 cmp_off -= 0x7ff0;
1233 add_off -= 0x7ff0;
1234 }
1235
1236 /* We don't currently support unaligned accesses.
1237 We could do so with mips32r6. */
1238 if (a_bits < s_bits) {
1239 a_bits = s_bits;
1240 }
1241
1242 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1243
1244 /* Load the (low half) tlb comparator. Mask the page bits, keeping the
1245 alignment bits to compare against. */
1246 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1247 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF);
1248 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
1249 } else {
1250 tcg_out_ldst(s,
1251 (TARGET_LONG_BITS == 64 ? OPC_LD
1252 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1253 TCG_TMP0, TCG_REG_A0, cmp_off);
1254 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
1255 /* No second compare is required here;
1256 load the tlb addend for the fast path. */
1257 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_REG_A0, add_off);
1258 }
1259 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
1260
1261 /* Zero extend a 32-bit guest address for a 64-bit host. */
1262 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1263 tcg_out_ext32u(s, base, addrl);
1264 addrl = base;
1265 }
1266
1267 label_ptr[0] = s->code_ptr;
1268 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1269
1270 /* Load and test the high half tlb comparator. */
1271 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1272 /* delay slot */
1273 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A0, cmp_off + HI_OFF);
1274
1275 /* Load the tlb addend for the fast path. */
1276 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_REG_A0, add_off);
1277
1278 label_ptr[1] = s->code_ptr;
1279 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
1280 }
1281
1282 /* delay slot */
1283 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1284 }
1285
1286 static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1287 TCGType ext,
1288 TCGReg datalo, TCGReg datahi,
1289 TCGReg addrlo, TCGReg addrhi,
1290 void *raddr, tcg_insn_unit *label_ptr[2])
1291 {
1292 TCGLabelQemuLdst *label = new_ldst_label(s);
1293
1294 label->is_ld = is_ld;
1295 label->oi = oi;
1296 label->type = ext;
1297 label->datalo_reg = datalo;
1298 label->datahi_reg = datahi;
1299 label->addrlo_reg = addrlo;
1300 label->addrhi_reg = addrhi;
1301 label->raddr = raddr;
1302 label->label_ptr[0] = label_ptr[0];
1303 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1304 label->label_ptr[1] = label_ptr[1];
1305 }
1306 }
1307
1308 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1309 {
1310 TCGMemOpIdx oi = l->oi;
1311 TCGMemOp opc = get_memop(oi);
1312 TCGReg v0;
1313 int i;
1314
1315 /* resolve label address */
1316 reloc_pc16(l->label_ptr[0], s->code_ptr);
1317 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1318 reloc_pc16(l->label_ptr[1], s->code_ptr);
1319 }
1320
1321 i = 1;
1322 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1323 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1324 } else {
1325 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1326 }
1327 i = tcg_out_call_iarg_imm(s, i, oi);
1328 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
1329 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
1330 /* delay slot */
1331 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1332
1333 v0 = l->datalo_reg;
1334 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1335 /* We eliminated V0 from the possible output registers, so it
1336 cannot be clobbered here. So we must move V1 first. */
1337 if (MIPS_BE) {
1338 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1339 v0 = l->datahi_reg;
1340 } else {
1341 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1342 }
1343 }
1344
1345 reloc_pc16(s->code_ptr, l->raddr);
1346 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1347 /* delay slot */
1348 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1349 /* we always sign-extend 32-bit loads */
1350 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1351 } else {
1352 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1353 }
1354 }
1355
1356 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1357 {
1358 TCGMemOpIdx oi = l->oi;
1359 TCGMemOp opc = get_memop(oi);
1360 TCGMemOp s_bits = opc & MO_SIZE;
1361 int i;
1362
1363 /* resolve label address */
1364 reloc_pc16(l->label_ptr[0], s->code_ptr);
1365 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1366 reloc_pc16(l->label_ptr[1], s->code_ptr);
1367 }
1368
1369 i = 1;
1370 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1371 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1372 } else {
1373 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1374 }
1375 switch (s_bits) {
1376 case MO_8:
1377 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1378 break;
1379 case MO_16:
1380 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1381 break;
1382 case MO_32:
1383 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1384 break;
1385 case MO_64:
1386 if (TCG_TARGET_REG_BITS == 32) {
1387 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1388 } else {
1389 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1390 }
1391 break;
1392 default:
1393 tcg_abort();
1394 }
1395 i = tcg_out_call_iarg_imm(s, i, oi);
1396
1397 /* Tail call to the store helper. Thus force the return address
1398 computation to take place in the return address register. */
1399 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1400 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
1401 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
1402 /* delay slot */
1403 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1404 }
1405 #endif
1406
1407 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1408 TCGReg base, TCGMemOp opc, bool is_64)
1409 {
1410 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1411 case MO_UB:
1412 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1413 break;
1414 case MO_SB:
1415 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1416 break;
1417 case MO_UW | MO_BSWAP:
1418 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1419 tcg_out_bswap16(s, lo, TCG_TMP1);
1420 break;
1421 case MO_UW:
1422 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1423 break;
1424 case MO_SW | MO_BSWAP:
1425 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1426 tcg_out_bswap16s(s, lo, TCG_TMP1);
1427 break;
1428 case MO_SW:
1429 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1430 break;
1431 case MO_UL | MO_BSWAP:
1432 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1433 if (use_mips32r2_instructions) {
1434 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1435 tcg_out_bswap32u(s, lo, lo);
1436 } else {
1437 tcg_out_bswap_subr(s, bswap32u_addr);
1438 /* delay slot */
1439 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1440 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1441 }
1442 break;
1443 }
1444 /* FALLTHRU */
1445 case MO_SL | MO_BSWAP:
1446 if (use_mips32r2_instructions) {
1447 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1448 tcg_out_bswap32(s, lo, lo);
1449 } else {
1450 tcg_out_bswap_subr(s, bswap32_addr);
1451 /* delay slot */
1452 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1453 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1454 }
1455 break;
1456 case MO_UL:
1457 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1458 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1459 break;
1460 }
1461 /* FALLTHRU */
1462 case MO_SL:
1463 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1464 break;
1465 case MO_Q | MO_BSWAP:
1466 if (TCG_TARGET_REG_BITS == 64) {
1467 if (use_mips32r2_instructions) {
1468 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1469 tcg_out_bswap64(s, lo, lo);
1470 } else {
1471 tcg_out_bswap_subr(s, bswap64_addr);
1472 /* delay slot */
1473 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1474 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1475 }
1476 } else if (use_mips32r2_instructions) {
1477 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1478 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1479 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1480 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1481 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1482 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1483 } else {
1484 tcg_out_bswap_subr(s, bswap32_addr);
1485 /* delay slot */
1486 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1487 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1488 tcg_out_bswap_subr(s, bswap32_addr);
1489 /* delay slot */
1490 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1491 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1492 }
1493 break;
1494 case MO_Q:
1495 /* Prefer to load from offset 0 first, but allow for overlap. */
1496 if (TCG_TARGET_REG_BITS == 64) {
1497 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1498 } else if (MIPS_BE ? hi != base : lo == base) {
1499 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1500 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1501 } else {
1502 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1503 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1504 }
1505 break;
1506 default:
1507 tcg_abort();
1508 }
1509 }
1510
1511 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1512 {
1513 TCGReg addr_regl, addr_regh __attribute__((unused));
1514 TCGReg data_regl, data_regh;
1515 TCGMemOpIdx oi;
1516 TCGMemOp opc;
1517 #if defined(CONFIG_SOFTMMU)
1518 tcg_insn_unit *label_ptr[2];
1519 #endif
1520 TCGReg base = TCG_REG_A0;
1521
1522 data_regl = *args++;
1523 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1524 addr_regl = *args++;
1525 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1526 oi = *args++;
1527 opc = get_memop(oi);
1528
1529 #if defined(CONFIG_SOFTMMU)
1530 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
1531 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1532 add_qemu_ldst_label(s, 1, oi,
1533 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1534 data_regl, data_regh, addr_regl, addr_regh,
1535 s->code_ptr, label_ptr);
1536 #else
1537 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1538 tcg_out_ext32u(s, base, addr_regl);
1539 addr_regl = base;
1540 }
1541 if (guest_base == 0 && data_regl != addr_regl) {
1542 base = addr_regl;
1543 } else if (guest_base == (int16_t)guest_base) {
1544 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1545 } else {
1546 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1547 }
1548 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1549 #endif
1550 }
1551
1552 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1553 TCGReg base, TCGMemOp opc)
1554 {
1555 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1556 if ((lo | hi) == 0) {
1557 opc &= ~MO_BSWAP;
1558 }
1559
1560 switch (opc & (MO_SIZE | MO_BSWAP)) {
1561 case MO_8:
1562 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1563 break;
1564
1565 case MO_16 | MO_BSWAP:
1566 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
1567 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
1568 lo = TCG_TMP1;
1569 /* FALLTHRU */
1570 case MO_16:
1571 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1572 break;
1573
1574 case MO_32 | MO_BSWAP:
1575 tcg_out_bswap32(s, TCG_TMP3, lo);
1576 lo = TCG_TMP3;
1577 /* FALLTHRU */
1578 case MO_32:
1579 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1580 break;
1581
1582 case MO_64 | MO_BSWAP:
1583 if (TCG_TARGET_REG_BITS == 64) {
1584 tcg_out_bswap64(s, TCG_TMP3, lo);
1585 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1586 } else if (use_mips32r2_instructions) {
1587 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1588 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1589 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1590 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1591 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1592 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1593 } else {
1594 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
1595 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1596 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
1597 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1598 }
1599 break;
1600 case MO_64:
1601 if (TCG_TARGET_REG_BITS == 64) {
1602 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1603 } else {
1604 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1605 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1606 }
1607 break;
1608
1609 default:
1610 tcg_abort();
1611 }
1612 }
1613
1614 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1615 {
1616 TCGReg addr_regl, addr_regh __attribute__((unused));
1617 TCGReg data_regl, data_regh;
1618 TCGMemOpIdx oi;
1619 TCGMemOp opc;
1620 #if defined(CONFIG_SOFTMMU)
1621 tcg_insn_unit *label_ptr[2];
1622 #endif
1623 TCGReg base = TCG_REG_A0;
1624
1625 data_regl = *args++;
1626 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1627 addr_regl = *args++;
1628 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1629 oi = *args++;
1630 opc = get_memop(oi);
1631
1632 #if defined(CONFIG_SOFTMMU)
1633 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
1634 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1635 add_qemu_ldst_label(s, 0, oi,
1636 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1637 data_regl, data_regh, addr_regl, addr_regh,
1638 s->code_ptr, label_ptr);
1639 #else
1640 base = TCG_REG_A0;
1641 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1642 tcg_out_ext32u(s, base, addr_regl);
1643 addr_regl = base;
1644 }
1645 if (guest_base == 0) {
1646 base = addr_regl;
1647 } else if (guest_base == (int16_t)guest_base) {
1648 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1649 } else {
1650 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1651 }
1652 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1653 #endif
1654 }
1655
1656 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1657 {
1658 static const MIPSInsn sync[] = {
1659 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1660 as the former is an ordering barrier and the latter
1661 is a completion barrier. */
1662 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1663 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1664 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1665 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1666 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1667 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1668 };
1669 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1670 }
1671
1672 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1673 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1674 {
1675 if (use_mips32r6_instructions) {
1676 if (a2 == width) {
1677 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1678 } else {
1679 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1680 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1681 }
1682 } else {
1683 if (a2 == width) {
1684 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1685 } else if (a0 == a2) {
1686 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1687 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1688 } else if (a0 != a1) {
1689 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1690 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1691 } else {
1692 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1693 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1694 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1695 }
1696 }
1697 }
1698
1699 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1700 const TCGArg *args, const int *const_args)
1701 {
1702 MIPSInsn i1, i2;
1703 TCGArg a0, a1, a2;
1704 int c2;
1705
1706 a0 = args[0];
1707 a1 = args[1];
1708 a2 = args[2];
1709 c2 = const_args[2];
1710
1711 switch (opc) {
1712 case INDEX_op_exit_tb:
1713 {
1714 TCGReg b0 = TCG_REG_ZERO;
1715
1716 a0 = (intptr_t)a0;
1717 if (a0 & ~0xffff) {
1718 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1719 b0 = TCG_REG_V0;
1720 }
1721 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1722 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
1723 (uintptr_t)tb_ret_addr);
1724 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1725 }
1726 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
1727 }
1728 break;
1729 case INDEX_op_goto_tb:
1730 if (s->tb_jmp_insn_offset) {
1731 /* direct jump method */
1732 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1733 /* Avoid clobbering the address during retranslation. */
1734 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
1735 } else {
1736 /* indirect jump method */
1737 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
1738 (uintptr_t)(s->tb_jmp_target_addr + a0));
1739 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1740 }
1741 tcg_out_nop(s);
1742 set_jmp_reset_offset(s, a0);
1743 break;
1744 case INDEX_op_goto_ptr:
1745 /* jmp to the given host address (could be epilogue) */
1746 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1747 tcg_out_nop(s);
1748 break;
1749 case INDEX_op_br:
1750 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1751 arg_label(a0));
1752 break;
1753
1754 case INDEX_op_ld8u_i32:
1755 case INDEX_op_ld8u_i64:
1756 i1 = OPC_LBU;
1757 goto do_ldst;
1758 case INDEX_op_ld8s_i32:
1759 case INDEX_op_ld8s_i64:
1760 i1 = OPC_LB;
1761 goto do_ldst;
1762 case INDEX_op_ld16u_i32:
1763 case INDEX_op_ld16u_i64:
1764 i1 = OPC_LHU;
1765 goto do_ldst;
1766 case INDEX_op_ld16s_i32:
1767 case INDEX_op_ld16s_i64:
1768 i1 = OPC_LH;
1769 goto do_ldst;
1770 case INDEX_op_ld_i32:
1771 case INDEX_op_ld32s_i64:
1772 i1 = OPC_LW;
1773 goto do_ldst;
1774 case INDEX_op_ld32u_i64:
1775 i1 = OPC_LWU;
1776 goto do_ldst;
1777 case INDEX_op_ld_i64:
1778 i1 = OPC_LD;
1779 goto do_ldst;
1780 case INDEX_op_st8_i32:
1781 case INDEX_op_st8_i64:
1782 i1 = OPC_SB;
1783 goto do_ldst;
1784 case INDEX_op_st16_i32:
1785 case INDEX_op_st16_i64:
1786 i1 = OPC_SH;
1787 goto do_ldst;
1788 case INDEX_op_st_i32:
1789 case INDEX_op_st32_i64:
1790 i1 = OPC_SW;
1791 goto do_ldst;
1792 case INDEX_op_st_i64:
1793 i1 = OPC_SD;
1794 do_ldst:
1795 tcg_out_ldst(s, i1, a0, a1, a2);
1796 break;
1797
1798 case INDEX_op_add_i32:
1799 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1800 goto do_binary;
1801 case INDEX_op_add_i64:
1802 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1803 goto do_binary;
1804 case INDEX_op_or_i32:
1805 case INDEX_op_or_i64:
1806 i1 = OPC_OR, i2 = OPC_ORI;
1807 goto do_binary;
1808 case INDEX_op_xor_i32:
1809 case INDEX_op_xor_i64:
1810 i1 = OPC_XOR, i2 = OPC_XORI;
1811 do_binary:
1812 if (c2) {
1813 tcg_out_opc_imm(s, i2, a0, a1, a2);
1814 break;
1815 }
1816 do_binaryv:
1817 tcg_out_opc_reg(s, i1, a0, a1, a2);
1818 break;
1819
1820 case INDEX_op_sub_i32:
1821 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1822 goto do_subtract;
1823 case INDEX_op_sub_i64:
1824 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1825 do_subtract:
1826 if (c2) {
1827 tcg_out_opc_imm(s, i2, a0, a1, -a2);
1828 break;
1829 }
1830 goto do_binaryv;
1831 case INDEX_op_and_i32:
1832 if (c2 && a2 != (uint16_t)a2) {
1833 int msb = ctz32(~a2) - 1;
1834 tcg_debug_assert(use_mips32r2_instructions);
1835 tcg_debug_assert(is_p2m1(a2));
1836 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1837 break;
1838 }
1839 i1 = OPC_AND, i2 = OPC_ANDI;
1840 goto do_binary;
1841 case INDEX_op_and_i64:
1842 if (c2 && a2 != (uint16_t)a2) {
1843 int msb = ctz64(~a2) - 1;
1844 tcg_debug_assert(use_mips32r2_instructions);
1845 tcg_debug_assert(is_p2m1(a2));
1846 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1847 break;
1848 }
1849 i1 = OPC_AND, i2 = OPC_ANDI;
1850 goto do_binary;
1851 case INDEX_op_nor_i32:
1852 case INDEX_op_nor_i64:
1853 i1 = OPC_NOR;
1854 goto do_binaryv;
1855
1856 case INDEX_op_mul_i32:
1857 if (use_mips32_instructions) {
1858 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1859 break;
1860 }
1861 i1 = OPC_MULT, i2 = OPC_MFLO;
1862 goto do_hilo1;
1863 case INDEX_op_mulsh_i32:
1864 if (use_mips32r6_instructions) {
1865 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1866 break;
1867 }
1868 i1 = OPC_MULT, i2 = OPC_MFHI;
1869 goto do_hilo1;
1870 case INDEX_op_muluh_i32:
1871 if (use_mips32r6_instructions) {
1872 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1873 break;
1874 }
1875 i1 = OPC_MULTU, i2 = OPC_MFHI;
1876 goto do_hilo1;
1877 case INDEX_op_div_i32:
1878 if (use_mips32r6_instructions) {
1879 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1880 break;
1881 }
1882 i1 = OPC_DIV, i2 = OPC_MFLO;
1883 goto do_hilo1;
1884 case INDEX_op_divu_i32:
1885 if (use_mips32r6_instructions) {
1886 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1887 break;
1888 }
1889 i1 = OPC_DIVU, i2 = OPC_MFLO;
1890 goto do_hilo1;
1891 case INDEX_op_rem_i32:
1892 if (use_mips32r6_instructions) {
1893 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1894 break;
1895 }
1896 i1 = OPC_DIV, i2 = OPC_MFHI;
1897 goto do_hilo1;
1898 case INDEX_op_remu_i32:
1899 if (use_mips32r6_instructions) {
1900 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1901 break;
1902 }
1903 i1 = OPC_DIVU, i2 = OPC_MFHI;
1904 goto do_hilo1;
1905 case INDEX_op_mul_i64:
1906 if (use_mips32r6_instructions) {
1907 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1908 break;
1909 }
1910 i1 = OPC_DMULT, i2 = OPC_MFLO;
1911 goto do_hilo1;
1912 case INDEX_op_mulsh_i64:
1913 if (use_mips32r6_instructions) {
1914 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1915 break;
1916 }
1917 i1 = OPC_DMULT, i2 = OPC_MFHI;
1918 goto do_hilo1;
1919 case INDEX_op_muluh_i64:
1920 if (use_mips32r6_instructions) {
1921 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1922 break;
1923 }
1924 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1925 goto do_hilo1;
1926 case INDEX_op_div_i64:
1927 if (use_mips32r6_instructions) {
1928 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1929 break;
1930 }
1931 i1 = OPC_DDIV, i2 = OPC_MFLO;
1932 goto do_hilo1;
1933 case INDEX_op_divu_i64:
1934 if (use_mips32r6_instructions) {
1935 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1936 break;
1937 }
1938 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1939 goto do_hilo1;
1940 case INDEX_op_rem_i64:
1941 if (use_mips32r6_instructions) {
1942 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1943 break;
1944 }
1945 i1 = OPC_DDIV, i2 = OPC_MFHI;
1946 goto do_hilo1;
1947 case INDEX_op_remu_i64:
1948 if (use_mips32r6_instructions) {
1949 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1950 break;
1951 }
1952 i1 = OPC_DDIVU, i2 = OPC_MFHI;
1953 do_hilo1:
1954 tcg_out_opc_reg(s, i1, 0, a1, a2);
1955 tcg_out_opc_reg(s, i2, a0, 0, 0);
1956 break;
1957
1958 case INDEX_op_muls2_i32:
1959 i1 = OPC_MULT;
1960 goto do_hilo2;
1961 case INDEX_op_mulu2_i32:
1962 i1 = OPC_MULTU;
1963 goto do_hilo2;
1964 case INDEX_op_muls2_i64:
1965 i1 = OPC_DMULT;
1966 goto do_hilo2;
1967 case INDEX_op_mulu2_i64:
1968 i1 = OPC_DMULTU;
1969 do_hilo2:
1970 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1971 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1972 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
1973 break;
1974
1975 case INDEX_op_not_i32:
1976 case INDEX_op_not_i64:
1977 i1 = OPC_NOR;
1978 goto do_unary;
1979 case INDEX_op_bswap16_i32:
1980 case INDEX_op_bswap16_i64:
1981 i1 = OPC_WSBH;
1982 goto do_unary;
1983 case INDEX_op_ext8s_i32:
1984 case INDEX_op_ext8s_i64:
1985 i1 = OPC_SEB;
1986 goto do_unary;
1987 case INDEX_op_ext16s_i32:
1988 case INDEX_op_ext16s_i64:
1989 i1 = OPC_SEH;
1990 do_unary:
1991 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
1992 break;
1993
1994 case INDEX_op_bswap32_i32:
1995 tcg_out_bswap32(s, a0, a1);
1996 break;
1997 case INDEX_op_bswap32_i64:
1998 tcg_out_bswap32u(s, a0, a1);
1999 break;
2000 case INDEX_op_bswap64_i64:
2001 tcg_out_bswap64(s, a0, a1);
2002 break;
2003 case INDEX_op_extrh_i64_i32:
2004 tcg_out_dsra(s, a0, a1, 32);
2005 break;
2006 case INDEX_op_ext32s_i64:
2007 case INDEX_op_ext_i32_i64:
2008 case INDEX_op_extrl_i64_i32:
2009 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
2010 break;
2011 case INDEX_op_ext32u_i64:
2012 case INDEX_op_extu_i32_i64:
2013 tcg_out_ext32u(s, a0, a1);
2014 break;
2015
2016 case INDEX_op_sar_i32:
2017 i1 = OPC_SRAV, i2 = OPC_SRA;
2018 goto do_shift;
2019 case INDEX_op_shl_i32:
2020 i1 = OPC_SLLV, i2 = OPC_SLL;
2021 goto do_shift;
2022 case INDEX_op_shr_i32:
2023 i1 = OPC_SRLV, i2 = OPC_SRL;
2024 goto do_shift;
2025 case INDEX_op_rotr_i32:
2026 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2027 do_shift:
2028 if (c2) {
2029 tcg_out_opc_sa(s, i2, a0, a1, a2);
2030 break;
2031 }
2032 do_shiftv:
2033 tcg_out_opc_reg(s, i1, a0, a2, a1);
2034 break;
2035 case INDEX_op_rotl_i32:
2036 if (c2) {
2037 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
2038 } else {
2039 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2040 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
2041 }
2042 break;
2043 case INDEX_op_sar_i64:
2044 if (c2) {
2045 tcg_out_dsra(s, a0, a1, a2);
2046 break;
2047 }
2048 i1 = OPC_DSRAV;
2049 goto do_shiftv;
2050 case INDEX_op_shl_i64:
2051 if (c2) {
2052 tcg_out_dsll(s, a0, a1, a2);
2053 break;
2054 }
2055 i1 = OPC_DSLLV;
2056 goto do_shiftv;
2057 case INDEX_op_shr_i64:
2058 if (c2) {
2059 tcg_out_dsrl(s, a0, a1, a2);
2060 break;
2061 }
2062 i1 = OPC_DSRLV;
2063 goto do_shiftv;
2064 case INDEX_op_rotr_i64:
2065 if (c2) {
2066 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2067 break;
2068 }
2069 i1 = OPC_DROTRV;
2070 goto do_shiftv;
2071 case INDEX_op_rotl_i64:
2072 if (c2) {
2073 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2074 } else {
2075 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2076 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2077 }
2078 break;
2079
2080 case INDEX_op_clz_i32:
2081 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2082 break;
2083 case INDEX_op_clz_i64:
2084 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2085 break;
2086
2087 case INDEX_op_deposit_i32:
2088 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2089 break;
2090 case INDEX_op_deposit_i64:
2091 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2092 args[3] + args[4] - 1, args[3]);
2093 break;
2094 case INDEX_op_extract_i32:
2095 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2096 break;
2097 case INDEX_op_extract_i64:
2098 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2099 args[3] - 1, a2);
2100 break;
2101
2102 case INDEX_op_brcond_i32:
2103 case INDEX_op_brcond_i64:
2104 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2105 break;
2106 case INDEX_op_brcond2_i32:
2107 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2108 break;
2109
2110 case INDEX_op_movcond_i32:
2111 case INDEX_op_movcond_i64:
2112 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2113 break;
2114
2115 case INDEX_op_setcond_i32:
2116 case INDEX_op_setcond_i64:
2117 tcg_out_setcond(s, args[3], a0, a1, a2);
2118 break;
2119 case INDEX_op_setcond2_i32:
2120 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2121 break;
2122
2123 case INDEX_op_qemu_ld_i32:
2124 tcg_out_qemu_ld(s, args, false);
2125 break;
2126 case INDEX_op_qemu_ld_i64:
2127 tcg_out_qemu_ld(s, args, true);
2128 break;
2129 case INDEX_op_qemu_st_i32:
2130 tcg_out_qemu_st(s, args, false);
2131 break;
2132 case INDEX_op_qemu_st_i64:
2133 tcg_out_qemu_st(s, args, true);
2134 break;
2135
2136 case INDEX_op_add2_i32:
2137 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2138 const_args[4], const_args[5], false);
2139 break;
2140 case INDEX_op_sub2_i32:
2141 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2142 const_args[4], const_args[5], true);
2143 break;
2144
2145 case INDEX_op_mb:
2146 tcg_out_mb(s, a0);
2147 break;
2148 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2149 case INDEX_op_mov_i64:
2150 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2151 case INDEX_op_movi_i64:
2152 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2153 default:
2154 tcg_abort();
2155 }
2156 }
2157
2158 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2159 {
2160 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2161 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2162 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2163 static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
2164 static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
2165 static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
2166 static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
2167 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2168 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2169 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2170 static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
2171 static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
2172 static const TCGTargetOpDef SZ_SZ_S
2173 = { .args_ct_str = { "SZ", "SZ", "S" } };
2174 static const TCGTargetOpDef SZ_SZ_S_S
2175 = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
2176 static const TCGTargetOpDef r_rZ_rN
2177 = { .args_ct_str = { "r", "rZ", "rN" } };
2178 static const TCGTargetOpDef r_rZ_rZ
2179 = { .args_ct_str = { "r", "rZ", "rZ" } };
2180 static const TCGTargetOpDef r_r_rIK
2181 = { .args_ct_str = { "r", "r", "rIK" } };
2182 static const TCGTargetOpDef r_r_rWZ
2183 = { .args_ct_str = { "r", "r", "rWZ" } };
2184 static const TCGTargetOpDef r_r_r_r
2185 = { .args_ct_str = { "r", "r", "r", "r" } };
2186 static const TCGTargetOpDef r_r_L_L
2187 = { .args_ct_str = { "r", "r", "L", "L" } };
2188 static const TCGTargetOpDef dep
2189 = { .args_ct_str = { "r", "0", "rZ" } };
2190 static const TCGTargetOpDef movc
2191 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
2192 static const TCGTargetOpDef movc_r6
2193 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2194 static const TCGTargetOpDef add2
2195 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
2196 static const TCGTargetOpDef br2
2197 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
2198 static const TCGTargetOpDef setc2
2199 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2200
2201 switch (op) {
2202 case INDEX_op_goto_ptr:
2203 return &r;
2204
2205 case INDEX_op_ld8u_i32:
2206 case INDEX_op_ld8s_i32:
2207 case INDEX_op_ld16u_i32:
2208 case INDEX_op_ld16s_i32:
2209 case INDEX_op_ld_i32:
2210 case INDEX_op_not_i32:
2211 case INDEX_op_bswap16_i32:
2212 case INDEX_op_bswap32_i32:
2213 case INDEX_op_ext8s_i32:
2214 case INDEX_op_ext16s_i32:
2215 case INDEX_op_extract_i32:
2216 case INDEX_op_ld8u_i64:
2217 case INDEX_op_ld8s_i64:
2218 case INDEX_op_ld16u_i64:
2219 case INDEX_op_ld16s_i64:
2220 case INDEX_op_ld32s_i64:
2221 case INDEX_op_ld32u_i64:
2222 case INDEX_op_ld_i64:
2223 case INDEX_op_not_i64:
2224 case INDEX_op_bswap16_i64:
2225 case INDEX_op_bswap32_i64:
2226 case INDEX_op_bswap64_i64:
2227 case INDEX_op_ext8s_i64:
2228 case INDEX_op_ext16s_i64:
2229 case INDEX_op_ext32s_i64:
2230 case INDEX_op_ext32u_i64:
2231 case INDEX_op_ext_i32_i64:
2232 case INDEX_op_extu_i32_i64:
2233 case INDEX_op_extrl_i64_i32:
2234 case INDEX_op_extrh_i64_i32:
2235 case INDEX_op_extract_i64:
2236 return &r_r;
2237
2238 case INDEX_op_st8_i32:
2239 case INDEX_op_st16_i32:
2240 case INDEX_op_st_i32:
2241 case INDEX_op_st8_i64:
2242 case INDEX_op_st16_i64:
2243 case INDEX_op_st32_i64:
2244 case INDEX_op_st_i64:
2245 return &rZ_r;
2246
2247 case INDEX_op_add_i32:
2248 case INDEX_op_add_i64:
2249 return &r_r_rJ;
2250 case INDEX_op_sub_i32:
2251 case INDEX_op_sub_i64:
2252 return &r_rZ_rN;
2253 case INDEX_op_mul_i32:
2254 case INDEX_op_mulsh_i32:
2255 case INDEX_op_muluh_i32:
2256 case INDEX_op_div_i32:
2257 case INDEX_op_divu_i32:
2258 case INDEX_op_rem_i32:
2259 case INDEX_op_remu_i32:
2260 case INDEX_op_nor_i32:
2261 case INDEX_op_setcond_i32:
2262 case INDEX_op_mul_i64:
2263 case INDEX_op_mulsh_i64:
2264 case INDEX_op_muluh_i64:
2265 case INDEX_op_div_i64:
2266 case INDEX_op_divu_i64:
2267 case INDEX_op_rem_i64:
2268 case INDEX_op_remu_i64:
2269 case INDEX_op_nor_i64:
2270 case INDEX_op_setcond_i64:
2271 return &r_rZ_rZ;
2272 case INDEX_op_muls2_i32:
2273 case INDEX_op_mulu2_i32:
2274 case INDEX_op_muls2_i64:
2275 case INDEX_op_mulu2_i64:
2276 return &r_r_r_r;
2277 case INDEX_op_and_i32:
2278 case INDEX_op_and_i64:
2279 return &r_r_rIK;
2280 case INDEX_op_or_i32:
2281 case INDEX_op_xor_i32:
2282 case INDEX_op_or_i64:
2283 case INDEX_op_xor_i64:
2284 return &r_r_rI;
2285 case INDEX_op_shl_i32:
2286 case INDEX_op_shr_i32:
2287 case INDEX_op_sar_i32:
2288 case INDEX_op_rotr_i32:
2289 case INDEX_op_rotl_i32:
2290 case INDEX_op_shl_i64:
2291 case INDEX_op_shr_i64:
2292 case INDEX_op_sar_i64:
2293 case INDEX_op_rotr_i64:
2294 case INDEX_op_rotl_i64:
2295 return &r_r_ri;
2296 case INDEX_op_clz_i32:
2297 case INDEX_op_clz_i64:
2298 return &r_r_rWZ;
2299
2300 case INDEX_op_deposit_i32:
2301 case INDEX_op_deposit_i64:
2302 return &dep;
2303 case INDEX_op_brcond_i32:
2304 case INDEX_op_brcond_i64:
2305 return &rZ_rZ;
2306 case INDEX_op_movcond_i32:
2307 case INDEX_op_movcond_i64:
2308 return use_mips32r6_instructions ? &movc_r6 : &movc;
2309
2310 case INDEX_op_add2_i32:
2311 case INDEX_op_sub2_i32:
2312 return &add2;
2313 case INDEX_op_setcond2_i32:
2314 return &setc2;
2315 case INDEX_op_brcond2_i32:
2316 return &br2;
2317
2318 case INDEX_op_qemu_ld_i32:
2319 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2320 ? &r_L : &r_L_L);
2321 case INDEX_op_qemu_st_i32:
2322 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2323 ? &SZ_S : &SZ_S_S);
2324 case INDEX_op_qemu_ld_i64:
2325 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2326 : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
2327 case INDEX_op_qemu_st_i64:
2328 return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
2329 : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
2330
2331 default:
2332 return NULL;
2333 }
2334 }
2335
2336 static const int tcg_target_callee_save_regs[] = {
2337 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2338 TCG_REG_S1,
2339 TCG_REG_S2,
2340 TCG_REG_S3,
2341 TCG_REG_S4,
2342 TCG_REG_S5,
2343 TCG_REG_S6,
2344 TCG_REG_S7,
2345 TCG_REG_S8,
2346 TCG_REG_RA, /* should be last for ABI compliance */
2347 };
2348
2349 /* The Linux kernel doesn't provide any information about the available
2350 instruction set. Probe it using a signal handler. */
2351
2352
2353 #ifndef use_movnz_instructions
2354 bool use_movnz_instructions = false;
2355 #endif
2356
2357 #ifndef use_mips32_instructions
2358 bool use_mips32_instructions = false;
2359 #endif
2360
2361 #ifndef use_mips32r2_instructions
2362 bool use_mips32r2_instructions = false;
2363 #endif
2364
2365 static volatile sig_atomic_t got_sigill;
2366
2367 static void sigill_handler(int signo, siginfo_t *si, void *data)
2368 {
2369 /* Skip the faulty instruction */
2370 ucontext_t *uc = (ucontext_t *)data;
2371 uc->uc_mcontext.pc += 4;
2372
2373 got_sigill = 1;
2374 }
2375
2376 static void tcg_target_detect_isa(void)
2377 {
2378 struct sigaction sa_old, sa_new;
2379
2380 memset(&sa_new, 0, sizeof(sa_new));
2381 sa_new.sa_flags = SA_SIGINFO;
2382 sa_new.sa_sigaction = sigill_handler;
2383 sigaction(SIGILL, &sa_new, &sa_old);
2384
2385 /* Probe for movn/movz, necessary to implement movcond. */
2386 #ifndef use_movnz_instructions
2387 got_sigill = 0;
2388 asm volatile(".set push\n"
2389 ".set mips32\n"
2390 "movn $zero, $zero, $zero\n"
2391 "movz $zero, $zero, $zero\n"
2392 ".set pop\n"
2393 : : : );
2394 use_movnz_instructions = !got_sigill;
2395 #endif
2396
2397 /* Probe for MIPS32 instructions. As no subsetting is allowed
2398 by the specification, it is only necessary to probe for one
2399 of the instructions. */
2400 #ifndef use_mips32_instructions
2401 got_sigill = 0;
2402 asm volatile(".set push\n"
2403 ".set mips32\n"
2404 "mul $zero, $zero\n"
2405 ".set pop\n"
2406 : : : );
2407 use_mips32_instructions = !got_sigill;
2408 #endif
2409
2410 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2411 available. As no subsetting is allowed by the specification,
2412 it is only necessary to probe for one of the instructions. */
2413 #ifndef use_mips32r2_instructions
2414 if (use_mips32_instructions) {
2415 got_sigill = 0;
2416 asm volatile(".set push\n"
2417 ".set mips32r2\n"
2418 "seb $zero, $zero\n"
2419 ".set pop\n"
2420 : : : );
2421 use_mips32r2_instructions = !got_sigill;
2422 }
2423 #endif
2424
2425 sigaction(SIGILL, &sa_old, NULL);
2426 }
2427
2428 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2429 {
2430 uintptr_t p = (uintptr_t)s->code_ptr;
2431 if (p & 15) {
2432 p = (p + 15) & -16;
2433 s->code_ptr = (void *)p;
2434 }
2435 return s->code_ptr;
2436 }
2437
2438 /* Stack frame parameters. */
2439 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2440 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2441 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2442
2443 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2444 + TCG_TARGET_STACK_ALIGN - 1) \
2445 & -TCG_TARGET_STACK_ALIGN)
2446 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2447
2448 /* We're expecting to be able to use an immediate for frame allocation. */
2449 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2450
2451 /* Generate global QEMU prologue and epilogue code */
2452 static void tcg_target_qemu_prologue(TCGContext *s)
2453 {
2454 int i;
2455
2456 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2457
2458 /* TB prologue */
2459 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2460 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2461 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2462 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2463 }
2464
2465 #ifndef CONFIG_SOFTMMU
2466 if (guest_base) {
2467 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2468 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2469 }
2470 #endif
2471
2472 /* Call generated code */
2473 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2474 /* delay slot */
2475 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2476
2477 /*
2478 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2479 * and fall through to the rest of the epilogue.
2480 */
2481 s->code_gen_epilogue = s->code_ptr;
2482 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2483
2484 /* TB epilogue */
2485 tb_ret_addr = s->code_ptr;
2486 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2487 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2488 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2489 }
2490
2491 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2492 /* delay slot */
2493 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2494
2495 if (use_mips32r2_instructions) {
2496 return;
2497 }
2498
2499 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2500 clobbers TCG_TMP1, TCG_TMP2. */
2501
2502 /*
2503 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2504 */
2505 bswap32_addr = align_code_ptr(s);
2506 /* t3 = (ssss)d000 */
2507 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2508 /* t1 = 000a */
2509 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2510 /* t2 = 00c0 */
2511 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2512 /* t3 = d00a */
2513 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2514 /* t1 = 0abc */
2515 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2516 /* t2 = 0c00 */
2517 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2518 /* t1 = 00b0 */
2519 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2520 /* t3 = dc0a */
2521 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2522 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2523 /* t3 = dcba -- delay slot */
2524 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2525
2526 if (TCG_TARGET_REG_BITS == 32) {
2527 return;
2528 }
2529
2530 /*
2531 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2532 */
2533 bswap32u_addr = align_code_ptr(s);
2534 /* t1 = (0000)000d */
2535 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2536 /* t3 = 000a */
2537 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2538 /* t1 = (0000)d000 */
2539 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2540 /* t2 = 00c0 */
2541 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2542 /* t3 = d00a */
2543 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2544 /* t1 = 0abc */
2545 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2546 /* t2 = 0c00 */
2547 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2548 /* t1 = 00b0 */
2549 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2550 /* t3 = dc0a */
2551 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2552 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2553 /* t3 = dcba -- delay slot */
2554 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2555
2556 /*
2557 * bswap64 -- 64-bit swap. a0 = abcdefgh
2558 */
2559 bswap64_addr = align_code_ptr(s);
2560 /* t3 = h0000000 */
2561 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2562 /* t1 = 0000000a */
2563 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2564
2565 /* t2 = 000000g0 */
2566 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2567 /* t3 = h000000a */
2568 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2569 /* t1 = 00000abc */
2570 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2571 /* t2 = 0g000000 */
2572 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2573 /* t1 = 000000b0 */
2574 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2575
2576 /* t3 = hg00000a */
2577 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2578 /* t2 = 0000abcd */
2579 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2580 /* t3 = hg0000ba */
2581 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2582
2583 /* t1 = 000000c0 */
2584 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2585 /* t2 = 0000000d */
2586 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2587 /* t1 = 00000c00 */
2588 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2589 /* t2 = 0000d000 */
2590 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2591
2592 /* t3 = hg000cba */
2593 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2594 /* t1 = 00abcdef */
2595 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2596 /* t3 = hg00dcba */
2597 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2598
2599 /* t2 = 0000000f */
2600 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2601 /* t1 = 000000e0 */
2602 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2603 /* t2 = 00f00000 */
2604 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2605 /* t1 = 000e0000 */
2606 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2607
2608 /* t3 = hgf0dcba */
2609 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2610 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2611 /* t3 = hgfedcba -- delay slot */
2612 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2613 }
2614
2615 static void tcg_target_init(TCGContext *s)
2616 {
2617 tcg_target_detect_isa();
2618 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2619 if (TCG_TARGET_REG_BITS == 64) {
2620 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2621 }
2622
2623 tcg_target_call_clobber_regs = 0;
2624 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2625 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2626 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2627 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2628 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2629 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2630 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2631 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2632 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2633 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2634 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2635 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2636 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2637 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2638 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2639 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2640
2641 s->reserved_regs = 0;
2642 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2643 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2644 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2645 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2646 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2647 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2648 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2649 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2650 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2651 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2652 }
2653
2654 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
2655 uintptr_t addr)
2656 {
2657 atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2));
2658 flush_icache_range(jmp_addr, jmp_addr + 4);
2659 }
2660
2661 typedef struct {
2662 DebugFrameHeader h;
2663 uint8_t fde_def_cfa[4];
2664 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2665 } DebugFrame;
2666
2667 #define ELF_HOST_MACHINE EM_MIPS
2668 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2669 which is good because they're really quite complicated for MIPS. */
2670
2671 static const DebugFrame debug_frame = {
2672 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2673 .h.cie.id = -1,
2674 .h.cie.version = 1,
2675 .h.cie.code_align = 1,
2676 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2677 .h.cie.return_column = TCG_REG_RA,
2678
2679 /* Total FDE size does not include the "len" member. */
2680 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2681
2682 .fde_def_cfa = {
2683 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2684 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2685 (FRAME_SIZE >> 7)
2686 },
2687 .fde_reg_ofs = {
2688 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2689 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2690 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2691 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2692 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2693 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2694 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2695 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2696 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2697 }
2698 };
2699
2700 void tcg_register_jit(void *buf, size_t buf_size)
2701 {
2702 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2703 }
AR7 emulation for QEMU