2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 * Only host-mode and non-DMA accesses are currently supported.
23 #include "qemu-common.h"
24 #include "qemu/timer.h"
29 /* Common USB registers */
30 #define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31 #define MUSB_HDRC_POWER 0x01 /* 8-bit */
33 #define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34 #define MUSB_HDRC_INTRRX 0x04
35 #define MUSB_HDRC_INTRTXE 0x06
36 #define MUSB_HDRC_INTRRXE 0x08
37 #define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38 #define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39 #define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40 #define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41 #define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
43 /* Per-EP registers in indexed mode */
44 #define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
47 #define MUSB_HDRC_FIFO 0x20
49 /* Additional Control Registers */
50 #define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
52 /* These are indexed */
53 #define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54 #define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55 #define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56 #define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
58 /* Some more registers */
59 #define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60 #define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
62 /* Added in HDRC 1.9(?) & MHDRC 1.4 */
63 /* ULPI pass-through */
64 #define MUSB_HDRC_ULPI_VBUSCTL 0x70
65 #define MUSB_HDRC_ULPI_REGDATA 0x74
66 #define MUSB_HDRC_ULPI_REGADDR 0x75
67 #define MUSB_HDRC_ULPI_REGCTL 0x76
69 /* Extended config & PHY control */
70 #define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71 #define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72 #define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73 #define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74 #define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75 #define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76 #define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
78 /* Per-EP BUSCTL registers */
79 #define MUSB_HDRC_BUSCTL 0x80
81 /* Per-EP registers in flat mode */
82 #define MUSB_HDRC_EP 0x100
84 /* offsets to registers in flat model */
85 #define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86 #define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87 #define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88 #define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89 #define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90 #define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91 #define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92 #define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93 #define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94 #define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95 #define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96 #define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97 #define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98 #define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99 #define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
101 /* "Bus control" registers */
102 #define MUSB_HDRC_TXFUNCADDR 0x00
103 #define MUSB_HDRC_TXHUBADDR 0x02
104 #define MUSB_HDRC_TXHUBPORT 0x03
106 #define MUSB_HDRC_RXFUNCADDR 0x04
107 #define MUSB_HDRC_RXHUBADDR 0x06
108 #define MUSB_HDRC_RXHUBPORT 0x07
111 * MUSBHDRC Register bit masks
115 #define MGC_M_POWER_ISOUPDATE 0x80
116 #define MGC_M_POWER_SOFTCONN 0x40
117 #define MGC_M_POWER_HSENAB 0x20
118 #define MGC_M_POWER_HSMODE 0x10
119 #define MGC_M_POWER_RESET 0x08
120 #define MGC_M_POWER_RESUME 0x04
121 #define MGC_M_POWER_SUSPENDM 0x02
122 #define MGC_M_POWER_ENSUSPEND 0x01
125 #define MGC_M_INTR_SUSPEND 0x01
126 #define MGC_M_INTR_RESUME 0x02
127 #define MGC_M_INTR_RESET 0x04
128 #define MGC_M_INTR_BABBLE 0x04
129 #define MGC_M_INTR_SOF 0x08
130 #define MGC_M_INTR_CONNECT 0x10
131 #define MGC_M_INTR_DISCONNECT 0x20
132 #define MGC_M_INTR_SESSREQ 0x40
133 #define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134 #define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
137 #define MGC_M_DEVCTL_BDEVICE 0x80
138 #define MGC_M_DEVCTL_FSDEV 0x40
139 #define MGC_M_DEVCTL_LSDEV 0x20
140 #define MGC_M_DEVCTL_VBUS 0x18
141 #define MGC_S_DEVCTL_VBUS 3
142 #define MGC_M_DEVCTL_HM 0x04
143 #define MGC_M_DEVCTL_HR 0x02
144 #define MGC_M_DEVCTL_SESSION 0x01
147 #define MGC_M_TEST_FORCE_HOST 0x80
148 #define MGC_M_TEST_FIFO_ACCESS 0x40
149 #define MGC_M_TEST_FORCE_FS 0x20
150 #define MGC_M_TEST_FORCE_HS 0x10
151 #define MGC_M_TEST_PACKET 0x08
152 #define MGC_M_TEST_K 0x04
153 #define MGC_M_TEST_J 0x02
154 #define MGC_M_TEST_SE0_NAK 0x01
157 #define MGC_M_CSR0_FLUSHFIFO 0x0100
158 #define MGC_M_CSR0_TXPKTRDY 0x0002
159 #define MGC_M_CSR0_RXPKTRDY 0x0001
161 /* CSR0 in Peripheral mode */
162 #define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163 #define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164 #define MGC_M_CSR0_P_SENDSTALL 0x0020
165 #define MGC_M_CSR0_P_SETUPEND 0x0010
166 #define MGC_M_CSR0_P_DATAEND 0x0008
167 #define MGC_M_CSR0_P_SENTSTALL 0x0004
169 /* CSR0 in Host mode */
170 #define MGC_M_CSR0_H_NO_PING 0x0800
171 #define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172 #define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173 #define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174 #define MGC_M_CSR0_H_STATUSPKT 0x0040
175 #define MGC_M_CSR0_H_REQPKT 0x0020
176 #define MGC_M_CSR0_H_ERROR 0x0010
177 #define MGC_M_CSR0_H_SETUPPKT 0x0008
178 #define MGC_M_CSR0_H_RXSTALL 0x0004
181 #define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182 #define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183 #define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184 #define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185 #define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186 #define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187 #define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188 #define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
190 /* TXCSR in Peripheral and Host mode */
191 #define MGC_M_TXCSR_AUTOSET 0x8000
192 #define MGC_M_TXCSR_ISO 0x4000
193 #define MGC_M_TXCSR_MODE 0x2000
194 #define MGC_M_TXCSR_DMAENAB 0x1000
195 #define MGC_M_TXCSR_FRCDATATOG 0x0800
196 #define MGC_M_TXCSR_DMAMODE 0x0400
197 #define MGC_M_TXCSR_CLRDATATOG 0x0040
198 #define MGC_M_TXCSR_FLUSHFIFO 0x0008
199 #define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200 #define MGC_M_TXCSR_TXPKTRDY 0x0001
202 /* TXCSR in Peripheral mode */
203 #define MGC_M_TXCSR_P_INCOMPTX 0x0080
204 #define MGC_M_TXCSR_P_SENTSTALL 0x0020
205 #define MGC_M_TXCSR_P_SENDSTALL 0x0010
206 #define MGC_M_TXCSR_P_UNDERRUN 0x0004
208 /* TXCSR in Host mode */
209 #define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210 #define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211 #define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212 #define MGC_M_TXCSR_H_RXSTALL 0x0020
213 #define MGC_M_TXCSR_H_ERROR 0x0004
215 /* RXCSR in Peripheral and Host mode */
216 #define MGC_M_RXCSR_AUTOCLEAR 0x8000
217 #define MGC_M_RXCSR_DMAENAB 0x2000
218 #define MGC_M_RXCSR_DISNYET 0x1000
219 #define MGC_M_RXCSR_DMAMODE 0x0800
220 #define MGC_M_RXCSR_INCOMPRX 0x0100
221 #define MGC_M_RXCSR_CLRDATATOG 0x0080
222 #define MGC_M_RXCSR_FLUSHFIFO 0x0010
223 #define MGC_M_RXCSR_DATAERROR 0x0008
224 #define MGC_M_RXCSR_FIFOFULL 0x0002
225 #define MGC_M_RXCSR_RXPKTRDY 0x0001
227 /* RXCSR in Peripheral mode */
228 #define MGC_M_RXCSR_P_ISO 0x4000
229 #define MGC_M_RXCSR_P_SENTSTALL 0x0040
230 #define MGC_M_RXCSR_P_SENDSTALL 0x0020
231 #define MGC_M_RXCSR_P_OVERRUN 0x0004
233 /* RXCSR in Host mode */
234 #define MGC_M_RXCSR_H_AUTOREQ 0x4000
235 #define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236 #define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237 #define MGC_M_RXCSR_H_RXSTALL 0x0040
238 #define MGC_M_RXCSR_H_REQPKT 0x0020
239 #define MGC_M_RXCSR_H_ERROR 0x0004
242 #define MGC_M_HUBADDR_MULTI_TT 0x80
244 /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245 #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246 #define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247 #define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248 #define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249 #define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250 #define MGC_M_ULPI_REGCTL_REG 0x01
252 /* #define MUSB_DEBUG */
255 #define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
262 static void musb_attach(USBPort
*port
);
263 static void musb_detach(USBPort
*port
);
264 static void musb_child_detach(USBPort
*port
, USBDevice
*child
);
265 static void musb_schedule_cb(USBPort
*port
, USBPacket
*p
);
266 static void musb_async_cancel_device(MUSBState
*s
, USBDevice
*dev
);
268 static USBPortOps musb_port_ops
= {
269 .attach
= musb_attach
,
270 .detach
= musb_detach
,
271 .child_detach
= musb_child_detach
,
272 .complete
= musb_schedule_cb
,
275 static USBBusOps musb_bus_ops
= {
278 typedef struct MUSBPacket MUSBPacket
;
279 typedef struct MUSBEndPoint MUSBEndPoint
;
287 struct MUSBEndPoint
{
298 int timeout
[2]; /* Always in microframes */
304 MUSBPacket packey
[2];
308 /* For callbacks' use */
312 USBCallback
*delayed_cb
[2];
313 QEMUTimer
*intv_timer
[2];
317 qemu_irq irqs
[musb_irq_max
];
338 /* Duplicating the world since 2008!... probably we should have 32
339 * logical, single endpoints instead. */
343 void musb_reset(MUSBState
*s
)
349 s
->power
= MGC_M_POWER_HSENAB
;
360 memset(s
->buf
, 0, sizeof(s
->buf
));
363 s
->ep
[0].config
= MGC_M_CONFIGDATA_SOFTCONE
| MGC_M_CONFIGDATA_DYNFIFO
;
364 for (i
= 0; i
< 16; i
++) {
365 s
->ep
[i
].fifosize
= 64;
366 s
->ep
[i
].maxp
[0] = 0x40;
367 s
->ep
[i
].maxp
[1] = 0x40;
370 usb_packet_init(&s
->ep
[i
].packey
[0].p
);
371 usb_packet_init(&s
->ep
[i
].packey
[1].p
);
375 struct MUSBState
*musb_init(DeviceState
*parent_device
, int gpio_base
)
377 MUSBState
*s
= g_malloc0(sizeof(*s
));
380 for (i
= 0; i
< musb_irq_max
; i
++) {
381 s
->irqs
[i
] = qdev_get_gpio_in(parent_device
, gpio_base
+ i
);
386 usb_bus_new(&s
->bus
, sizeof(s
->bus
), &musb_bus_ops
, parent_device
);
387 usb_register_port(&s
->bus
, &s
->port
, s
, 0, &musb_port_ops
,
388 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
393 static void musb_vbus_set(MUSBState
*s
, int level
)
396 s
->devctl
|= 3 << MGC_S_DEVCTL_VBUS
;
398 s
->devctl
&= ~MGC_M_DEVCTL_VBUS
;
400 qemu_set_irq(s
->irqs
[musb_set_vbus
], level
);
403 static void musb_intr_set(MUSBState
*s
, int line
, int level
)
406 s
->intr
&= ~(1 << line
);
407 qemu_irq_lower(s
->irqs
[line
]);
408 } else if (s
->mask
& (1 << line
)) {
409 s
->intr
|= 1 << line
;
410 qemu_irq_raise(s
->irqs
[line
]);
414 static void musb_tx_intr_set(MUSBState
*s
, int line
, int level
)
417 s
->tx_intr
&= ~(1 << line
);
419 qemu_irq_lower(s
->irqs
[musb_irq_tx
]);
420 } else if (s
->tx_mask
& (1 << line
)) {
421 s
->tx_intr
|= 1 << line
;
422 qemu_irq_raise(s
->irqs
[musb_irq_tx
]);
426 static void musb_rx_intr_set(MUSBState
*s
, int line
, int level
)
430 s
->rx_intr
&= ~(1 << line
);
432 qemu_irq_lower(s
->irqs
[musb_irq_rx
]);
433 } else if (s
->rx_mask
& (1 << line
)) {
434 s
->rx_intr
|= 1 << line
;
435 qemu_irq_raise(s
->irqs
[musb_irq_rx
]);
438 musb_tx_intr_set(s
, line
, level
);
441 uint32_t musb_core_intr_get(MUSBState
*s
)
443 return (s
->rx_intr
<< 15) | s
->tx_intr
;
446 void musb_core_intr_clear(MUSBState
*s
, uint32_t mask
)
449 s
->rx_intr
&= mask
>> 15;
451 qemu_irq_lower(s
->irqs
[musb_irq_rx
]);
455 s
->tx_intr
&= mask
& 0xffff;
457 qemu_irq_lower(s
->irqs
[musb_irq_tx
]);
461 void musb_set_size(MUSBState
*s
, int epnum
, int size
, int is_tx
)
463 s
->ep
[epnum
].ext_size
[!is_tx
] = size
;
464 s
->ep
[epnum
].fifostart
[0] = 0;
465 s
->ep
[epnum
].fifostart
[1] = 0;
466 s
->ep
[epnum
].fifolen
[0] = 0;
467 s
->ep
[epnum
].fifolen
[1] = 0;
470 static void musb_session_update(MUSBState
*s
, int prev_dev
, int prev_sess
)
472 int detect_prev
= prev_dev
&& prev_sess
;
473 int detect
= !!s
->port
.dev
&& s
->session
;
475 if (detect
&& !detect_prev
) {
476 /* Let's skip the ID pin sense and VBUS sense formalities and
477 * and signal a successful SRP directly. This should work at least
478 * for the Linux driver stack. */
479 musb_intr_set(s
, musb_irq_connect
, 1);
481 if (s
->port
.dev
->speed
== USB_SPEED_LOW
) {
482 s
->devctl
&= ~MGC_M_DEVCTL_FSDEV
;
483 s
->devctl
|= MGC_M_DEVCTL_LSDEV
;
485 s
->devctl
|= MGC_M_DEVCTL_FSDEV
;
486 s
->devctl
&= ~MGC_M_DEVCTL_LSDEV
;
490 s
->devctl
&= ~MGC_M_DEVCTL_BDEVICE
;
493 s
->devctl
|= MGC_M_DEVCTL_HM
;
497 } else if (!detect
&& detect_prev
) {
504 /* Attach or detach a device on our only port. */
505 static void musb_attach(USBPort
*port
)
507 MUSBState
*s
= (MUSBState
*) port
->opaque
;
509 musb_intr_set(s
, musb_irq_vbus_request
, 1);
510 musb_session_update(s
, 0, s
->session
);
513 static void musb_detach(USBPort
*port
)
515 MUSBState
*s
= (MUSBState
*) port
->opaque
;
517 musb_async_cancel_device(s
, port
->dev
);
519 musb_intr_set(s
, musb_irq_disconnect
, 1);
520 musb_session_update(s
, 1, s
->session
);
523 static void musb_child_detach(USBPort
*port
, USBDevice
*child
)
525 MUSBState
*s
= (MUSBState
*) port
->opaque
;
527 musb_async_cancel_device(s
, child
);
530 static void musb_cb_tick0(void *opaque
)
532 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
534 ep
->delayed_cb
[0](&ep
->packey
[0].p
, opaque
);
537 static void musb_cb_tick1(void *opaque
)
539 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
541 ep
->delayed_cb
[1](&ep
->packey
[1].p
, opaque
);
544 #define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
546 static void musb_schedule_cb(USBPort
*port
, USBPacket
*packey
)
548 MUSBPacket
*p
= container_of(packey
, MUSBPacket
, p
);
549 MUSBEndPoint
*ep
= p
->ep
;
553 if (ep
->status
[dir
] == USB_RET_NAK
)
554 timeout
= ep
->timeout
[dir
];
555 else if (ep
->interrupt
[dir
])
558 return musb_cb_tick(ep
);
560 if (!ep
->intv_timer
[dir
])
561 ep
->intv_timer
[dir
] = timer_new_ns(QEMU_CLOCK_VIRTUAL
, musb_cb_tick
, ep
);
563 timer_mod(ep
->intv_timer
[dir
], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
564 muldiv64(timeout
, get_ticks_per_sec(), 8000));
567 static int musb_timeout(int ttype
, int speed
, int val
)
574 case USB_ENDPOINT_XFER_CONTROL
:
577 else if (speed
== USB_SPEED_HIGH
)
578 return 1 << (val
- 1);
580 return 8 << (val
- 1);
582 case USB_ENDPOINT_XFER_INT
:
583 if (speed
== USB_SPEED_HIGH
)
587 return 1 << (val
- 1);
591 case USB_ENDPOINT_XFER_BULK
:
592 case USB_ENDPOINT_XFER_ISOC
:
595 else if (speed
== USB_SPEED_HIGH
)
596 return 1 << (val
- 1);
598 return 8 << (val
- 1);
599 /* TODO: what with low-speed Bulk and Isochronous? */
602 hw_error("bad interval\n");
605 static void musb_packet(MUSBState
*s
, MUSBEndPoint
*ep
,
606 int epnum
, int pid
, int len
, USBCallback cb
, int dir
)
610 int idx
= epnum
&& dir
;
614 /* ep->type[0,1] contains:
615 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
616 * in bits 5:4 the transfer type (BULK / INT)
617 * in bits 3:0 the EP num
619 ttype
= epnum
? (ep
->type
[idx
] >> 4) & 3 : 0;
621 ep
->timeout
[dir
] = musb_timeout(ttype
,
622 ep
->type
[idx
] >> 6, ep
->interval
[idx
]);
623 ep
->interrupt
[dir
] = ttype
== USB_ENDPOINT_XFER_INT
;
624 ep
->delayed_cb
[dir
] = cb
;
626 /* A wild guess on the FADDR semantics... */
627 dev
= usb_find_device(&s
->port
, ep
->faddr
[idx
]);
628 uep
= usb_ep_get(dev
, pid
, ep
->type
[idx
] & 0xf);
631 id
|= (dev
->addr
<< 16) | (uep
->nr
<< 8);
633 usb_packet_setup(&ep
->packey
[dir
].p
, pid
, uep
, 0, id
, false, true);
634 usb_packet_addbuf(&ep
->packey
[dir
].p
, ep
->buf
[idx
], len
);
635 ep
->packey
[dir
].ep
= ep
;
636 ep
->packey
[dir
].dir
= dir
;
638 usb_handle_packet(dev
, &ep
->packey
[dir
].p
);
640 if (ep
->packey
[dir
].p
.status
== USB_RET_ASYNC
) {
641 usb_device_flush_ep_queue(dev
, uep
);
642 ep
->status
[dir
] = len
;
646 if (ep
->packey
[dir
].p
.status
== USB_RET_SUCCESS
) {
647 ep
->status
[dir
] = ep
->packey
[dir
].p
.actual_length
;
649 ep
->status
[dir
] = ep
->packey
[dir
].p
.status
;
651 musb_schedule_cb(&s
->port
, &ep
->packey
[dir
].p
);
654 static void musb_tx_packet_complete(USBPacket
*packey
, void *opaque
)
656 /* Unfortunately we can't use packey->devep because that's the remote
657 * endpoint number and may be different than our local. */
658 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
659 int epnum
= ep
->epnum
;
660 MUSBState
*s
= ep
->musb
;
662 ep
->fifostart
[0] = 0;
665 if (ep
->status
[0] != USB_RET_NAK
) {
668 ep
->csr
[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY
| MGC_M_TXCSR_TXPKTRDY
);
670 ep
->csr
[0] &= ~MGC_M_CSR0_TXPKTRDY
;
675 /* Clear all of the error bits first */
677 ep
->csr
[0] &= ~(MGC_M_TXCSR_H_ERROR
| MGC_M_TXCSR_H_RXSTALL
|
678 MGC_M_TXCSR_H_NAKTIMEOUT
);
680 ep
->csr
[0] &= ~(MGC_M_CSR0_H_ERROR
| MGC_M_CSR0_H_RXSTALL
|
681 MGC_M_CSR0_H_NAKTIMEOUT
| MGC_M_CSR0_H_NO_PING
);
683 if (ep
->status
[0] == USB_RET_STALL
) {
684 /* Command not supported by target! */
688 ep
->csr
[0] |= MGC_M_TXCSR_H_RXSTALL
;
690 ep
->csr
[0] |= MGC_M_CSR0_H_RXSTALL
;
693 if (ep
->status
[0] == USB_RET_NAK
) {
696 /* NAK timeouts are only generated in Bulk transfers and
697 * Data-errors in Isochronous. */
698 if (ep
->interrupt
[0]) {
703 ep
->csr
[0] |= MGC_M_TXCSR_H_NAKTIMEOUT
;
705 ep
->csr
[0] |= MGC_M_CSR0_H_NAKTIMEOUT
;
708 if (ep
->status
[0] < 0) {
709 if (ep
->status
[0] == USB_RET_BABBLE
)
710 musb_intr_set(s
, musb_irq_rst_babble
, 1);
712 /* Pretend we've tried three times already and failed (in
713 * case of USB_TOKEN_SETUP). */
715 ep
->csr
[0] |= MGC_M_TXCSR_H_ERROR
;
717 ep
->csr
[0] |= MGC_M_CSR0_H_ERROR
;
719 musb_tx_intr_set(s
, epnum
, 1);
722 /* TODO: check len for over/underruns of an OUT packet? */
725 if (!epnum
&& ep
->packey
[0].pid
== USB_TOKEN_SETUP
)
726 s
->setup_len
= ep
->packey
[0].data
[6];
729 /* In DMA mode: if no error, assert DMA request for this EP,
730 * and skip the interrupt. */
731 musb_tx_intr_set(s
, epnum
, 1);
734 static void musb_rx_packet_complete(USBPacket
*packey
, void *opaque
)
736 /* Unfortunately we can't use packey->devep because that's the remote
737 * endpoint number and may be different than our local. */
738 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
739 int epnum
= ep
->epnum
;
740 MUSBState
*s
= ep
->musb
;
742 ep
->fifostart
[1] = 0;
746 if (ep
->status
[1] != USB_RET_NAK
) {
748 ep
->csr
[1] &= ~MGC_M_RXCSR_H_REQPKT
;
750 ep
->csr
[0] &= ~MGC_M_CSR0_H_REQPKT
;
755 /* Clear all of the imaginable error bits first */
756 ep
->csr
[1] &= ~(MGC_M_RXCSR_H_ERROR
| MGC_M_RXCSR_H_RXSTALL
|
757 MGC_M_RXCSR_DATAERROR
);
759 ep
->csr
[0] &= ~(MGC_M_CSR0_H_ERROR
| MGC_M_CSR0_H_RXSTALL
|
760 MGC_M_CSR0_H_NAKTIMEOUT
| MGC_M_CSR0_H_NO_PING
);
762 if (ep
->status
[1] == USB_RET_STALL
) {
765 ep
->csr
[1] |= MGC_M_RXCSR_H_RXSTALL
;
767 ep
->csr
[0] |= MGC_M_CSR0_H_RXSTALL
;
770 if (ep
->status
[1] == USB_RET_NAK
) {
773 /* NAK timeouts are only generated in Bulk transfers and
774 * Data-errors in Isochronous. */
775 if (ep
->interrupt
[1])
776 return musb_packet(s
, ep
, epnum
, USB_TOKEN_IN
,
777 packey
->iov
.size
, musb_rx_packet_complete
, 1);
779 ep
->csr
[1] |= MGC_M_RXCSR_DATAERROR
;
781 ep
->csr
[0] |= MGC_M_CSR0_H_NAKTIMEOUT
;
784 if (ep
->status
[1] < 0) {
785 if (ep
->status
[1] == USB_RET_BABBLE
) {
786 musb_intr_set(s
, musb_irq_rst_babble
, 1);
790 /* Pretend we've tried three times already and failed (in
791 * case of a control transfer). */
792 ep
->csr
[1] |= MGC_M_RXCSR_H_ERROR
;
794 ep
->csr
[0] |= MGC_M_CSR0_H_ERROR
;
796 musb_rx_intr_set(s
, epnum
, 1);
799 /* TODO: check len for over/underruns of an OUT packet? */
800 /* TODO: perhaps make use of e->ext_size[1] here. */
802 if (!(ep
->csr
[1] & (MGC_M_RXCSR_H_RXSTALL
| MGC_M_RXCSR_DATAERROR
))) {
803 ep
->csr
[1] |= MGC_M_RXCSR_FIFOFULL
| MGC_M_RXCSR_RXPKTRDY
;
805 ep
->csr
[0] |= MGC_M_CSR0_RXPKTRDY
;
807 ep
->rxcount
= ep
->status
[1]; /* XXX: MIN(packey->len, ep->maxp[1]); */
808 /* In DMA mode: assert DMA request for this EP */
811 /* Only if DMA has not been asserted */
812 musb_rx_intr_set(s
, epnum
, 1);
815 static void musb_async_cancel_device(MUSBState
*s
, USBDevice
*dev
)
819 for (ep
= 0; ep
< 16; ep
++) {
820 for (dir
= 0; dir
< 2; dir
++) {
821 if (!usb_packet_is_inflight(&s
->ep
[ep
].packey
[dir
].p
) ||
822 s
->ep
[ep
].packey
[dir
].p
.ep
->dev
!= dev
) {
825 usb_cancel_packet(&s
->ep
[ep
].packey
[dir
].p
);
826 /* status updates needed here? */
831 static void musb_tx_rdy(MUSBState
*s
, int epnum
)
833 MUSBEndPoint
*ep
= s
->ep
+ epnum
;
835 int total
, valid
= 0;
836 TRACE("start %d, len %d", ep
->fifostart
[0], ep
->fifolen
[0] );
837 ep
->fifostart
[0] += ep
->fifolen
[0];
840 /* XXX: how's the total size of the packet retrieved exactly in
841 * the generic case? */
842 total
= ep
->maxp
[0] & 0x3ff;
844 if (ep
->ext_size
[0]) {
845 total
= ep
->ext_size
[0];
850 /* If the packet is not fully ready yet, wait for a next segment. */
851 if (epnum
&& (ep
->fifostart
[0]) < total
)
855 total
= ep
->fifostart
[0];
858 if (!epnum
&& (ep
->csr
[0] & MGC_M_CSR0_H_SETUPPKT
)) {
859 pid
= USB_TOKEN_SETUP
;
861 TRACE("illegal SETUPPKT length of %i bytes", total
);
863 /* Controller should retry SETUP packets three times on errors
864 * but it doesn't make sense for us to do that. */
867 return musb_packet(s
, ep
, epnum
, pid
,
868 total
, musb_tx_packet_complete
, 0);
871 static void musb_rx_req(MUSBState
*s
, int epnum
)
873 MUSBEndPoint
*ep
= s
->ep
+ epnum
;
876 /* If we already have a packet, which didn't fit into the
877 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
878 if (ep
->packey
[1].p
.pid
== USB_TOKEN_IN
&& ep
->status
[1] >= 0 &&
879 (ep
->fifostart
[1]) + ep
->rxcount
<
880 ep
->packey
[1].p
.iov
.size
) {
881 TRACE("0x%08x, %d", ep
->fifostart
[1], ep
->rxcount
);
882 ep
->fifostart
[1] += ep
->rxcount
;
885 ep
->rxcount
= MIN(ep
->packey
[0].p
.iov
.size
- (ep
->fifostart
[1]),
888 ep
->csr
[1] &= ~MGC_M_RXCSR_H_REQPKT
;
890 ep
->csr
[0] &= ~MGC_M_CSR0_H_REQPKT
;
892 /* Clear all of the error bits first */
893 ep
->csr
[1] &= ~(MGC_M_RXCSR_H_ERROR
| MGC_M_RXCSR_H_RXSTALL
|
894 MGC_M_RXCSR_DATAERROR
);
896 ep
->csr
[0] &= ~(MGC_M_CSR0_H_ERROR
| MGC_M_CSR0_H_RXSTALL
|
897 MGC_M_CSR0_H_NAKTIMEOUT
| MGC_M_CSR0_H_NO_PING
);
899 ep
->csr
[1] |= MGC_M_RXCSR_FIFOFULL
| MGC_M_RXCSR_RXPKTRDY
;
901 ep
->csr
[0] |= MGC_M_CSR0_RXPKTRDY
;
902 musb_rx_intr_set(s
, epnum
, 1);
906 /* The driver sets maxp[1] to 64 or less because it knows the hardware
907 * FIFO is this deep. Bigger packets get split in
908 * usb_generic_handle_packet but we can also do the splitting locally
909 * for performance. It turns out we can also have a bigger FIFO and
910 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
911 * OK with single packets of even 32KB and we avoid splitting, however
912 * usb_msd.c sometimes sends a packet bigger than what Linux expects
913 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
914 * hides this overrun from Linux. Up to 4096 everything is fine
915 * though. Currently this is disabled.
917 * XXX: mind ep->fifosize. */
918 total
= MIN(ep
->maxp
[1] & 0x3ff, sizeof(s
->buf
));
921 /* Why should *we* do that instead of Linux? */
923 if (ep
->packey
[0].p
.devaddr
== 2) {
924 total
= MIN(s
->setup_len
, 8);
926 total
= MIN(s
->setup_len
, 64);
928 s
->setup_len
-= total
;
932 return musb_packet(s
, ep
, epnum
, USB_TOKEN_IN
,
933 total
, musb_rx_packet_complete
, 1);
936 static uint8_t musb_read_fifo(MUSBEndPoint
*ep
)
939 if (ep
->fifolen
[1] >= 64) {
940 /* We have a FIFO underrun */
941 TRACE("EP%d FIFO is now empty, stop reading", ep
->epnum
);
944 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
945 * (if AUTOREQ is set) */
947 ep
->csr
[1] &= ~MGC_M_RXCSR_FIFOFULL
;
948 value
=ep
->buf
[1][ep
->fifostart
[1] + ep
->fifolen
[1] ++];
949 TRACE("EP%d 0x%02x, %d", ep
->epnum
, value
, ep
->fifolen
[1] );
953 static void musb_write_fifo(MUSBEndPoint
*ep
, uint8_t value
)
955 TRACE("EP%d = %02x", ep
->epnum
, value
);
956 if (ep
->fifolen
[0] >= 64) {
957 /* We have a FIFO overrun */
958 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep
->epnum
);
962 ep
->buf
[0][ep
->fifostart
[0] + ep
->fifolen
[0] ++] = value
;
963 ep
->csr
[0] |= MGC_M_TXCSR_FIFONOTEMPTY
;
966 static void musb_ep_frame_cancel(MUSBEndPoint
*ep
, int dir
)
968 if (ep
->intv_timer
[dir
])
969 timer_del(ep
->intv_timer
[dir
]);
973 static uint8_t musb_busctl_readb(void *opaque
, int ep
, int addr
)
975 MUSBState
*s
= (MUSBState
*) opaque
;
978 /* For USB2.0 HS hubs only */
979 case MUSB_HDRC_TXHUBADDR
:
980 return s
->ep
[ep
].haddr
[0];
981 case MUSB_HDRC_TXHUBPORT
:
982 return s
->ep
[ep
].hport
[0];
983 case MUSB_HDRC_RXHUBADDR
:
984 return s
->ep
[ep
].haddr
[1];
985 case MUSB_HDRC_RXHUBPORT
:
986 return s
->ep
[ep
].hport
[1];
989 TRACE("unknown register 0x%02x", addr
);
994 static void musb_busctl_writeb(void *opaque
, int ep
, int addr
, uint8_t value
)
996 MUSBState
*s
= (MUSBState
*) opaque
;
999 case MUSB_HDRC_TXFUNCADDR
:
1000 s
->ep
[ep
].faddr
[0] = value
;
1002 case MUSB_HDRC_RXFUNCADDR
:
1003 s
->ep
[ep
].faddr
[1] = value
;
1005 case MUSB_HDRC_TXHUBADDR
:
1006 s
->ep
[ep
].haddr
[0] = value
;
1008 case MUSB_HDRC_TXHUBPORT
:
1009 s
->ep
[ep
].hport
[0] = value
;
1011 case MUSB_HDRC_RXHUBADDR
:
1012 s
->ep
[ep
].haddr
[1] = value
;
1014 case MUSB_HDRC_RXHUBPORT
:
1015 s
->ep
[ep
].hport
[1] = value
;
1019 TRACE("unknown register 0x%02x", addr
);
1024 static uint16_t musb_busctl_readh(void *opaque
, int ep
, int addr
)
1026 MUSBState
*s
= (MUSBState
*) opaque
;
1029 case MUSB_HDRC_TXFUNCADDR
:
1030 return s
->ep
[ep
].faddr
[0];
1031 case MUSB_HDRC_RXFUNCADDR
:
1032 return s
->ep
[ep
].faddr
[1];
1035 return musb_busctl_readb(s
, ep
, addr
) |
1036 (musb_busctl_readb(s
, ep
, addr
| 1) << 8);
1040 static void musb_busctl_writeh(void *opaque
, int ep
, int addr
, uint16_t value
)
1042 MUSBState
*s
= (MUSBState
*) opaque
;
1045 case MUSB_HDRC_TXFUNCADDR
:
1046 s
->ep
[ep
].faddr
[0] = value
;
1048 case MUSB_HDRC_RXFUNCADDR
:
1049 s
->ep
[ep
].faddr
[1] = value
;
1053 musb_busctl_writeb(s
, ep
, addr
, value
& 0xff);
1054 musb_busctl_writeb(s
, ep
, addr
| 1, value
>> 8);
1058 /* Endpoint control */
1059 static uint8_t musb_ep_readb(void *opaque
, int ep
, int addr
)
1061 MUSBState
*s
= (MUSBState
*) opaque
;
1064 case MUSB_HDRC_TXTYPE
:
1065 return s
->ep
[ep
].type
[0];
1066 case MUSB_HDRC_TXINTERVAL
:
1067 return s
->ep
[ep
].interval
[0];
1068 case MUSB_HDRC_RXTYPE
:
1069 return s
->ep
[ep
].type
[1];
1070 case MUSB_HDRC_RXINTERVAL
:
1071 return s
->ep
[ep
].interval
[1];
1072 case (MUSB_HDRC_FIFOSIZE
& ~1):
1074 case MUSB_HDRC_FIFOSIZE
:
1075 return ep
? s
->ep
[ep
].fifosize
: s
->ep
[ep
].config
;
1076 case MUSB_HDRC_RXCOUNT
:
1077 return s
->ep
[ep
].rxcount
;
1080 TRACE("unknown register 0x%02x", addr
);
1085 static void musb_ep_writeb(void *opaque
, int ep
, int addr
, uint8_t value
)
1087 MUSBState
*s
= (MUSBState
*) opaque
;
1090 case MUSB_HDRC_TXTYPE
:
1091 s
->ep
[ep
].type
[0] = value
;
1093 case MUSB_HDRC_TXINTERVAL
:
1094 s
->ep
[ep
].interval
[0] = value
;
1095 musb_ep_frame_cancel(&s
->ep
[ep
], 0);
1097 case MUSB_HDRC_RXTYPE
:
1098 s
->ep
[ep
].type
[1] = value
;
1100 case MUSB_HDRC_RXINTERVAL
:
1101 s
->ep
[ep
].interval
[1] = value
;
1102 musb_ep_frame_cancel(&s
->ep
[ep
], 1);
1104 case (MUSB_HDRC_FIFOSIZE
& ~1):
1106 case MUSB_HDRC_FIFOSIZE
:
1107 TRACE("somebody messes with fifosize (now %i bytes)", value
);
1108 s
->ep
[ep
].fifosize
= value
;
1111 TRACE("unknown register 0x%02x", addr
);
1116 static uint16_t musb_ep_readh(void *opaque
, int ep
, int addr
)
1118 MUSBState
*s
= (MUSBState
*) opaque
;
1122 case MUSB_HDRC_TXMAXP
:
1123 return s
->ep
[ep
].maxp
[0];
1124 case MUSB_HDRC_TXCSR
:
1125 return s
->ep
[ep
].csr
[0];
1126 case MUSB_HDRC_RXMAXP
:
1127 return s
->ep
[ep
].maxp
[1];
1128 case MUSB_HDRC_RXCSR
:
1129 ret
= s
->ep
[ep
].csr
[1];
1131 /* TODO: This and other bits probably depend on
1132 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1133 if (s
->ep
[ep
].csr
[1] & MGC_M_RXCSR_AUTOCLEAR
)
1134 s
->ep
[ep
].csr
[1] &= ~MGC_M_RXCSR_RXPKTRDY
;
1137 case MUSB_HDRC_RXCOUNT
:
1138 return s
->ep
[ep
].rxcount
;
1141 return musb_ep_readb(s
, ep
, addr
) |
1142 (musb_ep_readb(s
, ep
, addr
| 1) << 8);
1146 static void musb_ep_writeh(void *opaque
, int ep
, int addr
, uint16_t value
)
1148 MUSBState
*s
= (MUSBState
*) opaque
;
1151 case MUSB_HDRC_TXMAXP
:
1152 s
->ep
[ep
].maxp
[0] = value
;
1154 case MUSB_HDRC_TXCSR
:
1156 s
->ep
[ep
].csr
[0] &= value
& 0xa6;
1157 s
->ep
[ep
].csr
[0] |= value
& 0xff59;
1159 s
->ep
[ep
].csr
[0] &= value
& 0x85;
1160 s
->ep
[ep
].csr
[0] |= value
& 0xf7a;
1163 musb_ep_frame_cancel(&s
->ep
[ep
], 0);
1165 if ((ep
&& (value
& MGC_M_TXCSR_FLUSHFIFO
)) ||
1166 (!ep
&& (value
& MGC_M_CSR0_FLUSHFIFO
))) {
1167 s
->ep
[ep
].fifolen
[0] = 0;
1168 s
->ep
[ep
].fifostart
[0] = 0;
1171 ~(MGC_M_TXCSR_FIFONOTEMPTY
| MGC_M_TXCSR_TXPKTRDY
);
1174 ~(MGC_M_CSR0_TXPKTRDY
| MGC_M_CSR0_RXPKTRDY
);
1179 (value
& MGC_M_TXCSR_TXPKTRDY
) &&
1180 !(value
& MGC_M_TXCSR_H_NAKTIMEOUT
)) ||
1182 (value
& MGC_M_TXCSR_TXPKTRDY
)) ||
1186 (value
& MGC_M_CSR0_TXPKTRDY
) &&
1187 !(value
& MGC_M_CSR0_H_NAKTIMEOUT
)))
1189 (value
& MGC_M_CSR0_TXPKTRDY
)))
1193 (value
& MGC_M_CSR0_H_REQPKT
) &&
1195 !(value
& (MGC_M_CSR0_H_NAKTIMEOUT
|
1196 MGC_M_CSR0_RXPKTRDY
)))
1198 !(value
& MGC_M_CSR0_RXPKTRDY
))
1203 case MUSB_HDRC_RXMAXP
:
1204 s
->ep
[ep
].maxp
[1] = value
;
1206 case MUSB_HDRC_RXCSR
:
1207 /* (DMA mode only) */
1209 (value
& MGC_M_RXCSR_H_AUTOREQ
) &&
1210 !(value
& MGC_M_RXCSR_RXPKTRDY
) &&
1211 (s
->ep
[ep
].csr
[1] & MGC_M_RXCSR_RXPKTRDY
))
1212 value
|= MGC_M_RXCSR_H_REQPKT
;
1214 s
->ep
[ep
].csr
[1] &= 0x102 | (value
& 0x4d);
1215 s
->ep
[ep
].csr
[1] |= value
& 0xfeb0;
1217 musb_ep_frame_cancel(&s
->ep
[ep
], 1);
1219 if (value
& MGC_M_RXCSR_FLUSHFIFO
) {
1220 s
->ep
[ep
].fifolen
[1] = 0;
1221 s
->ep
[ep
].fifostart
[1] = 0;
1222 s
->ep
[ep
].csr
[1] &= ~(MGC_M_RXCSR_FIFOFULL
| MGC_M_RXCSR_RXPKTRDY
);
1223 /* If double buffering and we have two packets ready, flush
1224 * only the first one and set up the fifo at the second packet. */
1227 if ((value
& MGC_M_RXCSR_H_REQPKT
) && !(value
& MGC_M_RXCSR_DATAERROR
))
1229 if (value
& MGC_M_RXCSR_H_REQPKT
)
1233 case MUSB_HDRC_RXCOUNT
:
1234 s
->ep
[ep
].rxcount
= value
;
1238 musb_ep_writeb(s
, ep
, addr
, value
& 0xff);
1239 musb_ep_writeb(s
, ep
, addr
| 1, value
>> 8);
1243 /* Generic control */
1244 static uint32_t musb_readb(void *opaque
, hwaddr addr
)
1246 MUSBState
*s
= (MUSBState
*) opaque
;
1251 case MUSB_HDRC_FADDR
:
1253 case MUSB_HDRC_POWER
:
1255 case MUSB_HDRC_INTRUSB
:
1257 for (i
= 0; i
< sizeof(ret
) * 8; i
++)
1259 musb_intr_set(s
, i
, 0);
1261 case MUSB_HDRC_INTRUSBE
:
1263 case MUSB_HDRC_INDEX
:
1265 case MUSB_HDRC_TESTMODE
:
1268 case MUSB_HDRC_EP_IDX
... (MUSB_HDRC_EP_IDX
+ 0xf):
1269 return musb_ep_readb(s
, s
->idx
, addr
& 0xf);
1271 case MUSB_HDRC_DEVCTL
:
1274 case MUSB_HDRC_TXFIFOSZ
:
1275 case MUSB_HDRC_RXFIFOSZ
:
1276 case MUSB_HDRC_VCTRL
:
1280 case MUSB_HDRC_HWVERS
:
1281 return (1 << 10) | 400;
1283 case (MUSB_HDRC_VCTRL
| 1):
1284 case (MUSB_HDRC_HWVERS
| 1):
1285 case (MUSB_HDRC_DEVCTL
| 1):
1288 case MUSB_HDRC_BUSCTL
... (MUSB_HDRC_BUSCTL
+ 0x7f):
1289 ep
= (addr
>> 3) & 0xf;
1290 return musb_busctl_readb(s
, ep
, addr
& 0x7);
1292 case MUSB_HDRC_EP
... (MUSB_HDRC_EP
+ 0xff):
1293 ep
= (addr
>> 4) & 0xf;
1294 return musb_ep_readb(s
, ep
, addr
& 0xf);
1296 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1297 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1298 return musb_read_fifo(s
->ep
+ ep
);
1301 TRACE("unknown register 0x%02x", (int) addr
);
1306 static void musb_writeb(void *opaque
, hwaddr addr
, uint32_t value
)
1308 MUSBState
*s
= (MUSBState
*) opaque
;
1312 case MUSB_HDRC_FADDR
:
1313 s
->faddr
= value
& 0x7f;
1315 case MUSB_HDRC_POWER
:
1316 s
->power
= (value
& 0xef) | (s
->power
& 0x10);
1317 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1318 if ((value
& MGC_M_POWER_RESET
) && s
->port
.dev
) {
1319 usb_device_reset(s
->port
.dev
);
1320 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1321 if ((value
& MGC_M_POWER_HSENAB
) &&
1322 s
->port
.dev
->speed
== USB_SPEED_HIGH
)
1323 s
->power
|= MGC_M_POWER_HSMODE
; /* Success */
1324 /* Restart frame counting. */
1326 if (value
& MGC_M_POWER_SUSPENDM
) {
1327 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1328 * is set, also go into low power mode. Frame counting stops. */
1329 /* XXX: Cleared when the interrupt register is read */
1331 if (value
& MGC_M_POWER_RESUME
) {
1332 /* Wait 20ms and signal resuming on the bus. Frame counting
1336 case MUSB_HDRC_INTRUSB
:
1338 case MUSB_HDRC_INTRUSBE
:
1339 s
->mask
= value
& 0xff;
1341 case MUSB_HDRC_INDEX
:
1342 s
->idx
= value
& 0xf;
1344 case MUSB_HDRC_TESTMODE
:
1347 case MUSB_HDRC_EP_IDX
... (MUSB_HDRC_EP_IDX
+ 0xf):
1348 musb_ep_writeb(s
, s
->idx
, addr
& 0xf, value
);
1351 case MUSB_HDRC_DEVCTL
:
1352 s
->session
= !!(value
& MGC_M_DEVCTL_SESSION
);
1353 musb_session_update(s
,
1355 !!(s
->devctl
& MGC_M_DEVCTL_SESSION
));
1357 /* It seems this is the only R/W bit in this register? */
1358 s
->devctl
&= ~MGC_M_DEVCTL_SESSION
;
1359 s
->devctl
|= value
& MGC_M_DEVCTL_SESSION
;
1362 case MUSB_HDRC_TXFIFOSZ
:
1363 case MUSB_HDRC_RXFIFOSZ
:
1364 case MUSB_HDRC_VCTRL
:
1368 case (MUSB_HDRC_VCTRL
| 1):
1369 case (MUSB_HDRC_DEVCTL
| 1):
1372 case MUSB_HDRC_BUSCTL
... (MUSB_HDRC_BUSCTL
+ 0x7f):
1373 ep
= (addr
>> 3) & 0xf;
1374 musb_busctl_writeb(s
, ep
, addr
& 0x7, value
);
1377 case MUSB_HDRC_EP
... (MUSB_HDRC_EP
+ 0xff):
1378 ep
= (addr
>> 4) & 0xf;
1379 musb_ep_writeb(s
, ep
, addr
& 0xf, value
);
1382 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1383 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1384 musb_write_fifo(s
->ep
+ ep
, value
& 0xff);
1388 TRACE("unknown register 0x%02x", (int) addr
);
1393 static uint32_t musb_readh(void *opaque
, hwaddr addr
)
1395 MUSBState
*s
= (MUSBState
*) opaque
;
1400 case MUSB_HDRC_INTRTX
:
1403 for (i
= 0; i
< sizeof(ret
) * 8; i
++)
1405 musb_tx_intr_set(s
, i
, 0);
1407 case MUSB_HDRC_INTRRX
:
1410 for (i
= 0; i
< sizeof(ret
) * 8; i
++)
1412 musb_rx_intr_set(s
, i
, 0);
1414 case MUSB_HDRC_INTRTXE
:
1416 case MUSB_HDRC_INTRRXE
:
1419 case MUSB_HDRC_FRAME
:
1422 case MUSB_HDRC_TXFIFOADDR
:
1423 return s
->ep
[s
->idx
].fifoaddr
[0];
1424 case MUSB_HDRC_RXFIFOADDR
:
1425 return s
->ep
[s
->idx
].fifoaddr
[1];
1427 case MUSB_HDRC_EP_IDX
... (MUSB_HDRC_EP_IDX
+ 0xf):
1428 return musb_ep_readh(s
, s
->idx
, addr
& 0xf);
1430 case MUSB_HDRC_BUSCTL
... (MUSB_HDRC_BUSCTL
+ 0x7f):
1431 ep
= (addr
>> 3) & 0xf;
1432 return musb_busctl_readh(s
, ep
, addr
& 0x7);
1434 case MUSB_HDRC_EP
... (MUSB_HDRC_EP
+ 0xff):
1435 ep
= (addr
>> 4) & 0xf;
1436 return musb_ep_readh(s
, ep
, addr
& 0xf);
1438 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1439 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1440 return (musb_read_fifo(s
->ep
+ ep
) | musb_read_fifo(s
->ep
+ ep
) << 8);
1443 return musb_readb(s
, addr
) | (musb_readb(s
, addr
| 1) << 8);
1447 static void musb_writeh(void *opaque
, hwaddr addr
, uint32_t value
)
1449 MUSBState
*s
= (MUSBState
*) opaque
;
1453 case MUSB_HDRC_INTRTXE
:
1455 /* XXX: the masks seem to apply on the raising edge like with
1456 * edge-triggered interrupts, thus no need to update. I may be
1459 case MUSB_HDRC_INTRRXE
:
1463 case MUSB_HDRC_FRAME
:
1466 case MUSB_HDRC_TXFIFOADDR
:
1467 s
->ep
[s
->idx
].fifoaddr
[0] = value
;
1468 s
->ep
[s
->idx
].buf
[0] =
1469 s
->buf
+ ((value
<< 3) & 0x7ff );
1471 case MUSB_HDRC_RXFIFOADDR
:
1472 s
->ep
[s
->idx
].fifoaddr
[1] = value
;
1473 s
->ep
[s
->idx
].buf
[1] =
1474 s
->buf
+ ((value
<< 3) & 0x7ff);
1477 case MUSB_HDRC_EP_IDX
... (MUSB_HDRC_EP_IDX
+ 0xf):
1478 musb_ep_writeh(s
, s
->idx
, addr
& 0xf, value
);
1481 case MUSB_HDRC_BUSCTL
... (MUSB_HDRC_BUSCTL
+ 0x7f):
1482 ep
= (addr
>> 3) & 0xf;
1483 musb_busctl_writeh(s
, ep
, addr
& 0x7, value
);
1486 case MUSB_HDRC_EP
... (MUSB_HDRC_EP
+ 0xff):
1487 ep
= (addr
>> 4) & 0xf;
1488 musb_ep_writeh(s
, ep
, addr
& 0xf, value
);
1491 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1492 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1493 musb_write_fifo(s
->ep
+ ep
, value
& 0xff);
1494 musb_write_fifo(s
->ep
+ ep
, (value
>> 8) & 0xff);
1498 musb_writeb(s
, addr
, value
& 0xff);
1499 musb_writeb(s
, addr
| 1, value
>> 8);
1503 static uint32_t musb_readw(void *opaque
, hwaddr addr
)
1505 MUSBState
*s
= (MUSBState
*) opaque
;
1509 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1510 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1511 return ( musb_read_fifo(s
->ep
+ ep
) |
1512 musb_read_fifo(s
->ep
+ ep
) << 8 |
1513 musb_read_fifo(s
->ep
+ ep
) << 16 |
1514 musb_read_fifo(s
->ep
+ ep
) << 24 );
1516 TRACE("unknown register 0x%02x", (int) addr
);
1521 static void musb_writew(void *opaque
, hwaddr addr
, uint32_t value
)
1523 MUSBState
*s
= (MUSBState
*) opaque
;
1527 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1528 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1529 musb_write_fifo(s
->ep
+ ep
, value
& 0xff);
1530 musb_write_fifo(s
->ep
+ ep
, (value
>> 8 ) & 0xff);
1531 musb_write_fifo(s
->ep
+ ep
, (value
>> 16) & 0xff);
1532 musb_write_fifo(s
->ep
+ ep
, (value
>> 24) & 0xff);
1535 TRACE("unknown register 0x%02x", (int) addr
);
1540 CPUReadMemoryFunc
* const musb_read
[] = {
1546 CPUWriteMemoryFunc
* const musb_write
[] = {