2 * QEMU PowerPC Booke hardware System Emulator
4 * Copyright (c) 2011 AdaCore
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/ppc/ppc.h"
26 #include "qemu/timer.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/timer/m48t59.h"
30 #include "hw/loader.h"
34 /* Timer Control Register */
36 #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
37 #define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
38 #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
39 #define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
40 #define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
41 #define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
42 #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
43 #define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
44 #define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
45 #define TCR_ARE (1U << 22) /* Auto-Reload Enable */
47 /* Timer Control Register (e500 specific fields) */
49 #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
50 #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
51 #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
52 #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
54 /* Timer Status Register */
56 #define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
57 #define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
58 #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
59 #define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
60 #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
61 #define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
63 typedef struct booke_timer_t booke_timer_t
;
64 struct booke_timer_t
{
75 static void booke_update_irq(PowerPCCPU
*cpu
)
77 CPUPPCState
*env
= &cpu
->env
;
79 ppc_set_irq(cpu
, PPC_INTERRUPT_DECR
,
80 (env
->spr
[SPR_BOOKE_TSR
] & TSR_DIS
81 && env
->spr
[SPR_BOOKE_TCR
] & TCR_DIE
));
83 ppc_set_irq(cpu
, PPC_INTERRUPT_WDT
,
84 (env
->spr
[SPR_BOOKE_TSR
] & TSR_WIS
85 && env
->spr
[SPR_BOOKE_TCR
] & TCR_WIE
));
87 ppc_set_irq(cpu
, PPC_INTERRUPT_FIT
,
88 (env
->spr
[SPR_BOOKE_TSR
] & TSR_FIS
89 && env
->spr
[SPR_BOOKE_TCR
] & TCR_FIE
));
92 /* Return the location of the bit of time base at which the FIT will raise an
94 static uint8_t booke_get_fit_target(CPUPPCState
*env
, ppc_tb_t
*tb_env
)
96 uint8_t fp
= (env
->spr
[SPR_BOOKE_TCR
] & TCR_FP_MASK
) >> TCR_FP_SHIFT
;
98 if (tb_env
->flags
& PPC_TIMER_E500
) {
99 /* e500 Fixed-interval timer period extension */
100 uint32_t fpext
= (env
->spr
[SPR_BOOKE_TCR
] & TCR_E500_FPEXT_MASK
)
101 >> TCR_E500_FPEXT_SHIFT
;
102 fp
= 63 - (fp
| fpext
<< 2);
104 fp
= env
->fit_period
[fp
];
110 /* Return the location of the bit of time base at which the WDT will raise an
112 static uint8_t booke_get_wdt_target(CPUPPCState
*env
, ppc_tb_t
*tb_env
)
114 uint8_t wp
= (env
->spr
[SPR_BOOKE_TCR
] & TCR_WP_MASK
) >> TCR_WP_SHIFT
;
116 if (tb_env
->flags
& PPC_TIMER_E500
) {
117 /* e500 Watchdog timer period extension */
118 uint32_t wpext
= (env
->spr
[SPR_BOOKE_TCR
] & TCR_E500_WPEXT_MASK
)
119 >> TCR_E500_WPEXT_SHIFT
;
120 wp
= 63 - (wp
| wpext
<< 2);
122 wp
= env
->wdt_period
[wp
];
128 static void booke_update_fixed_timer(CPUPPCState
*env
,
134 ppc_tb_t
*tb_env
= env
->tb_env
;
135 uint64_t delta_tick
, ticks
= 0;
140 if (!(env
->spr
[SPR_BOOKE_TSR
] & tsr_bit
)) {
142 * Don't arm the timer again when the guest has the current
143 * interrupt still pending. Wait for it to ack it.
148 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
149 tb
= cpu_ppc_get_tb(tb_env
, now
, tb_env
->tb_offset
);
150 period
= 1ULL << target_bit
;
151 delta_tick
= period
- (tb
& (period
- 1));
153 /* the timer triggers only when the selected bit toggles from 0 to 1 */
158 if (ticks
+ delta_tick
< ticks
) {
159 /* Overflow, so assume the biggest number we can express. */
165 *next
= now
+ muldiv64(ticks
, get_ticks_per_sec(), tb_env
->tb_freq
);
166 if ((*next
< now
) || (*next
> INT64_MAX
)) {
167 /* Overflow, so assume the biggest number the qemu timer supports. */
171 /* XXX: If expire time is now. We can't run the callback because we don't
172 * have access to it. So we just set the timer one nanosecond later.
179 * There's no point to fake any granularity that's more fine grained
180 * than milliseconds. Anything beyond that just overloads the system.
182 *next
= MAX(*next
, now
+ SCALE_MS
);
185 /* Fire the next timer */
186 timer_mod(timer
, *next
);
189 static void booke_decr_cb(void *opaque
)
191 PowerPCCPU
*cpu
= opaque
;
192 CPUPPCState
*env
= &cpu
->env
;
194 env
->spr
[SPR_BOOKE_TSR
] |= TSR_DIS
;
195 booke_update_irq(cpu
);
197 if (env
->spr
[SPR_BOOKE_TCR
] & TCR_ARE
) {
199 cpu_ppc_store_decr(env
, env
->spr
[SPR_BOOKE_DECAR
]);
203 static void booke_fit_cb(void *opaque
)
205 PowerPCCPU
*cpu
= opaque
;
206 CPUPPCState
*env
= &cpu
->env
;
208 booke_timer_t
*booke_timer
;
210 tb_env
= env
->tb_env
;
211 booke_timer
= tb_env
->opaque
;
212 env
->spr
[SPR_BOOKE_TSR
] |= TSR_FIS
;
214 booke_update_irq(cpu
);
216 booke_update_fixed_timer(env
,
217 booke_get_fit_target(env
, tb_env
),
218 &booke_timer
->fit_next
,
219 booke_timer
->fit_timer
,
223 static void booke_wdt_cb(void *opaque
)
225 PowerPCCPU
*cpu
= opaque
;
226 CPUPPCState
*env
= &cpu
->env
;
228 booke_timer_t
*booke_timer
;
230 tb_env
= env
->tb_env
;
231 booke_timer
= tb_env
->opaque
;
233 /* TODO: There's lots of complicated stuff to do here */
235 booke_update_irq(cpu
);
237 booke_update_fixed_timer(env
,
238 booke_get_wdt_target(env
, tb_env
),
239 &booke_timer
->wdt_next
,
240 booke_timer
->wdt_timer
,
244 void store_booke_tsr(CPUPPCState
*env
, target_ulong val
)
246 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
247 ppc_tb_t
*tb_env
= env
->tb_env
;
248 booke_timer_t
*booke_timer
= tb_env
->opaque
;
250 env
->spr
[SPR_BOOKE_TSR
] &= ~val
;
251 kvmppc_clear_tsr_bits(cpu
, val
);
254 booke_update_fixed_timer(env
,
255 booke_get_fit_target(env
, tb_env
),
256 &booke_timer
->fit_next
,
257 booke_timer
->fit_timer
,
262 booke_update_fixed_timer(env
,
263 booke_get_wdt_target(env
, tb_env
),
264 &booke_timer
->wdt_next
,
265 booke_timer
->wdt_timer
,
269 booke_update_irq(cpu
);
272 void store_booke_tcr(CPUPPCState
*env
, target_ulong val
)
274 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
275 ppc_tb_t
*tb_env
= env
->tb_env
;
276 booke_timer_t
*booke_timer
= tb_env
->opaque
;
278 tb_env
= env
->tb_env
;
279 env
->spr
[SPR_BOOKE_TCR
] = val
;
282 booke_update_irq(cpu
);
284 booke_update_fixed_timer(env
,
285 booke_get_fit_target(env
, tb_env
),
286 &booke_timer
->fit_next
,
287 booke_timer
->fit_timer
,
290 booke_update_fixed_timer(env
,
291 booke_get_wdt_target(env
, tb_env
),
292 &booke_timer
->wdt_next
,
293 booke_timer
->wdt_timer
,
297 static void ppc_booke_timer_reset_handle(void *opaque
)
299 PowerPCCPU
*cpu
= opaque
;
300 CPUPPCState
*env
= &cpu
->env
;
302 store_booke_tcr(env
, 0);
303 store_booke_tsr(env
, -1);
307 * This function will be called whenever the CPU state changes.
308 * CPU states are defined "typedef enum RunState".
309 * Regarding timer, When CPU state changes to running after debug halt
310 * or similar cases which takes time then in between final watchdog
311 * expiry happenes. This will cause exit to QEMU and configured watchdog
312 * action will be taken. To avoid this we always clear the watchdog state when
313 * state changes to running.
315 static void cpu_state_change_handler(void *opaque
, int running
, RunState state
)
317 PowerPCCPU
*cpu
= opaque
;
318 CPUPPCState
*env
= &cpu
->env
;
325 * Clear watchdog interrupt condition by clearing TSR.
327 store_booke_tsr(env
, TSR_ENW
| TSR_WIS
| TSR_WRS_MASK
);
330 void ppc_booke_timers_init(PowerPCCPU
*cpu
, uint32_t freq
, uint32_t flags
)
333 booke_timer_t
*booke_timer
;
336 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
337 booke_timer
= g_malloc0(sizeof(booke_timer_t
));
339 cpu
->env
.tb_env
= tb_env
;
340 tb_env
->flags
= flags
| PPC_TIMER_BOOKE
| PPC_DECR_ZERO_TRIGGERED
;
342 tb_env
->tb_freq
= freq
;
343 tb_env
->decr_freq
= freq
;
344 tb_env
->opaque
= booke_timer
;
345 tb_env
->decr_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &booke_decr_cb
, cpu
);
347 booke_timer
->fit_timer
=
348 timer_new_ns(QEMU_CLOCK_VIRTUAL
, &booke_fit_cb
, cpu
);
349 booke_timer
->wdt_timer
=
350 timer_new_ns(QEMU_CLOCK_VIRTUAL
, &booke_wdt_cb
, cpu
);
352 ret
= kvmppc_booke_watchdog_enable(cpu
);
355 /* TODO: Start the QEMU emulated watchdog if not running on KVM.
356 * Also start the QEMU emulated watchdog if KVM does not support
357 * emulated watchdog or somehow it is not enabled (supported but
358 * not enabled is though some bug and requires debugging :)).
362 qemu_add_vm_change_state_handler(cpu_state_change_handler
, cpu
);
364 qemu_register_reset(ppc_booke_timer_reset_handle
, cpu
);