2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
14 * Copyright IBM Corp. 2008
16 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 /* This file implements emulation of the 32-bit PCI controller found in some
20 * 4xx SoCs, such as the 440EP. */
23 #include "hw/ppc/ppc.h"
24 #include "hw/ppc/ppc4xx.h"
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pci_host.h"
27 #include "exec/address-spaces.h"
31 #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
33 #define DPRINTF(fmt, ...)
48 #define PPC4xx_PCI_HOST_BRIDGE(obj) \
49 OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
51 #define PPC4xx_PCI_NR_PMMS 3
52 #define PPC4xx_PCI_NR_PTMS 2
54 struct PPC4xxPCIState
{
55 PCIHostState parent_obj
;
57 struct PCIMasterMap pmm
[PPC4xx_PCI_NR_PMMS
];
58 struct PCITargetMap ptm
[PPC4xx_PCI_NR_PTMS
];
61 MemoryRegion container
;
64 typedef struct PPC4xxPCIState PPC4xxPCIState
;
66 #define PCIC0_CFGADDR 0x0
67 #define PCIC0_CFGDATA 0x4
69 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
71 #define PCIL0_PMM0LA 0x0
72 #define PCIL0_PMM0MA 0x4
73 #define PCIL0_PMM0PCILA 0x8
74 #define PCIL0_PMM0PCIHA 0xc
75 #define PCIL0_PMM1LA 0x10
76 #define PCIL0_PMM1MA 0x14
77 #define PCIL0_PMM1PCILA 0x18
78 #define PCIL0_PMM1PCIHA 0x1c
79 #define PCIL0_PMM2LA 0x20
80 #define PCIL0_PMM2MA 0x24
81 #define PCIL0_PMM2PCILA 0x28
82 #define PCIL0_PMM2PCIHA 0x2c
84 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
86 #define PCIL0_PTM1MS 0x30
87 #define PCIL0_PTM1LA 0x34
88 #define PCIL0_PTM2MS 0x38
89 #define PCIL0_PTM2LA 0x3c
90 #define PCI_REG_BASE 0x800000
91 #define PCI_REG_SIZE 0x40
93 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
95 static void ppc4xx_pci_reg_write4(void *opaque
, hwaddr offset
,
96 uint64_t value
, unsigned size
)
98 struct PPC4xxPCIState
*pci
= opaque
;
100 /* We ignore all target attempts at PCI configuration, effectively
101 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
105 pci
->pmm
[0].la
= value
;
108 pci
->pmm
[0].ma
= value
;
110 case PCIL0_PMM0PCIHA
:
111 pci
->pmm
[0].pciha
= value
;
113 case PCIL0_PMM0PCILA
:
114 pci
->pmm
[0].pcila
= value
;
118 pci
->pmm
[1].la
= value
;
121 pci
->pmm
[1].ma
= value
;
123 case PCIL0_PMM1PCIHA
:
124 pci
->pmm
[1].pciha
= value
;
126 case PCIL0_PMM1PCILA
:
127 pci
->pmm
[1].pcila
= value
;
131 pci
->pmm
[2].la
= value
;
134 pci
->pmm
[2].ma
= value
;
136 case PCIL0_PMM2PCIHA
:
137 pci
->pmm
[2].pciha
= value
;
139 case PCIL0_PMM2PCILA
:
140 pci
->pmm
[2].pcila
= value
;
144 pci
->ptm
[0].ms
= value
;
147 pci
->ptm
[0].la
= value
;
150 pci
->ptm
[1].ms
= value
;
153 pci
->ptm
[1].la
= value
;
157 printf("%s: unhandled PCI internal register 0x%lx\n", __func__
,
158 (unsigned long)offset
);
163 static uint64_t ppc4xx_pci_reg_read4(void *opaque
, hwaddr offset
,
166 struct PPC4xxPCIState
*pci
= opaque
;
171 value
= pci
->pmm
[0].la
;
174 value
= pci
->pmm
[0].ma
;
176 case PCIL0_PMM0PCIHA
:
177 value
= pci
->pmm
[0].pciha
;
179 case PCIL0_PMM0PCILA
:
180 value
= pci
->pmm
[0].pcila
;
184 value
= pci
->pmm
[1].la
;
187 value
= pci
->pmm
[1].ma
;
189 case PCIL0_PMM1PCIHA
:
190 value
= pci
->pmm
[1].pciha
;
192 case PCIL0_PMM1PCILA
:
193 value
= pci
->pmm
[1].pcila
;
197 value
= pci
->pmm
[2].la
;
200 value
= pci
->pmm
[2].ma
;
202 case PCIL0_PMM2PCIHA
:
203 value
= pci
->pmm
[2].pciha
;
205 case PCIL0_PMM2PCILA
:
206 value
= pci
->pmm
[2].pcila
;
210 value
= pci
->ptm
[0].ms
;
213 value
= pci
->ptm
[0].la
;
216 value
= pci
->ptm
[1].ms
;
219 value
= pci
->ptm
[1].la
;
223 printf("%s: invalid PCI internal register 0x%lx\n", __func__
,
224 (unsigned long)offset
);
231 static const MemoryRegionOps pci_reg_ops
= {
232 .read
= ppc4xx_pci_reg_read4
,
233 .write
= ppc4xx_pci_reg_write4
,
234 .endianness
= DEVICE_LITTLE_ENDIAN
,
237 static void ppc4xx_pci_reset(void *opaque
)
239 struct PPC4xxPCIState
*pci
= opaque
;
241 memset(pci
->pmm
, 0, sizeof(pci
->pmm
));
242 memset(pci
->ptm
, 0, sizeof(pci
->ptm
));
245 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
246 * may need further refactoring for other boards. */
247 static int ppc4xx_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
249 int slot
= pci_dev
->devfn
>> 3;
251 DPRINTF("%s: devfn %x irq %d -> %d\n", __func__
,
252 pci_dev
->devfn
, irq_num
, slot
);
257 static void ppc4xx_pci_set_irq(void *opaque
, int irq_num
, int level
)
259 qemu_irq
*pci_irqs
= opaque
;
261 DPRINTF("%s: PCI irq %d\n", __func__
, irq_num
);
263 fprintf(stderr
, "%s: PCI irq %d\n", __func__
, irq_num
);
266 qemu_set_irq(pci_irqs
[irq_num
], level
);
269 static const VMStateDescription vmstate_pci_master_map
= {
270 .name
= "pci_master_map",
272 .minimum_version_id
= 0,
273 .fields
= (VMStateField
[]) {
274 VMSTATE_UINT32(la
, struct PCIMasterMap
),
275 VMSTATE_UINT32(ma
, struct PCIMasterMap
),
276 VMSTATE_UINT32(pcila
, struct PCIMasterMap
),
277 VMSTATE_UINT32(pciha
, struct PCIMasterMap
),
278 VMSTATE_END_OF_LIST()
282 static const VMStateDescription vmstate_pci_target_map
= {
283 .name
= "pci_target_map",
285 .minimum_version_id
= 0,
286 .fields
= (VMStateField
[]) {
287 VMSTATE_UINT32(ms
, struct PCITargetMap
),
288 VMSTATE_UINT32(la
, struct PCITargetMap
),
289 VMSTATE_END_OF_LIST()
293 static const VMStateDescription vmstate_ppc4xx_pci
= {
294 .name
= "ppc4xx_pci",
296 .minimum_version_id
= 1,
297 .fields
= (VMStateField
[]) {
298 VMSTATE_STRUCT_ARRAY(pmm
, PPC4xxPCIState
, PPC4xx_PCI_NR_PMMS
, 1,
299 vmstate_pci_master_map
,
300 struct PCIMasterMap
),
301 VMSTATE_STRUCT_ARRAY(ptm
, PPC4xxPCIState
, PPC4xx_PCI_NR_PTMS
, 1,
302 vmstate_pci_target_map
,
303 struct PCITargetMap
),
304 VMSTATE_END_OF_LIST()
308 /* XXX Interrupt acknowledge cycles not supported. */
309 static int ppc4xx_pcihost_initfn(SysBusDevice
*dev
)
316 h
= PCI_HOST_BRIDGE(dev
);
317 s
= PPC4xx_PCI_HOST_BRIDGE(dev
);
319 for (i
= 0; i
< ARRAY_SIZE(s
->irq
); i
++) {
320 sysbus_init_irq(dev
, &s
->irq
[i
]);
323 b
= pci_register_bus(DEVICE(dev
), NULL
, ppc4xx_pci_set_irq
,
324 ppc4xx_pci_map_irq
, s
->irq
, get_system_memory(),
325 get_system_io(), 0, 4, TYPE_PCI_BUS
);
328 pci_create_simple(b
, 0, "ppc4xx-host-bridge");
330 /* XXX split into 2 memory regions, one for config space, one for regs */
331 memory_region_init(&s
->container
, OBJECT(s
), "pci-container", PCI_ALL_SIZE
);
332 memory_region_init_io(&h
->conf_mem
, OBJECT(s
), &pci_host_conf_le_ops
, h
,
334 memory_region_init_io(&h
->data_mem
, OBJECT(s
), &pci_host_data_le_ops
, h
,
336 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pci_reg_ops
, s
,
337 "pci.reg", PCI_REG_SIZE
);
338 memory_region_add_subregion(&s
->container
, PCIC0_CFGADDR
, &h
->conf_mem
);
339 memory_region_add_subregion(&s
->container
, PCIC0_CFGDATA
, &h
->data_mem
);
340 memory_region_add_subregion(&s
->container
, PCI_REG_BASE
, &s
->iomem
);
341 sysbus_init_mmio(dev
, &s
->container
);
342 qemu_register_reset(ppc4xx_pci_reset
, s
);
347 static void ppc4xx_host_bridge_class_init(ObjectClass
*klass
, void *data
)
349 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
350 DeviceClass
*dc
= DEVICE_CLASS(klass
);
352 dc
->desc
= "Host bridge";
353 k
->vendor_id
= PCI_VENDOR_ID_IBM
;
354 k
->device_id
= PCI_DEVICE_ID_IBM_440GX
;
355 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
357 * PCI-facing part of the host bridge, not usable without the
358 * host-facing part, which can't be device_add'ed, yet.
360 dc
->cannot_instantiate_with_device_add_yet
= true;
363 static const TypeInfo ppc4xx_host_bridge_info
= {
364 .name
= "ppc4xx-host-bridge",
365 .parent
= TYPE_PCI_DEVICE
,
366 .instance_size
= sizeof(PCIDevice
),
367 .class_init
= ppc4xx_host_bridge_class_init
,
370 static void ppc4xx_pcihost_class_init(ObjectClass
*klass
, void *data
)
372 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
373 DeviceClass
*dc
= DEVICE_CLASS(klass
);
375 k
->init
= ppc4xx_pcihost_initfn
;
376 dc
->vmsd
= &vmstate_ppc4xx_pci
;
379 static const TypeInfo ppc4xx_pcihost_info
= {
380 .name
= TYPE_PPC4xx_PCI_HOST_BRIDGE
,
381 .parent
= TYPE_PCI_HOST_BRIDGE
,
382 .instance_size
= sizeof(PPC4xxPCIState
),
383 .class_init
= ppc4xx_pcihost_class_init
,
386 static void ppc4xx_pci_register_types(void)
388 type_register_static(&ppc4xx_pcihost_info
);
389 type_register_static(&ppc4xx_host_bridge_info
);
392 type_init(ppc4xx_pci_register_types
)