4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline int get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
111 switch (s
->mmu_idx
) {
112 case ARMMMUIdx_S12NSE1
:
113 useridx
= ARMMMUIdx_S12NSE0
;
115 case ARMMMUIdx_S1SE1
:
116 useridx
= ARMMMUIdx_S1SE0
;
119 g_assert_not_reached();
121 useridx
= s
->mmu_idx
;
124 return arm_to_core_mmu_idx(useridx
);
127 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
128 fprintf_function cpu_fprintf
, int flags
)
130 ARMCPU
*cpu
= ARM_CPU(cs
);
131 CPUARMState
*env
= &cpu
->env
;
132 uint32_t psr
= pstate_read(env
);
134 int el
= arm_current_el(env
);
135 const char *ns_status
;
137 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
138 env
->pc
, env
->xregs
[31]);
139 for (i
= 0; i
< 31; i
++) {
140 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
142 cpu_fprintf(f
, "\n");
148 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
149 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
154 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
156 psr
& PSTATE_N
? 'N' : '-',
157 psr
& PSTATE_Z
? 'Z' : '-',
158 psr
& PSTATE_C
? 'C' : '-',
159 psr
& PSTATE_V
? 'V' : '-',
162 psr
& PSTATE_SP
? 'h' : 't');
164 if (flags
& CPU_DUMP_FPU
) {
166 for (i
= 0; i
< numvfpregs
; i
+= 2) {
167 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
168 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
169 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
171 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
172 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
173 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
176 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
177 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
181 void gen_a64_set_pc_im(uint64_t val
)
183 tcg_gen_movi_i64(cpu_pc
, val
);
186 /* Load the PC from a generic TCG variable.
188 * If address tagging is enabled via the TCR TBI bits, then loading
189 * an address into the PC will clear out any tag in the it:
190 * + for EL2 and EL3 there is only one TBI bit, and if it is set
191 * then the address is zero-extended, clearing bits [63:56]
192 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
193 * and TBI1 controls addressses with bit 55 == 1.
194 * If the appropriate TBI bit is set for the address then
195 * the address is sign-extended from bit 55 into bits [63:56]
197 * We can avoid doing this for relative-branches, because the
198 * PC + offset can never overflow into the tag bits (assuming
199 * that virtual addresses are less than 56 bits wide, as they
200 * are currently), but we must handle it for branch-to-register.
202 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
205 if (s
->current_el
<= 1) {
206 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
207 * examine bit 55 of address, can just generate code.
208 * If mixed, then test via generated code
210 if (s
->tbi0
&& s
->tbi1
) {
211 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
212 /* Both bits set, sign extension from bit 55 into [63:56] will
215 tcg_gen_shli_i64(tmp_reg
, src
, 8);
216 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
217 tcg_temp_free_i64(tmp_reg
);
218 } else if (!s
->tbi0
&& !s
->tbi1
) {
219 /* Neither bit set, just load it as-is */
220 tcg_gen_mov_i64(cpu_pc
, src
);
222 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
223 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
224 TCGv_i64 tcg_zero
= tcg_const_i64(0);
226 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
229 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
230 tcg_gen_andi_i64(tcg_tmpval
, src
,
231 0x00FFFFFFFFFFFFFFull
);
232 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
236 tcg_gen_ori_i64(tcg_tmpval
, src
,
237 0xFF00000000000000ull
);
238 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
241 tcg_temp_free_i64(tcg_zero
);
242 tcg_temp_free_i64(tcg_bit55
);
243 tcg_temp_free_i64(tcg_tmpval
);
245 } else { /* EL > 1 */
247 /* Force tag byte to all zero */
248 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
250 /* Load unmodified address */
251 tcg_gen_mov_i64(cpu_pc
, src
);
256 typedef struct DisasCompare64
{
261 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
265 arm_test_cc(&c32
, cc
);
267 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
268 * properly. The NE/EQ comparisons are also fine with this choice. */
269 c64
->cond
= c32
.cond
;
270 c64
->value
= tcg_temp_new_i64();
271 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
276 static void a64_free_cc(DisasCompare64
*c64
)
278 tcg_temp_free_i64(c64
->value
);
281 static void gen_exception_internal(int excp
)
283 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
285 assert(excp_is_internal(excp
));
286 gen_helper_exception_internal(cpu_env
, tcg_excp
);
287 tcg_temp_free_i32(tcg_excp
);
290 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
292 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
293 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
294 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
296 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
298 tcg_temp_free_i32(tcg_el
);
299 tcg_temp_free_i32(tcg_syn
);
300 tcg_temp_free_i32(tcg_excp
);
303 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
305 gen_a64_set_pc_im(s
->pc
- offset
);
306 gen_exception_internal(excp
);
307 s
->is_jmp
= DISAS_EXC
;
310 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
311 uint32_t syndrome
, uint32_t target_el
)
313 gen_a64_set_pc_im(s
->pc
- offset
);
314 gen_exception(excp
, syndrome
, target_el
);
315 s
->is_jmp
= DISAS_EXC
;
318 static void gen_ss_advance(DisasContext
*s
)
320 /* If the singlestep state is Active-not-pending, advance to
325 gen_helper_clear_pstate_ss(cpu_env
);
329 static void gen_step_complete_exception(DisasContext
*s
)
331 /* We just completed step of an insn. Move from Active-not-pending
332 * to Active-pending, and then also take the swstep exception.
333 * This corresponds to making the (IMPDEF) choice to prioritize
334 * swstep exceptions over asynchronous exceptions taken to an exception
335 * level where debug is disabled. This choice has the advantage that
336 * we do not need to maintain internal state corresponding to the
337 * ISV/EX syndrome bits between completion of the step and generation
338 * of the exception, and our syndrome information is always correct.
341 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
342 default_exception_el(s
));
343 s
->is_jmp
= DISAS_EXC
;
346 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
348 /* No direct tb linking with singlestep (either QEMU's or the ARM
349 * debug architecture kind) or deterministic io
351 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
355 #ifndef CONFIG_USER_ONLY
356 /* Only link tbs from inside the same guest page */
357 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
365 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
367 TranslationBlock
*tb
;
370 if (use_goto_tb(s
, n
, dest
)) {
372 gen_a64_set_pc_im(dest
);
373 tcg_gen_exit_tb((intptr_t)tb
+ n
);
374 s
->is_jmp
= DISAS_TB_JUMP
;
376 gen_a64_set_pc_im(dest
);
378 gen_step_complete_exception(s
);
379 } else if (s
->singlestep_enabled
) {
380 gen_exception_internal(EXCP_DEBUG
);
383 s
->is_jmp
= DISAS_TB_JUMP
;
388 static void unallocated_encoding(DisasContext
*s
)
390 /* Unallocated and reserved encodings are uncategorized */
391 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
392 default_exception_el(s
));
395 #define unsupported_encoding(s, insn) \
397 qemu_log_mask(LOG_UNIMP, \
398 "%s:%d: unsupported instruction encoding 0x%08x " \
399 "at pc=%016" PRIx64 "\n", \
400 __FILE__, __LINE__, insn, s->pc - 4); \
401 unallocated_encoding(s); \
404 static void init_tmp_a64_array(DisasContext
*s
)
406 #ifdef CONFIG_DEBUG_TCG
408 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
409 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
412 s
->tmp_a64_count
= 0;
415 static void free_tmp_a64(DisasContext
*s
)
418 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
419 tcg_temp_free_i64(s
->tmp_a64
[i
]);
421 init_tmp_a64_array(s
);
424 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
426 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
427 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
430 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
432 TCGv_i64 t
= new_tmp_a64(s
);
433 tcg_gen_movi_i64(t
, 0);
438 * Register access functions
440 * These functions are used for directly accessing a register in where
441 * changes to the final register value are likely to be made. If you
442 * need to use a register for temporary calculation (e.g. index type
443 * operations) use the read_* form.
445 * B1.2.1 Register mappings
447 * In instruction register encoding 31 can refer to ZR (zero register) or
448 * the SP (stack pointer) depending on context. In QEMU's case we map SP
449 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
450 * This is the point of the _sp forms.
452 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
455 return new_tmp_a64_zero(s
);
461 /* register access for when 31 == SP */
462 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
467 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
468 * representing the register contents. This TCGv is an auto-freed
469 * temporary so it need not be explicitly freed, and may be modified.
471 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
473 TCGv_i64 v
= new_tmp_a64(s
);
476 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
478 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
481 tcg_gen_movi_i64(v
, 0);
486 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
488 TCGv_i64 v
= new_tmp_a64(s
);
490 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
492 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
497 /* We should have at some point before trying to access an FP register
498 * done the necessary access check, so assert that
499 * (a) we did the check and
500 * (b) we didn't then just plough ahead anyway if it failed.
501 * Print the instruction pattern in the abort message so we can figure
502 * out what we need to fix if a user encounters this problem in the wild.
504 static inline void assert_fp_access_checked(DisasContext
*s
)
506 #ifdef CONFIG_DEBUG_TCG
507 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
508 fprintf(stderr
, "target-arm: FP access check missing for "
509 "instruction 0x%08x\n", s
->insn
);
515 /* Return the offset into CPUARMState of an element of specified
516 * size, 'element' places in from the least significant end of
517 * the FP/vector register Qn.
519 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
520 int element
, TCGMemOp size
)
523 #ifdef HOST_WORDS_BIGENDIAN
524 /* This is complicated slightly because vfp.regs[2n] is
525 * still the low half and vfp.regs[2n+1] the high half
526 * of the 128 bit vector, even on big endian systems.
527 * Calculate the offset assuming a fully bigendian 128 bits,
528 * then XOR to account for the order of the two 64 bit halves.
530 offs
+= (16 - ((element
+ 1) * (1 << size
)));
533 offs
+= element
* (1 << size
);
535 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
536 assert_fp_access_checked(s
);
540 /* Return the offset into CPUARMState of a slice (from
541 * the least significant end) of FP register Qn (ie
543 * (Note that this is not the same mapping as for A32; see cpu.h)
545 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
547 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
548 #ifdef HOST_WORDS_BIGENDIAN
549 offs
+= (8 - (1 << size
));
551 assert_fp_access_checked(s
);
555 /* Offset of the high half of the 128 bit vector Qn */
556 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
558 assert_fp_access_checked(s
);
559 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
562 /* Convenience accessors for reading and writing single and double
563 * FP registers. Writing clears the upper parts of the associated
564 * 128 bit vector register, as required by the architecture.
565 * Note that unlike the GP register accessors, the values returned
566 * by the read functions must be manually freed.
568 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
570 TCGv_i64 v
= tcg_temp_new_i64();
572 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
576 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
578 TCGv_i32 v
= tcg_temp_new_i32();
580 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
584 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
586 TCGv_i64 tcg_zero
= tcg_const_i64(0);
588 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
589 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
590 tcg_temp_free_i64(tcg_zero
);
593 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
595 TCGv_i64 tmp
= tcg_temp_new_i64();
597 tcg_gen_extu_i32_i64(tmp
, v
);
598 write_fp_dreg(s
, reg
, tmp
);
599 tcg_temp_free_i64(tmp
);
602 static TCGv_ptr
get_fpstatus_ptr(void)
604 TCGv_ptr statusptr
= tcg_temp_new_ptr();
607 /* In A64 all instructions (both FP and Neon) use the FPCR;
608 * there is no equivalent of the A32 Neon "standard FPSCR value"
609 * and all operations use vfp.fp_status.
611 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
612 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
616 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
617 * than the 32 bit equivalent.
619 static inline void gen_set_NZ64(TCGv_i64 result
)
621 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
622 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
625 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
626 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
629 gen_set_NZ64(result
);
631 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
632 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
634 tcg_gen_movi_i32(cpu_CF
, 0);
635 tcg_gen_movi_i32(cpu_VF
, 0);
638 /* dest = T0 + T1; compute C, N, V and Z flags */
639 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
642 TCGv_i64 result
, flag
, tmp
;
643 result
= tcg_temp_new_i64();
644 flag
= tcg_temp_new_i64();
645 tmp
= tcg_temp_new_i64();
647 tcg_gen_movi_i64(tmp
, 0);
648 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
650 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
652 gen_set_NZ64(result
);
654 tcg_gen_xor_i64(flag
, result
, t0
);
655 tcg_gen_xor_i64(tmp
, t0
, t1
);
656 tcg_gen_andc_i64(flag
, flag
, tmp
);
657 tcg_temp_free_i64(tmp
);
658 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
660 tcg_gen_mov_i64(dest
, result
);
661 tcg_temp_free_i64(result
);
662 tcg_temp_free_i64(flag
);
664 /* 32 bit arithmetic */
665 TCGv_i32 t0_32
= tcg_temp_new_i32();
666 TCGv_i32 t1_32
= tcg_temp_new_i32();
667 TCGv_i32 tmp
= tcg_temp_new_i32();
669 tcg_gen_movi_i32(tmp
, 0);
670 tcg_gen_extrl_i64_i32(t0_32
, t0
);
671 tcg_gen_extrl_i64_i32(t1_32
, t1
);
672 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
673 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
674 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
675 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
676 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
677 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
679 tcg_temp_free_i32(tmp
);
680 tcg_temp_free_i32(t0_32
);
681 tcg_temp_free_i32(t1_32
);
685 /* dest = T0 - T1; compute C, N, V and Z flags */
686 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
689 /* 64 bit arithmetic */
690 TCGv_i64 result
, flag
, tmp
;
692 result
= tcg_temp_new_i64();
693 flag
= tcg_temp_new_i64();
694 tcg_gen_sub_i64(result
, t0
, t1
);
696 gen_set_NZ64(result
);
698 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
699 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
701 tcg_gen_xor_i64(flag
, result
, t0
);
702 tmp
= tcg_temp_new_i64();
703 tcg_gen_xor_i64(tmp
, t0
, t1
);
704 tcg_gen_and_i64(flag
, flag
, tmp
);
705 tcg_temp_free_i64(tmp
);
706 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
707 tcg_gen_mov_i64(dest
, result
);
708 tcg_temp_free_i64(flag
);
709 tcg_temp_free_i64(result
);
711 /* 32 bit arithmetic */
712 TCGv_i32 t0_32
= tcg_temp_new_i32();
713 TCGv_i32 t1_32
= tcg_temp_new_i32();
716 tcg_gen_extrl_i64_i32(t0_32
, t0
);
717 tcg_gen_extrl_i64_i32(t1_32
, t1
);
718 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
719 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
720 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
721 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
722 tmp
= tcg_temp_new_i32();
723 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
724 tcg_temp_free_i32(t0_32
);
725 tcg_temp_free_i32(t1_32
);
726 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
727 tcg_temp_free_i32(tmp
);
728 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
732 /* dest = T0 + T1 + CF; do not compute flags. */
733 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
735 TCGv_i64 flag
= tcg_temp_new_i64();
736 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
737 tcg_gen_add_i64(dest
, t0
, t1
);
738 tcg_gen_add_i64(dest
, dest
, flag
);
739 tcg_temp_free_i64(flag
);
742 tcg_gen_ext32u_i64(dest
, dest
);
746 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
747 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
750 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
751 result
= tcg_temp_new_i64();
752 cf_64
= tcg_temp_new_i64();
753 vf_64
= tcg_temp_new_i64();
754 tmp
= tcg_const_i64(0);
756 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
757 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
758 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
759 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
760 gen_set_NZ64(result
);
762 tcg_gen_xor_i64(vf_64
, result
, t0
);
763 tcg_gen_xor_i64(tmp
, t0
, t1
);
764 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
765 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
767 tcg_gen_mov_i64(dest
, result
);
769 tcg_temp_free_i64(tmp
);
770 tcg_temp_free_i64(vf_64
);
771 tcg_temp_free_i64(cf_64
);
772 tcg_temp_free_i64(result
);
774 TCGv_i32 t0_32
, t1_32
, tmp
;
775 t0_32
= tcg_temp_new_i32();
776 t1_32
= tcg_temp_new_i32();
777 tmp
= tcg_const_i32(0);
779 tcg_gen_extrl_i64_i32(t0_32
, t0
);
780 tcg_gen_extrl_i64_i32(t1_32
, t1
);
781 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
782 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
784 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
785 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
786 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
787 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
788 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
790 tcg_temp_free_i32(tmp
);
791 tcg_temp_free_i32(t1_32
);
792 tcg_temp_free_i32(t0_32
);
797 * Load/Store generators
801 * Store from GPR register to memory.
803 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
804 TCGv_i64 tcg_addr
, int size
, int memidx
,
806 unsigned int iss_srt
,
807 bool iss_sf
, bool iss_ar
)
810 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
815 syn
= syn_data_abort_with_iss(0,
821 0, 0, 0, 0, 0, false);
822 disas_set_insn_syndrome(s
, syn
);
826 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
827 TCGv_i64 tcg_addr
, int size
,
829 unsigned int iss_srt
,
830 bool iss_sf
, bool iss_ar
)
832 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
833 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
837 * Load from memory to GPR register
839 static void do_gpr_ld_memidx(DisasContext
*s
,
840 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
841 int size
, bool is_signed
,
842 bool extend
, int memidx
,
843 bool iss_valid
, unsigned int iss_srt
,
844 bool iss_sf
, bool iss_ar
)
846 TCGMemOp memop
= s
->be_data
+ size
;
854 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
856 if (extend
&& is_signed
) {
858 tcg_gen_ext32u_i64(dest
, dest
);
864 syn
= syn_data_abort_with_iss(0,
870 0, 0, 0, 0, 0, false);
871 disas_set_insn_syndrome(s
, syn
);
875 static void do_gpr_ld(DisasContext
*s
,
876 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
877 int size
, bool is_signed
, bool extend
,
878 bool iss_valid
, unsigned int iss_srt
,
879 bool iss_sf
, bool iss_ar
)
881 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
883 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
887 * Store from FP register to memory
889 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
891 /* This writes the bottom N bits of a 128 bit wide vector to memory */
892 TCGv_i64 tmp
= tcg_temp_new_i64();
893 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
895 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
898 bool be
= s
->be_data
== MO_BE
;
899 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
901 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
902 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
904 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
905 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
907 tcg_temp_free_i64(tcg_hiaddr
);
910 tcg_temp_free_i64(tmp
);
914 * Load from memory to FP register
916 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
918 /* This always zero-extends and writes to a full 128 bit wide vector */
919 TCGv_i64 tmplo
= tcg_temp_new_i64();
923 TCGMemOp memop
= s
->be_data
+ size
;
924 tmphi
= tcg_const_i64(0);
925 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
927 bool be
= s
->be_data
== MO_BE
;
930 tmphi
= tcg_temp_new_i64();
931 tcg_hiaddr
= tcg_temp_new_i64();
933 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
934 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
936 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
938 tcg_temp_free_i64(tcg_hiaddr
);
941 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
942 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
944 tcg_temp_free_i64(tmplo
);
945 tcg_temp_free_i64(tmphi
);
949 * Vector load/store helpers.
951 * The principal difference between this and a FP load is that we don't
952 * zero extend as we are filling a partial chunk of the vector register.
953 * These functions don't support 128 bit loads/stores, which would be
954 * normal load/store operations.
956 * The _i32 versions are useful when operating on 32 bit quantities
957 * (eg for floating point single or using Neon helper functions).
960 /* Get value of an element within a vector register */
961 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
962 int element
, TCGMemOp memop
)
964 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
967 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
979 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
982 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
986 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
989 g_assert_not_reached();
993 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
994 int element
, TCGMemOp memop
)
996 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
999 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1005 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1008 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1015 g_assert_not_reached();
1019 /* Set value of an element within a vector register */
1020 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1021 int element
, TCGMemOp memop
)
1023 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1026 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1032 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1035 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1038 g_assert_not_reached();
1042 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1043 int destidx
, int element
, TCGMemOp memop
)
1045 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1048 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1051 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1054 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1057 g_assert_not_reached();
1061 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1062 * vector ops all need to do this).
1064 static void clear_vec_high(DisasContext
*s
, int rd
)
1066 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1068 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1069 tcg_temp_free_i64(tcg_zero
);
1072 /* Store from vector register to memory */
1073 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1074 TCGv_i64 tcg_addr
, int size
)
1076 TCGMemOp memop
= s
->be_data
+ size
;
1077 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1079 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1080 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1082 tcg_temp_free_i64(tcg_tmp
);
1085 /* Load from memory to vector register */
1086 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1087 TCGv_i64 tcg_addr
, int size
)
1089 TCGMemOp memop
= s
->be_data
+ size
;
1090 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1092 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1093 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1095 tcg_temp_free_i64(tcg_tmp
);
1098 /* Check that FP/Neon access is enabled. If it is, return
1099 * true. If not, emit code to generate an appropriate exception,
1100 * and return false; the caller should not emit any code for
1101 * the instruction. Note that this check must happen after all
1102 * unallocated-encoding checks (otherwise the syndrome information
1103 * for the resulting exception will be incorrect).
1105 static inline bool fp_access_check(DisasContext
*s
)
1107 assert(!s
->fp_access_checked
);
1108 s
->fp_access_checked
= true;
1110 if (!s
->fp_excp_el
) {
1114 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1120 * This utility function is for doing register extension with an
1121 * optional shift. You will likely want to pass a temporary for the
1122 * destination register. See DecodeRegExtend() in the ARM ARM.
1124 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1125 int option
, unsigned int shift
)
1127 int extsize
= extract32(option
, 0, 2);
1128 bool is_signed
= extract32(option
, 2, 1);
1133 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1139 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1142 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1154 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1157 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1163 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1167 static inline void gen_check_sp_alignment(DisasContext
*s
)
1169 /* The AArch64 architecture mandates that (if enabled via PSTATE
1170 * or SCTLR bits) there is a check that SP is 16-aligned on every
1171 * SP-relative load or store (with an exception generated if it is not).
1172 * In line with general QEMU practice regarding misaligned accesses,
1173 * we omit these checks for the sake of guest program performance.
1174 * This function is provided as a hook so we can more easily add these
1175 * checks in future (possibly as a "favour catching guest program bugs
1176 * over speed" user selectable option).
1181 * This provides a simple table based table lookup decoder. It is
1182 * intended to be used when the relevant bits for decode are too
1183 * awkwardly placed and switch/if based logic would be confusing and
1184 * deeply nested. Since it's a linear search through the table, tables
1185 * should be kept small.
1187 * It returns the first handler where insn & mask == pattern, or
1188 * NULL if there is no match.
1189 * The table is terminated by an empty mask (i.e. 0)
1191 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1194 const AArch64DecodeTable
*tptr
= table
;
1196 while (tptr
->mask
) {
1197 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1198 return tptr
->disas_fn
;
1206 * the instruction disassembly implemented here matches
1207 * the instruction encoding classifications in chapter 3 (C3)
1208 * of the ARM Architecture Reference Manual (DDI0487A_a)
1211 /* C3.2.7 Unconditional branch (immediate)
1213 * +----+-----------+-------------------------------------+
1214 * | op | 0 0 1 0 1 | imm26 |
1215 * +----+-----------+-------------------------------------+
1217 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1219 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1221 if (insn
& (1U << 31)) {
1222 /* C5.6.26 BL Branch with link */
1223 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1226 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1227 gen_goto_tb(s
, 0, addr
);
1230 /* C3.2.1 Compare & branch (immediate)
1231 * 31 30 25 24 23 5 4 0
1232 * +----+-------------+----+---------------------+--------+
1233 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1234 * +----+-------------+----+---------------------+--------+
1236 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1238 unsigned int sf
, op
, rt
;
1240 TCGLabel
*label_match
;
1243 sf
= extract32(insn
, 31, 1);
1244 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1245 rt
= extract32(insn
, 0, 5);
1246 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1248 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1249 label_match
= gen_new_label();
1251 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1252 tcg_cmp
, 0, label_match
);
1254 gen_goto_tb(s
, 0, s
->pc
);
1255 gen_set_label(label_match
);
1256 gen_goto_tb(s
, 1, addr
);
1259 /* C3.2.5 Test & branch (immediate)
1260 * 31 30 25 24 23 19 18 5 4 0
1261 * +----+-------------+----+-------+-------------+------+
1262 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1263 * +----+-------------+----+-------+-------------+------+
1265 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1267 unsigned int bit_pos
, op
, rt
;
1269 TCGLabel
*label_match
;
1272 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1273 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1274 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1275 rt
= extract32(insn
, 0, 5);
1277 tcg_cmp
= tcg_temp_new_i64();
1278 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1279 label_match
= gen_new_label();
1280 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1281 tcg_cmp
, 0, label_match
);
1282 tcg_temp_free_i64(tcg_cmp
);
1283 gen_goto_tb(s
, 0, s
->pc
);
1284 gen_set_label(label_match
);
1285 gen_goto_tb(s
, 1, addr
);
1288 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1289 * 31 25 24 23 5 4 3 0
1290 * +---------------+----+---------------------+----+------+
1291 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1292 * +---------------+----+---------------------+----+------+
1294 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1299 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1300 unallocated_encoding(s
);
1303 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1304 cond
= extract32(insn
, 0, 4);
1307 /* genuinely conditional branches */
1308 TCGLabel
*label_match
= gen_new_label();
1309 arm_gen_test_cc(cond
, label_match
);
1310 gen_goto_tb(s
, 0, s
->pc
);
1311 gen_set_label(label_match
);
1312 gen_goto_tb(s
, 1, addr
);
1314 /* 0xe and 0xf are both "always" conditions */
1315 gen_goto_tb(s
, 0, addr
);
1320 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1321 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1323 unsigned int selector
= crm
<< 3 | op2
;
1326 unallocated_encoding(s
);
1334 s
->is_jmp
= DISAS_WFI
;
1337 if (!parallel_cpus
) {
1338 s
->is_jmp
= DISAS_YIELD
;
1342 if (!parallel_cpus
) {
1343 s
->is_jmp
= DISAS_WFE
;
1348 /* we treat all as NOP at least for now */
1351 /* default specified as NOP equivalent */
1356 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1358 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1361 /* CLREX, DSB, DMB, ISB */
1362 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1363 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1368 unallocated_encoding(s
);
1379 case 1: /* MBReqTypes_Reads */
1380 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1382 case 2: /* MBReqTypes_Writes */
1383 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1385 default: /* MBReqTypes_All */
1386 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1392 /* We need to break the TB after this insn to execute
1393 * a self-modified code correctly and also to take
1394 * any pending interrupts immediately.
1396 s
->is_jmp
= DISAS_UPDATE
;
1399 unallocated_encoding(s
);
1404 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1405 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1406 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1408 int op
= op1
<< 3 | op2
;
1410 case 0x05: /* SPSel */
1411 if (s
->current_el
== 0) {
1412 unallocated_encoding(s
);
1416 case 0x1e: /* DAIFSet */
1417 case 0x1f: /* DAIFClear */
1419 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1420 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1421 gen_a64_set_pc_im(s
->pc
- 4);
1422 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1423 tcg_temp_free_i32(tcg_imm
);
1424 tcg_temp_free_i32(tcg_op
);
1425 s
->is_jmp
= DISAS_UPDATE
;
1429 unallocated_encoding(s
);
1434 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1436 TCGv_i32 tmp
= tcg_temp_new_i32();
1437 TCGv_i32 nzcv
= tcg_temp_new_i32();
1439 /* build bit 31, N */
1440 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1441 /* build bit 30, Z */
1442 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1443 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1444 /* build bit 29, C */
1445 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1446 /* build bit 28, V */
1447 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1448 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1449 /* generate result */
1450 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1452 tcg_temp_free_i32(nzcv
);
1453 tcg_temp_free_i32(tmp
);
1456 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1459 TCGv_i32 nzcv
= tcg_temp_new_i32();
1461 /* take NZCV from R[t] */
1462 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1465 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1467 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1468 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1470 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1471 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1473 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1474 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1475 tcg_temp_free_i32(nzcv
);
1478 /* C5.6.129 MRS - move from system register
1479 * C5.6.131 MSR (register) - move to system register
1482 * These are all essentially the same insn in 'read' and 'write'
1483 * versions, with varying op0 fields.
1485 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1486 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1487 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1489 const ARMCPRegInfo
*ri
;
1492 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1493 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1494 crn
, crm
, op0
, op1
, op2
));
1497 /* Unknown register; this might be a guest error or a QEMU
1498 * unimplemented feature.
1500 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1501 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1502 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1503 unallocated_encoding(s
);
1507 /* Check access permissions */
1508 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1509 unallocated_encoding(s
);
1514 /* Emit code to perform further access permissions checks at
1515 * runtime; this may result in an exception.
1518 TCGv_i32 tcg_syn
, tcg_isread
;
1521 gen_a64_set_pc_im(s
->pc
- 4);
1522 tmpptr
= tcg_const_ptr(ri
);
1523 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1524 tcg_syn
= tcg_const_i32(syndrome
);
1525 tcg_isread
= tcg_const_i32(isread
);
1526 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1527 tcg_temp_free_ptr(tmpptr
);
1528 tcg_temp_free_i32(tcg_syn
);
1529 tcg_temp_free_i32(tcg_isread
);
1532 /* Handle special cases first */
1533 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1537 tcg_rt
= cpu_reg(s
, rt
);
1539 gen_get_nzcv(tcg_rt
);
1541 gen_set_nzcv(tcg_rt
);
1544 case ARM_CP_CURRENTEL
:
1545 /* Reads as current EL value from pstate, which is
1546 * guaranteed to be constant by the tb flags.
1548 tcg_rt
= cpu_reg(s
, rt
);
1549 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1552 /* Writes clear the aligned block of memory which rt points into. */
1553 tcg_rt
= cpu_reg(s
, rt
);
1554 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1560 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1564 tcg_rt
= cpu_reg(s
, rt
);
1567 if (ri
->type
& ARM_CP_CONST
) {
1568 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1569 } else if (ri
->readfn
) {
1571 tmpptr
= tcg_const_ptr(ri
);
1572 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1573 tcg_temp_free_ptr(tmpptr
);
1575 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1578 if (ri
->type
& ARM_CP_CONST
) {
1579 /* If not forbidden by access permissions, treat as WI */
1581 } else if (ri
->writefn
) {
1583 tmpptr
= tcg_const_ptr(ri
);
1584 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1585 tcg_temp_free_ptr(tmpptr
);
1587 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1591 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1592 /* I/O operations must end the TB here (whether read or write) */
1594 s
->is_jmp
= DISAS_UPDATE
;
1595 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1596 /* We default to ending the TB on a coprocessor register write,
1597 * but allow this to be suppressed by the register definition
1598 * (usually only necessary to work around guest bugs).
1600 s
->is_jmp
= DISAS_UPDATE
;
1605 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1606 * +---------------------+---+-----+-----+-------+-------+-----+------+
1607 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1608 * +---------------------+---+-----+-----+-------+-------+-----+------+
1610 static void disas_system(DisasContext
*s
, uint32_t insn
)
1612 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1613 l
= extract32(insn
, 21, 1);
1614 op0
= extract32(insn
, 19, 2);
1615 op1
= extract32(insn
, 16, 3);
1616 crn
= extract32(insn
, 12, 4);
1617 crm
= extract32(insn
, 8, 4);
1618 op2
= extract32(insn
, 5, 3);
1619 rt
= extract32(insn
, 0, 5);
1622 if (l
|| rt
!= 31) {
1623 unallocated_encoding(s
);
1627 case 2: /* C5.6.68 HINT */
1628 handle_hint(s
, insn
, op1
, op2
, crm
);
1630 case 3: /* CLREX, DSB, DMB, ISB */
1631 handle_sync(s
, insn
, op1
, op2
, crm
);
1633 case 4: /* C5.6.130 MSR (immediate) */
1634 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1637 unallocated_encoding(s
);
1642 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1645 /* C3.2.3 Exception generation
1647 * 31 24 23 21 20 5 4 2 1 0
1648 * +-----------------+-----+------------------------+-----+----+
1649 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1650 * +-----------------------+------------------------+----------+
1652 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1654 int opc
= extract32(insn
, 21, 3);
1655 int op2_ll
= extract32(insn
, 0, 5);
1656 int imm16
= extract32(insn
, 5, 16);
1661 /* For SVC, HVC and SMC we advance the single-step state
1662 * machine before taking the exception. This is architecturally
1663 * mandated, to ensure that single-stepping a system call
1664 * instruction works properly.
1669 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1670 default_exception_el(s
));
1673 if (s
->current_el
== 0) {
1674 unallocated_encoding(s
);
1677 /* The pre HVC helper handles cases when HVC gets trapped
1678 * as an undefined insn by runtime configuration.
1680 gen_a64_set_pc_im(s
->pc
- 4);
1681 gen_helper_pre_hvc(cpu_env
);
1683 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1686 if (s
->current_el
== 0) {
1687 unallocated_encoding(s
);
1690 gen_a64_set_pc_im(s
->pc
- 4);
1691 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1692 gen_helper_pre_smc(cpu_env
, tmp
);
1693 tcg_temp_free_i32(tmp
);
1695 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1698 unallocated_encoding(s
);
1704 unallocated_encoding(s
);
1708 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1709 default_exception_el(s
));
1713 unallocated_encoding(s
);
1716 /* HLT. This has two purposes.
1717 * Architecturally, it is an external halting debug instruction.
1718 * Since QEMU doesn't implement external debug, we treat this as
1719 * it is required for halting debug disabled: it will UNDEF.
1720 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1722 if (semihosting_enabled() && imm16
== 0xf000) {
1723 #ifndef CONFIG_USER_ONLY
1724 /* In system mode, don't allow userspace access to semihosting,
1725 * to provide some semblance of security (and for consistency
1726 * with our 32-bit semihosting).
1728 if (s
->current_el
== 0) {
1729 unsupported_encoding(s
, insn
);
1733 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1735 unsupported_encoding(s
, insn
);
1739 if (op2_ll
< 1 || op2_ll
> 3) {
1740 unallocated_encoding(s
);
1743 /* DCPS1, DCPS2, DCPS3 */
1744 unsupported_encoding(s
, insn
);
1747 unallocated_encoding(s
);
1752 /* C3.2.7 Unconditional branch (register)
1753 * 31 25 24 21 20 16 15 10 9 5 4 0
1754 * +---------------+-------+-------+-------+------+-------+
1755 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1756 * +---------------+-------+-------+-------+------+-------+
1758 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1760 unsigned int opc
, op2
, op3
, rn
, op4
;
1762 opc
= extract32(insn
, 21, 4);
1763 op2
= extract32(insn
, 16, 5);
1764 op3
= extract32(insn
, 10, 6);
1765 rn
= extract32(insn
, 5, 5);
1766 op4
= extract32(insn
, 0, 5);
1768 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1769 unallocated_encoding(s
);
1777 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1778 /* BLR also needs to load return address */
1780 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1784 if (s
->current_el
== 0) {
1785 unallocated_encoding(s
);
1788 gen_helper_exception_return(cpu_env
);
1789 s
->is_jmp
= DISAS_JUMP
;
1793 unallocated_encoding(s
);
1795 unsupported_encoding(s
, insn
);
1799 unallocated_encoding(s
);
1803 s
->is_jmp
= DISAS_JUMP
;
1806 /* C3.2 Branches, exception generating and system instructions */
1807 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1809 switch (extract32(insn
, 25, 7)) {
1810 case 0x0a: case 0x0b:
1811 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1812 disas_uncond_b_imm(s
, insn
);
1814 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1815 disas_comp_b_imm(s
, insn
);
1817 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1818 disas_test_b_imm(s
, insn
);
1820 case 0x2a: /* Conditional branch (immediate) */
1821 disas_cond_b_imm(s
, insn
);
1823 case 0x6a: /* Exception generation / System */
1824 if (insn
& (1 << 24)) {
1825 disas_system(s
, insn
);
1830 case 0x6b: /* Unconditional branch (register) */
1831 disas_uncond_b_reg(s
, insn
);
1834 unallocated_encoding(s
);
1840 * Load/Store exclusive instructions are implemented by remembering
1841 * the value/address loaded, and seeing if these are the same
1842 * when the store is performed. This is not actually the architecturally
1843 * mandated semantics, but it works for typical guest code sequences
1844 * and avoids having to monitor regular stores.
1846 * The store exclusive uses the atomic cmpxchg primitives to avoid
1847 * races in multi-threaded linux-user and when MTTCG softmmu is
1850 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1851 TCGv_i64 addr
, int size
, bool is_pair
)
1853 TCGv_i64 tmp
= tcg_temp_new_i64();
1854 TCGMemOp memop
= s
->be_data
+ size
;
1856 g_assert(size
<= 3);
1857 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1860 TCGv_i64 addr2
= tcg_temp_new_i64();
1861 TCGv_i64 hitmp
= tcg_temp_new_i64();
1863 g_assert(size
>= 2);
1864 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1865 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1866 tcg_temp_free_i64(addr2
);
1867 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1868 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1869 tcg_temp_free_i64(hitmp
);
1872 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1873 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1875 tcg_temp_free_i64(tmp
);
1876 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1879 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1880 TCGv_i64 inaddr
, int size
, int is_pair
)
1882 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1883 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1886 * [addr + datasize] = {Rt2};
1892 * env->exclusive_addr = -1;
1894 TCGLabel
*fail_label
= gen_new_label();
1895 TCGLabel
*done_label
= gen_new_label();
1896 TCGv_i64 addr
= tcg_temp_local_new_i64();
1899 /* Copy input into a local temp so it is not trashed when the
1900 * basic block ends at the branch insn.
1902 tcg_gen_mov_i64(addr
, inaddr
);
1903 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1905 tmp
= tcg_temp_new_i64();
1908 TCGv_i64 val
= tcg_temp_new_i64();
1909 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1910 tcg_gen_concat32_i64(val
, cpu_exclusive_val
, cpu_exclusive_high
);
1911 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, val
, tmp
,
1913 size
| MO_ALIGN
| s
->be_data
);
1914 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, val
);
1915 tcg_temp_free_i64(val
);
1916 } else if (s
->be_data
== MO_LE
) {
1917 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1920 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1924 TCGv_i64 val
= cpu_reg(s
, rt
);
1925 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, cpu_exclusive_val
, val
,
1927 size
| MO_ALIGN
| s
->be_data
);
1928 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1931 tcg_temp_free_i64(addr
);
1933 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
1934 tcg_temp_free_i64(tmp
);
1935 tcg_gen_br(done_label
);
1937 gen_set_label(fail_label
);
1938 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1939 gen_set_label(done_label
);
1940 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1943 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1944 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1946 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1948 int opc0
= extract32(opc
, 0, 1);
1952 regsize
= opc0
? 32 : 64;
1954 regsize
= size
== 3 ? 64 : 32;
1956 return regsize
== 64;
1959 /* C3.3.6 Load/store exclusive
1961 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1962 * +-----+-------------+----+---+----+------+----+-------+------+------+
1963 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1964 * +-----+-------------+----+---+----+------+----+-------+------+------+
1966 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1967 * L: 0 -> store, 1 -> load
1968 * o2: 0 -> exclusive, 1 -> not
1969 * o1: 0 -> single register, 1 -> register pair
1970 * o0: 1 -> load-acquire/store-release, 0 -> not
1972 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1974 int rt
= extract32(insn
, 0, 5);
1975 int rn
= extract32(insn
, 5, 5);
1976 int rt2
= extract32(insn
, 10, 5);
1977 int is_lasr
= extract32(insn
, 15, 1);
1978 int rs
= extract32(insn
, 16, 5);
1979 int is_pair
= extract32(insn
, 21, 1);
1980 int is_store
= !extract32(insn
, 22, 1);
1981 int is_excl
= !extract32(insn
, 23, 1);
1982 int size
= extract32(insn
, 30, 2);
1985 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1986 (!is_excl
&& is_pair
) ||
1987 (is_pair
&& size
< 2)) {
1988 unallocated_encoding(s
);
1993 gen_check_sp_alignment(s
);
1995 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1997 /* Note that since TCG is single threaded load-acquire/store-release
1998 * semantics require no extra if (is_lasr) { ... } handling.
2004 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2006 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2010 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2012 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2015 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2016 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2018 /* Generate ISS for non-exclusive accesses including LASR. */
2021 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2023 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2024 true, rt
, iss_sf
, is_lasr
);
2026 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2027 true, rt
, iss_sf
, is_lasr
);
2029 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2036 * C3.3.5 Load register (literal)
2038 * 31 30 29 27 26 25 24 23 5 4 0
2039 * +-----+-------+---+-----+-------------------+-------+
2040 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2041 * +-----+-------+---+-----+-------------------+-------+
2043 * V: 1 -> vector (simd/fp)
2044 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2045 * 10-> 32 bit signed, 11 -> prefetch
2046 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2048 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2050 int rt
= extract32(insn
, 0, 5);
2051 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2052 bool is_vector
= extract32(insn
, 26, 1);
2053 int opc
= extract32(insn
, 30, 2);
2054 bool is_signed
= false;
2056 TCGv_i64 tcg_rt
, tcg_addr
;
2060 unallocated_encoding(s
);
2064 if (!fp_access_check(s
)) {
2069 /* PRFM (literal) : prefetch */
2072 size
= 2 + extract32(opc
, 0, 1);
2073 is_signed
= extract32(opc
, 1, 1);
2076 tcg_rt
= cpu_reg(s
, rt
);
2078 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2080 do_fp_ld(s
, rt
, tcg_addr
, size
);
2082 /* Only unsigned 32bit loads target 32bit registers. */
2083 bool iss_sf
= opc
!= 0;
2085 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2086 true, rt
, iss_sf
, false);
2088 tcg_temp_free_i64(tcg_addr
);
2092 * C5.6.80 LDNP (Load Pair - non-temporal hint)
2093 * C5.6.81 LDP (Load Pair - non vector)
2094 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
2095 * C5.6.176 STNP (Store Pair - non-temporal hint)
2096 * C5.6.177 STP (Store Pair - non vector)
2097 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
2098 * C6.3.165 LDP (Load Pair of SIMD&FP)
2099 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
2100 * C6.3.284 STP (Store Pair of SIMD&FP)
2102 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2103 * +-----+-------+---+---+-------+---+-----------------------------+
2104 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2105 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2107 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2109 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2110 * V: 0 -> GPR, 1 -> Vector
2111 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2112 * 10 -> signed offset, 11 -> pre-index
2113 * L: 0 -> Store 1 -> Load
2115 * Rt, Rt2 = GPR or SIMD registers to be stored
2116 * Rn = general purpose register containing address
2117 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2119 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2121 int rt
= extract32(insn
, 0, 5);
2122 int rn
= extract32(insn
, 5, 5);
2123 int rt2
= extract32(insn
, 10, 5);
2124 uint64_t offset
= sextract64(insn
, 15, 7);
2125 int index
= extract32(insn
, 23, 2);
2126 bool is_vector
= extract32(insn
, 26, 1);
2127 bool is_load
= extract32(insn
, 22, 1);
2128 int opc
= extract32(insn
, 30, 2);
2130 bool is_signed
= false;
2131 bool postindex
= false;
2134 TCGv_i64 tcg_addr
; /* calculated address */
2138 unallocated_encoding(s
);
2145 size
= 2 + extract32(opc
, 1, 1);
2146 is_signed
= extract32(opc
, 0, 1);
2147 if (!is_load
&& is_signed
) {
2148 unallocated_encoding(s
);
2154 case 1: /* post-index */
2159 /* signed offset with "non-temporal" hint. Since we don't emulate
2160 * caches we don't care about hints to the cache system about
2161 * data access patterns, and handle this identically to plain
2165 /* There is no non-temporal-hint version of LDPSW */
2166 unallocated_encoding(s
);
2171 case 2: /* signed offset, rn not updated */
2174 case 3: /* pre-index */
2180 if (is_vector
&& !fp_access_check(s
)) {
2187 gen_check_sp_alignment(s
);
2190 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2193 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2198 do_fp_ld(s
, rt
, tcg_addr
, size
);
2200 do_fp_st(s
, rt
, tcg_addr
, size
);
2203 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2205 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2206 false, 0, false, false);
2208 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2209 false, 0, false, false);
2212 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2215 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2217 do_fp_st(s
, rt2
, tcg_addr
, size
);
2220 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2222 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2223 false, 0, false, false);
2225 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2226 false, 0, false, false);
2232 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2234 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2236 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2241 * C3.3.8 Load/store (immediate post-indexed)
2242 * C3.3.9 Load/store (immediate pre-indexed)
2243 * C3.3.12 Load/store (unscaled immediate)
2245 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2246 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2247 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2248 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2250 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2252 * V = 0 -> non-vector
2253 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2254 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2256 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2262 int rn
= extract32(insn
, 5, 5);
2263 int imm9
= sextract32(insn
, 12, 9);
2264 int idx
= extract32(insn
, 10, 2);
2265 bool is_signed
= false;
2266 bool is_store
= false;
2267 bool is_extended
= false;
2268 bool is_unpriv
= (idx
== 2);
2269 bool iss_valid
= !is_vector
;
2276 size
|= (opc
& 2) << 1;
2277 if (size
> 4 || is_unpriv
) {
2278 unallocated_encoding(s
);
2281 is_store
= ((opc
& 1) == 0);
2282 if (!fp_access_check(s
)) {
2286 if (size
== 3 && opc
== 2) {
2287 /* PRFM - prefetch */
2289 unallocated_encoding(s
);
2294 if (opc
== 3 && size
> 1) {
2295 unallocated_encoding(s
);
2298 is_store
= (opc
== 0);
2299 is_signed
= extract32(opc
, 1, 1);
2300 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2320 gen_check_sp_alignment(s
);
2322 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2325 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2330 do_fp_st(s
, rt
, tcg_addr
, size
);
2332 do_fp_ld(s
, rt
, tcg_addr
, size
);
2335 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2336 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2337 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2340 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2341 iss_valid
, rt
, iss_sf
, false);
2343 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2344 is_signed
, is_extended
, memidx
,
2345 iss_valid
, rt
, iss_sf
, false);
2350 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2352 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2354 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2359 * C3.3.10 Load/store (register offset)
2361 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2362 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2363 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2364 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2367 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2368 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2370 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2371 * opc<0>: 0 -> store, 1 -> load
2372 * V: 1 -> vector/simd
2373 * opt: extend encoding (see DecodeRegExtend)
2374 * S: if S=1 then scale (essentially index by sizeof(size))
2375 * Rt: register to transfer into/out of
2376 * Rn: address register or SP for base
2377 * Rm: offset register or ZR for offset
2379 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2385 int rn
= extract32(insn
, 5, 5);
2386 int shift
= extract32(insn
, 12, 1);
2387 int rm
= extract32(insn
, 16, 5);
2388 int opt
= extract32(insn
, 13, 3);
2389 bool is_signed
= false;
2390 bool is_store
= false;
2391 bool is_extended
= false;
2396 if (extract32(opt
, 1, 1) == 0) {
2397 unallocated_encoding(s
);
2402 size
|= (opc
& 2) << 1;
2404 unallocated_encoding(s
);
2407 is_store
= !extract32(opc
, 0, 1);
2408 if (!fp_access_check(s
)) {
2412 if (size
== 3 && opc
== 2) {
2413 /* PRFM - prefetch */
2416 if (opc
== 3 && size
> 1) {
2417 unallocated_encoding(s
);
2420 is_store
= (opc
== 0);
2421 is_signed
= extract32(opc
, 1, 1);
2422 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2426 gen_check_sp_alignment(s
);
2428 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2430 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2431 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2433 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2437 do_fp_st(s
, rt
, tcg_addr
, size
);
2439 do_fp_ld(s
, rt
, tcg_addr
, size
);
2442 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2443 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2445 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2446 true, rt
, iss_sf
, false);
2448 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2449 is_signed
, is_extended
,
2450 true, rt
, iss_sf
, false);
2456 * C3.3.13 Load/store (unsigned immediate)
2458 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2459 * +----+-------+---+-----+-----+------------+-------+------+
2460 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2461 * +----+-------+---+-----+-----+------------+-------+------+
2464 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2465 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2467 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2468 * opc<0>: 0 -> store, 1 -> load
2469 * Rn: base address register (inc SP)
2470 * Rt: target register
2472 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2478 int rn
= extract32(insn
, 5, 5);
2479 unsigned int imm12
= extract32(insn
, 10, 12);
2480 unsigned int offset
;
2485 bool is_signed
= false;
2486 bool is_extended
= false;
2489 size
|= (opc
& 2) << 1;
2491 unallocated_encoding(s
);
2494 is_store
= !extract32(opc
, 0, 1);
2495 if (!fp_access_check(s
)) {
2499 if (size
== 3 && opc
== 2) {
2500 /* PRFM - prefetch */
2503 if (opc
== 3 && size
> 1) {
2504 unallocated_encoding(s
);
2507 is_store
= (opc
== 0);
2508 is_signed
= extract32(opc
, 1, 1);
2509 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2513 gen_check_sp_alignment(s
);
2515 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2516 offset
= imm12
<< size
;
2517 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2521 do_fp_st(s
, rt
, tcg_addr
, size
);
2523 do_fp_ld(s
, rt
, tcg_addr
, size
);
2526 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2527 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2529 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2530 true, rt
, iss_sf
, false);
2532 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2533 true, rt
, iss_sf
, false);
2538 /* Load/store register (all forms) */
2539 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2541 int rt
= extract32(insn
, 0, 5);
2542 int opc
= extract32(insn
, 22, 2);
2543 bool is_vector
= extract32(insn
, 26, 1);
2544 int size
= extract32(insn
, 30, 2);
2546 switch (extract32(insn
, 24, 2)) {
2548 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2549 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2551 /* Load/store register (unscaled immediate)
2552 * Load/store immediate pre/post-indexed
2553 * Load/store register unprivileged
2555 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2559 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2562 unallocated_encoding(s
);
2567 /* C3.3.1 AdvSIMD load/store multiple structures
2569 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2570 * +---+---+---------------+---+-------------+--------+------+------+------+
2571 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2572 * +---+---+---------------+---+-------------+--------+------+------+------+
2574 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2576 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2577 * +---+---+---------------+---+---+---------+--------+------+------+------+
2578 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2579 * +---+---+---------------+---+---+---------+--------+------+------+------+
2581 * Rt: first (or only) SIMD&FP register to be transferred
2582 * Rn: base address or SP
2583 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2585 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2587 int rt
= extract32(insn
, 0, 5);
2588 int rn
= extract32(insn
, 5, 5);
2589 int size
= extract32(insn
, 10, 2);
2590 int opcode
= extract32(insn
, 12, 4);
2591 bool is_store
= !extract32(insn
, 22, 1);
2592 bool is_postidx
= extract32(insn
, 23, 1);
2593 bool is_q
= extract32(insn
, 30, 1);
2594 TCGv_i64 tcg_addr
, tcg_rn
;
2596 int ebytes
= 1 << size
;
2597 int elements
= (is_q
? 128 : 64) / (8 << size
);
2598 int rpt
; /* num iterations */
2599 int selem
; /* structure elements */
2602 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2603 unallocated_encoding(s
);
2607 /* From the shared decode logic */
2638 unallocated_encoding(s
);
2642 if (size
== 3 && !is_q
&& selem
!= 1) {
2644 unallocated_encoding(s
);
2648 if (!fp_access_check(s
)) {
2653 gen_check_sp_alignment(s
);
2656 tcg_rn
= cpu_reg_sp(s
, rn
);
2657 tcg_addr
= tcg_temp_new_i64();
2658 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2660 for (r
= 0; r
< rpt
; r
++) {
2662 for (e
= 0; e
< elements
; e
++) {
2663 int tt
= (rt
+ r
) % 32;
2665 for (xs
= 0; xs
< selem
; xs
++) {
2667 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2669 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2671 /* For non-quad operations, setting a slice of the low
2672 * 64 bits of the register clears the high 64 bits (in
2673 * the ARM ARM pseudocode this is implicit in the fact
2674 * that 'rval' is a 64 bit wide variable). We optimize
2675 * by noticing that we only need to do this the first
2676 * time we touch a register.
2678 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2679 clear_vec_high(s
, tt
);
2682 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2689 int rm
= extract32(insn
, 16, 5);
2691 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2693 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2696 tcg_temp_free_i64(tcg_addr
);
2699 /* C3.3.3 AdvSIMD load/store single structure
2701 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2702 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2703 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2704 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2706 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2708 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2709 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2710 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2711 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2713 * Rt: first (or only) SIMD&FP register to be transferred
2714 * Rn: base address or SP
2715 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2716 * index = encoded in Q:S:size dependent on size
2718 * lane_size = encoded in R, opc
2719 * transfer width = encoded in opc, S, size
2721 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2723 int rt
= extract32(insn
, 0, 5);
2724 int rn
= extract32(insn
, 5, 5);
2725 int size
= extract32(insn
, 10, 2);
2726 int S
= extract32(insn
, 12, 1);
2727 int opc
= extract32(insn
, 13, 3);
2728 int R
= extract32(insn
, 21, 1);
2729 int is_load
= extract32(insn
, 22, 1);
2730 int is_postidx
= extract32(insn
, 23, 1);
2731 int is_q
= extract32(insn
, 30, 1);
2733 int scale
= extract32(opc
, 1, 2);
2734 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2735 bool replicate
= false;
2736 int index
= is_q
<< 3 | S
<< 2 | size
;
2738 TCGv_i64 tcg_addr
, tcg_rn
;
2742 if (!is_load
|| S
) {
2743 unallocated_encoding(s
);
2752 if (extract32(size
, 0, 1)) {
2753 unallocated_encoding(s
);
2759 if (extract32(size
, 1, 1)) {
2760 unallocated_encoding(s
);
2763 if (!extract32(size
, 0, 1)) {
2767 unallocated_encoding(s
);
2775 g_assert_not_reached();
2778 if (!fp_access_check(s
)) {
2782 ebytes
= 1 << scale
;
2785 gen_check_sp_alignment(s
);
2788 tcg_rn
= cpu_reg_sp(s
, rn
);
2789 tcg_addr
= tcg_temp_new_i64();
2790 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2792 for (xs
= 0; xs
< selem
; xs
++) {
2794 /* Load and replicate to all elements */
2796 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2798 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2799 get_mem_index(s
), s
->be_data
+ scale
);
2802 mulconst
= 0x0101010101010101ULL
;
2805 mulconst
= 0x0001000100010001ULL
;
2808 mulconst
= 0x0000000100000001ULL
;
2814 g_assert_not_reached();
2817 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2819 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2821 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2823 clear_vec_high(s
, rt
);
2825 tcg_temp_free_i64(tcg_tmp
);
2827 /* Load/store one element per register */
2829 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2831 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2834 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2839 int rm
= extract32(insn
, 16, 5);
2841 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2843 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2846 tcg_temp_free_i64(tcg_addr
);
2849 /* C3.3 Loads and stores */
2850 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2852 switch (extract32(insn
, 24, 6)) {
2853 case 0x08: /* Load/store exclusive */
2854 disas_ldst_excl(s
, insn
);
2856 case 0x18: case 0x1c: /* Load register (literal) */
2857 disas_ld_lit(s
, insn
);
2859 case 0x28: case 0x29:
2860 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2861 disas_ldst_pair(s
, insn
);
2863 case 0x38: case 0x39:
2864 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2865 disas_ldst_reg(s
, insn
);
2867 case 0x0c: /* AdvSIMD load/store multiple structures */
2868 disas_ldst_multiple_struct(s
, insn
);
2870 case 0x0d: /* AdvSIMD load/store single structure */
2871 disas_ldst_single_struct(s
, insn
);
2874 unallocated_encoding(s
);
2879 /* C3.4.6 PC-rel. addressing
2880 * 31 30 29 28 24 23 5 4 0
2881 * +----+-------+-----------+-------------------+------+
2882 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2883 * +----+-------+-----------+-------------------+------+
2885 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2887 unsigned int page
, rd
;
2891 page
= extract32(insn
, 31, 1);
2892 /* SignExtend(immhi:immlo) -> offset */
2893 offset
= sextract64(insn
, 5, 19);
2894 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2895 rd
= extract32(insn
, 0, 5);
2899 /* ADRP (page based) */
2904 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2908 * C3.4.1 Add/subtract (immediate)
2910 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2911 * +--+--+--+-----------+-----+-------------+-----+-----+
2912 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2913 * +--+--+--+-----------+-----+-------------+-----+-----+
2915 * sf: 0 -> 32bit, 1 -> 64bit
2916 * op: 0 -> add , 1 -> sub
2918 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2920 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2922 int rd
= extract32(insn
, 0, 5);
2923 int rn
= extract32(insn
, 5, 5);
2924 uint64_t imm
= extract32(insn
, 10, 12);
2925 int shift
= extract32(insn
, 22, 2);
2926 bool setflags
= extract32(insn
, 29, 1);
2927 bool sub_op
= extract32(insn
, 30, 1);
2928 bool is_64bit
= extract32(insn
, 31, 1);
2930 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2931 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2932 TCGv_i64 tcg_result
;
2941 unallocated_encoding(s
);
2945 tcg_result
= tcg_temp_new_i64();
2948 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2950 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2953 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2955 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2957 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2959 tcg_temp_free_i64(tcg_imm
);
2963 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2965 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2968 tcg_temp_free_i64(tcg_result
);
2971 /* The input should be a value in the bottom e bits (with higher
2972 * bits zero); returns that value replicated into every element
2973 * of size e in a 64 bit integer.
2975 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2985 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2986 static inline uint64_t bitmask64(unsigned int length
)
2988 assert(length
> 0 && length
<= 64);
2989 return ~0ULL >> (64 - length
);
2992 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2993 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2994 * value (ie should cause a guest UNDEF exception), and true if they are
2995 * valid, in which case the decoded bit pattern is written to result.
2997 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2998 unsigned int imms
, unsigned int immr
)
3001 unsigned e
, levels
, s
, r
;
3004 assert(immn
< 2 && imms
< 64 && immr
< 64);
3006 /* The bit patterns we create here are 64 bit patterns which
3007 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3008 * 64 bits each. Each element contains the same value: a run
3009 * of between 1 and e-1 non-zero bits, rotated within the
3010 * element by between 0 and e-1 bits.
3012 * The element size and run length are encoded into immn (1 bit)
3013 * and imms (6 bits) as follows:
3014 * 64 bit elements: immn = 1, imms = <length of run - 1>
3015 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3016 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3017 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3018 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3019 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3020 * Notice that immn = 0, imms = 11111x is the only combination
3021 * not covered by one of the above options; this is reserved.
3022 * Further, <length of run - 1> all-ones is a reserved pattern.
3024 * In all cases the rotation is by immr % e (and immr is 6 bits).
3027 /* First determine the element size */
3028 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3030 /* This is the immn == 0, imms == 0x11111x case */
3040 /* <length of run - 1> mustn't be all-ones. */
3044 /* Create the value of one element: s+1 set bits rotated
3045 * by r within the element (which is e bits wide)...
3047 mask
= bitmask64(s
+ 1);
3049 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3050 mask
&= bitmask64(e
);
3052 /* ...then replicate the element over the whole 64 bit value */
3053 mask
= bitfield_replicate(mask
, e
);
3058 /* C3.4.4 Logical (immediate)
3059 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3060 * +----+-----+-------------+---+------+------+------+------+
3061 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3062 * +----+-----+-------------+---+------+------+------+------+
3064 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3066 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3067 TCGv_i64 tcg_rd
, tcg_rn
;
3069 bool is_and
= false;
3071 sf
= extract32(insn
, 31, 1);
3072 opc
= extract32(insn
, 29, 2);
3073 is_n
= extract32(insn
, 22, 1);
3074 immr
= extract32(insn
, 16, 6);
3075 imms
= extract32(insn
, 10, 6);
3076 rn
= extract32(insn
, 5, 5);
3077 rd
= extract32(insn
, 0, 5);
3080 unallocated_encoding(s
);
3084 if (opc
== 0x3) { /* ANDS */
3085 tcg_rd
= cpu_reg(s
, rd
);
3087 tcg_rd
= cpu_reg_sp(s
, rd
);
3089 tcg_rn
= cpu_reg(s
, rn
);
3091 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3092 /* some immediate field values are reserved */
3093 unallocated_encoding(s
);
3098 wmask
&= 0xffffffff;
3102 case 0x3: /* ANDS */
3104 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3108 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3111 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3114 assert(FALSE
); /* must handle all above */
3118 if (!sf
&& !is_and
) {
3119 /* zero extend final result; we know we can skip this for AND
3120 * since the immediate had the high 32 bits clear.
3122 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3125 if (opc
== 3) { /* ANDS */
3126 gen_logic_CC(sf
, tcg_rd
);
3131 * C3.4.5 Move wide (immediate)
3133 * 31 30 29 28 23 22 21 20 5 4 0
3134 * +--+-----+-------------+-----+----------------+------+
3135 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3136 * +--+-----+-------------+-----+----------------+------+
3138 * sf: 0 -> 32 bit, 1 -> 64 bit
3139 * opc: 00 -> N, 10 -> Z, 11 -> K
3140 * hw: shift/16 (0,16, and sf only 32, 48)
3142 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3144 int rd
= extract32(insn
, 0, 5);
3145 uint64_t imm
= extract32(insn
, 5, 16);
3146 int sf
= extract32(insn
, 31, 1);
3147 int opc
= extract32(insn
, 29, 2);
3148 int pos
= extract32(insn
, 21, 2) << 4;
3149 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3152 if (!sf
&& (pos
>= 32)) {
3153 unallocated_encoding(s
);
3167 tcg_gen_movi_i64(tcg_rd
, imm
);
3170 tcg_imm
= tcg_const_i64(imm
);
3171 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3172 tcg_temp_free_i64(tcg_imm
);
3174 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3178 unallocated_encoding(s
);
3184 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3185 * +----+-----+-------------+---+------+------+------+------+
3186 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3187 * +----+-----+-------------+---+------+------+------+------+
3189 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3191 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3192 TCGv_i64 tcg_rd
, tcg_tmp
;
3194 sf
= extract32(insn
, 31, 1);
3195 opc
= extract32(insn
, 29, 2);
3196 n
= extract32(insn
, 22, 1);
3197 ri
= extract32(insn
, 16, 6);
3198 si
= extract32(insn
, 10, 6);
3199 rn
= extract32(insn
, 5, 5);
3200 rd
= extract32(insn
, 0, 5);
3201 bitsize
= sf
? 64 : 32;
3203 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3204 unallocated_encoding(s
);
3208 tcg_rd
= cpu_reg(s
, rd
);
3210 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3211 to be smaller than bitsize, we'll never reference data outside the
3212 low 32-bits anyway. */
3213 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3215 /* Recognize simple(r) extractions. */
3217 /* Wd<s-r:0> = Wn<s:r> */
3218 len
= (si
- ri
) + 1;
3219 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3220 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3222 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3223 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3226 /* opc == 1, BXFIL fall through to deposit */
3227 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3230 /* Handle the ri > si case with a deposit
3231 * Wd<32+s-r,32-r> = Wn<s:0>
3234 pos
= (bitsize
- ri
) & (bitsize
- 1);
3237 if (opc
== 0 && len
< ri
) {
3238 /* SBFM: sign extend the destination field from len to fill
3239 the balance of the word. Let the deposit below insert all
3240 of those sign bits. */
3241 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3245 if (opc
== 1) { /* BFM, BXFIL */
3246 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3248 /* SBFM or UBFM: We start with zero, and we haven't modified
3249 any bits outside bitsize, therefore the zero-extension
3250 below is unneeded. */
3251 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3256 if (!sf
) { /* zero extend final result */
3257 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3262 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3263 * +----+------+-------------+---+----+------+--------+------+------+
3264 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3265 * +----+------+-------------+---+----+------+--------+------+------+
3267 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3269 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3271 sf
= extract32(insn
, 31, 1);
3272 n
= extract32(insn
, 22, 1);
3273 rm
= extract32(insn
, 16, 5);
3274 imm
= extract32(insn
, 10, 6);
3275 rn
= extract32(insn
, 5, 5);
3276 rd
= extract32(insn
, 0, 5);
3277 op21
= extract32(insn
, 29, 2);
3278 op0
= extract32(insn
, 21, 1);
3279 bitsize
= sf
? 64 : 32;
3281 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3282 unallocated_encoding(s
);
3284 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3286 tcg_rd
= cpu_reg(s
, rd
);
3288 if (unlikely(imm
== 0)) {
3289 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3290 * so an extract from bit 0 is a special case.
3293 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3295 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3297 } else if (rm
== rn
) { /* ROR */
3298 tcg_rm
= cpu_reg(s
, rm
);
3300 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3302 TCGv_i32 tmp
= tcg_temp_new_i32();
3303 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3304 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3305 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3306 tcg_temp_free_i32(tmp
);
3309 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3310 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3311 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3312 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3313 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3315 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3321 /* C3.4 Data processing - immediate */
3322 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3324 switch (extract32(insn
, 23, 6)) {
3325 case 0x20: case 0x21: /* PC-rel. addressing */
3326 disas_pc_rel_adr(s
, insn
);
3328 case 0x22: case 0x23: /* Add/subtract (immediate) */
3329 disas_add_sub_imm(s
, insn
);
3331 case 0x24: /* Logical (immediate) */
3332 disas_logic_imm(s
, insn
);
3334 case 0x25: /* Move wide (immediate) */
3335 disas_movw_imm(s
, insn
);
3337 case 0x26: /* Bitfield */
3338 disas_bitfield(s
, insn
);
3340 case 0x27: /* Extract */
3341 disas_extract(s
, insn
);
3344 unallocated_encoding(s
);
3349 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3350 * Note that it is the caller's responsibility to ensure that the
3351 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3352 * mandated semantics for out of range shifts.
3354 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3355 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3357 switch (shift_type
) {
3358 case A64_SHIFT_TYPE_LSL
:
3359 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3361 case A64_SHIFT_TYPE_LSR
:
3362 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3364 case A64_SHIFT_TYPE_ASR
:
3366 tcg_gen_ext32s_i64(dst
, src
);
3368 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3370 case A64_SHIFT_TYPE_ROR
:
3372 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3375 t0
= tcg_temp_new_i32();
3376 t1
= tcg_temp_new_i32();
3377 tcg_gen_extrl_i64_i32(t0
, src
);
3378 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3379 tcg_gen_rotr_i32(t0
, t0
, t1
);
3380 tcg_gen_extu_i32_i64(dst
, t0
);
3381 tcg_temp_free_i32(t0
);
3382 tcg_temp_free_i32(t1
);
3386 assert(FALSE
); /* all shift types should be handled */
3390 if (!sf
) { /* zero extend final result */
3391 tcg_gen_ext32u_i64(dst
, dst
);
3395 /* Shift a TCGv src by immediate, put result in dst.
3396 * The shift amount must be in range (this should always be true as the
3397 * relevant instructions will UNDEF on bad shift immediates).
3399 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3400 enum a64_shift_type shift_type
, unsigned int shift_i
)
3402 assert(shift_i
< (sf
? 64 : 32));
3405 tcg_gen_mov_i64(dst
, src
);
3407 TCGv_i64 shift_const
;
3409 shift_const
= tcg_const_i64(shift_i
);
3410 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3411 tcg_temp_free_i64(shift_const
);
3415 /* C3.5.10 Logical (shifted register)
3416 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3417 * +----+-----+-----------+-------+---+------+--------+------+------+
3418 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3419 * +----+-----+-----------+-------+---+------+--------+------+------+
3421 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3423 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3424 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3426 sf
= extract32(insn
, 31, 1);
3427 opc
= extract32(insn
, 29, 2);
3428 shift_type
= extract32(insn
, 22, 2);
3429 invert
= extract32(insn
, 21, 1);
3430 rm
= extract32(insn
, 16, 5);
3431 shift_amount
= extract32(insn
, 10, 6);
3432 rn
= extract32(insn
, 5, 5);
3433 rd
= extract32(insn
, 0, 5);
3435 if (!sf
&& (shift_amount
& (1 << 5))) {
3436 unallocated_encoding(s
);
3440 tcg_rd
= cpu_reg(s
, rd
);
3442 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3443 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3444 * register-register MOV and MVN, so it is worth special casing.
3446 tcg_rm
= cpu_reg(s
, rm
);
3448 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3450 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3454 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3456 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3462 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3465 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3468 tcg_rn
= cpu_reg(s
, rn
);
3470 switch (opc
| (invert
<< 2)) {
3473 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3476 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3479 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3483 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3486 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3489 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3497 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3501 gen_logic_CC(sf
, tcg_rd
);
3506 * C3.5.1 Add/subtract (extended register)
3508 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3509 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3510 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3511 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3513 * sf: 0 -> 32bit, 1 -> 64bit
3514 * op: 0 -> add , 1 -> sub
3517 * option: extension type (see DecodeRegExtend)
3518 * imm3: optional shift to Rm
3520 * Rd = Rn + LSL(extend(Rm), amount)
3522 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3524 int rd
= extract32(insn
, 0, 5);
3525 int rn
= extract32(insn
, 5, 5);
3526 int imm3
= extract32(insn
, 10, 3);
3527 int option
= extract32(insn
, 13, 3);
3528 int rm
= extract32(insn
, 16, 5);
3529 bool setflags
= extract32(insn
, 29, 1);
3530 bool sub_op
= extract32(insn
, 30, 1);
3531 bool sf
= extract32(insn
, 31, 1);
3533 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3535 TCGv_i64 tcg_result
;
3538 unallocated_encoding(s
);
3542 /* non-flag setting ops may use SP */
3544 tcg_rd
= cpu_reg_sp(s
, rd
);
3546 tcg_rd
= cpu_reg(s
, rd
);
3548 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3550 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3551 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3553 tcg_result
= tcg_temp_new_i64();
3557 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3559 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3563 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3565 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3570 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3572 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3575 tcg_temp_free_i64(tcg_result
);
3579 * C3.5.2 Add/subtract (shifted register)
3581 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3582 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3583 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3584 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3586 * sf: 0 -> 32bit, 1 -> 64bit
3587 * op: 0 -> add , 1 -> sub
3589 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3590 * imm6: Shift amount to apply to Rm before the add/sub
3592 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3594 int rd
= extract32(insn
, 0, 5);
3595 int rn
= extract32(insn
, 5, 5);
3596 int imm6
= extract32(insn
, 10, 6);
3597 int rm
= extract32(insn
, 16, 5);
3598 int shift_type
= extract32(insn
, 22, 2);
3599 bool setflags
= extract32(insn
, 29, 1);
3600 bool sub_op
= extract32(insn
, 30, 1);
3601 bool sf
= extract32(insn
, 31, 1);
3603 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3604 TCGv_i64 tcg_rn
, tcg_rm
;
3605 TCGv_i64 tcg_result
;
3607 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3608 unallocated_encoding(s
);
3612 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3613 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3615 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3617 tcg_result
= tcg_temp_new_i64();
3621 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3623 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3627 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3629 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3634 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3636 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3639 tcg_temp_free_i64(tcg_result
);
3642 /* C3.5.9 Data-processing (3 source)
3644 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3645 +--+------+-----------+------+------+----+------+------+------+
3646 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3647 +--+------+-----------+------+------+----+------+------+------+
3650 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3652 int rd
= extract32(insn
, 0, 5);
3653 int rn
= extract32(insn
, 5, 5);
3654 int ra
= extract32(insn
, 10, 5);
3655 int rm
= extract32(insn
, 16, 5);
3656 int op_id
= (extract32(insn
, 29, 3) << 4) |
3657 (extract32(insn
, 21, 3) << 1) |
3658 extract32(insn
, 15, 1);
3659 bool sf
= extract32(insn
, 31, 1);
3660 bool is_sub
= extract32(op_id
, 0, 1);
3661 bool is_high
= extract32(op_id
, 2, 1);
3662 bool is_signed
= false;
3667 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3669 case 0x42: /* SMADDL */
3670 case 0x43: /* SMSUBL */
3671 case 0x44: /* SMULH */
3674 case 0x0: /* MADD (32bit) */
3675 case 0x1: /* MSUB (32bit) */
3676 case 0x40: /* MADD (64bit) */
3677 case 0x41: /* MSUB (64bit) */
3678 case 0x4a: /* UMADDL */
3679 case 0x4b: /* UMSUBL */
3680 case 0x4c: /* UMULH */
3683 unallocated_encoding(s
);
3688 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3689 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3690 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3691 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3694 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3696 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3699 tcg_temp_free_i64(low_bits
);
3703 tcg_op1
= tcg_temp_new_i64();
3704 tcg_op2
= tcg_temp_new_i64();
3705 tcg_tmp
= tcg_temp_new_i64();
3708 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3709 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3712 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3713 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3715 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3716 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3720 if (ra
== 31 && !is_sub
) {
3721 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3722 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3724 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3726 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3728 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3733 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3736 tcg_temp_free_i64(tcg_op1
);
3737 tcg_temp_free_i64(tcg_op2
);
3738 tcg_temp_free_i64(tcg_tmp
);
3741 /* C3.5.3 - Add/subtract (with carry)
3742 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3743 * +--+--+--+------------------------+------+---------+------+-----+
3744 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3745 * +--+--+--+------------------------+------+---------+------+-----+
3749 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3751 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3752 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3754 if (extract32(insn
, 10, 6) != 0) {
3755 unallocated_encoding(s
);
3759 sf
= extract32(insn
, 31, 1);
3760 op
= extract32(insn
, 30, 1);
3761 setflags
= extract32(insn
, 29, 1);
3762 rm
= extract32(insn
, 16, 5);
3763 rn
= extract32(insn
, 5, 5);
3764 rd
= extract32(insn
, 0, 5);
3766 tcg_rd
= cpu_reg(s
, rd
);
3767 tcg_rn
= cpu_reg(s
, rn
);
3770 tcg_y
= new_tmp_a64(s
);
3771 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3773 tcg_y
= cpu_reg(s
, rm
);
3777 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3779 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3783 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3784 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3785 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3786 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3787 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3790 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3792 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3793 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3794 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3797 if (!extract32(insn
, 29, 1)) {
3798 unallocated_encoding(s
);
3801 if (insn
& (1 << 10 | 1 << 4)) {
3802 unallocated_encoding(s
);
3805 sf
= extract32(insn
, 31, 1);
3806 op
= extract32(insn
, 30, 1);
3807 is_imm
= extract32(insn
, 11, 1);
3808 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3809 cond
= extract32(insn
, 12, 4);
3810 rn
= extract32(insn
, 5, 5);
3811 nzcv
= extract32(insn
, 0, 4);
3813 /* Set T0 = !COND. */
3814 tcg_t0
= tcg_temp_new_i32();
3815 arm_test_cc(&c
, cond
);
3816 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3819 /* Load the arguments for the new comparison. */
3821 tcg_y
= new_tmp_a64(s
);
3822 tcg_gen_movi_i64(tcg_y
, y
);
3824 tcg_y
= cpu_reg(s
, y
);
3826 tcg_rn
= cpu_reg(s
, rn
);
3828 /* Set the flags for the new comparison. */
3829 tcg_tmp
= tcg_temp_new_i64();
3831 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3833 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3835 tcg_temp_free_i64(tcg_tmp
);
3837 /* If COND was false, force the flags to #nzcv. Compute two masks
3838 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3839 * For tcg hosts that support ANDC, we can make do with just T1.
3840 * In either case, allow the tcg optimizer to delete any unused mask.
3842 tcg_t1
= tcg_temp_new_i32();
3843 tcg_t2
= tcg_temp_new_i32();
3844 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3845 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3847 if (nzcv
& 8) { /* N */
3848 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3850 if (TCG_TARGET_HAS_andc_i32
) {
3851 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3853 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3856 if (nzcv
& 4) { /* Z */
3857 if (TCG_TARGET_HAS_andc_i32
) {
3858 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3860 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3863 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3865 if (nzcv
& 2) { /* C */
3866 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3868 if (TCG_TARGET_HAS_andc_i32
) {
3869 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3871 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3874 if (nzcv
& 1) { /* V */
3875 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3877 if (TCG_TARGET_HAS_andc_i32
) {
3878 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3880 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3883 tcg_temp_free_i32(tcg_t0
);
3884 tcg_temp_free_i32(tcg_t1
);
3885 tcg_temp_free_i32(tcg_t2
);
3888 /* C3.5.6 Conditional select
3889 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3890 * +----+----+---+-----------------+------+------+-----+------+------+
3891 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3892 * +----+----+---+-----------------+------+------+-----+------+------+
3894 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3896 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3897 TCGv_i64 tcg_rd
, zero
;
3900 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3901 /* S == 1 or op2<1> == 1 */
3902 unallocated_encoding(s
);
3905 sf
= extract32(insn
, 31, 1);
3906 else_inv
= extract32(insn
, 30, 1);
3907 rm
= extract32(insn
, 16, 5);
3908 cond
= extract32(insn
, 12, 4);
3909 else_inc
= extract32(insn
, 10, 1);
3910 rn
= extract32(insn
, 5, 5);
3911 rd
= extract32(insn
, 0, 5);
3913 tcg_rd
= cpu_reg(s
, rd
);
3915 a64_test_cc(&c
, cond
);
3916 zero
= tcg_const_i64(0);
3918 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3920 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3922 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3925 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3926 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3927 if (else_inv
&& else_inc
) {
3928 tcg_gen_neg_i64(t_false
, t_false
);
3929 } else if (else_inv
) {
3930 tcg_gen_not_i64(t_false
, t_false
);
3931 } else if (else_inc
) {
3932 tcg_gen_addi_i64(t_false
, t_false
, 1);
3934 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3937 tcg_temp_free_i64(zero
);
3941 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3945 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3946 unsigned int rn
, unsigned int rd
)
3948 TCGv_i64 tcg_rd
, tcg_rn
;
3949 tcg_rd
= cpu_reg(s
, rd
);
3950 tcg_rn
= cpu_reg(s
, rn
);
3953 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
3955 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3956 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3957 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
3958 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3959 tcg_temp_free_i32(tcg_tmp32
);
3963 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3964 unsigned int rn
, unsigned int rd
)
3966 TCGv_i64 tcg_rd
, tcg_rn
;
3967 tcg_rd
= cpu_reg(s
, rd
);
3968 tcg_rn
= cpu_reg(s
, rn
);
3971 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
3973 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3974 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3975 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
3976 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3977 tcg_temp_free_i32(tcg_tmp32
);
3981 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3982 unsigned int rn
, unsigned int rd
)
3984 TCGv_i64 tcg_rd
, tcg_rn
;
3985 tcg_rd
= cpu_reg(s
, rd
);
3986 tcg_rn
= cpu_reg(s
, rn
);
3989 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3991 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3992 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3993 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3994 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3995 tcg_temp_free_i32(tcg_tmp32
);
3999 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
4000 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4001 unsigned int rn
, unsigned int rd
)
4004 unallocated_encoding(s
);
4007 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4010 /* C5.6.149 REV with sf==0, opcode==2
4011 * C5.6.151 REV32 (sf==1, opcode==2)
4013 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4014 unsigned int rn
, unsigned int rd
)
4016 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4019 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4020 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4022 /* bswap32_i64 requires zero high word */
4023 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4024 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4025 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4026 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4027 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4029 tcg_temp_free_i64(tcg_tmp
);
4031 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4032 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4036 /* C5.6.150 REV16 (opcode==1) */
4037 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4038 unsigned int rn
, unsigned int rd
)
4040 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4041 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4042 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4044 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
4045 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
4047 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
4048 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4049 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4050 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
4053 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4054 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4055 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4056 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
4058 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
4059 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4060 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
4063 tcg_temp_free_i64(tcg_tmp
);
4066 /* C3.5.7 Data-processing (1 source)
4067 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4068 * +----+---+---+-----------------+---------+--------+------+------+
4069 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4070 * +----+---+---+-----------------+---------+--------+------+------+
4072 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4074 unsigned int sf
, opcode
, rn
, rd
;
4076 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4077 unallocated_encoding(s
);
4081 sf
= extract32(insn
, 31, 1);
4082 opcode
= extract32(insn
, 10, 6);
4083 rn
= extract32(insn
, 5, 5);
4084 rd
= extract32(insn
, 0, 5);
4088 handle_rbit(s
, sf
, rn
, rd
);
4091 handle_rev16(s
, sf
, rn
, rd
);
4094 handle_rev32(s
, sf
, rn
, rd
);
4097 handle_rev64(s
, sf
, rn
, rd
);
4100 handle_clz(s
, sf
, rn
, rd
);
4103 handle_cls(s
, sf
, rn
, rd
);
4108 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4109 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4111 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4112 tcg_rd
= cpu_reg(s
, rd
);
4114 if (!sf
&& is_signed
) {
4115 tcg_n
= new_tmp_a64(s
);
4116 tcg_m
= new_tmp_a64(s
);
4117 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4118 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4120 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4121 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4125 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4127 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4130 if (!sf
) { /* zero extend final result */
4131 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4135 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
4136 static void handle_shift_reg(DisasContext
*s
,
4137 enum a64_shift_type shift_type
, unsigned int sf
,
4138 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4140 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4141 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4142 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4144 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4145 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4146 tcg_temp_free_i64(tcg_shift
);
4149 /* CRC32[BHWX], CRC32C[BHWX] */
4150 static void handle_crc32(DisasContext
*s
,
4151 unsigned int sf
, unsigned int sz
, bool crc32c
,
4152 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4154 TCGv_i64 tcg_acc
, tcg_val
;
4157 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4158 || (sf
== 1 && sz
!= 3)
4159 || (sf
== 0 && sz
== 3)) {
4160 unallocated_encoding(s
);
4165 tcg_val
= cpu_reg(s
, rm
);
4179 g_assert_not_reached();
4181 tcg_val
= new_tmp_a64(s
);
4182 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4185 tcg_acc
= cpu_reg(s
, rn
);
4186 tcg_bytes
= tcg_const_i32(1 << sz
);
4189 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4191 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4194 tcg_temp_free_i32(tcg_bytes
);
4197 /* C3.5.8 Data-processing (2 source)
4198 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4199 * +----+---+---+-----------------+------+--------+------+------+
4200 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4201 * +----+---+---+-----------------+------+--------+------+------+
4203 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4205 unsigned int sf
, rm
, opcode
, rn
, rd
;
4206 sf
= extract32(insn
, 31, 1);
4207 rm
= extract32(insn
, 16, 5);
4208 opcode
= extract32(insn
, 10, 6);
4209 rn
= extract32(insn
, 5, 5);
4210 rd
= extract32(insn
, 0, 5);
4212 if (extract32(insn
, 29, 1)) {
4213 unallocated_encoding(s
);
4219 handle_div(s
, false, sf
, rm
, rn
, rd
);
4222 handle_div(s
, true, sf
, rm
, rn
, rd
);
4225 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4228 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4231 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4234 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4243 case 23: /* CRC32 */
4245 int sz
= extract32(opcode
, 0, 2);
4246 bool crc32c
= extract32(opcode
, 2, 1);
4247 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4251 unallocated_encoding(s
);
4256 /* C3.5 Data processing - register */
4257 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4259 switch (extract32(insn
, 24, 5)) {
4260 case 0x0a: /* Logical (shifted register) */
4261 disas_logic_reg(s
, insn
);
4263 case 0x0b: /* Add/subtract */
4264 if (insn
& (1 << 21)) { /* (extended register) */
4265 disas_add_sub_ext_reg(s
, insn
);
4267 disas_add_sub_reg(s
, insn
);
4270 case 0x1b: /* Data-processing (3 source) */
4271 disas_data_proc_3src(s
, insn
);
4274 switch (extract32(insn
, 21, 3)) {
4275 case 0x0: /* Add/subtract (with carry) */
4276 disas_adc_sbc(s
, insn
);
4278 case 0x2: /* Conditional compare */
4279 disas_cc(s
, insn
); /* both imm and reg forms */
4281 case 0x4: /* Conditional select */
4282 disas_cond_select(s
, insn
);
4284 case 0x6: /* Data-processing */
4285 if (insn
& (1 << 30)) { /* (1 source) */
4286 disas_data_proc_1src(s
, insn
);
4287 } else { /* (2 source) */
4288 disas_data_proc_2src(s
, insn
);
4292 unallocated_encoding(s
);
4297 unallocated_encoding(s
);
4302 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4303 unsigned int rn
, unsigned int rm
,
4304 bool cmp_with_zero
, bool signal_all_nans
)
4306 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4307 TCGv_ptr fpst
= get_fpstatus_ptr();
4310 TCGv_i64 tcg_vn
, tcg_vm
;
4312 tcg_vn
= read_fp_dreg(s
, rn
);
4313 if (cmp_with_zero
) {
4314 tcg_vm
= tcg_const_i64(0);
4316 tcg_vm
= read_fp_dreg(s
, rm
);
4318 if (signal_all_nans
) {
4319 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4321 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4323 tcg_temp_free_i64(tcg_vn
);
4324 tcg_temp_free_i64(tcg_vm
);
4326 TCGv_i32 tcg_vn
, tcg_vm
;
4328 tcg_vn
= read_fp_sreg(s
, rn
);
4329 if (cmp_with_zero
) {
4330 tcg_vm
= tcg_const_i32(0);
4332 tcg_vm
= read_fp_sreg(s
, rm
);
4334 if (signal_all_nans
) {
4335 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4337 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4339 tcg_temp_free_i32(tcg_vn
);
4340 tcg_temp_free_i32(tcg_vm
);
4343 tcg_temp_free_ptr(fpst
);
4345 gen_set_nzcv(tcg_flags
);
4347 tcg_temp_free_i64(tcg_flags
);
4350 /* C3.6.22 Floating point compare
4351 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4352 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4353 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4354 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4356 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4358 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4360 mos
= extract32(insn
, 29, 3);
4361 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4362 rm
= extract32(insn
, 16, 5);
4363 op
= extract32(insn
, 14, 2);
4364 rn
= extract32(insn
, 5, 5);
4365 opc
= extract32(insn
, 3, 2);
4366 op2r
= extract32(insn
, 0, 3);
4368 if (mos
|| op
|| op2r
|| type
> 1) {
4369 unallocated_encoding(s
);
4373 if (!fp_access_check(s
)) {
4377 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4380 /* C3.6.23 Floating point conditional compare
4381 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4382 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4383 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4384 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4386 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4388 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4390 TCGLabel
*label_continue
= NULL
;
4392 mos
= extract32(insn
, 29, 3);
4393 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4394 rm
= extract32(insn
, 16, 5);
4395 cond
= extract32(insn
, 12, 4);
4396 rn
= extract32(insn
, 5, 5);
4397 op
= extract32(insn
, 4, 1);
4398 nzcv
= extract32(insn
, 0, 4);
4400 if (mos
|| type
> 1) {
4401 unallocated_encoding(s
);
4405 if (!fp_access_check(s
)) {
4409 if (cond
< 0x0e) { /* not always */
4410 TCGLabel
*label_match
= gen_new_label();
4411 label_continue
= gen_new_label();
4412 arm_gen_test_cc(cond
, label_match
);
4414 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4415 gen_set_nzcv(tcg_flags
);
4416 tcg_temp_free_i64(tcg_flags
);
4417 tcg_gen_br(label_continue
);
4418 gen_set_label(label_match
);
4421 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4424 gen_set_label(label_continue
);
4428 /* C3.6.24 Floating point conditional select
4429 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4430 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4431 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4432 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4434 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4436 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4437 TCGv_i64 t_true
, t_false
, t_zero
;
4440 mos
= extract32(insn
, 29, 3);
4441 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4442 rm
= extract32(insn
, 16, 5);
4443 cond
= extract32(insn
, 12, 4);
4444 rn
= extract32(insn
, 5, 5);
4445 rd
= extract32(insn
, 0, 5);
4447 if (mos
|| type
> 1) {
4448 unallocated_encoding(s
);
4452 if (!fp_access_check(s
)) {
4456 /* Zero extend sreg inputs to 64 bits now. */
4457 t_true
= tcg_temp_new_i64();
4458 t_false
= tcg_temp_new_i64();
4459 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4460 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4462 a64_test_cc(&c
, cond
);
4463 t_zero
= tcg_const_i64(0);
4464 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4465 tcg_temp_free_i64(t_zero
);
4466 tcg_temp_free_i64(t_false
);
4469 /* Note that sregs write back zeros to the high bits,
4470 and we've already done the zero-extension. */
4471 write_fp_dreg(s
, rd
, t_true
);
4472 tcg_temp_free_i64(t_true
);
4475 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4476 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4482 fpst
= get_fpstatus_ptr();
4483 tcg_op
= read_fp_sreg(s
, rn
);
4484 tcg_res
= tcg_temp_new_i32();
4487 case 0x0: /* FMOV */
4488 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4490 case 0x1: /* FABS */
4491 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4493 case 0x2: /* FNEG */
4494 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4496 case 0x3: /* FSQRT */
4497 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4499 case 0x8: /* FRINTN */
4500 case 0x9: /* FRINTP */
4501 case 0xa: /* FRINTM */
4502 case 0xb: /* FRINTZ */
4503 case 0xc: /* FRINTA */
4505 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4507 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4508 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4510 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4511 tcg_temp_free_i32(tcg_rmode
);
4514 case 0xe: /* FRINTX */
4515 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4517 case 0xf: /* FRINTI */
4518 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4524 write_fp_sreg(s
, rd
, tcg_res
);
4526 tcg_temp_free_ptr(fpst
);
4527 tcg_temp_free_i32(tcg_op
);
4528 tcg_temp_free_i32(tcg_res
);
4531 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4532 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4538 fpst
= get_fpstatus_ptr();
4539 tcg_op
= read_fp_dreg(s
, rn
);
4540 tcg_res
= tcg_temp_new_i64();
4543 case 0x0: /* FMOV */
4544 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4546 case 0x1: /* FABS */
4547 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4549 case 0x2: /* FNEG */
4550 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4552 case 0x3: /* FSQRT */
4553 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4555 case 0x8: /* FRINTN */
4556 case 0x9: /* FRINTP */
4557 case 0xa: /* FRINTM */
4558 case 0xb: /* FRINTZ */
4559 case 0xc: /* FRINTA */
4561 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4563 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4564 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4566 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4567 tcg_temp_free_i32(tcg_rmode
);
4570 case 0xe: /* FRINTX */
4571 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4573 case 0xf: /* FRINTI */
4574 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4580 write_fp_dreg(s
, rd
, tcg_res
);
4582 tcg_temp_free_ptr(fpst
);
4583 tcg_temp_free_i64(tcg_op
);
4584 tcg_temp_free_i64(tcg_res
);
4587 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4588 int rd
, int rn
, int dtype
, int ntype
)
4593 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4595 /* Single to double */
4596 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4597 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4598 write_fp_dreg(s
, rd
, tcg_rd
);
4599 tcg_temp_free_i64(tcg_rd
);
4601 /* Single to half */
4602 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4603 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4604 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4605 write_fp_sreg(s
, rd
, tcg_rd
);
4606 tcg_temp_free_i32(tcg_rd
);
4608 tcg_temp_free_i32(tcg_rn
);
4613 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4614 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4616 /* Double to single */
4617 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4619 /* Double to half */
4620 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4621 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4623 write_fp_sreg(s
, rd
, tcg_rd
);
4624 tcg_temp_free_i32(tcg_rd
);
4625 tcg_temp_free_i64(tcg_rn
);
4630 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4631 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4633 /* Half to single */
4634 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4635 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4636 write_fp_sreg(s
, rd
, tcg_rd
);
4637 tcg_temp_free_i32(tcg_rd
);
4639 /* Half to double */
4640 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4641 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4642 write_fp_dreg(s
, rd
, tcg_rd
);
4643 tcg_temp_free_i64(tcg_rd
);
4645 tcg_temp_free_i32(tcg_rn
);
4653 /* C3.6.25 Floating point data-processing (1 source)
4654 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4655 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4656 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4657 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4659 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4661 int type
= extract32(insn
, 22, 2);
4662 int opcode
= extract32(insn
, 15, 6);
4663 int rn
= extract32(insn
, 5, 5);
4664 int rd
= extract32(insn
, 0, 5);
4667 case 0x4: case 0x5: case 0x7:
4669 /* FCVT between half, single and double precision */
4670 int dtype
= extract32(opcode
, 0, 2);
4671 if (type
== 2 || dtype
== type
) {
4672 unallocated_encoding(s
);
4675 if (!fp_access_check(s
)) {
4679 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4685 /* 32-to-32 and 64-to-64 ops */
4688 if (!fp_access_check(s
)) {
4692 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4695 if (!fp_access_check(s
)) {
4699 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4702 unallocated_encoding(s
);
4706 unallocated_encoding(s
);
4711 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4712 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4713 int rd
, int rn
, int rm
)
4720 tcg_res
= tcg_temp_new_i32();
4721 fpst
= get_fpstatus_ptr();
4722 tcg_op1
= read_fp_sreg(s
, rn
);
4723 tcg_op2
= read_fp_sreg(s
, rm
);
4726 case 0x0: /* FMUL */
4727 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4729 case 0x1: /* FDIV */
4730 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4732 case 0x2: /* FADD */
4733 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4735 case 0x3: /* FSUB */
4736 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4738 case 0x4: /* FMAX */
4739 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4741 case 0x5: /* FMIN */
4742 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4744 case 0x6: /* FMAXNM */
4745 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4747 case 0x7: /* FMINNM */
4748 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4750 case 0x8: /* FNMUL */
4751 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4752 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4756 write_fp_sreg(s
, rd
, tcg_res
);
4758 tcg_temp_free_ptr(fpst
);
4759 tcg_temp_free_i32(tcg_op1
);
4760 tcg_temp_free_i32(tcg_op2
);
4761 tcg_temp_free_i32(tcg_res
);
4764 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4765 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4766 int rd
, int rn
, int rm
)
4773 tcg_res
= tcg_temp_new_i64();
4774 fpst
= get_fpstatus_ptr();
4775 tcg_op1
= read_fp_dreg(s
, rn
);
4776 tcg_op2
= read_fp_dreg(s
, rm
);
4779 case 0x0: /* FMUL */
4780 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4782 case 0x1: /* FDIV */
4783 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4785 case 0x2: /* FADD */
4786 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4788 case 0x3: /* FSUB */
4789 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4791 case 0x4: /* FMAX */
4792 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4794 case 0x5: /* FMIN */
4795 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4797 case 0x6: /* FMAXNM */
4798 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4800 case 0x7: /* FMINNM */
4801 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4803 case 0x8: /* FNMUL */
4804 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4805 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4809 write_fp_dreg(s
, rd
, tcg_res
);
4811 tcg_temp_free_ptr(fpst
);
4812 tcg_temp_free_i64(tcg_op1
);
4813 tcg_temp_free_i64(tcg_op2
);
4814 tcg_temp_free_i64(tcg_res
);
4817 /* C3.6.26 Floating point data-processing (2 source)
4818 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4819 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4820 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4821 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4823 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4825 int type
= extract32(insn
, 22, 2);
4826 int rd
= extract32(insn
, 0, 5);
4827 int rn
= extract32(insn
, 5, 5);
4828 int rm
= extract32(insn
, 16, 5);
4829 int opcode
= extract32(insn
, 12, 4);
4832 unallocated_encoding(s
);
4838 if (!fp_access_check(s
)) {
4841 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4844 if (!fp_access_check(s
)) {
4847 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4850 unallocated_encoding(s
);
4854 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4855 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4856 int rd
, int rn
, int rm
, int ra
)
4858 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4859 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4860 TCGv_ptr fpst
= get_fpstatus_ptr();
4862 tcg_op1
= read_fp_sreg(s
, rn
);
4863 tcg_op2
= read_fp_sreg(s
, rm
);
4864 tcg_op3
= read_fp_sreg(s
, ra
);
4866 /* These are fused multiply-add, and must be done as one
4867 * floating point operation with no rounding between the
4868 * multiplication and addition steps.
4869 * NB that doing the negations here as separate steps is
4870 * correct : an input NaN should come out with its sign bit
4871 * flipped if it is a negated-input.
4874 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4878 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4881 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4883 write_fp_sreg(s
, rd
, tcg_res
);
4885 tcg_temp_free_ptr(fpst
);
4886 tcg_temp_free_i32(tcg_op1
);
4887 tcg_temp_free_i32(tcg_op2
);
4888 tcg_temp_free_i32(tcg_op3
);
4889 tcg_temp_free_i32(tcg_res
);
4892 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4893 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4894 int rd
, int rn
, int rm
, int ra
)
4896 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4897 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4898 TCGv_ptr fpst
= get_fpstatus_ptr();
4900 tcg_op1
= read_fp_dreg(s
, rn
);
4901 tcg_op2
= read_fp_dreg(s
, rm
);
4902 tcg_op3
= read_fp_dreg(s
, ra
);
4904 /* These are fused multiply-add, and must be done as one
4905 * floating point operation with no rounding between the
4906 * multiplication and addition steps.
4907 * NB that doing the negations here as separate steps is
4908 * correct : an input NaN should come out with its sign bit
4909 * flipped if it is a negated-input.
4912 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4916 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4919 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4921 write_fp_dreg(s
, rd
, tcg_res
);
4923 tcg_temp_free_ptr(fpst
);
4924 tcg_temp_free_i64(tcg_op1
);
4925 tcg_temp_free_i64(tcg_op2
);
4926 tcg_temp_free_i64(tcg_op3
);
4927 tcg_temp_free_i64(tcg_res
);
4930 /* C3.6.27 Floating point data-processing (3 source)
4931 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4932 * +---+---+---+-----------+------+----+------+----+------+------+------+
4933 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4934 * +---+---+---+-----------+------+----+------+----+------+------+------+
4936 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4938 int type
= extract32(insn
, 22, 2);
4939 int rd
= extract32(insn
, 0, 5);
4940 int rn
= extract32(insn
, 5, 5);
4941 int ra
= extract32(insn
, 10, 5);
4942 int rm
= extract32(insn
, 16, 5);
4943 bool o0
= extract32(insn
, 15, 1);
4944 bool o1
= extract32(insn
, 21, 1);
4948 if (!fp_access_check(s
)) {
4951 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4954 if (!fp_access_check(s
)) {
4957 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4960 unallocated_encoding(s
);
4964 /* C3.6.28 Floating point immediate
4965 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4966 * +---+---+---+-----------+------+---+------------+-------+------+------+
4967 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4968 * +---+---+---+-----------+------+---+------------+-------+------+------+
4970 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4972 int rd
= extract32(insn
, 0, 5);
4973 int imm8
= extract32(insn
, 13, 8);
4974 int is_double
= extract32(insn
, 22, 2);
4978 if (is_double
> 1) {
4979 unallocated_encoding(s
);
4983 if (!fp_access_check(s
)) {
4987 /* The imm8 encodes the sign bit, enough bits to represent
4988 * an exponent in the range 01....1xx to 10....0xx,
4989 * and the most significant 4 bits of the mantissa; see
4990 * VFPExpandImm() in the v8 ARM ARM.
4993 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4994 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4995 extract32(imm8
, 0, 6);
4998 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4999 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5000 (extract32(imm8
, 0, 6) << 3);
5004 tcg_res
= tcg_const_i64(imm
);
5005 write_fp_dreg(s
, rd
, tcg_res
);
5006 tcg_temp_free_i64(tcg_res
);
5009 /* Handle floating point <=> fixed point conversions. Note that we can
5010 * also deal with fp <=> integer conversions as a special case (scale == 64)
5011 * OPTME: consider handling that special case specially or at least skipping
5012 * the call to scalbn in the helpers for zero shifts.
5014 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5015 bool itof
, int rmode
, int scale
, int sf
, int type
)
5017 bool is_signed
= !(opcode
& 1);
5018 bool is_double
= type
;
5019 TCGv_ptr tcg_fpstatus
;
5022 tcg_fpstatus
= get_fpstatus_ptr();
5024 tcg_shift
= tcg_const_i32(64 - scale
);
5027 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5029 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5032 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5034 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5037 tcg_int
= tcg_extend
;
5041 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5043 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5044 tcg_shift
, tcg_fpstatus
);
5046 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5047 tcg_shift
, tcg_fpstatus
);
5049 write_fp_dreg(s
, rd
, tcg_double
);
5050 tcg_temp_free_i64(tcg_double
);
5052 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5054 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5055 tcg_shift
, tcg_fpstatus
);
5057 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5058 tcg_shift
, tcg_fpstatus
);
5060 write_fp_sreg(s
, rd
, tcg_single
);
5061 tcg_temp_free_i32(tcg_single
);
5064 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5067 if (extract32(opcode
, 2, 1)) {
5068 /* There are too many rounding modes to all fit into rmode,
5069 * so FCVTA[US] is a special case.
5071 rmode
= FPROUNDING_TIEAWAY
;
5074 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5076 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5079 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5082 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5083 tcg_shift
, tcg_fpstatus
);
5085 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5086 tcg_shift
, tcg_fpstatus
);
5090 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5091 tcg_shift
, tcg_fpstatus
);
5093 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5094 tcg_shift
, tcg_fpstatus
);
5097 tcg_temp_free_i64(tcg_double
);
5099 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5102 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5103 tcg_shift
, tcg_fpstatus
);
5105 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5106 tcg_shift
, tcg_fpstatus
);
5109 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5111 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5112 tcg_shift
, tcg_fpstatus
);
5114 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5115 tcg_shift
, tcg_fpstatus
);
5117 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5118 tcg_temp_free_i32(tcg_dest
);
5120 tcg_temp_free_i32(tcg_single
);
5123 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5124 tcg_temp_free_i32(tcg_rmode
);
5127 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5131 tcg_temp_free_ptr(tcg_fpstatus
);
5132 tcg_temp_free_i32(tcg_shift
);
5135 /* C3.6.29 Floating point <-> fixed point conversions
5136 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5137 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5138 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5139 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5141 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5143 int rd
= extract32(insn
, 0, 5);
5144 int rn
= extract32(insn
, 5, 5);
5145 int scale
= extract32(insn
, 10, 6);
5146 int opcode
= extract32(insn
, 16, 3);
5147 int rmode
= extract32(insn
, 19, 2);
5148 int type
= extract32(insn
, 22, 2);
5149 bool sbit
= extract32(insn
, 29, 1);
5150 bool sf
= extract32(insn
, 31, 1);
5153 if (sbit
|| (type
> 1)
5154 || (!sf
&& scale
< 32)) {
5155 unallocated_encoding(s
);
5159 switch ((rmode
<< 3) | opcode
) {
5160 case 0x2: /* SCVTF */
5161 case 0x3: /* UCVTF */
5164 case 0x18: /* FCVTZS */
5165 case 0x19: /* FCVTZU */
5169 unallocated_encoding(s
);
5173 if (!fp_access_check(s
)) {
5177 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5180 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5182 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5183 * without conversion.
5187 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5193 TCGv_i64 tmp
= tcg_temp_new_i64();
5194 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5195 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5196 tcg_gen_movi_i64(tmp
, 0);
5197 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5198 tcg_temp_free_i64(tmp
);
5204 TCGv_i64 tmp
= tcg_const_i64(0);
5205 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5206 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5207 tcg_temp_free_i64(tmp
);
5211 /* 64 bit to top half. */
5212 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5216 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5221 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5225 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5228 /* 64 bits from top half */
5229 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5235 /* C3.6.30 Floating point <-> integer conversions
5236 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5237 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5238 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5239 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5241 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5243 int rd
= extract32(insn
, 0, 5);
5244 int rn
= extract32(insn
, 5, 5);
5245 int opcode
= extract32(insn
, 16, 3);
5246 int rmode
= extract32(insn
, 19, 2);
5247 int type
= extract32(insn
, 22, 2);
5248 bool sbit
= extract32(insn
, 29, 1);
5249 bool sf
= extract32(insn
, 31, 1);
5252 unallocated_encoding(s
);
5258 bool itof
= opcode
& 1;
5261 unallocated_encoding(s
);
5265 switch (sf
<< 3 | type
<< 1 | rmode
) {
5266 case 0x0: /* 32 bit */
5267 case 0xa: /* 64 bit */
5268 case 0xd: /* 64 bit to top half of quad */
5271 /* all other sf/type/rmode combinations are invalid */
5272 unallocated_encoding(s
);
5276 if (!fp_access_check(s
)) {
5279 handle_fmov(s
, rd
, rn
, type
, itof
);
5281 /* actual FP conversions */
5282 bool itof
= extract32(opcode
, 1, 1);
5284 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5285 unallocated_encoding(s
);
5289 if (!fp_access_check(s
)) {
5292 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5296 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5297 * 31 30 29 28 25 24 0
5298 * +---+---+---+---------+-----------------------------+
5299 * | | 0 | | 1 1 1 1 | |
5300 * +---+---+---+---------+-----------------------------+
5302 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5304 if (extract32(insn
, 24, 1)) {
5305 /* Floating point data-processing (3 source) */
5306 disas_fp_3src(s
, insn
);
5307 } else if (extract32(insn
, 21, 1) == 0) {
5308 /* Floating point to fixed point conversions */
5309 disas_fp_fixed_conv(s
, insn
);
5311 switch (extract32(insn
, 10, 2)) {
5313 /* Floating point conditional compare */
5314 disas_fp_ccomp(s
, insn
);
5317 /* Floating point data-processing (2 source) */
5318 disas_fp_2src(s
, insn
);
5321 /* Floating point conditional select */
5322 disas_fp_csel(s
, insn
);
5325 switch (ctz32(extract32(insn
, 12, 4))) {
5326 case 0: /* [15:12] == xxx1 */
5327 /* Floating point immediate */
5328 disas_fp_imm(s
, insn
);
5330 case 1: /* [15:12] == xx10 */
5331 /* Floating point compare */
5332 disas_fp_compare(s
, insn
);
5334 case 2: /* [15:12] == x100 */
5335 /* Floating point data-processing (1 source) */
5336 disas_fp_1src(s
, insn
);
5338 case 3: /* [15:12] == 1000 */
5339 unallocated_encoding(s
);
5341 default: /* [15:12] == 0000 */
5342 /* Floating point <-> integer conversions */
5343 disas_fp_int_conv(s
, insn
);
5351 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5354 /* Extract 64 bits from the middle of two concatenated 64 bit
5355 * vector register slices left:right. The extracted bits start
5356 * at 'pos' bits into the right (least significant) side.
5357 * We return the result in tcg_right, and guarantee not to
5360 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5361 assert(pos
> 0 && pos
< 64);
5363 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5364 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5365 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5367 tcg_temp_free_i64(tcg_tmp
);
5371 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5372 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5373 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5374 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5376 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5378 int is_q
= extract32(insn
, 30, 1);
5379 int op2
= extract32(insn
, 22, 2);
5380 int imm4
= extract32(insn
, 11, 4);
5381 int rm
= extract32(insn
, 16, 5);
5382 int rn
= extract32(insn
, 5, 5);
5383 int rd
= extract32(insn
, 0, 5);
5384 int pos
= imm4
<< 3;
5385 TCGv_i64 tcg_resl
, tcg_resh
;
5387 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5388 unallocated_encoding(s
);
5392 if (!fp_access_check(s
)) {
5396 tcg_resh
= tcg_temp_new_i64();
5397 tcg_resl
= tcg_temp_new_i64();
5399 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5400 * either extracting 128 bits from a 128:128 concatenation, or
5401 * extracting 64 bits from a 64:64 concatenation.
5404 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5406 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5407 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5409 tcg_gen_movi_i64(tcg_resh
, 0);
5416 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5417 EltPosns
*elt
= eltposns
;
5424 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5426 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5429 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5430 tcg_hh
= tcg_temp_new_i64();
5431 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5432 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5433 tcg_temp_free_i64(tcg_hh
);
5437 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5438 tcg_temp_free_i64(tcg_resl
);
5439 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5440 tcg_temp_free_i64(tcg_resh
);
5444 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5445 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5446 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5447 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5449 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5451 int op2
= extract32(insn
, 22, 2);
5452 int is_q
= extract32(insn
, 30, 1);
5453 int rm
= extract32(insn
, 16, 5);
5454 int rn
= extract32(insn
, 5, 5);
5455 int rd
= extract32(insn
, 0, 5);
5456 int is_tblx
= extract32(insn
, 12, 1);
5457 int len
= extract32(insn
, 13, 2);
5458 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5459 TCGv_i32 tcg_regno
, tcg_numregs
;
5462 unallocated_encoding(s
);
5466 if (!fp_access_check(s
)) {
5470 /* This does a table lookup: for every byte element in the input
5471 * we index into a table formed from up to four vector registers,
5472 * and then the output is the result of the lookups. Our helper
5473 * function does the lookup operation for a single 64 bit part of
5476 tcg_resl
= tcg_temp_new_i64();
5477 tcg_resh
= tcg_temp_new_i64();
5480 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5482 tcg_gen_movi_i64(tcg_resl
, 0);
5484 if (is_tblx
&& is_q
) {
5485 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5487 tcg_gen_movi_i64(tcg_resh
, 0);
5490 tcg_idx
= tcg_temp_new_i64();
5491 tcg_regno
= tcg_const_i32(rn
);
5492 tcg_numregs
= tcg_const_i32(len
+ 1);
5493 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5494 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5495 tcg_regno
, tcg_numregs
);
5497 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5498 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5499 tcg_regno
, tcg_numregs
);
5501 tcg_temp_free_i64(tcg_idx
);
5502 tcg_temp_free_i32(tcg_regno
);
5503 tcg_temp_free_i32(tcg_numregs
);
5505 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5506 tcg_temp_free_i64(tcg_resl
);
5507 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5508 tcg_temp_free_i64(tcg_resh
);
5511 /* C3.6.3 ZIP/UZP/TRN
5512 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5513 * +---+---+-------------+------+---+------+---+------------------+------+
5514 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5515 * +---+---+-------------+------+---+------+---+------------------+------+
5517 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5519 int rd
= extract32(insn
, 0, 5);
5520 int rn
= extract32(insn
, 5, 5);
5521 int rm
= extract32(insn
, 16, 5);
5522 int size
= extract32(insn
, 22, 2);
5523 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5524 * bit 2 indicates 1 vs 2 variant of the insn.
5526 int opcode
= extract32(insn
, 12, 2);
5527 bool part
= extract32(insn
, 14, 1);
5528 bool is_q
= extract32(insn
, 30, 1);
5529 int esize
= 8 << size
;
5531 int datasize
= is_q
? 128 : 64;
5532 int elements
= datasize
/ esize
;
5533 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5535 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5536 unallocated_encoding(s
);
5540 if (!fp_access_check(s
)) {
5544 tcg_resl
= tcg_const_i64(0);
5545 tcg_resh
= tcg_const_i64(0);
5546 tcg_res
= tcg_temp_new_i64();
5548 for (i
= 0; i
< elements
; i
++) {
5550 case 1: /* UZP1/2 */
5552 int midpoint
= elements
/ 2;
5554 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5556 read_vec_element(s
, tcg_res
, rm
,
5557 2 * (i
- midpoint
) + part
, size
);
5561 case 2: /* TRN1/2 */
5563 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5565 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5568 case 3: /* ZIP1/2 */
5570 int base
= part
* elements
/ 2;
5572 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5574 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5579 g_assert_not_reached();
5584 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5585 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5587 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5588 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5592 tcg_temp_free_i64(tcg_res
);
5594 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5595 tcg_temp_free_i64(tcg_resl
);
5596 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5597 tcg_temp_free_i64(tcg_resh
);
5600 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5601 int opc
, bool is_min
, TCGv_ptr fpst
)
5603 /* Helper function for disas_simd_across_lanes: do a single precision
5604 * min/max operation on the specified two inputs,
5605 * and return the result in tcg_elt1.
5609 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5611 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5616 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5618 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5623 /* C3.6.4 AdvSIMD across lanes
5624 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5625 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5626 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5627 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5629 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5631 int rd
= extract32(insn
, 0, 5);
5632 int rn
= extract32(insn
, 5, 5);
5633 int size
= extract32(insn
, 22, 2);
5634 int opcode
= extract32(insn
, 12, 5);
5635 bool is_q
= extract32(insn
, 30, 1);
5636 bool is_u
= extract32(insn
, 29, 1);
5638 bool is_min
= false;
5642 TCGv_i64 tcg_res
, tcg_elt
;
5645 case 0x1b: /* ADDV */
5647 unallocated_encoding(s
);
5651 case 0x3: /* SADDLV, UADDLV */
5652 case 0xa: /* SMAXV, UMAXV */
5653 case 0x1a: /* SMINV, UMINV */
5654 if (size
== 3 || (size
== 2 && !is_q
)) {
5655 unallocated_encoding(s
);
5659 case 0xc: /* FMAXNMV, FMINNMV */
5660 case 0xf: /* FMAXV, FMINV */
5661 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5662 unallocated_encoding(s
);
5665 /* Bit 1 of size field encodes min vs max, and actual size is always
5666 * 32 bits: adjust the size variable so following code can rely on it
5668 is_min
= extract32(size
, 1, 1);
5673 unallocated_encoding(s
);
5677 if (!fp_access_check(s
)) {
5682 elements
= (is_q
? 128 : 64) / esize
;
5684 tcg_res
= tcg_temp_new_i64();
5685 tcg_elt
= tcg_temp_new_i64();
5687 /* These instructions operate across all lanes of a vector
5688 * to produce a single result. We can guarantee that a 64
5689 * bit intermediate is sufficient:
5690 * + for [US]ADDLV the maximum element size is 32 bits, and
5691 * the result type is 64 bits
5692 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5693 * same as the element size, which is 32 bits at most
5694 * For the integer operations we can choose to work at 64
5695 * or 32 bits and truncate at the end; for simplicity
5696 * we use 64 bits always. The floating point
5697 * ops do require 32 bit intermediates, though.
5700 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5702 for (i
= 1; i
< elements
; i
++) {
5703 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5706 case 0x03: /* SADDLV / UADDLV */
5707 case 0x1b: /* ADDV */
5708 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5710 case 0x0a: /* SMAXV / UMAXV */
5711 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5713 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5715 case 0x1a: /* SMINV / UMINV */
5716 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5718 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5722 g_assert_not_reached();
5727 /* Floating point ops which work on 32 bit (single) intermediates.
5728 * Note that correct NaN propagation requires that we do these
5729 * operations in exactly the order specified by the pseudocode.
5731 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5732 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5733 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5734 TCGv_ptr fpst
= get_fpstatus_ptr();
5736 assert(esize
== 32);
5737 assert(elements
== 4);
5739 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5740 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5741 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5742 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5744 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5746 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5747 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5748 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5749 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5751 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5753 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5755 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5756 tcg_temp_free_i32(tcg_elt1
);
5757 tcg_temp_free_i32(tcg_elt2
);
5758 tcg_temp_free_i32(tcg_elt3
);
5759 tcg_temp_free_ptr(fpst
);
5762 tcg_temp_free_i64(tcg_elt
);
5764 /* Now truncate the result to the width required for the final output */
5765 if (opcode
== 0x03) {
5766 /* SADDLV, UADDLV: result is 2*esize */
5772 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5775 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5778 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5783 g_assert_not_reached();
5786 write_fp_dreg(s
, rd
, tcg_res
);
5787 tcg_temp_free_i64(tcg_res
);
5790 /* C6.3.31 DUP (Element, Vector)
5792 * 31 30 29 21 20 16 15 10 9 5 4 0
5793 * +---+---+-------------------+--------+-------------+------+------+
5794 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5795 * +---+---+-------------------+--------+-------------+------+------+
5797 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5799 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5802 int size
= ctz32(imm5
);
5803 int esize
= 8 << size
;
5804 int elements
= (is_q
? 128 : 64) / esize
;
5808 if (size
> 3 || (size
== 3 && !is_q
)) {
5809 unallocated_encoding(s
);
5813 if (!fp_access_check(s
)) {
5817 index
= imm5
>> (size
+ 1);
5819 tmp
= tcg_temp_new_i64();
5820 read_vec_element(s
, tmp
, rn
, index
, size
);
5822 for (i
= 0; i
< elements
; i
++) {
5823 write_vec_element(s
, tmp
, rd
, i
, size
);
5827 clear_vec_high(s
, rd
);
5830 tcg_temp_free_i64(tmp
);
5833 /* C6.3.31 DUP (element, scalar)
5834 * 31 21 20 16 15 10 9 5 4 0
5835 * +-----------------------+--------+-------------+------+------+
5836 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5837 * +-----------------------+--------+-------------+------+------+
5839 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5842 int size
= ctz32(imm5
);
5847 unallocated_encoding(s
);
5851 if (!fp_access_check(s
)) {
5855 index
= imm5
>> (size
+ 1);
5857 /* This instruction just extracts the specified element and
5858 * zero-extends it into the bottom of the destination register.
5860 tmp
= tcg_temp_new_i64();
5861 read_vec_element(s
, tmp
, rn
, index
, size
);
5862 write_fp_dreg(s
, rd
, tmp
);
5863 tcg_temp_free_i64(tmp
);
5866 /* C6.3.32 DUP (General)
5868 * 31 30 29 21 20 16 15 10 9 5 4 0
5869 * +---+---+-------------------+--------+-------------+------+------+
5870 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5871 * +---+---+-------------------+--------+-------------+------+------+
5873 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5875 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5878 int size
= ctz32(imm5
);
5879 int esize
= 8 << size
;
5880 int elements
= (is_q
? 128 : 64)/esize
;
5883 if (size
> 3 || ((size
== 3) && !is_q
)) {
5884 unallocated_encoding(s
);
5888 if (!fp_access_check(s
)) {
5892 for (i
= 0; i
< elements
; i
++) {
5893 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5896 clear_vec_high(s
, rd
);
5900 /* C6.3.150 INS (Element)
5902 * 31 21 20 16 15 14 11 10 9 5 4 0
5903 * +-----------------------+--------+------------+---+------+------+
5904 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5905 * +-----------------------+--------+------------+---+------+------+
5907 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5908 * index: encoded in imm5<4:size+1>
5910 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5913 int size
= ctz32(imm5
);
5914 int src_index
, dst_index
;
5918 unallocated_encoding(s
);
5922 if (!fp_access_check(s
)) {
5926 dst_index
= extract32(imm5
, 1+size
, 5);
5927 src_index
= extract32(imm4
, size
, 4);
5929 tmp
= tcg_temp_new_i64();
5931 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5932 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5934 tcg_temp_free_i64(tmp
);
5938 /* C6.3.151 INS (General)
5940 * 31 21 20 16 15 10 9 5 4 0
5941 * +-----------------------+--------+-------------+------+------+
5942 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5943 * +-----------------------+--------+-------------+------+------+
5945 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5946 * index: encoded in imm5<4:size+1>
5948 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5950 int size
= ctz32(imm5
);
5954 unallocated_encoding(s
);
5958 if (!fp_access_check(s
)) {
5962 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5963 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5967 * C6.3.321 UMOV (General)
5968 * C6.3.237 SMOV (General)
5970 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5971 * +---+---+-------------------+--------+-------------+------+------+
5972 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5973 * +---+---+-------------------+--------+-------------+------+------+
5975 * U: unsigned when set
5976 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5978 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5979 int rn
, int rd
, int imm5
)
5981 int size
= ctz32(imm5
);
5985 /* Check for UnallocatedEncodings */
5987 if (size
> 2 || (size
== 2 && !is_q
)) {
5988 unallocated_encoding(s
);
5993 || (size
< 3 && is_q
)
5994 || (size
== 3 && !is_q
)) {
5995 unallocated_encoding(s
);
6000 if (!fp_access_check(s
)) {
6004 element
= extract32(imm5
, 1+size
, 4);
6006 tcg_rd
= cpu_reg(s
, rd
);
6007 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6008 if (is_signed
&& !is_q
) {
6009 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6013 /* C3.6.5 AdvSIMD copy
6014 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6015 * +---+---+----+-----------------+------+---+------+---+------+------+
6016 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6017 * +---+---+----+-----------------+------+---+------+---+------+------+
6019 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6021 int rd
= extract32(insn
, 0, 5);
6022 int rn
= extract32(insn
, 5, 5);
6023 int imm4
= extract32(insn
, 11, 4);
6024 int op
= extract32(insn
, 29, 1);
6025 int is_q
= extract32(insn
, 30, 1);
6026 int imm5
= extract32(insn
, 16, 5);
6031 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6033 unallocated_encoding(s
);
6038 /* DUP (element - vector) */
6039 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6043 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6048 handle_simd_insg(s
, rd
, rn
, imm5
);
6050 unallocated_encoding(s
);
6055 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6056 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6059 unallocated_encoding(s
);
6065 /* C3.6.6 AdvSIMD modified immediate
6066 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6067 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6068 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6069 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6071 * There are a number of operations that can be carried out here:
6072 * MOVI - move (shifted) imm into register
6073 * MVNI - move inverted (shifted) imm into register
6074 * ORR - bitwise OR of (shifted) imm with register
6075 * BIC - bitwise clear of (shifted) imm with register
6077 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6079 int rd
= extract32(insn
, 0, 5);
6080 int cmode
= extract32(insn
, 12, 4);
6081 int cmode_3_1
= extract32(cmode
, 1, 3);
6082 int cmode_0
= extract32(cmode
, 0, 1);
6083 int o2
= extract32(insn
, 11, 1);
6084 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6085 bool is_neg
= extract32(insn
, 29, 1);
6086 bool is_q
= extract32(insn
, 30, 1);
6088 TCGv_i64 tcg_rd
, tcg_imm
;
6091 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6092 unallocated_encoding(s
);
6096 if (!fp_access_check(s
)) {
6100 /* See AdvSIMDExpandImm() in ARM ARM */
6101 switch (cmode_3_1
) {
6102 case 0: /* Replicate(Zeros(24):imm8, 2) */
6103 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6104 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6105 case 3: /* Replicate(imm8:Zeros(24), 2) */
6107 int shift
= cmode_3_1
* 8;
6108 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6111 case 4: /* Replicate(Zeros(8):imm8, 4) */
6112 case 5: /* Replicate(imm8:Zeros(8), 4) */
6114 int shift
= (cmode_3_1
& 0x1) * 8;
6115 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6120 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6121 imm
= (abcdefgh
<< 16) | 0xffff;
6123 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6124 imm
= (abcdefgh
<< 8) | 0xff;
6126 imm
= bitfield_replicate(imm
, 32);
6129 if (!cmode_0
&& !is_neg
) {
6130 imm
= bitfield_replicate(abcdefgh
, 8);
6131 } else if (!cmode_0
&& is_neg
) {
6134 for (i
= 0; i
< 8; i
++) {
6135 if ((abcdefgh
) & (1 << i
)) {
6136 imm
|= 0xffULL
<< (i
* 8);
6139 } else if (cmode_0
) {
6141 imm
= (abcdefgh
& 0x3f) << 48;
6142 if (abcdefgh
& 0x80) {
6143 imm
|= 0x8000000000000000ULL
;
6145 if (abcdefgh
& 0x40) {
6146 imm
|= 0x3fc0000000000000ULL
;
6148 imm
|= 0x4000000000000000ULL
;
6151 imm
= (abcdefgh
& 0x3f) << 19;
6152 if (abcdefgh
& 0x80) {
6155 if (abcdefgh
& 0x40) {
6166 if (cmode_3_1
!= 7 && is_neg
) {
6170 tcg_imm
= tcg_const_i64(imm
);
6171 tcg_rd
= new_tmp_a64(s
);
6173 for (i
= 0; i
< 2; i
++) {
6174 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6176 if (i
== 1 && !is_q
) {
6177 /* non-quad ops clear high half of vector */
6178 tcg_gen_movi_i64(tcg_rd
, 0);
6179 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6180 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6183 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6186 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6190 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6192 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6195 tcg_temp_free_i64(tcg_imm
);
6198 /* C3.6.7 AdvSIMD scalar copy
6199 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6200 * +-----+----+-----------------+------+---+------+---+------+------+
6201 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6202 * +-----+----+-----------------+------+---+------+---+------+------+
6204 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6206 int rd
= extract32(insn
, 0, 5);
6207 int rn
= extract32(insn
, 5, 5);
6208 int imm4
= extract32(insn
, 11, 4);
6209 int imm5
= extract32(insn
, 16, 5);
6210 int op
= extract32(insn
, 29, 1);
6212 if (op
!= 0 || imm4
!= 0) {
6213 unallocated_encoding(s
);
6217 /* DUP (element, scalar) */
6218 handle_simd_dupes(s
, rd
, rn
, imm5
);
6221 /* C3.6.8 AdvSIMD scalar pairwise
6222 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6223 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6224 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6225 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6227 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6229 int u
= extract32(insn
, 29, 1);
6230 int size
= extract32(insn
, 22, 2);
6231 int opcode
= extract32(insn
, 12, 5);
6232 int rn
= extract32(insn
, 5, 5);
6233 int rd
= extract32(insn
, 0, 5);
6236 /* For some ops (the FP ones), size[1] is part of the encoding.
6237 * For ADDP strictly it is not but size[1] is always 1 for valid
6240 opcode
|= (extract32(size
, 1, 1) << 5);
6243 case 0x3b: /* ADDP */
6244 if (u
|| size
!= 3) {
6245 unallocated_encoding(s
);
6248 if (!fp_access_check(s
)) {
6252 TCGV_UNUSED_PTR(fpst
);
6254 case 0xc: /* FMAXNMP */
6255 case 0xd: /* FADDP */
6256 case 0xf: /* FMAXP */
6257 case 0x2c: /* FMINNMP */
6258 case 0x2f: /* FMINP */
6259 /* FP op, size[0] is 32 or 64 bit */
6261 unallocated_encoding(s
);
6264 if (!fp_access_check(s
)) {
6268 size
= extract32(size
, 0, 1) ? 3 : 2;
6269 fpst
= get_fpstatus_ptr();
6272 unallocated_encoding(s
);
6277 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6278 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6279 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6281 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6282 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6285 case 0x3b: /* ADDP */
6286 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6288 case 0xc: /* FMAXNMP */
6289 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6291 case 0xd: /* FADDP */
6292 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6294 case 0xf: /* FMAXP */
6295 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6297 case 0x2c: /* FMINNMP */
6298 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6300 case 0x2f: /* FMINP */
6301 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6304 g_assert_not_reached();
6307 write_fp_dreg(s
, rd
, tcg_res
);
6309 tcg_temp_free_i64(tcg_op1
);
6310 tcg_temp_free_i64(tcg_op2
);
6311 tcg_temp_free_i64(tcg_res
);
6313 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6314 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6315 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6317 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6318 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6321 case 0xc: /* FMAXNMP */
6322 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6324 case 0xd: /* FADDP */
6325 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6327 case 0xf: /* FMAXP */
6328 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6330 case 0x2c: /* FMINNMP */
6331 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6333 case 0x2f: /* FMINP */
6334 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6337 g_assert_not_reached();
6340 write_fp_sreg(s
, rd
, tcg_res
);
6342 tcg_temp_free_i32(tcg_op1
);
6343 tcg_temp_free_i32(tcg_op2
);
6344 tcg_temp_free_i32(tcg_res
);
6347 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6348 tcg_temp_free_ptr(fpst
);
6353 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6355 * This code is handles the common shifting code and is used by both
6356 * the vector and scalar code.
6358 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6359 TCGv_i64 tcg_rnd
, bool accumulate
,
6360 bool is_u
, int size
, int shift
)
6362 bool extended_result
= false;
6363 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6365 TCGv_i64 tcg_src_hi
;
6367 if (round
&& size
== 3) {
6368 extended_result
= true;
6369 ext_lshift
= 64 - shift
;
6370 tcg_src_hi
= tcg_temp_new_i64();
6371 } else if (shift
== 64) {
6372 if (!accumulate
&& is_u
) {
6373 /* result is zero */
6374 tcg_gen_movi_i64(tcg_res
, 0);
6379 /* Deal with the rounding step */
6381 if (extended_result
) {
6382 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6384 /* take care of sign extending tcg_res */
6385 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6386 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6387 tcg_src
, tcg_src_hi
,
6390 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6394 tcg_temp_free_i64(tcg_zero
);
6396 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6400 /* Now do the shift right */
6401 if (round
&& extended_result
) {
6402 /* extended case, >64 bit precision required */
6403 if (ext_lshift
== 0) {
6404 /* special case, only high bits matter */
6405 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6407 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6408 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6409 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6414 /* essentially shifting in 64 zeros */
6415 tcg_gen_movi_i64(tcg_src
, 0);
6417 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6421 /* effectively extending the sign-bit */
6422 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6424 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6430 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6432 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6435 if (extended_result
) {
6436 tcg_temp_free_i64(tcg_src_hi
);
6440 /* Common SHL/SLI - Shift left with an optional insert */
6441 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6442 bool insert
, int shift
)
6444 if (insert
) { /* SLI */
6445 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6447 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6451 /* SRI: shift right with insert */
6452 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6453 int size
, int shift
)
6455 int esize
= 8 << size
;
6457 /* shift count same as element size is valid but does nothing;
6458 * special case to avoid potential shift by 64.
6460 if (shift
!= esize
) {
6461 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6462 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6466 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6467 static void handle_scalar_simd_shri(DisasContext
*s
,
6468 bool is_u
, int immh
, int immb
,
6469 int opcode
, int rn
, int rd
)
6472 int immhb
= immh
<< 3 | immb
;
6473 int shift
= 2 * (8 << size
) - immhb
;
6474 bool accumulate
= false;
6476 bool insert
= false;
6481 if (!extract32(immh
, 3, 1)) {
6482 unallocated_encoding(s
);
6486 if (!fp_access_check(s
)) {
6491 case 0x02: /* SSRA / USRA (accumulate) */
6494 case 0x04: /* SRSHR / URSHR (rounding) */
6497 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6498 accumulate
= round
= true;
6500 case 0x08: /* SRI */
6506 uint64_t round_const
= 1ULL << (shift
- 1);
6507 tcg_round
= tcg_const_i64(round_const
);
6509 TCGV_UNUSED_I64(tcg_round
);
6512 tcg_rn
= read_fp_dreg(s
, rn
);
6513 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6516 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6518 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6519 accumulate
, is_u
, size
, shift
);
6522 write_fp_dreg(s
, rd
, tcg_rd
);
6524 tcg_temp_free_i64(tcg_rn
);
6525 tcg_temp_free_i64(tcg_rd
);
6527 tcg_temp_free_i64(tcg_round
);
6531 /* SHL/SLI - Scalar shift left */
6532 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6533 int immh
, int immb
, int opcode
,
6536 int size
= 32 - clz32(immh
) - 1;
6537 int immhb
= immh
<< 3 | immb
;
6538 int shift
= immhb
- (8 << size
);
6539 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6540 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6542 if (!extract32(immh
, 3, 1)) {
6543 unallocated_encoding(s
);
6547 if (!fp_access_check(s
)) {
6551 tcg_rn
= read_fp_dreg(s
, rn
);
6552 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6554 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6556 write_fp_dreg(s
, rd
, tcg_rd
);
6558 tcg_temp_free_i64(tcg_rn
);
6559 tcg_temp_free_i64(tcg_rd
);
6562 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6563 * (signed/unsigned) narrowing */
6564 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6565 bool is_u_shift
, bool is_u_narrow
,
6566 int immh
, int immb
, int opcode
,
6569 int immhb
= immh
<< 3 | immb
;
6570 int size
= 32 - clz32(immh
) - 1;
6571 int esize
= 8 << size
;
6572 int shift
= (2 * esize
) - immhb
;
6573 int elements
= is_scalar
? 1 : (64 / esize
);
6574 bool round
= extract32(opcode
, 0, 1);
6575 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6576 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6577 TCGv_i32 tcg_rd_narrowed
;
6580 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6581 { gen_helper_neon_narrow_sat_s8
,
6582 gen_helper_neon_unarrow_sat8
},
6583 { gen_helper_neon_narrow_sat_s16
,
6584 gen_helper_neon_unarrow_sat16
},
6585 { gen_helper_neon_narrow_sat_s32
,
6586 gen_helper_neon_unarrow_sat32
},
6589 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6590 gen_helper_neon_narrow_sat_u8
,
6591 gen_helper_neon_narrow_sat_u16
,
6592 gen_helper_neon_narrow_sat_u32
,
6595 NeonGenNarrowEnvFn
*narrowfn
;
6601 if (extract32(immh
, 3, 1)) {
6602 unallocated_encoding(s
);
6606 if (!fp_access_check(s
)) {
6611 narrowfn
= unsigned_narrow_fns
[size
];
6613 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6616 tcg_rn
= tcg_temp_new_i64();
6617 tcg_rd
= tcg_temp_new_i64();
6618 tcg_rd_narrowed
= tcg_temp_new_i32();
6619 tcg_final
= tcg_const_i64(0);
6622 uint64_t round_const
= 1ULL << (shift
- 1);
6623 tcg_round
= tcg_const_i64(round_const
);
6625 TCGV_UNUSED_I64(tcg_round
);
6628 for (i
= 0; i
< elements
; i
++) {
6629 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6630 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6631 false, is_u_shift
, size
+1, shift
);
6632 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6633 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6634 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6638 clear_vec_high(s
, rd
);
6639 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6641 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6645 tcg_temp_free_i64(tcg_round
);
6647 tcg_temp_free_i64(tcg_rn
);
6648 tcg_temp_free_i64(tcg_rd
);
6649 tcg_temp_free_i32(tcg_rd_narrowed
);
6650 tcg_temp_free_i64(tcg_final
);
6654 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6655 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6656 bool src_unsigned
, bool dst_unsigned
,
6657 int immh
, int immb
, int rn
, int rd
)
6659 int immhb
= immh
<< 3 | immb
;
6660 int size
= 32 - clz32(immh
) - 1;
6661 int shift
= immhb
- (8 << size
);
6665 assert(!(scalar
&& is_q
));
6668 if (!is_q
&& extract32(immh
, 3, 1)) {
6669 unallocated_encoding(s
);
6673 /* Since we use the variable-shift helpers we must
6674 * replicate the shift count into each element of
6675 * the tcg_shift value.
6679 shift
|= shift
<< 8;
6682 shift
|= shift
<< 16;
6688 g_assert_not_reached();
6692 if (!fp_access_check(s
)) {
6697 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6698 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6699 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6700 { NULL
, gen_helper_neon_qshl_u64
},
6702 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6703 int maxpass
= is_q
? 2 : 1;
6705 for (pass
= 0; pass
< maxpass
; pass
++) {
6706 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6708 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6709 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6710 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6712 tcg_temp_free_i64(tcg_op
);
6714 tcg_temp_free_i64(tcg_shift
);
6717 clear_vec_high(s
, rd
);
6720 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6721 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6723 { gen_helper_neon_qshl_s8
,
6724 gen_helper_neon_qshl_s16
,
6725 gen_helper_neon_qshl_s32
},
6726 { gen_helper_neon_qshlu_s8
,
6727 gen_helper_neon_qshlu_s16
,
6728 gen_helper_neon_qshlu_s32
}
6730 { NULL
, NULL
, NULL
},
6731 { gen_helper_neon_qshl_u8
,
6732 gen_helper_neon_qshl_u16
,
6733 gen_helper_neon_qshl_u32
}
6736 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6737 TCGMemOp memop
= scalar
? size
: MO_32
;
6738 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6740 for (pass
= 0; pass
< maxpass
; pass
++) {
6741 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6743 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6744 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6748 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6751 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6756 g_assert_not_reached();
6758 write_fp_sreg(s
, rd
, tcg_op
);
6760 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6763 tcg_temp_free_i32(tcg_op
);
6765 tcg_temp_free_i32(tcg_shift
);
6767 if (!is_q
&& !scalar
) {
6768 clear_vec_high(s
, rd
);
6773 /* Common vector code for handling integer to FP conversion */
6774 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6775 int elements
, int is_signed
,
6776 int fracbits
, int size
)
6778 bool is_double
= size
== 3 ? true : false;
6779 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6780 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6781 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6782 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6785 for (pass
= 0; pass
< elements
; pass
++) {
6786 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6789 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6791 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6792 tcg_shift
, tcg_fpst
);
6794 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6795 tcg_shift
, tcg_fpst
);
6797 if (elements
== 1) {
6798 write_fp_dreg(s
, rd
, tcg_double
);
6800 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6802 tcg_temp_free_i64(tcg_double
);
6804 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6806 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6807 tcg_shift
, tcg_fpst
);
6809 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6810 tcg_shift
, tcg_fpst
);
6812 if (elements
== 1) {
6813 write_fp_sreg(s
, rd
, tcg_single
);
6815 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6817 tcg_temp_free_i32(tcg_single
);
6821 if (!is_double
&& elements
== 2) {
6822 clear_vec_high(s
, rd
);
6825 tcg_temp_free_i64(tcg_int
);
6826 tcg_temp_free_ptr(tcg_fpst
);
6827 tcg_temp_free_i32(tcg_shift
);
6830 /* UCVTF/SCVTF - Integer to FP conversion */
6831 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6832 bool is_q
, bool is_u
,
6833 int immh
, int immb
, int opcode
,
6836 bool is_double
= extract32(immh
, 3, 1);
6837 int size
= is_double
? MO_64
: MO_32
;
6839 int immhb
= immh
<< 3 | immb
;
6840 int fracbits
= (is_double
? 128 : 64) - immhb
;
6842 if (!extract32(immh
, 2, 2)) {
6843 unallocated_encoding(s
);
6850 elements
= is_double
? 2 : is_q
? 4 : 2;
6851 if (is_double
&& !is_q
) {
6852 unallocated_encoding(s
);
6857 if (!fp_access_check(s
)) {
6861 /* immh == 0 would be a failure of the decode logic */
6864 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6867 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6868 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6869 bool is_q
, bool is_u
,
6870 int immh
, int immb
, int rn
, int rd
)
6872 bool is_double
= extract32(immh
, 3, 1);
6873 int immhb
= immh
<< 3 | immb
;
6874 int fracbits
= (is_double
? 128 : 64) - immhb
;
6876 TCGv_ptr tcg_fpstatus
;
6877 TCGv_i32 tcg_rmode
, tcg_shift
;
6879 if (!extract32(immh
, 2, 2)) {
6880 unallocated_encoding(s
);
6884 if (!is_scalar
&& !is_q
&& is_double
) {
6885 unallocated_encoding(s
);
6889 if (!fp_access_check(s
)) {
6893 assert(!(is_scalar
&& is_q
));
6895 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6896 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6897 tcg_fpstatus
= get_fpstatus_ptr();
6898 tcg_shift
= tcg_const_i32(fracbits
);
6901 int maxpass
= is_scalar
? 1 : 2;
6903 for (pass
= 0; pass
< maxpass
; pass
++) {
6904 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6906 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6908 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6910 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6912 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6913 tcg_temp_free_i64(tcg_op
);
6916 clear_vec_high(s
, rd
);
6919 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6920 for (pass
= 0; pass
< maxpass
; pass
++) {
6921 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6923 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6925 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6927 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6930 write_fp_sreg(s
, rd
, tcg_op
);
6932 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6934 tcg_temp_free_i32(tcg_op
);
6936 if (!is_q
&& !is_scalar
) {
6937 clear_vec_high(s
, rd
);
6941 tcg_temp_free_ptr(tcg_fpstatus
);
6942 tcg_temp_free_i32(tcg_shift
);
6943 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6944 tcg_temp_free_i32(tcg_rmode
);
6947 /* C3.6.9 AdvSIMD scalar shift by immediate
6948 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6949 * +-----+---+-------------+------+------+--------+---+------+------+
6950 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6951 * +-----+---+-------------+------+------+--------+---+------+------+
6953 * This is the scalar version so it works on a fixed sized registers
6955 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6957 int rd
= extract32(insn
, 0, 5);
6958 int rn
= extract32(insn
, 5, 5);
6959 int opcode
= extract32(insn
, 11, 5);
6960 int immb
= extract32(insn
, 16, 3);
6961 int immh
= extract32(insn
, 19, 4);
6962 bool is_u
= extract32(insn
, 29, 1);
6965 unallocated_encoding(s
);
6970 case 0x08: /* SRI */
6972 unallocated_encoding(s
);
6976 case 0x00: /* SSHR / USHR */
6977 case 0x02: /* SSRA / USRA */
6978 case 0x04: /* SRSHR / URSHR */
6979 case 0x06: /* SRSRA / URSRA */
6980 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6982 case 0x0a: /* SHL / SLI */
6983 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6985 case 0x1c: /* SCVTF, UCVTF */
6986 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6989 case 0x10: /* SQSHRUN, SQSHRUN2 */
6990 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6992 unallocated_encoding(s
);
6995 handle_vec_simd_sqshrn(s
, true, false, false, true,
6996 immh
, immb
, opcode
, rn
, rd
);
6998 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6999 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7000 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7001 immh
, immb
, opcode
, rn
, rd
);
7003 case 0xc: /* SQSHLU */
7005 unallocated_encoding(s
);
7008 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7010 case 0xe: /* SQSHL, UQSHL */
7011 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7013 case 0x1f: /* FCVTZS, FCVTZU */
7014 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7017 unallocated_encoding(s
);
7022 /* C3.6.10 AdvSIMD scalar three different
7023 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7024 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7025 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7026 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7028 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7030 bool is_u
= extract32(insn
, 29, 1);
7031 int size
= extract32(insn
, 22, 2);
7032 int opcode
= extract32(insn
, 12, 4);
7033 int rm
= extract32(insn
, 16, 5);
7034 int rn
= extract32(insn
, 5, 5);
7035 int rd
= extract32(insn
, 0, 5);
7038 unallocated_encoding(s
);
7043 case 0x9: /* SQDMLAL, SQDMLAL2 */
7044 case 0xb: /* SQDMLSL, SQDMLSL2 */
7045 case 0xd: /* SQDMULL, SQDMULL2 */
7046 if (size
== 0 || size
== 3) {
7047 unallocated_encoding(s
);
7052 unallocated_encoding(s
);
7056 if (!fp_access_check(s
)) {
7061 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7062 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7063 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7065 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7066 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7068 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7069 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7072 case 0xd: /* SQDMULL, SQDMULL2 */
7074 case 0xb: /* SQDMLSL, SQDMLSL2 */
7075 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7077 case 0x9: /* SQDMLAL, SQDMLAL2 */
7078 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7079 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7083 g_assert_not_reached();
7086 write_fp_dreg(s
, rd
, tcg_res
);
7088 tcg_temp_free_i64(tcg_op1
);
7089 tcg_temp_free_i64(tcg_op2
);
7090 tcg_temp_free_i64(tcg_res
);
7092 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7093 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7094 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7096 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7097 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7099 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7100 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7103 case 0xd: /* SQDMULL, SQDMULL2 */
7105 case 0xb: /* SQDMLSL, SQDMLSL2 */
7106 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7108 case 0x9: /* SQDMLAL, SQDMLAL2 */
7110 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7111 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7112 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7114 tcg_temp_free_i64(tcg_op3
);
7118 g_assert_not_reached();
7121 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7122 write_fp_dreg(s
, rd
, tcg_res
);
7124 tcg_temp_free_i32(tcg_op1
);
7125 tcg_temp_free_i32(tcg_op2
);
7126 tcg_temp_free_i64(tcg_res
);
7130 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7131 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7133 /* Handle 64x64->64 opcodes which are shared between the scalar
7134 * and vector 3-same groups. We cover every opcode where size == 3
7135 * is valid in either the three-reg-same (integer, not pairwise)
7136 * or scalar-three-reg-same groups. (Some opcodes are not yet
7142 case 0x1: /* SQADD */
7144 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7146 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7149 case 0x5: /* SQSUB */
7151 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7153 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7156 case 0x6: /* CMGT, CMHI */
7157 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7158 * We implement this using setcond (test) and then negating.
7160 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7162 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7163 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7165 case 0x7: /* CMGE, CMHS */
7166 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7168 case 0x11: /* CMTST, CMEQ */
7173 /* CMTST : test is "if (X & Y != 0)". */
7174 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7175 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7176 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7178 case 0x8: /* SSHL, USHL */
7180 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7182 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7185 case 0x9: /* SQSHL, UQSHL */
7187 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7189 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7192 case 0xa: /* SRSHL, URSHL */
7194 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7196 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7199 case 0xb: /* SQRSHL, UQRSHL */
7201 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7203 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7206 case 0x10: /* ADD, SUB */
7208 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7210 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7214 g_assert_not_reached();
7218 /* Handle the 3-same-operands float operations; shared by the scalar
7219 * and vector encodings. The caller must filter out any encodings
7220 * not allocated for the encoding it is dealing with.
7222 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7223 int fpopcode
, int rd
, int rn
, int rm
)
7226 TCGv_ptr fpst
= get_fpstatus_ptr();
7228 for (pass
= 0; pass
< elements
; pass
++) {
7231 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7232 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7233 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7235 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7236 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7239 case 0x39: /* FMLS */
7240 /* As usual for ARM, separate negation for fused multiply-add */
7241 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7243 case 0x19: /* FMLA */
7244 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7245 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7248 case 0x18: /* FMAXNM */
7249 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7251 case 0x1a: /* FADD */
7252 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7254 case 0x1b: /* FMULX */
7255 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7257 case 0x1c: /* FCMEQ */
7258 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7260 case 0x1e: /* FMAX */
7261 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7263 case 0x1f: /* FRECPS */
7264 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7266 case 0x38: /* FMINNM */
7267 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7269 case 0x3a: /* FSUB */
7270 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7272 case 0x3e: /* FMIN */
7273 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7275 case 0x3f: /* FRSQRTS */
7276 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7278 case 0x5b: /* FMUL */
7279 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7281 case 0x5c: /* FCMGE */
7282 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7284 case 0x5d: /* FACGE */
7285 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7287 case 0x5f: /* FDIV */
7288 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7290 case 0x7a: /* FABD */
7291 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7292 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7294 case 0x7c: /* FCMGT */
7295 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7297 case 0x7d: /* FACGT */
7298 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7301 g_assert_not_reached();
7304 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7306 tcg_temp_free_i64(tcg_res
);
7307 tcg_temp_free_i64(tcg_op1
);
7308 tcg_temp_free_i64(tcg_op2
);
7311 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7312 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7313 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7315 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7316 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7319 case 0x39: /* FMLS */
7320 /* As usual for ARM, separate negation for fused multiply-add */
7321 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7323 case 0x19: /* FMLA */
7324 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7325 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7328 case 0x1a: /* FADD */
7329 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7331 case 0x1b: /* FMULX */
7332 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7334 case 0x1c: /* FCMEQ */
7335 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7337 case 0x1e: /* FMAX */
7338 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7340 case 0x1f: /* FRECPS */
7341 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7343 case 0x18: /* FMAXNM */
7344 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7346 case 0x38: /* FMINNM */
7347 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7349 case 0x3a: /* FSUB */
7350 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7352 case 0x3e: /* FMIN */
7353 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7355 case 0x3f: /* FRSQRTS */
7356 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7358 case 0x5b: /* FMUL */
7359 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7361 case 0x5c: /* FCMGE */
7362 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7364 case 0x5d: /* FACGE */
7365 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7367 case 0x5f: /* FDIV */
7368 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7370 case 0x7a: /* FABD */
7371 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7372 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7374 case 0x7c: /* FCMGT */
7375 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7377 case 0x7d: /* FACGT */
7378 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7381 g_assert_not_reached();
7384 if (elements
== 1) {
7385 /* scalar single so clear high part */
7386 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7388 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7389 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7390 tcg_temp_free_i64(tcg_tmp
);
7392 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7395 tcg_temp_free_i32(tcg_res
);
7396 tcg_temp_free_i32(tcg_op1
);
7397 tcg_temp_free_i32(tcg_op2
);
7401 tcg_temp_free_ptr(fpst
);
7403 if ((elements
<< size
) < 4) {
7404 /* scalar, or non-quad vector op */
7405 clear_vec_high(s
, rd
);
7409 /* C3.6.11 AdvSIMD scalar three same
7410 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7411 * +-----+---+-----------+------+---+------+--------+---+------+------+
7412 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7413 * +-----+---+-----------+------+---+------+--------+---+------+------+
7415 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7417 int rd
= extract32(insn
, 0, 5);
7418 int rn
= extract32(insn
, 5, 5);
7419 int opcode
= extract32(insn
, 11, 5);
7420 int rm
= extract32(insn
, 16, 5);
7421 int size
= extract32(insn
, 22, 2);
7422 bool u
= extract32(insn
, 29, 1);
7425 if (opcode
>= 0x18) {
7426 /* Floating point: U, size[1] and opcode indicate operation */
7427 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7429 case 0x1b: /* FMULX */
7430 case 0x1f: /* FRECPS */
7431 case 0x3f: /* FRSQRTS */
7432 case 0x5d: /* FACGE */
7433 case 0x7d: /* FACGT */
7434 case 0x1c: /* FCMEQ */
7435 case 0x5c: /* FCMGE */
7436 case 0x7c: /* FCMGT */
7437 case 0x7a: /* FABD */
7440 unallocated_encoding(s
);
7444 if (!fp_access_check(s
)) {
7448 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7453 case 0x1: /* SQADD, UQADD */
7454 case 0x5: /* SQSUB, UQSUB */
7455 case 0x9: /* SQSHL, UQSHL */
7456 case 0xb: /* SQRSHL, UQRSHL */
7458 case 0x8: /* SSHL, USHL */
7459 case 0xa: /* SRSHL, URSHL */
7460 case 0x6: /* CMGT, CMHI */
7461 case 0x7: /* CMGE, CMHS */
7462 case 0x11: /* CMTST, CMEQ */
7463 case 0x10: /* ADD, SUB (vector) */
7465 unallocated_encoding(s
);
7469 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7470 if (size
!= 1 && size
!= 2) {
7471 unallocated_encoding(s
);
7476 unallocated_encoding(s
);
7480 if (!fp_access_check(s
)) {
7484 tcg_rd
= tcg_temp_new_i64();
7487 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7488 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7490 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7491 tcg_temp_free_i64(tcg_rn
);
7492 tcg_temp_free_i64(tcg_rm
);
7494 /* Do a single operation on the lowest element in the vector.
7495 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7496 * no side effects for all these operations.
7497 * OPTME: special-purpose helpers would avoid doing some
7498 * unnecessary work in the helper for the 8 and 16 bit cases.
7500 NeonGenTwoOpEnvFn
*genenvfn
;
7501 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7502 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7503 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7505 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7506 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7509 case 0x1: /* SQADD, UQADD */
7511 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7512 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7513 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7514 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7516 genenvfn
= fns
[size
][u
];
7519 case 0x5: /* SQSUB, UQSUB */
7521 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7522 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7523 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7524 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7526 genenvfn
= fns
[size
][u
];
7529 case 0x9: /* SQSHL, UQSHL */
7531 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7532 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7533 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7534 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7536 genenvfn
= fns
[size
][u
];
7539 case 0xb: /* SQRSHL, UQRSHL */
7541 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7542 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7543 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7544 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7546 genenvfn
= fns
[size
][u
];
7549 case 0x16: /* SQDMULH, SQRDMULH */
7551 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7552 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7553 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7555 assert(size
== 1 || size
== 2);
7556 genenvfn
= fns
[size
- 1][u
];
7560 g_assert_not_reached();
7563 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7564 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7565 tcg_temp_free_i32(tcg_rd32
);
7566 tcg_temp_free_i32(tcg_rn
);
7567 tcg_temp_free_i32(tcg_rm
);
7570 write_fp_dreg(s
, rd
, tcg_rd
);
7572 tcg_temp_free_i64(tcg_rd
);
7575 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7576 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7577 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7579 /* Handle 64->64 opcodes which are shared between the scalar and
7580 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7581 * is valid in either group and also the double-precision fp ops.
7582 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7588 case 0x4: /* CLS, CLZ */
7590 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7592 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7596 /* This opcode is shared with CNT and RBIT but we have earlier
7597 * enforced that size == 3 if and only if this is the NOT insn.
7599 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7601 case 0x7: /* SQABS, SQNEG */
7603 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7605 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7608 case 0xa: /* CMLT */
7609 /* 64 bit integer comparison against zero, result is
7610 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7615 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7616 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7618 case 0x8: /* CMGT, CMGE */
7619 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7621 case 0x9: /* CMEQ, CMLE */
7622 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7624 case 0xb: /* ABS, NEG */
7626 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7628 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7629 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7630 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7632 tcg_temp_free_i64(tcg_zero
);
7635 case 0x2f: /* FABS */
7636 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7638 case 0x6f: /* FNEG */
7639 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7641 case 0x7f: /* FSQRT */
7642 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7644 case 0x1a: /* FCVTNS */
7645 case 0x1b: /* FCVTMS */
7646 case 0x1c: /* FCVTAS */
7647 case 0x3a: /* FCVTPS */
7648 case 0x3b: /* FCVTZS */
7650 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7651 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7652 tcg_temp_free_i32(tcg_shift
);
7655 case 0x5a: /* FCVTNU */
7656 case 0x5b: /* FCVTMU */
7657 case 0x5c: /* FCVTAU */
7658 case 0x7a: /* FCVTPU */
7659 case 0x7b: /* FCVTZU */
7661 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7662 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7663 tcg_temp_free_i32(tcg_shift
);
7666 case 0x18: /* FRINTN */
7667 case 0x19: /* FRINTM */
7668 case 0x38: /* FRINTP */
7669 case 0x39: /* FRINTZ */
7670 case 0x58: /* FRINTA */
7671 case 0x79: /* FRINTI */
7672 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7674 case 0x59: /* FRINTX */
7675 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7678 g_assert_not_reached();
7682 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7683 bool is_scalar
, bool is_u
, bool is_q
,
7684 int size
, int rn
, int rd
)
7686 bool is_double
= (size
== 3);
7689 if (!fp_access_check(s
)) {
7693 fpst
= get_fpstatus_ptr();
7696 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7697 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7698 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7699 NeonGenTwoDoubleOPFn
*genfn
;
7704 case 0x2e: /* FCMLT (zero) */
7707 case 0x2c: /* FCMGT (zero) */
7708 genfn
= gen_helper_neon_cgt_f64
;
7710 case 0x2d: /* FCMEQ (zero) */
7711 genfn
= gen_helper_neon_ceq_f64
;
7713 case 0x6d: /* FCMLE (zero) */
7716 case 0x6c: /* FCMGE (zero) */
7717 genfn
= gen_helper_neon_cge_f64
;
7720 g_assert_not_reached();
7723 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7724 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7726 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7728 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7730 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7733 clear_vec_high(s
, rd
);
7736 tcg_temp_free_i64(tcg_res
);
7737 tcg_temp_free_i64(tcg_zero
);
7738 tcg_temp_free_i64(tcg_op
);
7740 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7741 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7742 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7743 NeonGenTwoSingleOPFn
*genfn
;
7745 int pass
, maxpasses
;
7748 case 0x2e: /* FCMLT (zero) */
7751 case 0x2c: /* FCMGT (zero) */
7752 genfn
= gen_helper_neon_cgt_f32
;
7754 case 0x2d: /* FCMEQ (zero) */
7755 genfn
= gen_helper_neon_ceq_f32
;
7757 case 0x6d: /* FCMLE (zero) */
7760 case 0x6c: /* FCMGE (zero) */
7761 genfn
= gen_helper_neon_cge_f32
;
7764 g_assert_not_reached();
7770 maxpasses
= is_q
? 4 : 2;
7773 for (pass
= 0; pass
< maxpasses
; pass
++) {
7774 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7776 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7778 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7781 write_fp_sreg(s
, rd
, tcg_res
);
7783 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7786 tcg_temp_free_i32(tcg_res
);
7787 tcg_temp_free_i32(tcg_zero
);
7788 tcg_temp_free_i32(tcg_op
);
7789 if (!is_q
&& !is_scalar
) {
7790 clear_vec_high(s
, rd
);
7794 tcg_temp_free_ptr(fpst
);
7797 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7798 bool is_scalar
, bool is_u
, bool is_q
,
7799 int size
, int rn
, int rd
)
7801 bool is_double
= (size
== 3);
7802 TCGv_ptr fpst
= get_fpstatus_ptr();
7805 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7806 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7809 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7810 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7812 case 0x3d: /* FRECPE */
7813 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7815 case 0x3f: /* FRECPX */
7816 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7818 case 0x7d: /* FRSQRTE */
7819 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7822 g_assert_not_reached();
7824 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7827 clear_vec_high(s
, rd
);
7830 tcg_temp_free_i64(tcg_res
);
7831 tcg_temp_free_i64(tcg_op
);
7833 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7834 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7835 int pass
, maxpasses
;
7840 maxpasses
= is_q
? 4 : 2;
7843 for (pass
= 0; pass
< maxpasses
; pass
++) {
7844 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7847 case 0x3c: /* URECPE */
7848 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7850 case 0x3d: /* FRECPE */
7851 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7853 case 0x3f: /* FRECPX */
7854 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7856 case 0x7d: /* FRSQRTE */
7857 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7860 g_assert_not_reached();
7864 write_fp_sreg(s
, rd
, tcg_res
);
7866 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7869 tcg_temp_free_i32(tcg_res
);
7870 tcg_temp_free_i32(tcg_op
);
7871 if (!is_q
&& !is_scalar
) {
7872 clear_vec_high(s
, rd
);
7875 tcg_temp_free_ptr(fpst
);
7878 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7879 int opcode
, bool u
, bool is_q
,
7880 int size
, int rn
, int rd
)
7882 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7883 * in the source becomes a size element in the destination).
7886 TCGv_i32 tcg_res
[2];
7887 int destelt
= is_q
? 2 : 0;
7888 int passes
= scalar
? 1 : 2;
7891 tcg_res
[1] = tcg_const_i32(0);
7894 for (pass
= 0; pass
< passes
; pass
++) {
7895 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7896 NeonGenNarrowFn
*genfn
= NULL
;
7897 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7900 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7902 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7904 tcg_res
[pass
] = tcg_temp_new_i32();
7907 case 0x12: /* XTN, SQXTUN */
7909 static NeonGenNarrowFn
* const xtnfns
[3] = {
7910 gen_helper_neon_narrow_u8
,
7911 gen_helper_neon_narrow_u16
,
7912 tcg_gen_extrl_i64_i32
,
7914 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7915 gen_helper_neon_unarrow_sat8
,
7916 gen_helper_neon_unarrow_sat16
,
7917 gen_helper_neon_unarrow_sat32
,
7920 genenvfn
= sqxtunfns
[size
];
7922 genfn
= xtnfns
[size
];
7926 case 0x14: /* SQXTN, UQXTN */
7928 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7929 { gen_helper_neon_narrow_sat_s8
,
7930 gen_helper_neon_narrow_sat_u8
},
7931 { gen_helper_neon_narrow_sat_s16
,
7932 gen_helper_neon_narrow_sat_u16
},
7933 { gen_helper_neon_narrow_sat_s32
,
7934 gen_helper_neon_narrow_sat_u32
},
7936 genenvfn
= fns
[size
][u
];
7939 case 0x16: /* FCVTN, FCVTN2 */
7940 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7942 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7944 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7945 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7946 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7947 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7948 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7949 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7950 tcg_temp_free_i32(tcg_lo
);
7951 tcg_temp_free_i32(tcg_hi
);
7954 case 0x56: /* FCVTXN, FCVTXN2 */
7955 /* 64 bit to 32 bit float conversion
7956 * with von Neumann rounding (round to odd)
7959 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7962 g_assert_not_reached();
7966 genfn(tcg_res
[pass
], tcg_op
);
7967 } else if (genenvfn
) {
7968 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7971 tcg_temp_free_i64(tcg_op
);
7974 for (pass
= 0; pass
< 2; pass
++) {
7975 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7976 tcg_temp_free_i32(tcg_res
[pass
]);
7979 clear_vec_high(s
, rd
);
7983 /* Remaining saturating accumulating ops */
7984 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7985 bool is_q
, int size
, int rn
, int rd
)
7987 bool is_double
= (size
== 3);
7990 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7991 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7994 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7995 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7996 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7998 if (is_u
) { /* USQADD */
7999 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8000 } else { /* SUQADD */
8001 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8003 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8006 clear_vec_high(s
, rd
);
8009 tcg_temp_free_i64(tcg_rd
);
8010 tcg_temp_free_i64(tcg_rn
);
8012 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8013 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8014 int pass
, maxpasses
;
8019 maxpasses
= is_q
? 4 : 2;
8022 for (pass
= 0; pass
< maxpasses
; pass
++) {
8024 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8025 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8027 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8028 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8031 if (is_u
) { /* USQADD */
8034 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8037 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8040 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8043 g_assert_not_reached();
8045 } else { /* SUQADD */
8048 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8051 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8054 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8057 g_assert_not_reached();
8062 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8063 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8064 tcg_temp_free_i64(tcg_zero
);
8066 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8070 clear_vec_high(s
, rd
);
8073 tcg_temp_free_i32(tcg_rd
);
8074 tcg_temp_free_i32(tcg_rn
);
8078 /* C3.6.12 AdvSIMD scalar two reg misc
8079 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8080 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8081 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8082 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8084 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8086 int rd
= extract32(insn
, 0, 5);
8087 int rn
= extract32(insn
, 5, 5);
8088 int opcode
= extract32(insn
, 12, 5);
8089 int size
= extract32(insn
, 22, 2);
8090 bool u
= extract32(insn
, 29, 1);
8091 bool is_fcvt
= false;
8094 TCGv_ptr tcg_fpstatus
;
8097 case 0x3: /* USQADD / SUQADD*/
8098 if (!fp_access_check(s
)) {
8101 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8103 case 0x7: /* SQABS / SQNEG */
8105 case 0xa: /* CMLT */
8107 unallocated_encoding(s
);
8111 case 0x8: /* CMGT, CMGE */
8112 case 0x9: /* CMEQ, CMLE */
8113 case 0xb: /* ABS, NEG */
8115 unallocated_encoding(s
);
8119 case 0x12: /* SQXTUN */
8121 unallocated_encoding(s
);
8125 case 0x14: /* SQXTN, UQXTN */
8127 unallocated_encoding(s
);
8130 if (!fp_access_check(s
)) {
8133 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8138 /* Floating point: U, size[1] and opcode indicate operation;
8139 * size[0] indicates single or double precision.
8141 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8142 size
= extract32(size
, 0, 1) ? 3 : 2;
8144 case 0x2c: /* FCMGT (zero) */
8145 case 0x2d: /* FCMEQ (zero) */
8146 case 0x2e: /* FCMLT (zero) */
8147 case 0x6c: /* FCMGE (zero) */
8148 case 0x6d: /* FCMLE (zero) */
8149 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8151 case 0x1d: /* SCVTF */
8152 case 0x5d: /* UCVTF */
8154 bool is_signed
= (opcode
== 0x1d);
8155 if (!fp_access_check(s
)) {
8158 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8161 case 0x3d: /* FRECPE */
8162 case 0x3f: /* FRECPX */
8163 case 0x7d: /* FRSQRTE */
8164 if (!fp_access_check(s
)) {
8167 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8169 case 0x1a: /* FCVTNS */
8170 case 0x1b: /* FCVTMS */
8171 case 0x3a: /* FCVTPS */
8172 case 0x3b: /* FCVTZS */
8173 case 0x5a: /* FCVTNU */
8174 case 0x5b: /* FCVTMU */
8175 case 0x7a: /* FCVTPU */
8176 case 0x7b: /* FCVTZU */
8178 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8180 case 0x1c: /* FCVTAS */
8181 case 0x5c: /* FCVTAU */
8182 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8184 rmode
= FPROUNDING_TIEAWAY
;
8186 case 0x56: /* FCVTXN, FCVTXN2 */
8188 unallocated_encoding(s
);
8191 if (!fp_access_check(s
)) {
8194 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8197 unallocated_encoding(s
);
8202 unallocated_encoding(s
);
8206 if (!fp_access_check(s
)) {
8211 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8212 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8213 tcg_fpstatus
= get_fpstatus_ptr();
8215 TCGV_UNUSED_I32(tcg_rmode
);
8216 TCGV_UNUSED_PTR(tcg_fpstatus
);
8220 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8221 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8223 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8224 write_fp_dreg(s
, rd
, tcg_rd
);
8225 tcg_temp_free_i64(tcg_rd
);
8226 tcg_temp_free_i64(tcg_rn
);
8228 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8229 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8231 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8234 case 0x7: /* SQABS, SQNEG */
8236 NeonGenOneOpEnvFn
*genfn
;
8237 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8238 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8239 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8240 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8242 genfn
= fns
[size
][u
];
8243 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8246 case 0x1a: /* FCVTNS */
8247 case 0x1b: /* FCVTMS */
8248 case 0x1c: /* FCVTAS */
8249 case 0x3a: /* FCVTPS */
8250 case 0x3b: /* FCVTZS */
8252 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8253 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8254 tcg_temp_free_i32(tcg_shift
);
8257 case 0x5a: /* FCVTNU */
8258 case 0x5b: /* FCVTMU */
8259 case 0x5c: /* FCVTAU */
8260 case 0x7a: /* FCVTPU */
8261 case 0x7b: /* FCVTZU */
8263 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8264 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8265 tcg_temp_free_i32(tcg_shift
);
8269 g_assert_not_reached();
8272 write_fp_sreg(s
, rd
, tcg_rd
);
8273 tcg_temp_free_i32(tcg_rd
);
8274 tcg_temp_free_i32(tcg_rn
);
8278 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8279 tcg_temp_free_i32(tcg_rmode
);
8280 tcg_temp_free_ptr(tcg_fpstatus
);
8284 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8285 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8286 int immh
, int immb
, int opcode
, int rn
, int rd
)
8288 int size
= 32 - clz32(immh
) - 1;
8289 int immhb
= immh
<< 3 | immb
;
8290 int shift
= 2 * (8 << size
) - immhb
;
8291 bool accumulate
= false;
8293 bool insert
= false;
8294 int dsize
= is_q
? 128 : 64;
8295 int esize
= 8 << size
;
8296 int elements
= dsize
/esize
;
8297 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8298 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8299 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8303 if (extract32(immh
, 3, 1) && !is_q
) {
8304 unallocated_encoding(s
);
8308 if (size
> 3 && !is_q
) {
8309 unallocated_encoding(s
);
8313 if (!fp_access_check(s
)) {
8318 case 0x02: /* SSRA / USRA (accumulate) */
8321 case 0x04: /* SRSHR / URSHR (rounding) */
8324 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8325 accumulate
= round
= true;
8327 case 0x08: /* SRI */
8333 uint64_t round_const
= 1ULL << (shift
- 1);
8334 tcg_round
= tcg_const_i64(round_const
);
8336 TCGV_UNUSED_I64(tcg_round
);
8339 for (i
= 0; i
< elements
; i
++) {
8340 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8341 if (accumulate
|| insert
) {
8342 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8346 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8348 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8349 accumulate
, is_u
, size
, shift
);
8352 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8356 clear_vec_high(s
, rd
);
8360 tcg_temp_free_i64(tcg_round
);
8364 /* SHL/SLI - Vector shift left */
8365 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8366 int immh
, int immb
, int opcode
, int rn
, int rd
)
8368 int size
= 32 - clz32(immh
) - 1;
8369 int immhb
= immh
<< 3 | immb
;
8370 int shift
= immhb
- (8 << size
);
8371 int dsize
= is_q
? 128 : 64;
8372 int esize
= 8 << size
;
8373 int elements
= dsize
/esize
;
8374 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8375 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8378 if (extract32(immh
, 3, 1) && !is_q
) {
8379 unallocated_encoding(s
);
8383 if (size
> 3 && !is_q
) {
8384 unallocated_encoding(s
);
8388 if (!fp_access_check(s
)) {
8392 for (i
= 0; i
< elements
; i
++) {
8393 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8395 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8398 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8400 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8404 clear_vec_high(s
, rd
);
8408 /* USHLL/SHLL - Vector shift left with widening */
8409 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8410 int immh
, int immb
, int opcode
, int rn
, int rd
)
8412 int size
= 32 - clz32(immh
) - 1;
8413 int immhb
= immh
<< 3 | immb
;
8414 int shift
= immhb
- (8 << size
);
8416 int esize
= 8 << size
;
8417 int elements
= dsize
/esize
;
8418 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8419 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8423 unallocated_encoding(s
);
8427 if (!fp_access_check(s
)) {
8431 /* For the LL variants the store is larger than the load,
8432 * so if rd == rn we would overwrite parts of our input.
8433 * So load everything right now and use shifts in the main loop.
8435 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8437 for (i
= 0; i
< elements
; i
++) {
8438 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8439 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8440 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8441 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8445 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8446 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8447 int immh
, int immb
, int opcode
, int rn
, int rd
)
8449 int immhb
= immh
<< 3 | immb
;
8450 int size
= 32 - clz32(immh
) - 1;
8452 int esize
= 8 << size
;
8453 int elements
= dsize
/esize
;
8454 int shift
= (2 * esize
) - immhb
;
8455 bool round
= extract32(opcode
, 0, 1);
8456 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8460 if (extract32(immh
, 3, 1)) {
8461 unallocated_encoding(s
);
8465 if (!fp_access_check(s
)) {
8469 tcg_rn
= tcg_temp_new_i64();
8470 tcg_rd
= tcg_temp_new_i64();
8471 tcg_final
= tcg_temp_new_i64();
8472 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8475 uint64_t round_const
= 1ULL << (shift
- 1);
8476 tcg_round
= tcg_const_i64(round_const
);
8478 TCGV_UNUSED_I64(tcg_round
);
8481 for (i
= 0; i
< elements
; i
++) {
8482 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8483 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8484 false, true, size
+1, shift
);
8486 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8490 clear_vec_high(s
, rd
);
8491 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8493 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8497 tcg_temp_free_i64(tcg_round
);
8499 tcg_temp_free_i64(tcg_rn
);
8500 tcg_temp_free_i64(tcg_rd
);
8501 tcg_temp_free_i64(tcg_final
);
8506 /* C3.6.14 AdvSIMD shift by immediate
8507 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8508 * +---+---+---+-------------+------+------+--------+---+------+------+
8509 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8510 * +---+---+---+-------------+------+------+--------+---+------+------+
8512 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8514 int rd
= extract32(insn
, 0, 5);
8515 int rn
= extract32(insn
, 5, 5);
8516 int opcode
= extract32(insn
, 11, 5);
8517 int immb
= extract32(insn
, 16, 3);
8518 int immh
= extract32(insn
, 19, 4);
8519 bool is_u
= extract32(insn
, 29, 1);
8520 bool is_q
= extract32(insn
, 30, 1);
8523 case 0x08: /* SRI */
8525 unallocated_encoding(s
);
8529 case 0x00: /* SSHR / USHR */
8530 case 0x02: /* SSRA / USRA (accumulate) */
8531 case 0x04: /* SRSHR / URSHR (rounding) */
8532 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8533 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8535 case 0x0a: /* SHL / SLI */
8536 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8538 case 0x10: /* SHRN */
8539 case 0x11: /* RSHRN / SQRSHRUN */
8541 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8544 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8547 case 0x12: /* SQSHRN / UQSHRN */
8548 case 0x13: /* SQRSHRN / UQRSHRN */
8549 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8552 case 0x14: /* SSHLL / USHLL */
8553 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8555 case 0x1c: /* SCVTF / UCVTF */
8556 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8559 case 0xc: /* SQSHLU */
8561 unallocated_encoding(s
);
8564 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8566 case 0xe: /* SQSHL, UQSHL */
8567 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8569 case 0x1f: /* FCVTZS/ FCVTZU */
8570 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8573 unallocated_encoding(s
);
8578 /* Generate code to do a "long" addition or subtraction, ie one done in
8579 * TCGv_i64 on vector lanes twice the width specified by size.
8581 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8582 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8584 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8585 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8586 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8587 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8589 NeonGenTwo64OpFn
*genfn
;
8592 genfn
= fns
[size
][is_sub
];
8593 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8596 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8597 int opcode
, int rd
, int rn
, int rm
)
8599 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8600 TCGv_i64 tcg_res
[2];
8603 tcg_res
[0] = tcg_temp_new_i64();
8604 tcg_res
[1] = tcg_temp_new_i64();
8606 /* Does this op do an adding accumulate, a subtracting accumulate,
8607 * or no accumulate at all?
8625 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8626 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8629 /* size == 2 means two 32x32->64 operations; this is worth special
8630 * casing because we can generally handle it inline.
8633 for (pass
= 0; pass
< 2; pass
++) {
8634 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8635 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8636 TCGv_i64 tcg_passres
;
8637 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8639 int elt
= pass
+ is_q
* 2;
8641 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8642 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8645 tcg_passres
= tcg_res
[pass
];
8647 tcg_passres
= tcg_temp_new_i64();
8651 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8652 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8654 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8655 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8657 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8658 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8660 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8661 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8663 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8664 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8665 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8667 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8668 tcg_temp_free_i64(tcg_tmp1
);
8669 tcg_temp_free_i64(tcg_tmp2
);
8672 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8673 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8674 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8675 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8677 case 9: /* SQDMLAL, SQDMLAL2 */
8678 case 11: /* SQDMLSL, SQDMLSL2 */
8679 case 13: /* SQDMULL, SQDMULL2 */
8680 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8681 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8682 tcg_passres
, tcg_passres
);
8685 g_assert_not_reached();
8688 if (opcode
== 9 || opcode
== 11) {
8689 /* saturating accumulate ops */
8691 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8693 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8694 tcg_res
[pass
], tcg_passres
);
8695 } else if (accop
> 0) {
8696 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8697 } else if (accop
< 0) {
8698 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8702 tcg_temp_free_i64(tcg_passres
);
8705 tcg_temp_free_i64(tcg_op1
);
8706 tcg_temp_free_i64(tcg_op2
);
8709 /* size 0 or 1, generally helper functions */
8710 for (pass
= 0; pass
< 2; pass
++) {
8711 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8712 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8713 TCGv_i64 tcg_passres
;
8714 int elt
= pass
+ is_q
* 2;
8716 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8717 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8720 tcg_passres
= tcg_res
[pass
];
8722 tcg_passres
= tcg_temp_new_i64();
8726 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8727 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8729 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8730 static NeonGenWidenFn
* const widenfns
[2][2] = {
8731 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8732 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8734 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8736 widenfn(tcg_op2_64
, tcg_op2
);
8737 widenfn(tcg_passres
, tcg_op1
);
8738 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8739 tcg_passres
, tcg_op2_64
);
8740 tcg_temp_free_i64(tcg_op2_64
);
8743 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8744 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8747 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8749 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8753 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8755 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8759 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8760 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8761 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8764 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8766 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8770 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8772 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8776 case 9: /* SQDMLAL, SQDMLAL2 */
8777 case 11: /* SQDMLSL, SQDMLSL2 */
8778 case 13: /* SQDMULL, SQDMULL2 */
8780 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8781 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8782 tcg_passres
, tcg_passres
);
8784 case 14: /* PMULL */
8786 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8789 g_assert_not_reached();
8791 tcg_temp_free_i32(tcg_op1
);
8792 tcg_temp_free_i32(tcg_op2
);
8795 if (opcode
== 9 || opcode
== 11) {
8796 /* saturating accumulate ops */
8798 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8800 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8804 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8805 tcg_res
[pass
], tcg_passres
);
8807 tcg_temp_free_i64(tcg_passres
);
8812 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8813 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8814 tcg_temp_free_i64(tcg_res
[0]);
8815 tcg_temp_free_i64(tcg_res
[1]);
8818 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8819 int opcode
, int rd
, int rn
, int rm
)
8821 TCGv_i64 tcg_res
[2];
8822 int part
= is_q
? 2 : 0;
8825 for (pass
= 0; pass
< 2; pass
++) {
8826 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8827 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8828 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8829 static NeonGenWidenFn
* const widenfns
[3][2] = {
8830 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8831 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8832 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8834 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8836 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8837 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8838 widenfn(tcg_op2_wide
, tcg_op2
);
8839 tcg_temp_free_i32(tcg_op2
);
8840 tcg_res
[pass
] = tcg_temp_new_i64();
8841 gen_neon_addl(size
, (opcode
== 3),
8842 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8843 tcg_temp_free_i64(tcg_op1
);
8844 tcg_temp_free_i64(tcg_op2_wide
);
8847 for (pass
= 0; pass
< 2; pass
++) {
8848 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8849 tcg_temp_free_i64(tcg_res
[pass
]);
8853 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8855 tcg_gen_addi_i64(in
, in
, 1U << 31);
8856 tcg_gen_extrh_i64_i32(res
, in
);
8859 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8860 int opcode
, int rd
, int rn
, int rm
)
8862 TCGv_i32 tcg_res
[2];
8863 int part
= is_q
? 2 : 0;
8866 for (pass
= 0; pass
< 2; pass
++) {
8867 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8868 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8869 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8870 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8871 { gen_helper_neon_narrow_high_u8
,
8872 gen_helper_neon_narrow_round_high_u8
},
8873 { gen_helper_neon_narrow_high_u16
,
8874 gen_helper_neon_narrow_round_high_u16
},
8875 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8877 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8879 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8880 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8882 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8884 tcg_temp_free_i64(tcg_op1
);
8885 tcg_temp_free_i64(tcg_op2
);
8887 tcg_res
[pass
] = tcg_temp_new_i32();
8888 gennarrow(tcg_res
[pass
], tcg_wideres
);
8889 tcg_temp_free_i64(tcg_wideres
);
8892 for (pass
= 0; pass
< 2; pass
++) {
8893 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8894 tcg_temp_free_i32(tcg_res
[pass
]);
8897 clear_vec_high(s
, rd
);
8901 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8903 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8904 * is the only three-reg-diff instruction which produces a
8905 * 128-bit wide result from a single operation. However since
8906 * it's possible to calculate the two halves more or less
8907 * separately we just use two helper calls.
8909 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8910 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8911 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8913 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8914 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8915 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8916 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8917 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8918 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8920 tcg_temp_free_i64(tcg_op1
);
8921 tcg_temp_free_i64(tcg_op2
);
8922 tcg_temp_free_i64(tcg_res
);
8925 /* C3.6.15 AdvSIMD three different
8926 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8927 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8928 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8929 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8931 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8933 /* Instructions in this group fall into three basic classes
8934 * (in each case with the operation working on each element in
8935 * the input vectors):
8936 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8938 * (2) wide 64 x 128 -> 128
8939 * (3) narrowing 128 x 128 -> 64
8940 * Here we do initial decode, catch unallocated cases and
8941 * dispatch to separate functions for each class.
8943 int is_q
= extract32(insn
, 30, 1);
8944 int is_u
= extract32(insn
, 29, 1);
8945 int size
= extract32(insn
, 22, 2);
8946 int opcode
= extract32(insn
, 12, 4);
8947 int rm
= extract32(insn
, 16, 5);
8948 int rn
= extract32(insn
, 5, 5);
8949 int rd
= extract32(insn
, 0, 5);
8952 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8953 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8954 /* 64 x 128 -> 128 */
8956 unallocated_encoding(s
);
8959 if (!fp_access_check(s
)) {
8962 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8964 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8965 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8966 /* 128 x 128 -> 64 */
8968 unallocated_encoding(s
);
8971 if (!fp_access_check(s
)) {
8974 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8976 case 14: /* PMULL, PMULL2 */
8977 if (is_u
|| size
== 1 || size
== 2) {
8978 unallocated_encoding(s
);
8982 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8983 unallocated_encoding(s
);
8986 if (!fp_access_check(s
)) {
8989 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8993 case 9: /* SQDMLAL, SQDMLAL2 */
8994 case 11: /* SQDMLSL, SQDMLSL2 */
8995 case 13: /* SQDMULL, SQDMULL2 */
8996 if (is_u
|| size
== 0) {
8997 unallocated_encoding(s
);
9001 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9002 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9003 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9004 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9005 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9006 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9007 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9008 /* 64 x 64 -> 128 */
9010 unallocated_encoding(s
);
9014 if (!fp_access_check(s
)) {
9018 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9021 /* opcode 15 not allocated */
9022 unallocated_encoding(s
);
9027 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9028 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9030 int rd
= extract32(insn
, 0, 5);
9031 int rn
= extract32(insn
, 5, 5);
9032 int rm
= extract32(insn
, 16, 5);
9033 int size
= extract32(insn
, 22, 2);
9034 bool is_u
= extract32(insn
, 29, 1);
9035 bool is_q
= extract32(insn
, 30, 1);
9036 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9039 if (!fp_access_check(s
)) {
9043 tcg_op1
= tcg_temp_new_i64();
9044 tcg_op2
= tcg_temp_new_i64();
9045 tcg_res
[0] = tcg_temp_new_i64();
9046 tcg_res
[1] = tcg_temp_new_i64();
9048 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9049 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9050 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9055 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9058 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9061 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9064 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9069 /* B* ops need res loaded to operate on */
9070 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9075 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9077 case 1: /* BSL bitwise select */
9078 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9079 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9080 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9082 case 2: /* BIT, bitwise insert if true */
9083 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9084 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9085 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9087 case 3: /* BIF, bitwise insert if false */
9088 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9089 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9090 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9096 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9098 tcg_gen_movi_i64(tcg_res
[1], 0);
9100 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9102 tcg_temp_free_i64(tcg_op1
);
9103 tcg_temp_free_i64(tcg_op2
);
9104 tcg_temp_free_i64(tcg_res
[0]);
9105 tcg_temp_free_i64(tcg_res
[1]);
9108 /* Helper functions for 32 bit comparisons */
9109 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9111 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9114 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9116 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9119 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9121 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9124 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9126 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9129 /* Pairwise op subgroup of C3.6.16.
9131 * This is called directly or via the handle_3same_float for float pairwise
9132 * operations where the opcode and size are calculated differently.
9134 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9135 int size
, int rn
, int rm
, int rd
)
9140 /* Floating point operations need fpst */
9141 if (opcode
>= 0x58) {
9142 fpst
= get_fpstatus_ptr();
9144 TCGV_UNUSED_PTR(fpst
);
9147 if (!fp_access_check(s
)) {
9151 /* These operations work on the concatenated rm:rn, with each pair of
9152 * adjacent elements being operated on to produce an element in the result.
9155 TCGv_i64 tcg_res
[2];
9157 for (pass
= 0; pass
< 2; pass
++) {
9158 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9159 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9160 int passreg
= (pass
== 0) ? rn
: rm
;
9162 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9163 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9164 tcg_res
[pass
] = tcg_temp_new_i64();
9167 case 0x17: /* ADDP */
9168 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9170 case 0x58: /* FMAXNMP */
9171 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9173 case 0x5a: /* FADDP */
9174 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9176 case 0x5e: /* FMAXP */
9177 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9179 case 0x78: /* FMINNMP */
9180 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9182 case 0x7e: /* FMINP */
9183 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9186 g_assert_not_reached();
9189 tcg_temp_free_i64(tcg_op1
);
9190 tcg_temp_free_i64(tcg_op2
);
9193 for (pass
= 0; pass
< 2; pass
++) {
9194 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9195 tcg_temp_free_i64(tcg_res
[pass
]);
9198 int maxpass
= is_q
? 4 : 2;
9199 TCGv_i32 tcg_res
[4];
9201 for (pass
= 0; pass
< maxpass
; pass
++) {
9202 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9203 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9204 NeonGenTwoOpFn
*genfn
= NULL
;
9205 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9206 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9208 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9209 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9210 tcg_res
[pass
] = tcg_temp_new_i32();
9213 case 0x17: /* ADDP */
9215 static NeonGenTwoOpFn
* const fns
[3] = {
9216 gen_helper_neon_padd_u8
,
9217 gen_helper_neon_padd_u16
,
9223 case 0x14: /* SMAXP, UMAXP */
9225 static NeonGenTwoOpFn
* const fns
[3][2] = {
9226 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9227 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9228 { gen_max_s32
, gen_max_u32
},
9230 genfn
= fns
[size
][u
];
9233 case 0x15: /* SMINP, UMINP */
9235 static NeonGenTwoOpFn
* const fns
[3][2] = {
9236 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9237 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9238 { gen_min_s32
, gen_min_u32
},
9240 genfn
= fns
[size
][u
];
9243 /* The FP operations are all on single floats (32 bit) */
9244 case 0x58: /* FMAXNMP */
9245 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9247 case 0x5a: /* FADDP */
9248 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9250 case 0x5e: /* FMAXP */
9251 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9253 case 0x78: /* FMINNMP */
9254 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9256 case 0x7e: /* FMINP */
9257 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9260 g_assert_not_reached();
9263 /* FP ops called directly, otherwise call now */
9265 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9268 tcg_temp_free_i32(tcg_op1
);
9269 tcg_temp_free_i32(tcg_op2
);
9272 for (pass
= 0; pass
< maxpass
; pass
++) {
9273 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9274 tcg_temp_free_i32(tcg_res
[pass
]);
9277 clear_vec_high(s
, rd
);
9281 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9282 tcg_temp_free_ptr(fpst
);
9286 /* Floating point op subgroup of C3.6.16. */
9287 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9289 /* For floating point ops, the U, size[1] and opcode bits
9290 * together indicate the operation. size[0] indicates single
9293 int fpopcode
= extract32(insn
, 11, 5)
9294 | (extract32(insn
, 23, 1) << 5)
9295 | (extract32(insn
, 29, 1) << 6);
9296 int is_q
= extract32(insn
, 30, 1);
9297 int size
= extract32(insn
, 22, 1);
9298 int rm
= extract32(insn
, 16, 5);
9299 int rn
= extract32(insn
, 5, 5);
9300 int rd
= extract32(insn
, 0, 5);
9302 int datasize
= is_q
? 128 : 64;
9303 int esize
= 32 << size
;
9304 int elements
= datasize
/ esize
;
9306 if (size
== 1 && !is_q
) {
9307 unallocated_encoding(s
);
9312 case 0x58: /* FMAXNMP */
9313 case 0x5a: /* FADDP */
9314 case 0x5e: /* FMAXP */
9315 case 0x78: /* FMINNMP */
9316 case 0x7e: /* FMINP */
9317 if (size
&& !is_q
) {
9318 unallocated_encoding(s
);
9321 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9324 case 0x1b: /* FMULX */
9325 case 0x1f: /* FRECPS */
9326 case 0x3f: /* FRSQRTS */
9327 case 0x5d: /* FACGE */
9328 case 0x7d: /* FACGT */
9329 case 0x19: /* FMLA */
9330 case 0x39: /* FMLS */
9331 case 0x18: /* FMAXNM */
9332 case 0x1a: /* FADD */
9333 case 0x1c: /* FCMEQ */
9334 case 0x1e: /* FMAX */
9335 case 0x38: /* FMINNM */
9336 case 0x3a: /* FSUB */
9337 case 0x3e: /* FMIN */
9338 case 0x5b: /* FMUL */
9339 case 0x5c: /* FCMGE */
9340 case 0x5f: /* FDIV */
9341 case 0x7a: /* FABD */
9342 case 0x7c: /* FCMGT */
9343 if (!fp_access_check(s
)) {
9347 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9350 unallocated_encoding(s
);
9355 /* Integer op subgroup of C3.6.16. */
9356 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9358 int is_q
= extract32(insn
, 30, 1);
9359 int u
= extract32(insn
, 29, 1);
9360 int size
= extract32(insn
, 22, 2);
9361 int opcode
= extract32(insn
, 11, 5);
9362 int rm
= extract32(insn
, 16, 5);
9363 int rn
= extract32(insn
, 5, 5);
9364 int rd
= extract32(insn
, 0, 5);
9368 case 0x13: /* MUL, PMUL */
9369 if (u
&& size
!= 0) {
9370 unallocated_encoding(s
);
9374 case 0x0: /* SHADD, UHADD */
9375 case 0x2: /* SRHADD, URHADD */
9376 case 0x4: /* SHSUB, UHSUB */
9377 case 0xc: /* SMAX, UMAX */
9378 case 0xd: /* SMIN, UMIN */
9379 case 0xe: /* SABD, UABD */
9380 case 0xf: /* SABA, UABA */
9381 case 0x12: /* MLA, MLS */
9383 unallocated_encoding(s
);
9387 case 0x16: /* SQDMULH, SQRDMULH */
9388 if (size
== 0 || size
== 3) {
9389 unallocated_encoding(s
);
9394 if (size
== 3 && !is_q
) {
9395 unallocated_encoding(s
);
9401 if (!fp_access_check(s
)) {
9407 for (pass
= 0; pass
< 2; pass
++) {
9408 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9409 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9410 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9412 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9413 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9415 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9417 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9419 tcg_temp_free_i64(tcg_res
);
9420 tcg_temp_free_i64(tcg_op1
);
9421 tcg_temp_free_i64(tcg_op2
);
9424 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9425 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9426 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9427 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9428 NeonGenTwoOpFn
*genfn
= NULL
;
9429 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9431 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9432 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9435 case 0x0: /* SHADD, UHADD */
9437 static NeonGenTwoOpFn
* const fns
[3][2] = {
9438 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9439 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9440 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9442 genfn
= fns
[size
][u
];
9445 case 0x1: /* SQADD, UQADD */
9447 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9448 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9449 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9450 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9452 genenvfn
= fns
[size
][u
];
9455 case 0x2: /* SRHADD, URHADD */
9457 static NeonGenTwoOpFn
* const fns
[3][2] = {
9458 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9459 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9460 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9462 genfn
= fns
[size
][u
];
9465 case 0x4: /* SHSUB, UHSUB */
9467 static NeonGenTwoOpFn
* const fns
[3][2] = {
9468 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9469 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9470 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9472 genfn
= fns
[size
][u
];
9475 case 0x5: /* SQSUB, UQSUB */
9477 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9478 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9479 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9480 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9482 genenvfn
= fns
[size
][u
];
9485 case 0x6: /* CMGT, CMHI */
9487 static NeonGenTwoOpFn
* const fns
[3][2] = {
9488 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9489 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9490 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9492 genfn
= fns
[size
][u
];
9495 case 0x7: /* CMGE, CMHS */
9497 static NeonGenTwoOpFn
* const fns
[3][2] = {
9498 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9499 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9500 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9502 genfn
= fns
[size
][u
];
9505 case 0x8: /* SSHL, USHL */
9507 static NeonGenTwoOpFn
* const fns
[3][2] = {
9508 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9509 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9510 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9512 genfn
= fns
[size
][u
];
9515 case 0x9: /* SQSHL, UQSHL */
9517 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9518 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9519 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9520 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9522 genenvfn
= fns
[size
][u
];
9525 case 0xa: /* SRSHL, URSHL */
9527 static NeonGenTwoOpFn
* const fns
[3][2] = {
9528 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9529 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9530 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9532 genfn
= fns
[size
][u
];
9535 case 0xb: /* SQRSHL, UQRSHL */
9537 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9538 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9539 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9540 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9542 genenvfn
= fns
[size
][u
];
9545 case 0xc: /* SMAX, UMAX */
9547 static NeonGenTwoOpFn
* const fns
[3][2] = {
9548 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9549 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9550 { gen_max_s32
, gen_max_u32
},
9552 genfn
= fns
[size
][u
];
9556 case 0xd: /* SMIN, UMIN */
9558 static NeonGenTwoOpFn
* const fns
[3][2] = {
9559 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9560 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9561 { gen_min_s32
, gen_min_u32
},
9563 genfn
= fns
[size
][u
];
9566 case 0xe: /* SABD, UABD */
9567 case 0xf: /* SABA, UABA */
9569 static NeonGenTwoOpFn
* const fns
[3][2] = {
9570 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9571 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9572 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9574 genfn
= fns
[size
][u
];
9577 case 0x10: /* ADD, SUB */
9579 static NeonGenTwoOpFn
* const fns
[3][2] = {
9580 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9581 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9582 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9584 genfn
= fns
[size
][u
];
9587 case 0x11: /* CMTST, CMEQ */
9589 static NeonGenTwoOpFn
* const fns
[3][2] = {
9590 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9591 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9592 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9594 genfn
= fns
[size
][u
];
9597 case 0x13: /* MUL, PMUL */
9601 genfn
= gen_helper_neon_mul_p8
;
9604 /* fall through : MUL */
9605 case 0x12: /* MLA, MLS */
9607 static NeonGenTwoOpFn
* const fns
[3] = {
9608 gen_helper_neon_mul_u8
,
9609 gen_helper_neon_mul_u16
,
9615 case 0x16: /* SQDMULH, SQRDMULH */
9617 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9618 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9619 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9621 assert(size
== 1 || size
== 2);
9622 genenvfn
= fns
[size
- 1][u
];
9626 g_assert_not_reached();
9630 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9632 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9635 if (opcode
== 0xf || opcode
== 0x12) {
9636 /* SABA, UABA, MLA, MLS: accumulating ops */
9637 static NeonGenTwoOpFn
* const fns
[3][2] = {
9638 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9639 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9640 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9642 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9644 genfn
= fns
[size
][is_sub
];
9645 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9646 genfn(tcg_res
, tcg_op1
, tcg_res
);
9649 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9651 tcg_temp_free_i32(tcg_res
);
9652 tcg_temp_free_i32(tcg_op1
);
9653 tcg_temp_free_i32(tcg_op2
);
9658 clear_vec_high(s
, rd
);
9662 /* C3.6.16 AdvSIMD three same
9663 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9664 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9665 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9666 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9668 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9670 int opcode
= extract32(insn
, 11, 5);
9673 case 0x3: /* logic ops */
9674 disas_simd_3same_logic(s
, insn
);
9676 case 0x17: /* ADDP */
9677 case 0x14: /* SMAXP, UMAXP */
9678 case 0x15: /* SMINP, UMINP */
9680 /* Pairwise operations */
9681 int is_q
= extract32(insn
, 30, 1);
9682 int u
= extract32(insn
, 29, 1);
9683 int size
= extract32(insn
, 22, 2);
9684 int rm
= extract32(insn
, 16, 5);
9685 int rn
= extract32(insn
, 5, 5);
9686 int rd
= extract32(insn
, 0, 5);
9687 if (opcode
== 0x17) {
9688 if (u
|| (size
== 3 && !is_q
)) {
9689 unallocated_encoding(s
);
9694 unallocated_encoding(s
);
9698 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9702 /* floating point ops, sz[1] and U are part of opcode */
9703 disas_simd_3same_float(s
, insn
);
9706 disas_simd_3same_int(s
, insn
);
9711 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9712 int size
, int rn
, int rd
)
9714 /* Handle 2-reg-misc ops which are widening (so each size element
9715 * in the source becomes a 2*size element in the destination.
9716 * The only instruction like this is FCVTL.
9721 /* 32 -> 64 bit fp conversion */
9722 TCGv_i64 tcg_res
[2];
9723 int srcelt
= is_q
? 2 : 0;
9725 for (pass
= 0; pass
< 2; pass
++) {
9726 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9727 tcg_res
[pass
] = tcg_temp_new_i64();
9729 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9730 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9731 tcg_temp_free_i32(tcg_op
);
9733 for (pass
= 0; pass
< 2; pass
++) {
9734 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9735 tcg_temp_free_i64(tcg_res
[pass
]);
9738 /* 16 -> 32 bit fp conversion */
9739 int srcelt
= is_q
? 4 : 0;
9740 TCGv_i32 tcg_res
[4];
9742 for (pass
= 0; pass
< 4; pass
++) {
9743 tcg_res
[pass
] = tcg_temp_new_i32();
9745 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9746 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9749 for (pass
= 0; pass
< 4; pass
++) {
9750 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9751 tcg_temp_free_i32(tcg_res
[pass
]);
9756 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9757 bool is_q
, int size
, int rn
, int rd
)
9759 int op
= (opcode
<< 1) | u
;
9760 int opsz
= op
+ size
;
9761 int grp_size
= 3 - opsz
;
9762 int dsize
= is_q
? 128 : 64;
9766 unallocated_encoding(s
);
9770 if (!fp_access_check(s
)) {
9775 /* Special case bytes, use bswap op on each group of elements */
9776 int groups
= dsize
/ (8 << grp_size
);
9778 for (i
= 0; i
< groups
; i
++) {
9779 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9781 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9784 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9787 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9790 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9793 g_assert_not_reached();
9795 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9796 tcg_temp_free_i64(tcg_tmp
);
9799 clear_vec_high(s
, rd
);
9802 int revmask
= (1 << grp_size
) - 1;
9803 int esize
= 8 << size
;
9804 int elements
= dsize
/ esize
;
9805 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9806 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9807 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9809 for (i
= 0; i
< elements
; i
++) {
9810 int e_rev
= (i
& 0xf) ^ revmask
;
9811 int off
= e_rev
* esize
;
9812 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9814 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9815 tcg_rn
, off
- 64, esize
);
9817 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9820 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9821 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9823 tcg_temp_free_i64(tcg_rd_hi
);
9824 tcg_temp_free_i64(tcg_rd
);
9825 tcg_temp_free_i64(tcg_rn
);
9829 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9830 bool is_q
, int size
, int rn
, int rd
)
9832 /* Implement the pairwise operations from 2-misc:
9833 * SADDLP, UADDLP, SADALP, UADALP.
9834 * These all add pairs of elements in the input to produce a
9835 * double-width result element in the output (possibly accumulating).
9837 bool accum
= (opcode
== 0x6);
9838 int maxpass
= is_q
? 2 : 1;
9840 TCGv_i64 tcg_res
[2];
9843 /* 32 + 32 -> 64 op */
9844 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9846 for (pass
= 0; pass
< maxpass
; pass
++) {
9847 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9848 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9850 tcg_res
[pass
] = tcg_temp_new_i64();
9852 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9853 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9854 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9856 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9857 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9860 tcg_temp_free_i64(tcg_op1
);
9861 tcg_temp_free_i64(tcg_op2
);
9864 for (pass
= 0; pass
< maxpass
; pass
++) {
9865 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9866 NeonGenOneOpFn
*genfn
;
9867 static NeonGenOneOpFn
* const fns
[2][2] = {
9868 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9869 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9872 genfn
= fns
[size
][u
];
9874 tcg_res
[pass
] = tcg_temp_new_i64();
9876 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9877 genfn(tcg_res
[pass
], tcg_op
);
9880 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9882 gen_helper_neon_addl_u16(tcg_res
[pass
],
9883 tcg_res
[pass
], tcg_op
);
9885 gen_helper_neon_addl_u32(tcg_res
[pass
],
9886 tcg_res
[pass
], tcg_op
);
9889 tcg_temp_free_i64(tcg_op
);
9893 tcg_res
[1] = tcg_const_i64(0);
9895 for (pass
= 0; pass
< 2; pass
++) {
9896 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9897 tcg_temp_free_i64(tcg_res
[pass
]);
9901 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9903 /* Implement SHLL and SHLL2 */
9905 int part
= is_q
? 2 : 0;
9906 TCGv_i64 tcg_res
[2];
9908 for (pass
= 0; pass
< 2; pass
++) {
9909 static NeonGenWidenFn
* const widenfns
[3] = {
9910 gen_helper_neon_widen_u8
,
9911 gen_helper_neon_widen_u16
,
9912 tcg_gen_extu_i32_i64
,
9914 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9915 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9917 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9918 tcg_res
[pass
] = tcg_temp_new_i64();
9919 widenfn(tcg_res
[pass
], tcg_op
);
9920 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9922 tcg_temp_free_i32(tcg_op
);
9925 for (pass
= 0; pass
< 2; pass
++) {
9926 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9927 tcg_temp_free_i64(tcg_res
[pass
]);
9931 /* C3.6.17 AdvSIMD two reg misc
9932 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9933 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9934 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9935 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9937 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9939 int size
= extract32(insn
, 22, 2);
9940 int opcode
= extract32(insn
, 12, 5);
9941 bool u
= extract32(insn
, 29, 1);
9942 bool is_q
= extract32(insn
, 30, 1);
9943 int rn
= extract32(insn
, 5, 5);
9944 int rd
= extract32(insn
, 0, 5);
9945 bool need_fpstatus
= false;
9946 bool need_rmode
= false;
9949 TCGv_ptr tcg_fpstatus
;
9952 case 0x0: /* REV64, REV32 */
9953 case 0x1: /* REV16 */
9954 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9956 case 0x5: /* CNT, NOT, RBIT */
9957 if (u
&& size
== 0) {
9958 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9961 } else if (u
&& size
== 1) {
9964 } else if (!u
&& size
== 0) {
9968 unallocated_encoding(s
);
9970 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9971 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9973 unallocated_encoding(s
);
9976 if (!fp_access_check(s
)) {
9980 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9982 case 0x4: /* CLS, CLZ */
9984 unallocated_encoding(s
);
9988 case 0x2: /* SADDLP, UADDLP */
9989 case 0x6: /* SADALP, UADALP */
9991 unallocated_encoding(s
);
9994 if (!fp_access_check(s
)) {
9997 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9999 case 0x13: /* SHLL, SHLL2 */
10000 if (u
== 0 || size
== 3) {
10001 unallocated_encoding(s
);
10004 if (!fp_access_check(s
)) {
10007 handle_shll(s
, is_q
, size
, rn
, rd
);
10009 case 0xa: /* CMLT */
10011 unallocated_encoding(s
);
10015 case 0x8: /* CMGT, CMGE */
10016 case 0x9: /* CMEQ, CMLE */
10017 case 0xb: /* ABS, NEG */
10018 if (size
== 3 && !is_q
) {
10019 unallocated_encoding(s
);
10023 case 0x3: /* SUQADD, USQADD */
10024 if (size
== 3 && !is_q
) {
10025 unallocated_encoding(s
);
10028 if (!fp_access_check(s
)) {
10031 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10033 case 0x7: /* SQABS, SQNEG */
10034 if (size
== 3 && !is_q
) {
10035 unallocated_encoding(s
);
10040 case 0x16 ... 0x1d:
10043 /* Floating point: U, size[1] and opcode indicate operation;
10044 * size[0] indicates single or double precision.
10046 int is_double
= extract32(size
, 0, 1);
10047 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10048 size
= is_double
? 3 : 2;
10050 case 0x2f: /* FABS */
10051 case 0x6f: /* FNEG */
10052 if (size
== 3 && !is_q
) {
10053 unallocated_encoding(s
);
10057 case 0x1d: /* SCVTF */
10058 case 0x5d: /* UCVTF */
10060 bool is_signed
= (opcode
== 0x1d) ? true : false;
10061 int elements
= is_double
? 2 : is_q
? 4 : 2;
10062 if (is_double
&& !is_q
) {
10063 unallocated_encoding(s
);
10066 if (!fp_access_check(s
)) {
10069 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10072 case 0x2c: /* FCMGT (zero) */
10073 case 0x2d: /* FCMEQ (zero) */
10074 case 0x2e: /* FCMLT (zero) */
10075 case 0x6c: /* FCMGE (zero) */
10076 case 0x6d: /* FCMLE (zero) */
10077 if (size
== 3 && !is_q
) {
10078 unallocated_encoding(s
);
10081 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10083 case 0x7f: /* FSQRT */
10084 if (size
== 3 && !is_q
) {
10085 unallocated_encoding(s
);
10089 case 0x1a: /* FCVTNS */
10090 case 0x1b: /* FCVTMS */
10091 case 0x3a: /* FCVTPS */
10092 case 0x3b: /* FCVTZS */
10093 case 0x5a: /* FCVTNU */
10094 case 0x5b: /* FCVTMU */
10095 case 0x7a: /* FCVTPU */
10096 case 0x7b: /* FCVTZU */
10097 need_fpstatus
= true;
10099 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10100 if (size
== 3 && !is_q
) {
10101 unallocated_encoding(s
);
10105 case 0x5c: /* FCVTAU */
10106 case 0x1c: /* FCVTAS */
10107 need_fpstatus
= true;
10109 rmode
= FPROUNDING_TIEAWAY
;
10110 if (size
== 3 && !is_q
) {
10111 unallocated_encoding(s
);
10115 case 0x3c: /* URECPE */
10117 unallocated_encoding(s
);
10121 case 0x3d: /* FRECPE */
10122 case 0x7d: /* FRSQRTE */
10123 if (size
== 3 && !is_q
) {
10124 unallocated_encoding(s
);
10127 if (!fp_access_check(s
)) {
10130 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10132 case 0x56: /* FCVTXN, FCVTXN2 */
10134 unallocated_encoding(s
);
10138 case 0x16: /* FCVTN, FCVTN2 */
10139 /* handle_2misc_narrow does a 2*size -> size operation, but these
10140 * instructions encode the source size rather than dest size.
10142 if (!fp_access_check(s
)) {
10145 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10147 case 0x17: /* FCVTL, FCVTL2 */
10148 if (!fp_access_check(s
)) {
10151 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10153 case 0x18: /* FRINTN */
10154 case 0x19: /* FRINTM */
10155 case 0x38: /* FRINTP */
10156 case 0x39: /* FRINTZ */
10158 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10160 case 0x59: /* FRINTX */
10161 case 0x79: /* FRINTI */
10162 need_fpstatus
= true;
10163 if (size
== 3 && !is_q
) {
10164 unallocated_encoding(s
);
10168 case 0x58: /* FRINTA */
10170 rmode
= FPROUNDING_TIEAWAY
;
10171 need_fpstatus
= true;
10172 if (size
== 3 && !is_q
) {
10173 unallocated_encoding(s
);
10177 case 0x7c: /* URSQRTE */
10179 unallocated_encoding(s
);
10182 need_fpstatus
= true;
10185 unallocated_encoding(s
);
10191 unallocated_encoding(s
);
10195 if (!fp_access_check(s
)) {
10199 if (need_fpstatus
) {
10200 tcg_fpstatus
= get_fpstatus_ptr();
10202 TCGV_UNUSED_PTR(tcg_fpstatus
);
10205 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10206 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10208 TCGV_UNUSED_I32(tcg_rmode
);
10212 /* All 64-bit element operations can be shared with scalar 2misc */
10215 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10216 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10217 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10219 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10221 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10222 tcg_rmode
, tcg_fpstatus
);
10224 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10226 tcg_temp_free_i64(tcg_res
);
10227 tcg_temp_free_i64(tcg_op
);
10232 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10233 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10234 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10237 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10240 /* Special cases for 32 bit elements */
10242 case 0xa: /* CMLT */
10243 /* 32 bit integer comparison against zero, result is
10244 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10247 cond
= TCG_COND_LT
;
10249 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10250 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10252 case 0x8: /* CMGT, CMGE */
10253 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10255 case 0x9: /* CMEQ, CMLE */
10256 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10258 case 0x4: /* CLS */
10260 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10262 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10265 case 0x7: /* SQABS, SQNEG */
10267 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10269 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10272 case 0xb: /* ABS, NEG */
10274 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10276 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10277 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10278 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10279 tcg_zero
, tcg_op
, tcg_res
);
10280 tcg_temp_free_i32(tcg_zero
);
10283 case 0x2f: /* FABS */
10284 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10286 case 0x6f: /* FNEG */
10287 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10289 case 0x7f: /* FSQRT */
10290 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10292 case 0x1a: /* FCVTNS */
10293 case 0x1b: /* FCVTMS */
10294 case 0x1c: /* FCVTAS */
10295 case 0x3a: /* FCVTPS */
10296 case 0x3b: /* FCVTZS */
10298 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10299 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10300 tcg_shift
, tcg_fpstatus
);
10301 tcg_temp_free_i32(tcg_shift
);
10304 case 0x5a: /* FCVTNU */
10305 case 0x5b: /* FCVTMU */
10306 case 0x5c: /* FCVTAU */
10307 case 0x7a: /* FCVTPU */
10308 case 0x7b: /* FCVTZU */
10310 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10311 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10312 tcg_shift
, tcg_fpstatus
);
10313 tcg_temp_free_i32(tcg_shift
);
10316 case 0x18: /* FRINTN */
10317 case 0x19: /* FRINTM */
10318 case 0x38: /* FRINTP */
10319 case 0x39: /* FRINTZ */
10320 case 0x58: /* FRINTA */
10321 case 0x79: /* FRINTI */
10322 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10324 case 0x59: /* FRINTX */
10325 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10327 case 0x7c: /* URSQRTE */
10328 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10331 g_assert_not_reached();
10334 /* Use helpers for 8 and 16 bit elements */
10336 case 0x5: /* CNT, RBIT */
10337 /* For these two insns size is part of the opcode specifier
10338 * (handled earlier); they always operate on byte elements.
10341 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10343 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10346 case 0x7: /* SQABS, SQNEG */
10348 NeonGenOneOpEnvFn
*genfn
;
10349 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10350 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10351 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10353 genfn
= fns
[size
][u
];
10354 genfn(tcg_res
, cpu_env
, tcg_op
);
10357 case 0x8: /* CMGT, CMGE */
10358 case 0x9: /* CMEQ, CMLE */
10359 case 0xa: /* CMLT */
10361 static NeonGenTwoOpFn
* const fns
[3][2] = {
10362 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10363 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10364 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10366 NeonGenTwoOpFn
*genfn
;
10369 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10371 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10372 comp
= (opcode
- 0x8) * 2 + u
;
10373 /* ...but LE, LT are implemented as reverse GE, GT */
10374 reverse
= (comp
> 2);
10378 genfn
= fns
[comp
][size
];
10380 genfn(tcg_res
, tcg_zero
, tcg_op
);
10382 genfn(tcg_res
, tcg_op
, tcg_zero
);
10384 tcg_temp_free_i32(tcg_zero
);
10387 case 0xb: /* ABS, NEG */
10389 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10391 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10393 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10395 tcg_temp_free_i32(tcg_zero
);
10398 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10400 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10404 case 0x4: /* CLS, CLZ */
10407 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10409 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10413 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10415 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10420 g_assert_not_reached();
10424 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10426 tcg_temp_free_i32(tcg_res
);
10427 tcg_temp_free_i32(tcg_op
);
10431 clear_vec_high(s
, rd
);
10435 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10436 tcg_temp_free_i32(tcg_rmode
);
10438 if (need_fpstatus
) {
10439 tcg_temp_free_ptr(tcg_fpstatus
);
10443 /* C3.6.13 AdvSIMD scalar x indexed element
10444 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10445 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10446 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10447 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10448 * C3.6.18 AdvSIMD vector x indexed element
10449 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10450 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10451 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10452 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10454 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10456 /* This encoding has two kinds of instruction:
10457 * normal, where we perform elt x idxelt => elt for each
10458 * element in the vector
10459 * long, where we perform elt x idxelt and generate a result of
10460 * double the width of the input element
10461 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10463 bool is_scalar
= extract32(insn
, 28, 1);
10464 bool is_q
= extract32(insn
, 30, 1);
10465 bool u
= extract32(insn
, 29, 1);
10466 int size
= extract32(insn
, 22, 2);
10467 int l
= extract32(insn
, 21, 1);
10468 int m
= extract32(insn
, 20, 1);
10469 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10470 int rm
= extract32(insn
, 16, 4);
10471 int opcode
= extract32(insn
, 12, 4);
10472 int h
= extract32(insn
, 11, 1);
10473 int rn
= extract32(insn
, 5, 5);
10474 int rd
= extract32(insn
, 0, 5);
10475 bool is_long
= false;
10476 bool is_fp
= false;
10481 case 0x0: /* MLA */
10482 case 0x4: /* MLS */
10483 if (!u
|| is_scalar
) {
10484 unallocated_encoding(s
);
10488 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10489 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10490 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10492 unallocated_encoding(s
);
10497 case 0x3: /* SQDMLAL, SQDMLAL2 */
10498 case 0x7: /* SQDMLSL, SQDMLSL2 */
10499 case 0xb: /* SQDMULL, SQDMULL2 */
10502 case 0xc: /* SQDMULH */
10503 case 0xd: /* SQRDMULH */
10505 unallocated_encoding(s
);
10509 case 0x8: /* MUL */
10510 if (u
|| is_scalar
) {
10511 unallocated_encoding(s
);
10515 case 0x1: /* FMLA */
10516 case 0x5: /* FMLS */
10518 unallocated_encoding(s
);
10522 case 0x9: /* FMUL, FMULX */
10523 if (!extract32(size
, 1, 1)) {
10524 unallocated_encoding(s
);
10530 unallocated_encoding(s
);
10535 /* low bit of size indicates single/double */
10536 size
= extract32(size
, 0, 1) ? 3 : 2;
10538 index
= h
<< 1 | l
;
10541 unallocated_encoding(s
);
10550 index
= h
<< 2 | l
<< 1 | m
;
10553 index
= h
<< 1 | l
;
10557 unallocated_encoding(s
);
10562 if (!fp_access_check(s
)) {
10567 fpst
= get_fpstatus_ptr();
10569 TCGV_UNUSED_PTR(fpst
);
10573 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10576 assert(is_fp
&& is_q
&& !is_long
);
10578 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10580 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10581 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10582 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10584 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10587 case 0x5: /* FMLS */
10588 /* As usual for ARM, separate negation for fused multiply-add */
10589 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10591 case 0x1: /* FMLA */
10592 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10593 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10595 case 0x9: /* FMUL, FMULX */
10597 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10599 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10603 g_assert_not_reached();
10606 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10607 tcg_temp_free_i64(tcg_op
);
10608 tcg_temp_free_i64(tcg_res
);
10612 clear_vec_high(s
, rd
);
10615 tcg_temp_free_i64(tcg_idx
);
10616 } else if (!is_long
) {
10617 /* 32 bit floating point, or 16 or 32 bit integer.
10618 * For the 16 bit scalar case we use the usual Neon helpers and
10619 * rely on the fact that 0 op 0 == 0 with no side effects.
10621 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10622 int pass
, maxpasses
;
10627 maxpasses
= is_q
? 4 : 2;
10630 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10632 if (size
== 1 && !is_scalar
) {
10633 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10634 * the index into both halves of the 32 bit tcg_idx and then use
10635 * the usual Neon helpers.
10637 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10640 for (pass
= 0; pass
< maxpasses
; pass
++) {
10641 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10642 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10644 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10647 case 0x0: /* MLA */
10648 case 0x4: /* MLS */
10649 case 0x8: /* MUL */
10651 static NeonGenTwoOpFn
* const fns
[2][2] = {
10652 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10653 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10655 NeonGenTwoOpFn
*genfn
;
10656 bool is_sub
= opcode
== 0x4;
10659 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10661 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10663 if (opcode
== 0x8) {
10666 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10667 genfn
= fns
[size
- 1][is_sub
];
10668 genfn(tcg_res
, tcg_op
, tcg_res
);
10671 case 0x5: /* FMLS */
10672 /* As usual for ARM, separate negation for fused multiply-add */
10673 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10675 case 0x1: /* FMLA */
10676 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10677 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10679 case 0x9: /* FMUL, FMULX */
10681 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10683 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10686 case 0xc: /* SQDMULH */
10688 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10691 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10695 case 0xd: /* SQRDMULH */
10697 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10700 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10705 g_assert_not_reached();
10709 write_fp_sreg(s
, rd
, tcg_res
);
10711 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10714 tcg_temp_free_i32(tcg_op
);
10715 tcg_temp_free_i32(tcg_res
);
10718 tcg_temp_free_i32(tcg_idx
);
10721 clear_vec_high(s
, rd
);
10724 /* long ops: 16x16->32 or 32x32->64 */
10725 TCGv_i64 tcg_res
[2];
10727 bool satop
= extract32(opcode
, 0, 1);
10728 TCGMemOp memop
= MO_32
;
10735 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10737 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10739 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10740 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10741 TCGv_i64 tcg_passres
;
10747 passelt
= pass
+ (is_q
* 2);
10750 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10752 tcg_res
[pass
] = tcg_temp_new_i64();
10754 if (opcode
== 0xa || opcode
== 0xb) {
10755 /* Non-accumulating ops */
10756 tcg_passres
= tcg_res
[pass
];
10758 tcg_passres
= tcg_temp_new_i64();
10761 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10762 tcg_temp_free_i64(tcg_op
);
10765 /* saturating, doubling */
10766 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10767 tcg_passres
, tcg_passres
);
10770 if (opcode
== 0xa || opcode
== 0xb) {
10774 /* Accumulating op: handle accumulate step */
10775 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10778 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10779 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10781 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10782 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10784 case 0x7: /* SQDMLSL, SQDMLSL2 */
10785 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10787 case 0x3: /* SQDMLAL, SQDMLAL2 */
10788 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10793 g_assert_not_reached();
10795 tcg_temp_free_i64(tcg_passres
);
10797 tcg_temp_free_i64(tcg_idx
);
10800 clear_vec_high(s
, rd
);
10803 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10806 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10809 /* The simplest way to handle the 16x16 indexed ops is to
10810 * duplicate the index into both halves of the 32 bit tcg_idx
10811 * and then use the usual Neon helpers.
10813 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10816 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10817 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10818 TCGv_i64 tcg_passres
;
10821 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10823 read_vec_element_i32(s
, tcg_op
, rn
,
10824 pass
+ (is_q
* 2), MO_32
);
10827 tcg_res
[pass
] = tcg_temp_new_i64();
10829 if (opcode
== 0xa || opcode
== 0xb) {
10830 /* Non-accumulating ops */
10831 tcg_passres
= tcg_res
[pass
];
10833 tcg_passres
= tcg_temp_new_i64();
10836 if (memop
& MO_SIGN
) {
10837 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10839 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10842 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10843 tcg_passres
, tcg_passres
);
10845 tcg_temp_free_i32(tcg_op
);
10847 if (opcode
== 0xa || opcode
== 0xb) {
10851 /* Accumulating op: handle accumulate step */
10852 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10855 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10856 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10859 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10860 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10863 case 0x7: /* SQDMLSL, SQDMLSL2 */
10864 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10866 case 0x3: /* SQDMLAL, SQDMLAL2 */
10867 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10872 g_assert_not_reached();
10874 tcg_temp_free_i64(tcg_passres
);
10876 tcg_temp_free_i32(tcg_idx
);
10879 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10884 tcg_res
[1] = tcg_const_i64(0);
10887 for (pass
= 0; pass
< 2; pass
++) {
10888 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10889 tcg_temp_free_i64(tcg_res
[pass
]);
10893 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10894 tcg_temp_free_ptr(fpst
);
10898 /* C3.6.19 Crypto AES
10899 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10900 * +-----------------+------+-----------+--------+-----+------+------+
10901 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10902 * +-----------------+------+-----------+--------+-----+------+------+
10904 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10906 int size
= extract32(insn
, 22, 2);
10907 int opcode
= extract32(insn
, 12, 5);
10908 int rn
= extract32(insn
, 5, 5);
10909 int rd
= extract32(insn
, 0, 5);
10911 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10912 CryptoThreeOpEnvFn
*genfn
;
10914 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10916 unallocated_encoding(s
);
10921 case 0x4: /* AESE */
10923 genfn
= gen_helper_crypto_aese
;
10925 case 0x6: /* AESMC */
10927 genfn
= gen_helper_crypto_aesmc
;
10929 case 0x5: /* AESD */
10931 genfn
= gen_helper_crypto_aese
;
10933 case 0x7: /* AESIMC */
10935 genfn
= gen_helper_crypto_aesmc
;
10938 unallocated_encoding(s
);
10942 if (!fp_access_check(s
)) {
10946 /* Note that we convert the Vx register indexes into the
10947 * index within the vfp.regs[] array, so we can share the
10948 * helper with the AArch32 instructions.
10950 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10951 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10952 tcg_decrypt
= tcg_const_i32(decrypt
);
10954 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10956 tcg_temp_free_i32(tcg_rd_regno
);
10957 tcg_temp_free_i32(tcg_rn_regno
);
10958 tcg_temp_free_i32(tcg_decrypt
);
10961 /* C3.6.20 Crypto three-reg SHA
10962 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10963 * +-----------------+------+---+------+---+--------+-----+------+------+
10964 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10965 * +-----------------+------+---+------+---+--------+-----+------+------+
10967 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10969 int size
= extract32(insn
, 22, 2);
10970 int opcode
= extract32(insn
, 12, 3);
10971 int rm
= extract32(insn
, 16, 5);
10972 int rn
= extract32(insn
, 5, 5);
10973 int rd
= extract32(insn
, 0, 5);
10974 CryptoThreeOpEnvFn
*genfn
;
10975 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10976 int feature
= ARM_FEATURE_V8_SHA256
;
10979 unallocated_encoding(s
);
10984 case 0: /* SHA1C */
10985 case 1: /* SHA1P */
10986 case 2: /* SHA1M */
10987 case 3: /* SHA1SU0 */
10989 feature
= ARM_FEATURE_V8_SHA1
;
10991 case 4: /* SHA256H */
10992 genfn
= gen_helper_crypto_sha256h
;
10994 case 5: /* SHA256H2 */
10995 genfn
= gen_helper_crypto_sha256h2
;
10997 case 6: /* SHA256SU1 */
10998 genfn
= gen_helper_crypto_sha256su1
;
11001 unallocated_encoding(s
);
11005 if (!arm_dc_feature(s
, feature
)) {
11006 unallocated_encoding(s
);
11010 if (!fp_access_check(s
)) {
11014 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11015 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11016 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11019 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11021 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11023 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11024 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11025 tcg_temp_free_i32(tcg_opcode
);
11028 tcg_temp_free_i32(tcg_rd_regno
);
11029 tcg_temp_free_i32(tcg_rn_regno
);
11030 tcg_temp_free_i32(tcg_rm_regno
);
11033 /* C3.6.21 Crypto two-reg SHA
11034 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11035 * +-----------------+------+-----------+--------+-----+------+------+
11036 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11037 * +-----------------+------+-----------+--------+-----+------+------+
11039 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11041 int size
= extract32(insn
, 22, 2);
11042 int opcode
= extract32(insn
, 12, 5);
11043 int rn
= extract32(insn
, 5, 5);
11044 int rd
= extract32(insn
, 0, 5);
11045 CryptoTwoOpEnvFn
*genfn
;
11047 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11050 unallocated_encoding(s
);
11055 case 0: /* SHA1H */
11056 feature
= ARM_FEATURE_V8_SHA1
;
11057 genfn
= gen_helper_crypto_sha1h
;
11059 case 1: /* SHA1SU1 */
11060 feature
= ARM_FEATURE_V8_SHA1
;
11061 genfn
= gen_helper_crypto_sha1su1
;
11063 case 2: /* SHA256SU0 */
11064 feature
= ARM_FEATURE_V8_SHA256
;
11065 genfn
= gen_helper_crypto_sha256su0
;
11068 unallocated_encoding(s
);
11072 if (!arm_dc_feature(s
, feature
)) {
11073 unallocated_encoding(s
);
11077 if (!fp_access_check(s
)) {
11081 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11082 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11084 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11086 tcg_temp_free_i32(tcg_rd_regno
);
11087 tcg_temp_free_i32(tcg_rn_regno
);
11090 /* C3.6 Data processing - SIMD, inc Crypto
11092 * As the decode gets a little complex we are using a table based
11093 * approach for this part of the decode.
11095 static const AArch64DecodeTable data_proc_simd
[] = {
11096 /* pattern , mask , fn */
11097 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11098 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11099 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11100 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11101 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11102 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11103 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11104 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11105 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11106 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11107 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11108 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11109 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11110 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11111 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11112 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11113 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11114 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11115 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11116 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11117 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11118 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11119 { 0x00000000, 0x00000000, NULL
}
11122 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11124 /* Note that this is called with all non-FP cases from
11125 * table C3-6 so it must UNDEF for entries not specifically
11126 * allocated to instructions in that table.
11128 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11132 unallocated_encoding(s
);
11136 /* C3.6 Data processing - SIMD and floating point */
11137 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11139 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11140 disas_data_proc_fp(s
, insn
);
11142 /* SIMD, including crypto */
11143 disas_data_proc_simd(s
, insn
);
11147 /* C3.1 A64 instruction index by encoding */
11148 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11152 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11156 s
->fp_access_checked
= false;
11158 switch (extract32(insn
, 25, 4)) {
11159 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11160 unallocated_encoding(s
);
11162 case 0x8: case 0x9: /* Data processing - immediate */
11163 disas_data_proc_imm(s
, insn
);
11165 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11166 disas_b_exc_sys(s
, insn
);
11171 case 0xe: /* Loads and stores */
11172 disas_ldst(s
, insn
);
11175 case 0xd: /* Data processing - register */
11176 disas_data_proc_reg(s
, insn
);
11179 case 0xf: /* Data processing - SIMD and floating point */
11180 disas_data_proc_simd_fp(s
, insn
);
11183 assert(FALSE
); /* all 15 cases should be handled above */
11187 /* if we allocated any temporaries, free them here */
11191 void gen_intermediate_code_a64(ARMCPU
*cpu
, TranslationBlock
*tb
)
11193 CPUState
*cs
= CPU(cpu
);
11194 CPUARMState
*env
= &cpu
->env
;
11195 DisasContext dc1
, *dc
= &dc1
;
11196 target_ulong pc_start
;
11197 target_ulong next_page_start
;
11205 dc
->is_jmp
= DISAS_NEXT
;
11207 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11211 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11212 * there is no secure EL1, so we route exceptions to EL3.
11214 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11215 !arm_el_is_aa64(env
, 3);
11218 dc
->be_data
= ARM_TBFLAG_BE_DATA(tb
->flags
) ? MO_BE
: MO_LE
;
11219 dc
->condexec_mask
= 0;
11220 dc
->condexec_cond
= 0;
11221 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(tb
->flags
));
11222 dc
->tbi0
= ARM_TBFLAG_TBI0(tb
->flags
);
11223 dc
->tbi1
= ARM_TBFLAG_TBI1(tb
->flags
);
11224 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11225 #if !defined(CONFIG_USER_ONLY)
11226 dc
->user
= (dc
->current_el
== 0);
11228 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11230 dc
->vec_stride
= 0;
11231 dc
->cp_regs
= cpu
->cp_regs
;
11232 dc
->features
= env
->features
;
11234 /* Single step state. The code-generation logic here is:
11236 * generate code with no special handling for single-stepping (except
11237 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11238 * this happens anyway because those changes are all system register or
11240 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11241 * emit code for one insn
11242 * emit code to clear PSTATE.SS
11243 * emit code to generate software step exception for completed step
11244 * end TB (as usual for having generated an exception)
11245 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11246 * emit code to generate a software step exception
11249 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11250 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11251 dc
->is_ldex
= false;
11252 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11254 init_tmp_a64_array(dc
);
11256 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11258 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11259 if (max_insns
== 0) {
11260 max_insns
= CF_COUNT_MASK
;
11262 if (max_insns
> TCG_MAX_INSNS
) {
11263 max_insns
= TCG_MAX_INSNS
;
11268 tcg_clear_temp_count();
11271 dc
->insn_start_idx
= tcg_op_buf_count();
11272 tcg_gen_insn_start(dc
->pc
, 0, 0);
11275 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11277 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11278 if (bp
->pc
== dc
->pc
) {
11279 if (bp
->flags
& BP_CPU
) {
11280 gen_a64_set_pc_im(dc
->pc
);
11281 gen_helper_check_breakpoints(cpu_env
);
11282 /* End the TB early; it likely won't be executed */
11283 dc
->is_jmp
= DISAS_UPDATE
;
11285 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11286 /* The address covered by the breakpoint must be
11287 included in [tb->pc, tb->pc + tb->size) in order
11288 to for it to be properly cleared -- thus we
11289 increment the PC here so that the logic setting
11290 tb->size below does the right thing. */
11292 goto done_generating
;
11299 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11303 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11304 /* Singlestep state is Active-pending.
11305 * If we're in this state at the start of a TB then either
11306 * a) we just took an exception to an EL which is being debugged
11307 * and this is the first insn in the exception handler
11308 * b) debug exceptions were masked and we just unmasked them
11309 * without changing EL (eg by clearing PSTATE.D)
11310 * In either case we're going to take a swstep exception in the
11311 * "did not step an insn" case, and so the syndrome ISV and EX
11312 * bits should be zero.
11314 assert(num_insns
== 1);
11315 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11316 default_exception_el(dc
));
11317 dc
->is_jmp
= DISAS_EXC
;
11321 disas_a64_insn(env
, dc
);
11323 if (tcg_check_temp_count()) {
11324 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11328 /* Translation stops when a conditional branch is encountered.
11329 * Otherwise the subsequent code could get translated several times.
11330 * Also stop translation when a page boundary is reached. This
11331 * ensures prefetch aborts occur at the right place.
11333 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11334 !cs
->singlestep_enabled
&&
11337 dc
->pc
< next_page_start
&&
11338 num_insns
< max_insns
);
11340 if (tb
->cflags
& CF_LAST_IO
) {
11344 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11345 && dc
->is_jmp
!= DISAS_EXC
) {
11346 /* Note that this means single stepping WFI doesn't halt the CPU.
11347 * For conditional branch insns this is harmless unreachable code as
11348 * gen_goto_tb() has already handled emitting the debug exception
11349 * (and thus a tb-jump is not possible when singlestepping).
11351 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11352 if (dc
->is_jmp
!= DISAS_JUMP
) {
11353 gen_a64_set_pc_im(dc
->pc
);
11355 if (cs
->singlestep_enabled
) {
11356 gen_exception_internal(EXCP_DEBUG
);
11358 gen_step_complete_exception(dc
);
11361 switch (dc
->is_jmp
) {
11363 gen_goto_tb(dc
, 1, dc
->pc
);
11367 gen_a64_set_pc_im(dc
->pc
);
11370 /* indicate that the hash table must be used to find the next TB */
11371 tcg_gen_exit_tb(0);
11373 case DISAS_TB_JUMP
:
11378 gen_a64_set_pc_im(dc
->pc
);
11379 gen_helper_wfe(cpu_env
);
11382 gen_a64_set_pc_im(dc
->pc
);
11383 gen_helper_yield(cpu_env
);
11386 /* This is a special case because we don't want to just halt the CPU
11387 * if trying to debug across a WFI.
11389 gen_a64_set_pc_im(dc
->pc
);
11390 gen_helper_wfi(cpu_env
);
11391 /* The helper doesn't necessarily throw an exception, but we
11392 * must go back to the main loop to check for interrupts anyway.
11394 tcg_gen_exit_tb(0);
11400 gen_tb_end(tb
, num_insns
);
11403 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
) &&
11404 qemu_log_in_addr_range(pc_start
)) {
11406 qemu_log("----------------\n");
11407 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11408 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11409 4 | (bswap_code(dc
->sctlr_b
) ? 2 : 0));
11414 tb
->size
= dc
->pc
- pc_start
;
11415 tb
->icount
= num_insns
;