target/s390x/helper.c

   1 /*
   2  *  S/390 helpers
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2011 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "internal.h"
  24 #include "exec/gdbstub.h"
  25 #include "qemu/timer.h"
  26 #include "qemu/qemu-print.h"
  27 #include "hw/s390x/ioinst.h"
  28 #include "sysemu/hw_accel.h"
  29 #include "sysemu/runstate.h"
  30 #ifndef CONFIG_USER_ONLY
  31 #include "sysemu/tcg.h"
  32 #endif
  33
  34 #ifndef CONFIG_USER_ONLY
  35 void s390x_tod_timer(void *opaque)
  36 {
  37     cpu_inject_clock_comparator((S390CPU *) opaque);
  38 }
  39
  40 void s390x_cpu_timer(void *opaque)
  41 {
  42     cpu_inject_cpu_timer((S390CPU *) opaque);
  43 }
  44 #endif
  45
  46 #ifndef CONFIG_USER_ONLY
  47
  48 hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
  49 {
  50     S390CPU *cpu = S390_CPU(cs);
  51     CPUS390XState *env = &cpu->env;
  52     target_ulong raddr;
  53     int prot;
  54     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
  55     uint64_t tec;
  56
  57     /* 31-Bit mode */
  58     if (!(env->psw.mask & PSW_MASK_64)) {
  59         vaddr &= 0x7fffffff;
  60     }
  61
  62     /* We want to read the code (e.g., see what we are single-stepping).*/
  63     if (asc != PSW_ASC_HOME) {
  64         asc = PSW_ASC_PRIMARY;
  65     }
  66
  67     /*
  68      * We want to read code even if IEP is active. Use MMU_DATA_LOAD instead
  69      * of MMU_INST_FETCH.
  70      */
  71     if (mmu_translate(env, vaddr, MMU_DATA_LOAD, asc, &raddr, &prot, &tec)) {
  72         return -1;
  73     }
  74     return raddr;
  75 }
  76
  77 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
  78 {
  79     hwaddr phys_addr;
  80     target_ulong page;
  81
  82     page = vaddr & TARGET_PAGE_MASK;
  83     phys_addr = cpu_get_phys_page_debug(cs, page);
  84     phys_addr += (vaddr & ~TARGET_PAGE_MASK);
  85
  86     return phys_addr;
  87 }
  88
  89 static inline bool is_special_wait_psw(uint64_t psw_addr)
  90 {
  91     /* signal quiesce */
  92     return (psw_addr & 0xfffUL) == 0xfffUL;
  93 }
  94
  95 void s390_handle_wait(S390CPU *cpu)
  96 {
  97     CPUState *cs = CPU(cpu);
  98
  99     if (s390_cpu_halt(cpu) == 0) {
 100 #ifndef CONFIG_USER_ONLY
 101         if (is_special_wait_psw(cpu->env.psw.addr)) {
 102             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 103         } else {
 104             cpu->env.crash_reason = S390_CRASH_REASON_DISABLED_WAIT;
 105             qemu_system_guest_panicked(cpu_get_crash_info(cs));
 106         }
 107 #endif
 108     }
 109 }
 110
 111 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
 112 {
 113     uint64_t old_mask = env->psw.mask;
 114
 115     env->psw.addr = addr;
 116     env->psw.mask = mask;
 117
 118     /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */
 119     if (!tcg_enabled()) {
 120         return;
 121     }
 122     env->cc_op = (mask >> 44) & 3;
 123
 124     if ((old_mask ^ mask) & PSW_MASK_PER) {
 125         s390_cpu_recompute_watchpoints(env_cpu(env));
 126     }
 127
 128     if (mask & PSW_MASK_WAIT) {
 129         s390_handle_wait(env_archcpu(env));
 130     }
 131 }
 132
 133 uint64_t get_psw_mask(CPUS390XState *env)
 134 {
 135     uint64_t r = env->psw.mask;
 136
 137     if (tcg_enabled()) {
 138         env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
 139                              env->cc_vr);
 140
 141         r &= ~PSW_MASK_CC;
 142         assert(!(env->cc_op & ~3));
 143         r |= (uint64_t)env->cc_op << 44;
 144     }
 145
 146     return r;
 147 }
 148
 149 LowCore *cpu_map_lowcore(CPUS390XState *env)
 150 {
 151     LowCore *lowcore;
 152     hwaddr len = sizeof(LowCore);
 153
 154     lowcore = cpu_physical_memory_map(env->psa, &len, true);
 155
 156     if (len < sizeof(LowCore)) {
 157         cpu_abort(env_cpu(env), "Could not map lowcore\n");
 158     }
 159
 160     return lowcore;
 161 }
 162
 163 void cpu_unmap_lowcore(LowCore *lowcore)
 164 {
 165     cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
 166 }
 167
 168 void do_restart_interrupt(CPUS390XState *env)
 169 {
 170     uint64_t mask, addr;
 171     LowCore *lowcore;
 172
 173     lowcore = cpu_map_lowcore(env);
 174
 175     lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 176     lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr);
 177     mask = be64_to_cpu(lowcore->restart_new_psw.mask);
 178     addr = be64_to_cpu(lowcore->restart_new_psw.addr);
 179
 180     cpu_unmap_lowcore(lowcore);
 181     env->pending_int &= ~INTERRUPT_RESTART;
 182
 183     load_psw(env, mask, addr);
 184 }
 185
 186 void s390_cpu_recompute_watchpoints(CPUState *cs)
 187 {
 188     const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS;
 189     S390CPU *cpu = S390_CPU(cs);
 190     CPUS390XState *env = &cpu->env;
 191
 192     /* We are called when the watchpoints have changed. First
 193        remove them all.  */
 194     cpu_watchpoint_remove_all(cs, BP_CPU);
 195
 196     /* Return if PER is not enabled */
 197     if (!(env->psw.mask & PSW_MASK_PER)) {
 198         return;
 199     }
 200
 201     /* Return if storage-alteration event is not enabled.  */
 202     if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) {
 203         return;
 204     }
 205
 206     if (env->cregs[10] == 0 && env->cregs[11] == -1LL) {
 207         /* We can't create a watchoint spanning the whole memory range, so
 208            split it in two parts.   */
 209         cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL);
 210         cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL);
 211     } else if (env->cregs[10] > env->cregs[11]) {
 212         /* The address range loops, create two watchpoints.  */
 213         cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10],
 214                               wp_flags, NULL);
 215         cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL);
 216
 217     } else {
 218         /* Default case, create a single watchpoint.  */
 219         cpu_watchpoint_insert(cs, env->cregs[10],
 220                               env->cregs[11] - env->cregs[10] + 1,
 221                               wp_flags, NULL);
 222     }
 223 }
 224
 225 typedef struct SigpSaveArea {
 226     uint64_t    fprs[16];                       /* 0x0000 */
 227     uint64_t    grs[16];                        /* 0x0080 */
 228     PSW         psw;                            /* 0x0100 */
 229     uint8_t     pad_0x0110[0x0118 - 0x0110];    /* 0x0110 */
 230     uint32_t    prefix;                         /* 0x0118 */
 231     uint32_t    fpc;                            /* 0x011c */
 232     uint8_t     pad_0x0120[0x0124 - 0x0120];    /* 0x0120 */
 233     uint32_t    todpr;                          /* 0x0124 */
 234     uint64_t    cputm;                          /* 0x0128 */
 235     uint64_t    ckc;                            /* 0x0130 */
 236     uint8_t     pad_0x0138[0x0140 - 0x0138];    /* 0x0138 */
 237     uint32_t    ars[16];                        /* 0x0140 */
 238     uint64_t    crs[16];                        /* 0x0384 */
 239 } SigpSaveArea;
 240 QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512);
 241
 242 int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
 243 {
 244     static const uint8_t ar_id = 1;
 245     SigpSaveArea *sa;
 246     hwaddr len = sizeof(*sa);
 247     int i;
 248
 249     sa = cpu_physical_memory_map(addr, &len, true);
 250     if (!sa) {
 251         return -EFAULT;
 252     }
 253     if (len != sizeof(*sa)) {
 254         cpu_physical_memory_unmap(sa, len, 1, 0);
 255         return -EFAULT;
 256     }
 257
 258     if (store_arch) {
 259         cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1);
 260     }
 261     for (i = 0; i < 16; ++i) {
 262         sa->fprs[i] = cpu_to_be64(*get_freg(&cpu->env, i));
 263     }
 264     for (i = 0; i < 16; ++i) {
 265         sa->grs[i] = cpu_to_be64(cpu->env.regs[i]);
 266     }
 267     sa->psw.addr = cpu_to_be64(cpu->env.psw.addr);
 268     sa->psw.mask = cpu_to_be64(get_psw_mask(&cpu->env));
 269     sa->prefix = cpu_to_be32(cpu->env.psa);
 270     sa->fpc = cpu_to_be32(cpu->env.fpc);
 271     sa->todpr = cpu_to_be32(cpu->env.todpr);
 272     sa->cputm = cpu_to_be64(cpu->env.cputm);
 273     sa->ckc = cpu_to_be64(cpu->env.ckc >> 8);
 274     for (i = 0; i < 16; ++i) {
 275         sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]);
 276     }
 277     for (i = 0; i < 16; ++i) {
 278         sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]);
 279     }
 280
 281     cpu_physical_memory_unmap(sa, len, 1, len);
 282
 283     return 0;
 284 }
 285
 286 typedef struct SigpAdtlSaveArea {
 287     uint64_t    vregs[32][2];                     /* 0x0000 */
 288     uint8_t     pad_0x0200[0x0400 - 0x0200];      /* 0x0200 */
 289     uint64_t    gscb[4];                          /* 0x0400 */
 290     uint8_t     pad_0x0420[0x1000 - 0x0420];      /* 0x0420 */
 291 } SigpAdtlSaveArea;
 292 QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096);
 293
 294 #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
 295 int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
 296 {
 297     SigpAdtlSaveArea *sa;
 298     hwaddr save = len;
 299     int i;
 300
 301     sa = cpu_physical_memory_map(addr, &save, true);
 302     if (!sa) {
 303         return -EFAULT;
 304     }
 305     if (save != len) {
 306         cpu_physical_memory_unmap(sa, len, 1, 0);
 307         return -EFAULT;
 308     }
 309
 310     if (s390_has_feat(S390_FEAT_VECTOR)) {
 311         for (i = 0; i < 32; i++) {
 312             sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0]);
 313             sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1]);
 314         }
 315     }
 316     if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
 317         for (i = 0; i < 4; i++) {
 318             sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]);
 319         }
 320     }
 321
 322     cpu_physical_memory_unmap(sa, len, 1, len);
 323     return 0;
 324 }
 325 #endif /* CONFIG_USER_ONLY */
 326
 327 void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 328 {
 329     S390CPU *cpu = S390_CPU(cs);
 330     CPUS390XState *env = &cpu->env;
 331     int i;
 332
 333     if (env->cc_op > 3) {
 334         qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
 335                      env->psw.mask, env->psw.addr, cc_name(env->cc_op));
 336     } else {
 337         qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
 338                      env->psw.mask, env->psw.addr, env->cc_op);
 339     }
 340
 341     for (i = 0; i < 16; i++) {
 342         qemu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
 343         if ((i % 4) == 3) {
 344             qemu_fprintf(f, "\n");
 345         } else {
 346             qemu_fprintf(f, " ");
 347         }
 348     }
 349
 350     if (flags & CPU_DUMP_FPU) {
 351         if (s390_has_feat(S390_FEAT_VECTOR)) {
 352             for (i = 0; i < 32; i++) {
 353                 qemu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c",
 354                              i, env->vregs[i][0], env->vregs[i][1],
 355                              i % 2 ? '\n' : ' ');
 356             }
 357         } else {
 358             for (i = 0; i < 16; i++) {
 359                 qemu_fprintf(f, "F%02d=%016" PRIx64 "%c",
 360                              i, *get_freg(env, i),
 361                              (i % 4) == 3 ? '\n' : ' ');
 362             }
 363         }
 364     }
 365
 366 #ifndef CONFIG_USER_ONLY
 367     for (i = 0; i < 16; i++) {
 368         qemu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
 369         if ((i % 4) == 3) {
 370             qemu_fprintf(f, "\n");
 371         } else {
 372             qemu_fprintf(f, " ");
 373         }
 374     }
 375 #endif
 376
 377 #ifdef DEBUG_INLINE_BRANCHES
 378     for (i = 0; i < CC_OP_MAX; i++) {
 379         qemu_fprintf(f, "  %15s = %10ld\t%10ld\n", cc_name(i),
 380                      inline_branch_miss[i], inline_branch_hit[i]);
 381     }
 382 #endif
 383
 384     qemu_fprintf(f, "\n");
 385 }
 386
 387 const char *cc_name(enum cc_op cc_op)
 388 {
 389     static const char * const cc_names[] = {
 390         [CC_OP_CONST0]    = "CC_OP_CONST0",
 391         [CC_OP_CONST1]    = "CC_OP_CONST1",
 392         [CC_OP_CONST2]    = "CC_OP_CONST2",
 393         [CC_OP_CONST3]    = "CC_OP_CONST3",
 394         [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 395         [CC_OP_STATIC]    = "CC_OP_STATIC",
 396         [CC_OP_NZ]        = "CC_OP_NZ",
 397         [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 398         [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 399         [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 400         [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 401         [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 402         [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 403         [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 404         [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 405         [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 406         [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 407         [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 408         [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 409         [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 410         [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 411         [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 412         [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 413         [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 414         [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 415         [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 416         [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 417         [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 418         [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 419         [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 420         [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 421         [CC_OP_TM_32]     = "CC_OP_TM_32",
 422         [CC_OP_TM_64]     = "CC_OP_TM_64",
 423         [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 424         [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 425         [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 426         [CC_OP_ICM]       = "CC_OP_ICM",
 427         [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 428         [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 429         [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 430         [CC_OP_LCBB]      = "CC_OP_LCBB",
 431         [CC_OP_VC]        = "CC_OP_VC",
 432     };
 433
 434     return cc_names[cc_op];
 435 }