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target-arm: A64: Move handle_2misc_narrow function
[qemu/ar7.git] / target-arm / translate.c
blob3771953e029dd67d97c61e5c68be42f5f00ad93c
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <stdarg.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <string.h>
25 #include <inttypes.h>
26
27 #include "cpu.h"
28 #include "disas/disas.h"
29 #include "tcg-op.h"
30 #include "qemu/log.h"
31 #include "qemu/bitops.h"
32
33 #include "helper.h"
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 #define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T)
38 #define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5)
39 /* currently all emulated v5 cores are also v5TE, so don't bother */
40 #define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5)
41 #define ENABLE_ARCH_5J 0
42 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
43 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
44 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
45 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
46 #define ENABLE_ARCH_8 arm_feature(env, ARM_FEATURE_V8)
47
48 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
49
50 #include "translate.h"
51 static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
52
53 #if defined(CONFIG_USER_ONLY)
54 #define IS_USER(s) 1
55 #else
56 #define IS_USER(s) (s->user)
57 #endif
58
59 TCGv_ptr cpu_env;
60 /* We reuse the same 64-bit temporaries for efficiency. */
61 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
62 static TCGv_i32 cpu_R[16];
63 static TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
64 static TCGv_i64 cpu_exclusive_addr;
65 static TCGv_i64 cpu_exclusive_val;
66 #ifdef CONFIG_USER_ONLY
67 static TCGv_i64 cpu_exclusive_test;
68 static TCGv_i32 cpu_exclusive_info;
69 #endif
70
71 /* FIXME: These should be removed. */
72 static TCGv_i32 cpu_F0s, cpu_F1s;
73 static TCGv_i64 cpu_F0d, cpu_F1d;
74
75 #include "exec/gen-icount.h"
76
77 static const char *regnames[] =
78 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
79 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
80
81 /* initialize TCG globals. */
82 void arm_translate_init(void)
83 {
84 int i;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 for (i = 0; i < 16; i++) {
89 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
90 offsetof(CPUARMState, regs[i]),
91 regnames[i]);
92 }
93 cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
94 cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
95 cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
96 cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
97
98 cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
99 offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
100 cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
101 offsetof(CPUARMState, exclusive_val), "exclusive_val");
102 #ifdef CONFIG_USER_ONLY
103 cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
104 offsetof(CPUARMState, exclusive_test), "exclusive_test");
105 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
106 offsetof(CPUARMState, exclusive_info), "exclusive_info");
107 #endif
108
109 a64_translate_init();
110 }
111
112 static inline TCGv_i32 load_cpu_offset(int offset)
113 {
114 TCGv_i32 tmp = tcg_temp_new_i32();
115 tcg_gen_ld_i32(tmp, cpu_env, offset);
116 return tmp;
117 }
118
119 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
120
121 static inline void store_cpu_offset(TCGv_i32 var, int offset)
122 {
123 tcg_gen_st_i32(var, cpu_env, offset);
124 tcg_temp_free_i32(var);
125 }
126
127 #define store_cpu_field(var, name) \
128 store_cpu_offset(var, offsetof(CPUARMState, name))
129
130 /* Set a variable to the value of a CPU register. */
131 static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
132 {
133 if (reg == 15) {
134 uint32_t addr;
135 /* normally, since we updated PC, we need only to add one insn */
136 if (s->thumb)
137 addr = (long)s->pc + 2;
138 else
139 addr = (long)s->pc + 4;
140 tcg_gen_movi_i32(var, addr);
141 } else {
142 tcg_gen_mov_i32(var, cpu_R[reg]);
143 }
144 }
145
146 /* Create a new temporary and set it to the value of a CPU register. */
147 static inline TCGv_i32 load_reg(DisasContext *s, int reg)
148 {
149 TCGv_i32 tmp = tcg_temp_new_i32();
150 load_reg_var(s, tmp, reg);
151 return tmp;
152 }
153
154 /* Set a CPU register. The source must be a temporary and will be
155 marked as dead. */
156 static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
157 {
158 if (reg == 15) {
159 tcg_gen_andi_i32(var, var, ~1);
160 s->is_jmp = DISAS_JUMP;
161 }
162 tcg_gen_mov_i32(cpu_R[reg], var);
163 tcg_temp_free_i32(var);
164 }
165
166 /* Value extensions. */
167 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
168 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
169 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
170 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
171
172 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
173 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
174
175
176 static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
177 {
178 TCGv_i32 tmp_mask = tcg_const_i32(mask);
179 gen_helper_cpsr_write(cpu_env, var, tmp_mask);
180 tcg_temp_free_i32(tmp_mask);
181 }
182 /* Set NZCV flags from the high 4 bits of var. */
183 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
184
185 static void gen_exception(int excp)
186 {
187 TCGv_i32 tmp = tcg_temp_new_i32();
188 tcg_gen_movi_i32(tmp, excp);
189 gen_helper_exception(cpu_env, tmp);
190 tcg_temp_free_i32(tmp);
191 }
192
193 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
194 {
195 TCGv_i32 tmp1 = tcg_temp_new_i32();
196 TCGv_i32 tmp2 = tcg_temp_new_i32();
197 tcg_gen_ext16s_i32(tmp1, a);
198 tcg_gen_ext16s_i32(tmp2, b);
199 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
200 tcg_temp_free_i32(tmp2);
201 tcg_gen_sari_i32(a, a, 16);
202 tcg_gen_sari_i32(b, b, 16);
203 tcg_gen_mul_i32(b, b, a);
204 tcg_gen_mov_i32(a, tmp1);
205 tcg_temp_free_i32(tmp1);
206 }
207
208 /* Byteswap each halfword. */
209 static void gen_rev16(TCGv_i32 var)
210 {
211 TCGv_i32 tmp = tcg_temp_new_i32();
212 tcg_gen_shri_i32(tmp, var, 8);
213 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
214 tcg_gen_shli_i32(var, var, 8);
215 tcg_gen_andi_i32(var, var, 0xff00ff00);
216 tcg_gen_or_i32(var, var, tmp);
217 tcg_temp_free_i32(tmp);
218 }
219
220 /* Byteswap low halfword and sign extend. */
221 static void gen_revsh(TCGv_i32 var)
222 {
223 tcg_gen_ext16u_i32(var, var);
224 tcg_gen_bswap16_i32(var, var);
225 tcg_gen_ext16s_i32(var, var);
226 }
227
228 /* Unsigned bitfield extract. */
229 static void gen_ubfx(TCGv_i32 var, int shift, uint32_t mask)
230 {
231 if (shift)
232 tcg_gen_shri_i32(var, var, shift);
233 tcg_gen_andi_i32(var, var, mask);
234 }
235
236 /* Signed bitfield extract. */
237 static void gen_sbfx(TCGv_i32 var, int shift, int width)
238 {
239 uint32_t signbit;
240
241 if (shift)
242 tcg_gen_sari_i32(var, var, shift);
243 if (shift + width < 32) {
244 signbit = 1u << (width - 1);
245 tcg_gen_andi_i32(var, var, (1u << width) - 1);
246 tcg_gen_xori_i32(var, var, signbit);
247 tcg_gen_subi_i32(var, var, signbit);
248 }
249 }
250
251 /* Return (b << 32) + a. Mark inputs as dead */
252 static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv_i32 b)
253 {
254 TCGv_i64 tmp64 = tcg_temp_new_i64();
255
256 tcg_gen_extu_i32_i64(tmp64, b);
257 tcg_temp_free_i32(b);
258 tcg_gen_shli_i64(tmp64, tmp64, 32);
259 tcg_gen_add_i64(a, tmp64, a);
260
261 tcg_temp_free_i64(tmp64);
262 return a;
263 }
264
265 /* Return (b << 32) - a. Mark inputs as dead. */
266 static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv_i32 b)
267 {
268 TCGv_i64 tmp64 = tcg_temp_new_i64();
269
270 tcg_gen_extu_i32_i64(tmp64, b);
271 tcg_temp_free_i32(b);
272 tcg_gen_shli_i64(tmp64, tmp64, 32);
273 tcg_gen_sub_i64(a, tmp64, a);
274
275 tcg_temp_free_i64(tmp64);
276 return a;
277 }
278
279 /* 32x32->64 multiply. Marks inputs as dead. */
280 static TCGv_i64 gen_mulu_i64_i32(TCGv_i32 a, TCGv_i32 b)
281 {
282 TCGv_i32 lo = tcg_temp_new_i32();
283 TCGv_i32 hi = tcg_temp_new_i32();
284 TCGv_i64 ret;
285
286 tcg_gen_mulu2_i32(lo, hi, a, b);
287 tcg_temp_free_i32(a);
288 tcg_temp_free_i32(b);
289
290 ret = tcg_temp_new_i64();
291 tcg_gen_concat_i32_i64(ret, lo, hi);
292 tcg_temp_free_i32(lo);
293 tcg_temp_free_i32(hi);
294
295 return ret;
296 }
297
298 static TCGv_i64 gen_muls_i64_i32(TCGv_i32 a, TCGv_i32 b)
299 {
300 TCGv_i32 lo = tcg_temp_new_i32();
301 TCGv_i32 hi = tcg_temp_new_i32();
302 TCGv_i64 ret;
303
304 tcg_gen_muls2_i32(lo, hi, a, b);
305 tcg_temp_free_i32(a);
306 tcg_temp_free_i32(b);
307
308 ret = tcg_temp_new_i64();
309 tcg_gen_concat_i32_i64(ret, lo, hi);
310 tcg_temp_free_i32(lo);
311 tcg_temp_free_i32(hi);
312
313 return ret;
314 }
315
316 /* Swap low and high halfwords. */
317 static void gen_swap_half(TCGv_i32 var)
318 {
319 TCGv_i32 tmp = tcg_temp_new_i32();
320 tcg_gen_shri_i32(tmp, var, 16);
321 tcg_gen_shli_i32(var, var, 16);
322 tcg_gen_or_i32(var, var, tmp);
323 tcg_temp_free_i32(tmp);
324 }
325
326 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
327 tmp = (t0 ^ t1) & 0x8000;
328 t0 &= ~0x8000;
329 t1 &= ~0x8000;
330 t0 = (t0 + t1) ^ tmp;
331 */
332
333 static void gen_add16(TCGv_i32 t0, TCGv_i32 t1)
334 {
335 TCGv_i32 tmp = tcg_temp_new_i32();
336 tcg_gen_xor_i32(tmp, t0, t1);
337 tcg_gen_andi_i32(tmp, tmp, 0x8000);
338 tcg_gen_andi_i32(t0, t0, ~0x8000);
339 tcg_gen_andi_i32(t1, t1, ~0x8000);
340 tcg_gen_add_i32(t0, t0, t1);
341 tcg_gen_xor_i32(t0, t0, tmp);
342 tcg_temp_free_i32(tmp);
343 tcg_temp_free_i32(t1);
344 }
345
346 /* Set CF to the top bit of var. */
347 static void gen_set_CF_bit31(TCGv_i32 var)
348 {
349 tcg_gen_shri_i32(cpu_CF, var, 31);
350 }
351
352 /* Set N and Z flags from var. */
353 static inline void gen_logic_CC(TCGv_i32 var)
354 {
355 tcg_gen_mov_i32(cpu_NF, var);
356 tcg_gen_mov_i32(cpu_ZF, var);
357 }
358
359 /* T0 += T1 + CF. */
360 static void gen_adc(TCGv_i32 t0, TCGv_i32 t1)
361 {
362 tcg_gen_add_i32(t0, t0, t1);
363 tcg_gen_add_i32(t0, t0, cpu_CF);
364 }
365
366 /* dest = T0 + T1 + CF. */
367 static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
368 {
369 tcg_gen_add_i32(dest, t0, t1);
370 tcg_gen_add_i32(dest, dest, cpu_CF);
371 }
372
373 /* dest = T0 - T1 + CF - 1. */
374 static void gen_sub_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
375 {
376 tcg_gen_sub_i32(dest, t0, t1);
377 tcg_gen_add_i32(dest, dest, cpu_CF);
378 tcg_gen_subi_i32(dest, dest, 1);
379 }
380
381 /* dest = T0 + T1. Compute C, N, V and Z flags */
382 static void gen_add_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
383 {
384 TCGv_i32 tmp = tcg_temp_new_i32();
385 tcg_gen_movi_i32(tmp, 0);
386 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, t1, tmp);
387 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
388 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
389 tcg_gen_xor_i32(tmp, t0, t1);
390 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
391 tcg_temp_free_i32(tmp);
392 tcg_gen_mov_i32(dest, cpu_NF);
393 }
394
395 /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */
396 static void gen_adc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
397 {
398 TCGv_i32 tmp = tcg_temp_new_i32();
399 if (TCG_TARGET_HAS_add2_i32) {
400 tcg_gen_movi_i32(tmp, 0);
401 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp);
402 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp);
403 } else {
404 TCGv_i64 q0 = tcg_temp_new_i64();
405 TCGv_i64 q1 = tcg_temp_new_i64();
406 tcg_gen_extu_i32_i64(q0, t0);
407 tcg_gen_extu_i32_i64(q1, t1);
408 tcg_gen_add_i64(q0, q0, q1);
409 tcg_gen_extu_i32_i64(q1, cpu_CF);
410 tcg_gen_add_i64(q0, q0, q1);
411 tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0);
412 tcg_temp_free_i64(q0);
413 tcg_temp_free_i64(q1);
414 }
415 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
416 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
417 tcg_gen_xor_i32(tmp, t0, t1);
418 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
419 tcg_temp_free_i32(tmp);
420 tcg_gen_mov_i32(dest, cpu_NF);
421 }
422
423 /* dest = T0 - T1. Compute C, N, V and Z flags */
424 static void gen_sub_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
425 {
426 TCGv_i32 tmp;
427 tcg_gen_sub_i32(cpu_NF, t0, t1);
428 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
429 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0, t1);
430 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
431 tmp = tcg_temp_new_i32();
432 tcg_gen_xor_i32(tmp, t0, t1);
433 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
434 tcg_temp_free_i32(tmp);
435 tcg_gen_mov_i32(dest, cpu_NF);
436 }
437
438 /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */
439 static void gen_sbc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
440 {
441 TCGv_i32 tmp = tcg_temp_new_i32();
442 tcg_gen_not_i32(tmp, t1);
443 gen_adc_CC(dest, t0, tmp);
444 tcg_temp_free_i32(tmp);
445 }
446
447 #define GEN_SHIFT(name) \
448 static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \
449 { \
450 TCGv_i32 tmp1, tmp2, tmp3; \
451 tmp1 = tcg_temp_new_i32(); \
452 tcg_gen_andi_i32(tmp1, t1, 0xff); \
453 tmp2 = tcg_const_i32(0); \
454 tmp3 = tcg_const_i32(0x1f); \
455 tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \
456 tcg_temp_free_i32(tmp3); \
457 tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \
458 tcg_gen_##name##_i32(dest, tmp2, tmp1); \
459 tcg_temp_free_i32(tmp2); \
460 tcg_temp_free_i32(tmp1); \
461 }
462 GEN_SHIFT(shl)
463 GEN_SHIFT(shr)
464 #undef GEN_SHIFT
465
466 static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
467 {
468 TCGv_i32 tmp1, tmp2;
469 tmp1 = tcg_temp_new_i32();
470 tcg_gen_andi_i32(tmp1, t1, 0xff);
471 tmp2 = tcg_const_i32(0x1f);
472 tcg_gen_movcond_i32(TCG_COND_GTU, tmp1, tmp1, tmp2, tmp2, tmp1);
473 tcg_temp_free_i32(tmp2);
474 tcg_gen_sar_i32(dest, t0, tmp1);
475 tcg_temp_free_i32(tmp1);
476 }
477
478 static void tcg_gen_abs_i32(TCGv_i32 dest, TCGv_i32 src)
479 {
480 TCGv_i32 c0 = tcg_const_i32(0);
481 TCGv_i32 tmp = tcg_temp_new_i32();
482 tcg_gen_neg_i32(tmp, src);
483 tcg_gen_movcond_i32(TCG_COND_GT, dest, src, c0, src, tmp);
484 tcg_temp_free_i32(c0);
485 tcg_temp_free_i32(tmp);
486 }
487
488 static void shifter_out_im(TCGv_i32 var, int shift)
489 {
490 if (shift == 0) {
491 tcg_gen_andi_i32(cpu_CF, var, 1);
492 } else {
493 tcg_gen_shri_i32(cpu_CF, var, shift);
494 if (shift != 31) {
495 tcg_gen_andi_i32(cpu_CF, cpu_CF, 1);
496 }
497 }
498 }
499
500 /* Shift by immediate. Includes special handling for shift == 0. */
501 static inline void gen_arm_shift_im(TCGv_i32 var, int shiftop,
502 int shift, int flags)
503 {
504 switch (shiftop) {
505 case 0: /* LSL */
506 if (shift != 0) {
507 if (flags)
508 shifter_out_im(var, 32 - shift);
509 tcg_gen_shli_i32(var, var, shift);
510 }
511 break;
512 case 1: /* LSR */
513 if (shift == 0) {
514 if (flags) {
515 tcg_gen_shri_i32(cpu_CF, var, 31);
516 }
517 tcg_gen_movi_i32(var, 0);
518 } else {
519 if (flags)
520 shifter_out_im(var, shift - 1);
521 tcg_gen_shri_i32(var, var, shift);
522 }
523 break;
524 case 2: /* ASR */
525 if (shift == 0)
526 shift = 32;
527 if (flags)
528 shifter_out_im(var, shift - 1);
529 if (shift == 32)
530 shift = 31;
531 tcg_gen_sari_i32(var, var, shift);
532 break;
533 case 3: /* ROR/RRX */
534 if (shift != 0) {
535 if (flags)
536 shifter_out_im(var, shift - 1);
537 tcg_gen_rotri_i32(var, var, shift); break;
538 } else {
539 TCGv_i32 tmp = tcg_temp_new_i32();
540 tcg_gen_shli_i32(tmp, cpu_CF, 31);
541 if (flags)
542 shifter_out_im(var, 0);
543 tcg_gen_shri_i32(var, var, 1);
544 tcg_gen_or_i32(var, var, tmp);
545 tcg_temp_free_i32(tmp);
546 }
547 }
548 };
549
550 static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop,
551 TCGv_i32 shift, int flags)
552 {
553 if (flags) {
554 switch (shiftop) {
555 case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
556 case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
557 case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
558 case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
559 }
560 } else {
561 switch (shiftop) {
562 case 0:
563 gen_shl(var, var, shift);
564 break;
565 case 1:
566 gen_shr(var, var, shift);
567 break;
568 case 2:
569 gen_sar(var, var, shift);
570 break;
571 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
572 tcg_gen_rotr_i32(var, var, shift); break;
573 }
574 }
575 tcg_temp_free_i32(shift);
576 }
577
578 #define PAS_OP(pfx) \
579 switch (op2) { \
580 case 0: gen_pas_helper(glue(pfx,add16)); break; \
581 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
582 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
583 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
584 case 4: gen_pas_helper(glue(pfx,add8)); break; \
585 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
586 }
587 static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
588 {
589 TCGv_ptr tmp;
590
591 switch (op1) {
592 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
593 case 1:
594 tmp = tcg_temp_new_ptr();
595 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
596 PAS_OP(s)
597 tcg_temp_free_ptr(tmp);
598 break;
599 case 5:
600 tmp = tcg_temp_new_ptr();
601 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
602 PAS_OP(u)
603 tcg_temp_free_ptr(tmp);
604 break;
605 #undef gen_pas_helper
606 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
607 case 2:
608 PAS_OP(q);
609 break;
610 case 3:
611 PAS_OP(sh);
612 break;
613 case 6:
614 PAS_OP(uq);
615 break;
616 case 7:
617 PAS_OP(uh);
618 break;
619 #undef gen_pas_helper
620 }
621 }
622 #undef PAS_OP
623
624 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
625 #define PAS_OP(pfx) \
626 switch (op1) { \
627 case 0: gen_pas_helper(glue(pfx,add8)); break; \
628 case 1: gen_pas_helper(glue(pfx,add16)); break; \
629 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
630 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
631 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
632 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
633 }
634 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
635 {
636 TCGv_ptr tmp;
637
638 switch (op2) {
639 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
640 case 0:
641 tmp = tcg_temp_new_ptr();
642 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
643 PAS_OP(s)
644 tcg_temp_free_ptr(tmp);
645 break;
646 case 4:
647 tmp = tcg_temp_new_ptr();
648 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
649 PAS_OP(u)
650 tcg_temp_free_ptr(tmp);
651 break;
652 #undef gen_pas_helper
653 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
654 case 1:
655 PAS_OP(q);
656 break;
657 case 2:
658 PAS_OP(sh);
659 break;
660 case 5:
661 PAS_OP(uq);
662 break;
663 case 6:
664 PAS_OP(uh);
665 break;
666 #undef gen_pas_helper
667 }
668 }
669 #undef PAS_OP
670
671 /*
672 * generate a conditional branch based on ARM condition code cc.
673 * This is common between ARM and Aarch64 targets.
674 */
675 void arm_gen_test_cc(int cc, int label)
676 {
677 TCGv_i32 tmp;
678 int inv;
679
680 switch (cc) {
681 case 0: /* eq: Z */
682 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ZF, 0, label);
683 break;
684 case 1: /* ne: !Z */
685 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_ZF, 0, label);
686 break;
687 case 2: /* cs: C */
688 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_CF, 0, label);
689 break;
690 case 3: /* cc: !C */
691 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_CF, 0, label);
692 break;
693 case 4: /* mi: N */
694 tcg_gen_brcondi_i32(TCG_COND_LT, cpu_NF, 0, label);
695 break;
696 case 5: /* pl: !N */
697 tcg_gen_brcondi_i32(TCG_COND_GE, cpu_NF, 0, label);
698 break;
699 case 6: /* vs: V */
700 tcg_gen_brcondi_i32(TCG_COND_LT, cpu_VF, 0, label);
701 break;
702 case 7: /* vc: !V */
703 tcg_gen_brcondi_i32(TCG_COND_GE, cpu_VF, 0, label);
704 break;
705 case 8: /* hi: C && !Z */
706 inv = gen_new_label();
707 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_CF, 0, inv);
708 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_ZF, 0, label);
709 gen_set_label(inv);
710 break;
711 case 9: /* ls: !C || Z */
712 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_CF, 0, label);
713 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ZF, 0, label);
714 break;
715 case 10: /* ge: N == V -> N ^ V == 0 */
716 tmp = tcg_temp_new_i32();
717 tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
718 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
719 tcg_temp_free_i32(tmp);
720 break;
721 case 11: /* lt: N != V -> N ^ V != 0 */
722 tmp = tcg_temp_new_i32();
723 tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
724 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
725 tcg_temp_free_i32(tmp);
726 break;
727 case 12: /* gt: !Z && N == V */
728 inv = gen_new_label();
729 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ZF, 0, inv);
730 tmp = tcg_temp_new_i32();
731 tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
732 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
733 tcg_temp_free_i32(tmp);
734 gen_set_label(inv);
735 break;
736 case 13: /* le: Z || N != V */
737 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ZF, 0, label);
738 tmp = tcg_temp_new_i32();
739 tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
740 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
741 tcg_temp_free_i32(tmp);
742 break;
743 default:
744 fprintf(stderr, "Bad condition code 0x%x\n", cc);
745 abort();
746 }
747 }
748
749 static const uint8_t table_logic_cc[16] = {
750 1, /* and */
751 1, /* xor */
752 0, /* sub */
753 0, /* rsb */
754 0, /* add */
755 0, /* adc */
756 0, /* sbc */
757 0, /* rsc */
758 1, /* andl */
759 1, /* xorl */
760 0, /* cmp */
761 0, /* cmn */
762 1, /* orr */
763 1, /* mov */
764 1, /* bic */
765 1, /* mvn */
766 };
767
768 /* Set PC and Thumb state from an immediate address. */
769 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
770 {
771 TCGv_i32 tmp;
772
773 s->is_jmp = DISAS_UPDATE;
774 if (s->thumb != (addr & 1)) {
775 tmp = tcg_temp_new_i32();
776 tcg_gen_movi_i32(tmp, addr & 1);
777 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
778 tcg_temp_free_i32(tmp);
779 }
780 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
781 }
782
783 /* Set PC and Thumb state from var. var is marked as dead. */
784 static inline void gen_bx(DisasContext *s, TCGv_i32 var)
785 {
786 s->is_jmp = DISAS_UPDATE;
787 tcg_gen_andi_i32(cpu_R[15], var, ~1);
788 tcg_gen_andi_i32(var, var, 1);
789 store_cpu_field(var, thumb);
790 }
791
792 /* Variant of store_reg which uses branch&exchange logic when storing
793 to r15 in ARM architecture v7 and above. The source must be a temporary
794 and will be marked as dead. */
795 static inline void store_reg_bx(CPUARMState *env, DisasContext *s,
796 int reg, TCGv_i32 var)
797 {
798 if (reg == 15 && ENABLE_ARCH_7) {
799 gen_bx(s, var);
800 } else {
801 store_reg(s, reg, var);
802 }
803 }
804
805 /* Variant of store_reg which uses branch&exchange logic when storing
806 * to r15 in ARM architecture v5T and above. This is used for storing
807 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
808 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
809 static inline void store_reg_from_load(CPUARMState *env, DisasContext *s,
810 int reg, TCGv_i32 var)
811 {
812 if (reg == 15 && ENABLE_ARCH_5) {
813 gen_bx(s, var);
814 } else {
815 store_reg(s, reg, var);
816 }
817 }
818
819 /* Abstractions of "generate code to do a guest load/store for
820 * AArch32", where a vaddr is always 32 bits (and is zero
821 * extended if we're a 64 bit core) and data is also
822 * 32 bits unless specifically doing a 64 bit access.
823 * These functions work like tcg_gen_qemu_{ld,st}* except
824 * that the address argument is TCGv_i32 rather than TCGv.
825 */
826 #if TARGET_LONG_BITS == 32
827
828 #define DO_GEN_LD(SUFF, OPC) \
829 static inline void gen_aa32_ld##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
830 { \
831 tcg_gen_qemu_ld_i32(val, addr, index, OPC); \
832 }
833
834 #define DO_GEN_ST(SUFF, OPC) \
835 static inline void gen_aa32_st##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
836 { \
837 tcg_gen_qemu_st_i32(val, addr, index, OPC); \
838 }
839
840 static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
841 {
842 tcg_gen_qemu_ld_i64(val, addr, index, MO_TEQ);
843 }
844
845 static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
846 {
847 tcg_gen_qemu_st_i64(val, addr, index, MO_TEQ);
848 }
849
850 #else
851
852 #define DO_GEN_LD(SUFF, OPC) \
853 static inline void gen_aa32_ld##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
854 { \
855 TCGv addr64 = tcg_temp_new(); \
856 tcg_gen_extu_i32_i64(addr64, addr); \
857 tcg_gen_qemu_ld_i32(val, addr64, index, OPC); \
858 tcg_temp_free(addr64); \
859 }
860
861 #define DO_GEN_ST(SUFF, OPC) \
862 static inline void gen_aa32_st##SUFF(TCGv_i32 val, TCGv_i32 addr, int index) \
863 { \
864 TCGv addr64 = tcg_temp_new(); \
865 tcg_gen_extu_i32_i64(addr64, addr); \
866 tcg_gen_qemu_st_i32(val, addr64, index, OPC); \
867 tcg_temp_free(addr64); \
868 }
869
870 static inline void gen_aa32_ld64(TCGv_i64 val, TCGv_i32 addr, int index)
871 {
872 TCGv addr64 = tcg_temp_new();
873 tcg_gen_extu_i32_i64(addr64, addr);
874 tcg_gen_qemu_ld_i64(val, addr64, index, MO_TEQ);
875 tcg_temp_free(addr64);
876 }
877
878 static inline void gen_aa32_st64(TCGv_i64 val, TCGv_i32 addr, int index)
879 {
880 TCGv addr64 = tcg_temp_new();
881 tcg_gen_extu_i32_i64(addr64, addr);
882 tcg_gen_qemu_st_i64(val, addr64, index, MO_TEQ);
883 tcg_temp_free(addr64);
884 }
885
886 #endif
887
888 DO_GEN_LD(8s, MO_SB)
889 DO_GEN_LD(8u, MO_UB)
890 DO_GEN_LD(16s, MO_TESW)
891 DO_GEN_LD(16u, MO_TEUW)
892 DO_GEN_LD(32u, MO_TEUL)
893 DO_GEN_ST(8, MO_UB)
894 DO_GEN_ST(16, MO_TEUW)
895 DO_GEN_ST(32, MO_TEUL)
896
897 static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
898 {
899 tcg_gen_movi_i32(cpu_R[15], val);
900 }
901
902 /* Force a TB lookup after an instruction that changes the CPU state. */
903 static inline void gen_lookup_tb(DisasContext *s)
904 {
905 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
906 s->is_jmp = DISAS_UPDATE;
907 }
908
909 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
910 TCGv_i32 var)
911 {
912 int val, rm, shift, shiftop;
913 TCGv_i32 offset;
914
915 if (!(insn & (1 << 25))) {
916 /* immediate */
917 val = insn & 0xfff;
918 if (!(insn & (1 << 23)))
919 val = -val;
920 if (val != 0)
921 tcg_gen_addi_i32(var, var, val);
922 } else {
923 /* shift/register */
924 rm = (insn) & 0xf;
925 shift = (insn >> 7) & 0x1f;
926 shiftop = (insn >> 5) & 3;
927 offset = load_reg(s, rm);
928 gen_arm_shift_im(offset, shiftop, shift, 0);
929 if (!(insn & (1 << 23)))
930 tcg_gen_sub_i32(var, var, offset);
931 else
932 tcg_gen_add_i32(var, var, offset);
933 tcg_temp_free_i32(offset);
934 }
935 }
936
937 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
938 int extra, TCGv_i32 var)
939 {
940 int val, rm;
941 TCGv_i32 offset;
942
943 if (insn & (1 << 22)) {
944 /* immediate */
945 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
946 if (!(insn & (1 << 23)))
947 val = -val;
948 val += extra;
949 if (val != 0)
950 tcg_gen_addi_i32(var, var, val);
951 } else {
952 /* register */
953 if (extra)
954 tcg_gen_addi_i32(var, var, extra);
955 rm = (insn) & 0xf;
956 offset = load_reg(s, rm);
957 if (!(insn & (1 << 23)))
958 tcg_gen_sub_i32(var, var, offset);
959 else
960 tcg_gen_add_i32(var, var, offset);
961 tcg_temp_free_i32(offset);
962 }
963 }
964
965 static TCGv_ptr get_fpstatus_ptr(int neon)
966 {
967 TCGv_ptr statusptr = tcg_temp_new_ptr();
968 int offset;
969 if (neon) {
970 offset = offsetof(CPUARMState, vfp.standard_fp_status);
971 } else {
972 offset = offsetof(CPUARMState, vfp.fp_status);
973 }
974 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
975 return statusptr;
976 }
977
978 #define VFP_OP2(name) \
979 static inline void gen_vfp_##name(int dp) \
980 { \
981 TCGv_ptr fpst = get_fpstatus_ptr(0); \
982 if (dp) { \
983 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, fpst); \
984 } else { \
985 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, fpst); \
986 } \
987 tcg_temp_free_ptr(fpst); \
988 }
989
990 VFP_OP2(add)
991 VFP_OP2(sub)
992 VFP_OP2(mul)
993 VFP_OP2(div)
994
995 #undef VFP_OP2
996
997 static inline void gen_vfp_F1_mul(int dp)
998 {
999 /* Like gen_vfp_mul() but put result in F1 */
1000 TCGv_ptr fpst = get_fpstatus_ptr(0);
1001 if (dp) {
1002 gen_helper_vfp_muld(cpu_F1d, cpu_F0d, cpu_F1d, fpst);
1003 } else {
1004 gen_helper_vfp_muls(cpu_F1s, cpu_F0s, cpu_F1s, fpst);
1005 }
1006 tcg_temp_free_ptr(fpst);
1007 }
1008
1009 static inline void gen_vfp_F1_neg(int dp)
1010 {
1011 /* Like gen_vfp_neg() but put result in F1 */
1012 if (dp) {
1013 gen_helper_vfp_negd(cpu_F1d, cpu_F0d);
1014 } else {
1015 gen_helper_vfp_negs(cpu_F1s, cpu_F0s);
1016 }
1017 }
1018
1019 static inline void gen_vfp_abs(int dp)
1020 {
1021 if (dp)
1022 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
1023 else
1024 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
1025 }
1026
1027 static inline void gen_vfp_neg(int dp)
1028 {
1029 if (dp)
1030 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
1031 else
1032 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
1033 }
1034
1035 static inline void gen_vfp_sqrt(int dp)
1036 {
1037 if (dp)
1038 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
1039 else
1040 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
1041 }
1042
1043 static inline void gen_vfp_cmp(int dp)
1044 {
1045 if (dp)
1046 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
1047 else
1048 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
1049 }
1050
1051 static inline void gen_vfp_cmpe(int dp)
1052 {
1053 if (dp)
1054 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
1055 else
1056 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
1057 }
1058
1059 static inline void gen_vfp_F1_ld0(int dp)
1060 {
1061 if (dp)
1062 tcg_gen_movi_i64(cpu_F1d, 0);
1063 else
1064 tcg_gen_movi_i32(cpu_F1s, 0);
1065 }
1066
1067 #define VFP_GEN_ITOF(name) \
1068 static inline void gen_vfp_##name(int dp, int neon) \
1069 { \
1070 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1071 if (dp) { \
1072 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0s, statusptr); \
1073 } else { \
1074 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1075 } \
1076 tcg_temp_free_ptr(statusptr); \
1077 }
1078
1079 VFP_GEN_ITOF(uito)
1080 VFP_GEN_ITOF(sito)
1081 #undef VFP_GEN_ITOF
1082
1083 #define VFP_GEN_FTOI(name) \
1084 static inline void gen_vfp_##name(int dp, int neon) \
1085 { \
1086 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1087 if (dp) { \
1088 gen_helper_vfp_##name##d(cpu_F0s, cpu_F0d, statusptr); \
1089 } else { \
1090 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1091 } \
1092 tcg_temp_free_ptr(statusptr); \
1093 }
1094
1095 VFP_GEN_FTOI(toui)
1096 VFP_GEN_FTOI(touiz)
1097 VFP_GEN_FTOI(tosi)
1098 VFP_GEN_FTOI(tosiz)
1099 #undef VFP_GEN_FTOI
1100
1101 #define VFP_GEN_FIX(name, round) \
1102 static inline void gen_vfp_##name(int dp, int shift, int neon) \
1103 { \
1104 TCGv_i32 tmp_shift = tcg_const_i32(shift); \
1105 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1106 if (dp) { \
1107 gen_helper_vfp_##name##d##round(cpu_F0d, cpu_F0d, tmp_shift, \
1108 statusptr); \
1109 } else { \
1110 gen_helper_vfp_##name##s##round(cpu_F0s, cpu_F0s, tmp_shift, \
1111 statusptr); \
1112 } \
1113 tcg_temp_free_i32(tmp_shift); \
1114 tcg_temp_free_ptr(statusptr); \
1115 }
1116 VFP_GEN_FIX(tosh, _round_to_zero)
1117 VFP_GEN_FIX(tosl, _round_to_zero)
1118 VFP_GEN_FIX(touh, _round_to_zero)
1119 VFP_GEN_FIX(toul, _round_to_zero)
1120 VFP_GEN_FIX(shto, )
1121 VFP_GEN_FIX(slto, )
1122 VFP_GEN_FIX(uhto, )
1123 VFP_GEN_FIX(ulto, )
1124 #undef VFP_GEN_FIX
1125
1126 static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr)
1127 {
1128 if (dp) {
1129 gen_aa32_ld64(cpu_F0d, addr, IS_USER(s));
1130 } else {
1131 gen_aa32_ld32u(cpu_F0s, addr, IS_USER(s));
1132 }
1133 }
1134
1135 static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr)
1136 {
1137 if (dp) {
1138 gen_aa32_st64(cpu_F0d, addr, IS_USER(s));
1139 } else {
1140 gen_aa32_st32(cpu_F0s, addr, IS_USER(s));
1141 }
1142 }
1143
1144 static inline long
1145 vfp_reg_offset (int dp, int reg)
1146 {
1147 if (dp)
1148 return offsetof(CPUARMState, vfp.regs[reg]);
1149 else if (reg & 1) {
1150 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1151 + offsetof(CPU_DoubleU, l.upper);
1152 } else {
1153 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1154 + offsetof(CPU_DoubleU, l.lower);
1155 }
1156 }
1157
1158 /* Return the offset of a 32-bit piece of a NEON register.
1159 zero is the least significant end of the register. */
1160 static inline long
1161 neon_reg_offset (int reg, int n)
1162 {
1163 int sreg;
1164 sreg = reg * 2 + n;
1165 return vfp_reg_offset(0, sreg);
1166 }
1167
1168 static TCGv_i32 neon_load_reg(int reg, int pass)
1169 {
1170 TCGv_i32 tmp = tcg_temp_new_i32();
1171 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1172 return tmp;
1173 }
1174
1175 static void neon_store_reg(int reg, int pass, TCGv_i32 var)
1176 {
1177 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1178 tcg_temp_free_i32(var);
1179 }
1180
1181 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1182 {
1183 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1184 }
1185
1186 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1187 {
1188 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1189 }
1190
1191 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1192 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1193 #define tcg_gen_st_f32 tcg_gen_st_i32
1194 #define tcg_gen_st_f64 tcg_gen_st_i64
1195
1196 static inline void gen_mov_F0_vreg(int dp, int reg)
1197 {
1198 if (dp)
1199 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1200 else
1201 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1202 }
1203
1204 static inline void gen_mov_F1_vreg(int dp, int reg)
1205 {
1206 if (dp)
1207 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1208 else
1209 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1210 }
1211
1212 static inline void gen_mov_vreg_F0(int dp, int reg)
1213 {
1214 if (dp)
1215 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1216 else
1217 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1218 }
1219
1220 #define ARM_CP_RW_BIT (1 << 20)
1221
1222 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1223 {
1224 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
1225 }
1226
1227 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1228 {
1229 tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
1230 }
1231
1232 static inline TCGv_i32 iwmmxt_load_creg(int reg)
1233 {
1234 TCGv_i32 var = tcg_temp_new_i32();
1235 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
1236 return var;
1237 }
1238
1239 static inline void iwmmxt_store_creg(int reg, TCGv_i32 var)
1240 {
1241 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
1242 tcg_temp_free_i32(var);
1243 }
1244
1245 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1246 {
1247 iwmmxt_store_reg(cpu_M0, rn);
1248 }
1249
1250 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1251 {
1252 iwmmxt_load_reg(cpu_M0, rn);
1253 }
1254
1255 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1256 {
1257 iwmmxt_load_reg(cpu_V1, rn);
1258 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1259 }
1260
1261 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1262 {
1263 iwmmxt_load_reg(cpu_V1, rn);
1264 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1265 }
1266
1267 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1268 {
1269 iwmmxt_load_reg(cpu_V1, rn);
1270 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1271 }
1272
1273 #define IWMMXT_OP(name) \
1274 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1275 { \
1276 iwmmxt_load_reg(cpu_V1, rn); \
1277 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1278 }
1279
1280 #define IWMMXT_OP_ENV(name) \
1281 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1282 { \
1283 iwmmxt_load_reg(cpu_V1, rn); \
1284 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1285 }
1286
1287 #define IWMMXT_OP_ENV_SIZE(name) \
1288 IWMMXT_OP_ENV(name##b) \
1289 IWMMXT_OP_ENV(name##w) \
1290 IWMMXT_OP_ENV(name##l)
1291
1292 #define IWMMXT_OP_ENV1(name) \
1293 static inline void gen_op_iwmmxt_##name##_M0(void) \
1294 { \
1295 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1296 }
1297
1298 IWMMXT_OP(maddsq)
1299 IWMMXT_OP(madduq)
1300 IWMMXT_OP(sadb)
1301 IWMMXT_OP(sadw)
1302 IWMMXT_OP(mulslw)
1303 IWMMXT_OP(mulshw)
1304 IWMMXT_OP(mululw)
1305 IWMMXT_OP(muluhw)
1306 IWMMXT_OP(macsw)
1307 IWMMXT_OP(macuw)
1308
1309 IWMMXT_OP_ENV_SIZE(unpackl)
1310 IWMMXT_OP_ENV_SIZE(unpackh)
1311
1312 IWMMXT_OP_ENV1(unpacklub)
1313 IWMMXT_OP_ENV1(unpackluw)
1314 IWMMXT_OP_ENV1(unpacklul)
1315 IWMMXT_OP_ENV1(unpackhub)
1316 IWMMXT_OP_ENV1(unpackhuw)
1317 IWMMXT_OP_ENV1(unpackhul)
1318 IWMMXT_OP_ENV1(unpacklsb)
1319 IWMMXT_OP_ENV1(unpacklsw)
1320 IWMMXT_OP_ENV1(unpacklsl)
1321 IWMMXT_OP_ENV1(unpackhsb)
1322 IWMMXT_OP_ENV1(unpackhsw)
1323 IWMMXT_OP_ENV1(unpackhsl)
1324
1325 IWMMXT_OP_ENV_SIZE(cmpeq)
1326 IWMMXT_OP_ENV_SIZE(cmpgtu)
1327 IWMMXT_OP_ENV_SIZE(cmpgts)
1328
1329 IWMMXT_OP_ENV_SIZE(mins)
1330 IWMMXT_OP_ENV_SIZE(minu)
1331 IWMMXT_OP_ENV_SIZE(maxs)
1332 IWMMXT_OP_ENV_SIZE(maxu)
1333
1334 IWMMXT_OP_ENV_SIZE(subn)
1335 IWMMXT_OP_ENV_SIZE(addn)
1336 IWMMXT_OP_ENV_SIZE(subu)
1337 IWMMXT_OP_ENV_SIZE(addu)
1338 IWMMXT_OP_ENV_SIZE(subs)
1339 IWMMXT_OP_ENV_SIZE(adds)
1340
1341 IWMMXT_OP_ENV(avgb0)
1342 IWMMXT_OP_ENV(avgb1)
1343 IWMMXT_OP_ENV(avgw0)
1344 IWMMXT_OP_ENV(avgw1)
1345
1346 IWMMXT_OP(msadb)
1347
1348 IWMMXT_OP_ENV(packuw)
1349 IWMMXT_OP_ENV(packul)
1350 IWMMXT_OP_ENV(packuq)
1351 IWMMXT_OP_ENV(packsw)
1352 IWMMXT_OP_ENV(packsl)
1353 IWMMXT_OP_ENV(packsq)
1354
1355 static void gen_op_iwmmxt_set_mup(void)
1356 {
1357 TCGv_i32 tmp;
1358 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1359 tcg_gen_ori_i32(tmp, tmp, 2);
1360 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1361 }
1362
1363 static void gen_op_iwmmxt_set_cup(void)
1364 {
1365 TCGv_i32 tmp;
1366 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1367 tcg_gen_ori_i32(tmp, tmp, 1);
1368 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1369 }
1370
1371 static void gen_op_iwmmxt_setpsr_nz(void)
1372 {
1373 TCGv_i32 tmp = tcg_temp_new_i32();
1374 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1375 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1376 }
1377
1378 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1379 {
1380 iwmmxt_load_reg(cpu_V1, rn);
1381 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1382 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1383 }
1384
1385 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn,
1386 TCGv_i32 dest)
1387 {
1388 int rd;
1389 uint32_t offset;
1390 TCGv_i32 tmp;
1391
1392 rd = (insn >> 16) & 0xf;
1393 tmp = load_reg(s, rd);
1394
1395 offset = (insn & 0xff) << ((insn >> 7) & 2);
1396 if (insn & (1 << 24)) {
1397 /* Pre indexed */
1398 if (insn & (1 << 23))
1399 tcg_gen_addi_i32(tmp, tmp, offset);
1400 else
1401 tcg_gen_addi_i32(tmp, tmp, -offset);
1402 tcg_gen_mov_i32(dest, tmp);
1403 if (insn & (1 << 21))
1404 store_reg(s, rd, tmp);
1405 else
1406 tcg_temp_free_i32(tmp);
1407 } else if (insn & (1 << 21)) {
1408 /* Post indexed */
1409 tcg_gen_mov_i32(dest, tmp);
1410 if (insn & (1 << 23))
1411 tcg_gen_addi_i32(tmp, tmp, offset);
1412 else
1413 tcg_gen_addi_i32(tmp, tmp, -offset);
1414 store_reg(s, rd, tmp);
1415 } else if (!(insn & (1 << 23)))
1416 return 1;
1417 return 0;
1418 }
1419
1420 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest)
1421 {
1422 int rd = (insn >> 0) & 0xf;
1423 TCGv_i32 tmp;
1424
1425 if (insn & (1 << 8)) {
1426 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1427 return 1;
1428 } else {
1429 tmp = iwmmxt_load_creg(rd);
1430 }
1431 } else {
1432 tmp = tcg_temp_new_i32();
1433 iwmmxt_load_reg(cpu_V0, rd);
1434 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1435 }
1436 tcg_gen_andi_i32(tmp, tmp, mask);
1437 tcg_gen_mov_i32(dest, tmp);
1438 tcg_temp_free_i32(tmp);
1439 return 0;
1440 }
1441
1442 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
1443 (ie. an undefined instruction). */
1444 static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
1445 {
1446 int rd, wrd;
1447 int rdhi, rdlo, rd0, rd1, i;
1448 TCGv_i32 addr;
1449 TCGv_i32 tmp, tmp2, tmp3;
1450
1451 if ((insn & 0x0e000e00) == 0x0c000000) {
1452 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1453 wrd = insn & 0xf;
1454 rdlo = (insn >> 12) & 0xf;
1455 rdhi = (insn >> 16) & 0xf;
1456 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1457 iwmmxt_load_reg(cpu_V0, wrd);
1458 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1459 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1460 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
1461 } else { /* TMCRR */
1462 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1463 iwmmxt_store_reg(cpu_V0, wrd);
1464 gen_op_iwmmxt_set_mup();
1465 }
1466 return 0;
1467 }
1468
1469 wrd = (insn >> 12) & 0xf;
1470 addr = tcg_temp_new_i32();
1471 if (gen_iwmmxt_address(s, insn, addr)) {
1472 tcg_temp_free_i32(addr);
1473 return 1;
1474 }
1475 if (insn & ARM_CP_RW_BIT) {
1476 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1477 tmp = tcg_temp_new_i32();
1478 gen_aa32_ld32u(tmp, addr, IS_USER(s));
1479 iwmmxt_store_creg(wrd, tmp);
1480 } else {
1481 i = 1;
1482 if (insn & (1 << 8)) {
1483 if (insn & (1 << 22)) { /* WLDRD */
1484 gen_aa32_ld64(cpu_M0, addr, IS_USER(s));
1485 i = 0;
1486 } else { /* WLDRW wRd */
1487 tmp = tcg_temp_new_i32();
1488 gen_aa32_ld32u(tmp, addr, IS_USER(s));
1489 }
1490 } else {
1491 tmp = tcg_temp_new_i32();
1492 if (insn & (1 << 22)) { /* WLDRH */
1493 gen_aa32_ld16u(tmp, addr, IS_USER(s));
1494 } else { /* WLDRB */
1495 gen_aa32_ld8u(tmp, addr, IS_USER(s));
1496 }
1497 }
1498 if (i) {
1499 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1500 tcg_temp_free_i32(tmp);
1501 }
1502 gen_op_iwmmxt_movq_wRn_M0(wrd);
1503 }
1504 } else {
1505 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1506 tmp = iwmmxt_load_creg(wrd);
1507 gen_aa32_st32(tmp, addr, IS_USER(s));
1508 } else {
1509 gen_op_iwmmxt_movq_M0_wRn(wrd);
1510 tmp = tcg_temp_new_i32();
1511 if (insn & (1 << 8)) {
1512 if (insn & (1 << 22)) { /* WSTRD */
1513 gen_aa32_st64(cpu_M0, addr, IS_USER(s));
1514 } else { /* WSTRW wRd */
1515 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1516 gen_aa32_st32(tmp, addr, IS_USER(s));
1517 }
1518 } else {
1519 if (insn & (1 << 22)) { /* WSTRH */
1520 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1521 gen_aa32_st16(tmp, addr, IS_USER(s));
1522 } else { /* WSTRB */
1523 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1524 gen_aa32_st8(tmp, addr, IS_USER(s));
1525 }
1526 }
1527 }
1528 tcg_temp_free_i32(tmp);
1529 }
1530 tcg_temp_free_i32(addr);
1531 return 0;
1532 }
1533
1534 if ((insn & 0x0f000000) != 0x0e000000)
1535 return 1;
1536
1537 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1538 case 0x000: /* WOR */
1539 wrd = (insn >> 12) & 0xf;
1540 rd0 = (insn >> 0) & 0xf;
1541 rd1 = (insn >> 16) & 0xf;
1542 gen_op_iwmmxt_movq_M0_wRn(rd0);
1543 gen_op_iwmmxt_orq_M0_wRn(rd1);
1544 gen_op_iwmmxt_setpsr_nz();
1545 gen_op_iwmmxt_movq_wRn_M0(wrd);
1546 gen_op_iwmmxt_set_mup();
1547 gen_op_iwmmxt_set_cup();
1548 break;
1549 case 0x011: /* TMCR */
1550 if (insn & 0xf)
1551 return 1;
1552 rd = (insn >> 12) & 0xf;
1553 wrd = (insn >> 16) & 0xf;
1554 switch (wrd) {
1555 case ARM_IWMMXT_wCID:
1556 case ARM_IWMMXT_wCASF:
1557 break;
1558 case ARM_IWMMXT_wCon:
1559 gen_op_iwmmxt_set_cup();
1560 /* Fall through. */
1561 case ARM_IWMMXT_wCSSF:
1562 tmp = iwmmxt_load_creg(wrd);
1563 tmp2 = load_reg(s, rd);
1564 tcg_gen_andc_i32(tmp, tmp, tmp2);
1565 tcg_temp_free_i32(tmp2);
1566 iwmmxt_store_creg(wrd, tmp);
1567 break;
1568 case ARM_IWMMXT_wCGR0:
1569 case ARM_IWMMXT_wCGR1:
1570 case ARM_IWMMXT_wCGR2:
1571 case ARM_IWMMXT_wCGR3:
1572 gen_op_iwmmxt_set_cup();
1573 tmp = load_reg(s, rd);
1574 iwmmxt_store_creg(wrd, tmp);
1575 break;
1576 default:
1577 return 1;
1578 }
1579 break;
1580 case 0x100: /* WXOR */
1581 wrd = (insn >> 12) & 0xf;
1582 rd0 = (insn >> 0) & 0xf;
1583 rd1 = (insn >> 16) & 0xf;
1584 gen_op_iwmmxt_movq_M0_wRn(rd0);
1585 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1586 gen_op_iwmmxt_setpsr_nz();
1587 gen_op_iwmmxt_movq_wRn_M0(wrd);
1588 gen_op_iwmmxt_set_mup();
1589 gen_op_iwmmxt_set_cup();
1590 break;
1591 case 0x111: /* TMRC */
1592 if (insn & 0xf)
1593 return 1;
1594 rd = (insn >> 12) & 0xf;
1595 wrd = (insn >> 16) & 0xf;
1596 tmp = iwmmxt_load_creg(wrd);
1597 store_reg(s, rd, tmp);
1598 break;
1599 case 0x300: /* WANDN */
1600 wrd = (insn >> 12) & 0xf;
1601 rd0 = (insn >> 0) & 0xf;
1602 rd1 = (insn >> 16) & 0xf;
1603 gen_op_iwmmxt_movq_M0_wRn(rd0);
1604 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1605 gen_op_iwmmxt_andq_M0_wRn(rd1);
1606 gen_op_iwmmxt_setpsr_nz();
1607 gen_op_iwmmxt_movq_wRn_M0(wrd);
1608 gen_op_iwmmxt_set_mup();
1609 gen_op_iwmmxt_set_cup();
1610 break;
1611 case 0x200: /* WAND */
1612 wrd = (insn >> 12) & 0xf;
1613 rd0 = (insn >> 0) & 0xf;
1614 rd1 = (insn >> 16) & 0xf;
1615 gen_op_iwmmxt_movq_M0_wRn(rd0);
1616 gen_op_iwmmxt_andq_M0_wRn(rd1);
1617 gen_op_iwmmxt_setpsr_nz();
1618 gen_op_iwmmxt_movq_wRn_M0(wrd);
1619 gen_op_iwmmxt_set_mup();
1620 gen_op_iwmmxt_set_cup();
1621 break;
1622 case 0x810: case 0xa10: /* WMADD */
1623 wrd = (insn >> 12) & 0xf;
1624 rd0 = (insn >> 0) & 0xf;
1625 rd1 = (insn >> 16) & 0xf;
1626 gen_op_iwmmxt_movq_M0_wRn(rd0);
1627 if (insn & (1 << 21))
1628 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1629 else
1630 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1631 gen_op_iwmmxt_movq_wRn_M0(wrd);
1632 gen_op_iwmmxt_set_mup();
1633 break;
1634 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1635 wrd = (insn >> 12) & 0xf;
1636 rd0 = (insn >> 16) & 0xf;
1637 rd1 = (insn >> 0) & 0xf;
1638 gen_op_iwmmxt_movq_M0_wRn(rd0);
1639 switch ((insn >> 22) & 3) {
1640 case 0:
1641 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1642 break;
1643 case 1:
1644 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1645 break;
1646 case 2:
1647 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1648 break;
1649 case 3:
1650 return 1;
1651 }
1652 gen_op_iwmmxt_movq_wRn_M0(wrd);
1653 gen_op_iwmmxt_set_mup();
1654 gen_op_iwmmxt_set_cup();
1655 break;
1656 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1657 wrd = (insn >> 12) & 0xf;
1658 rd0 = (insn >> 16) & 0xf;
1659 rd1 = (insn >> 0) & 0xf;
1660 gen_op_iwmmxt_movq_M0_wRn(rd0);
1661 switch ((insn >> 22) & 3) {
1662 case 0:
1663 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1664 break;
1665 case 1:
1666 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1667 break;
1668 case 2:
1669 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1670 break;
1671 case 3:
1672 return 1;
1673 }
1674 gen_op_iwmmxt_movq_wRn_M0(wrd);
1675 gen_op_iwmmxt_set_mup();
1676 gen_op_iwmmxt_set_cup();
1677 break;
1678 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1679 wrd = (insn >> 12) & 0xf;
1680 rd0 = (insn >> 16) & 0xf;
1681 rd1 = (insn >> 0) & 0xf;
1682 gen_op_iwmmxt_movq_M0_wRn(rd0);
1683 if (insn & (1 << 22))
1684 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1685 else
1686 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1687 if (!(insn & (1 << 20)))
1688 gen_op_iwmmxt_addl_M0_wRn(wrd);
1689 gen_op_iwmmxt_movq_wRn_M0(wrd);
1690 gen_op_iwmmxt_set_mup();
1691 break;
1692 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1693 wrd = (insn >> 12) & 0xf;
1694 rd0 = (insn >> 16) & 0xf;
1695 rd1 = (insn >> 0) & 0xf;
1696 gen_op_iwmmxt_movq_M0_wRn(rd0);
1697 if (insn & (1 << 21)) {
1698 if (insn & (1 << 20))
1699 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1700 else
1701 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1702 } else {
1703 if (insn & (1 << 20))
1704 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1705 else
1706 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1707 }
1708 gen_op_iwmmxt_movq_wRn_M0(wrd);
1709 gen_op_iwmmxt_set_mup();
1710 break;
1711 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1712 wrd = (insn >> 12) & 0xf;
1713 rd0 = (insn >> 16) & 0xf;
1714 rd1 = (insn >> 0) & 0xf;
1715 gen_op_iwmmxt_movq_M0_wRn(rd0);
1716 if (insn & (1 << 21))
1717 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1718 else
1719 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1720 if (!(insn & (1 << 20))) {
1721 iwmmxt_load_reg(cpu_V1, wrd);
1722 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1723 }
1724 gen_op_iwmmxt_movq_wRn_M0(wrd);
1725 gen_op_iwmmxt_set_mup();
1726 break;
1727 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1728 wrd = (insn >> 12) & 0xf;
1729 rd0 = (insn >> 16) & 0xf;
1730 rd1 = (insn >> 0) & 0xf;
1731 gen_op_iwmmxt_movq_M0_wRn(rd0);
1732 switch ((insn >> 22) & 3) {
1733 case 0:
1734 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1735 break;
1736 case 1:
1737 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1738 break;
1739 case 2:
1740 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1741 break;
1742 case 3:
1743 return 1;
1744 }
1745 gen_op_iwmmxt_movq_wRn_M0(wrd);
1746 gen_op_iwmmxt_set_mup();
1747 gen_op_iwmmxt_set_cup();
1748 break;
1749 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1750 wrd = (insn >> 12) & 0xf;
1751 rd0 = (insn >> 16) & 0xf;
1752 rd1 = (insn >> 0) & 0xf;
1753 gen_op_iwmmxt_movq_M0_wRn(rd0);
1754 if (insn & (1 << 22)) {
1755 if (insn & (1 << 20))
1756 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1757 else
1758 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1759 } else {
1760 if (insn & (1 << 20))
1761 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1762 else
1763 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1764 }
1765 gen_op_iwmmxt_movq_wRn_M0(wrd);
1766 gen_op_iwmmxt_set_mup();
1767 gen_op_iwmmxt_set_cup();
1768 break;
1769 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1770 wrd = (insn >> 12) & 0xf;
1771 rd0 = (insn >> 16) & 0xf;
1772 rd1 = (insn >> 0) & 0xf;
1773 gen_op_iwmmxt_movq_M0_wRn(rd0);
1774 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1775 tcg_gen_andi_i32(tmp, tmp, 7);
1776 iwmmxt_load_reg(cpu_V1, rd1);
1777 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1778 tcg_temp_free_i32(tmp);
1779 gen_op_iwmmxt_movq_wRn_M0(wrd);
1780 gen_op_iwmmxt_set_mup();
1781 break;
1782 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1783 if (((insn >> 6) & 3) == 3)
1784 return 1;
1785 rd = (insn >> 12) & 0xf;
1786 wrd = (insn >> 16) & 0xf;
1787 tmp = load_reg(s, rd);
1788 gen_op_iwmmxt_movq_M0_wRn(wrd);
1789 switch ((insn >> 6) & 3) {
1790 case 0:
1791 tmp2 = tcg_const_i32(0xff);
1792 tmp3 = tcg_const_i32((insn & 7) << 3);
1793 break;
1794 case 1:
1795 tmp2 = tcg_const_i32(0xffff);
1796 tmp3 = tcg_const_i32((insn & 3) << 4);
1797 break;
1798 case 2:
1799 tmp2 = tcg_const_i32(0xffffffff);
1800 tmp3 = tcg_const_i32((insn & 1) << 5);
1801 break;
1802 default:
1803 TCGV_UNUSED_I32(tmp2);
1804 TCGV_UNUSED_I32(tmp3);
1805 }
1806 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1807 tcg_temp_free_i32(tmp3);
1808 tcg_temp_free_i32(tmp2);
1809 tcg_temp_free_i32(tmp);
1810 gen_op_iwmmxt_movq_wRn_M0(wrd);
1811 gen_op_iwmmxt_set_mup();
1812 break;
1813 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1814 rd = (insn >> 12) & 0xf;
1815 wrd = (insn >> 16) & 0xf;
1816 if (rd == 15 || ((insn >> 22) & 3) == 3)
1817 return 1;
1818 gen_op_iwmmxt_movq_M0_wRn(wrd);
1819 tmp = tcg_temp_new_i32();
1820 switch ((insn >> 22) & 3) {
1821 case 0:
1822 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1823 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1824 if (insn & 8) {
1825 tcg_gen_ext8s_i32(tmp, tmp);
1826 } else {
1827 tcg_gen_andi_i32(tmp, tmp, 0xff);
1828 }
1829 break;
1830 case 1:
1831 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1832 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1833 if (insn & 8) {
1834 tcg_gen_ext16s_i32(tmp, tmp);
1835 } else {
1836 tcg_gen_andi_i32(tmp, tmp, 0xffff);
1837 }
1838 break;
1839 case 2:
1840 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1841 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1842 break;
1843 }
1844 store_reg(s, rd, tmp);
1845 break;
1846 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1847 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1848 return 1;
1849 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1850 switch ((insn >> 22) & 3) {
1851 case 0:
1852 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
1853 break;
1854 case 1:
1855 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
1856 break;
1857 case 2:
1858 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
1859 break;
1860 }
1861 tcg_gen_shli_i32(tmp, tmp, 28);
1862 gen_set_nzcv(tmp);
1863 tcg_temp_free_i32(tmp);
1864 break;
1865 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1866 if (((insn >> 6) & 3) == 3)
1867 return 1;
1868 rd = (insn >> 12) & 0xf;
1869 wrd = (insn >> 16) & 0xf;
1870 tmp = load_reg(s, rd);
1871 switch ((insn >> 6) & 3) {
1872 case 0:
1873 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
1874 break;
1875 case 1:
1876 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
1877 break;
1878 case 2:
1879 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
1880 break;
1881 }
1882 tcg_temp_free_i32(tmp);
1883 gen_op_iwmmxt_movq_wRn_M0(wrd);
1884 gen_op_iwmmxt_set_mup();
1885 break;
1886 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1887 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1888 return 1;
1889 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1890 tmp2 = tcg_temp_new_i32();
1891 tcg_gen_mov_i32(tmp2, tmp);
1892 switch ((insn >> 22) & 3) {
1893 case 0:
1894 for (i = 0; i < 7; i ++) {
1895 tcg_gen_shli_i32(tmp2, tmp2, 4);
1896 tcg_gen_and_i32(tmp, tmp, tmp2);
1897 }
1898 break;
1899 case 1:
1900 for (i = 0; i < 3; i ++) {
1901 tcg_gen_shli_i32(tmp2, tmp2, 8);
1902 tcg_gen_and_i32(tmp, tmp, tmp2);
1903 }
1904 break;
1905 case 2:
1906 tcg_gen_shli_i32(tmp2, tmp2, 16);
1907 tcg_gen_and_i32(tmp, tmp, tmp2);
1908 break;
1909 }
1910 gen_set_nzcv(tmp);
1911 tcg_temp_free_i32(tmp2);
1912 tcg_temp_free_i32(tmp);
1913 break;
1914 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1915 wrd = (insn >> 12) & 0xf;
1916 rd0 = (insn >> 16) & 0xf;
1917 gen_op_iwmmxt_movq_M0_wRn(rd0);
1918 switch ((insn >> 22) & 3) {
1919 case 0:
1920 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1921 break;
1922 case 1:
1923 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1924 break;
1925 case 2:
1926 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1927 break;
1928 case 3:
1929 return 1;
1930 }
1931 gen_op_iwmmxt_movq_wRn_M0(wrd);
1932 gen_op_iwmmxt_set_mup();
1933 break;
1934 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1935 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1936 return 1;
1937 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1938 tmp2 = tcg_temp_new_i32();
1939 tcg_gen_mov_i32(tmp2, tmp);
1940 switch ((insn >> 22) & 3) {
1941 case 0:
1942 for (i = 0; i < 7; i ++) {
1943 tcg_gen_shli_i32(tmp2, tmp2, 4);
1944 tcg_gen_or_i32(tmp, tmp, tmp2);
1945 }
1946 break;
1947 case 1:
1948 for (i = 0; i < 3; i ++) {
1949 tcg_gen_shli_i32(tmp2, tmp2, 8);
1950 tcg_gen_or_i32(tmp, tmp, tmp2);
1951 }
1952 break;
1953 case 2:
1954 tcg_gen_shli_i32(tmp2, tmp2, 16);
1955 tcg_gen_or_i32(tmp, tmp, tmp2);
1956 break;
1957 }
1958 gen_set_nzcv(tmp);
1959 tcg_temp_free_i32(tmp2);
1960 tcg_temp_free_i32(tmp);
1961 break;
1962 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1963 rd = (insn >> 12) & 0xf;
1964 rd0 = (insn >> 16) & 0xf;
1965 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
1966 return 1;
1967 gen_op_iwmmxt_movq_M0_wRn(rd0);
1968 tmp = tcg_temp_new_i32();
1969 switch ((insn >> 22) & 3) {
1970 case 0:
1971 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
1972 break;
1973 case 1:
1974 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
1975 break;
1976 case 2:
1977 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
1978 break;
1979 }
1980 store_reg(s, rd, tmp);
1981 break;
1982 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1983 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1984 wrd = (insn >> 12) & 0xf;
1985 rd0 = (insn >> 16) & 0xf;
1986 rd1 = (insn >> 0) & 0xf;
1987 gen_op_iwmmxt_movq_M0_wRn(rd0);
1988 switch ((insn >> 22) & 3) {
1989 case 0:
1990 if (insn & (1 << 21))
1991 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1992 else
1993 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1994 break;
1995 case 1:
1996 if (insn & (1 << 21))
1997 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1998 else
1999 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
2000 break;
2001 case 2:
2002 if (insn & (1 << 21))
2003 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
2004 else
2005 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
2006 break;
2007 case 3:
2008 return 1;
2009 }
2010 gen_op_iwmmxt_movq_wRn_M0(wrd);
2011 gen_op_iwmmxt_set_mup();
2012 gen_op_iwmmxt_set_cup();
2013 break;
2014 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2015 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2016 wrd = (insn >> 12) & 0xf;
2017 rd0 = (insn >> 16) & 0xf;
2018 gen_op_iwmmxt_movq_M0_wRn(rd0);
2019 switch ((insn >> 22) & 3) {
2020 case 0:
2021 if (insn & (1 << 21))
2022 gen_op_iwmmxt_unpacklsb_M0();
2023 else
2024 gen_op_iwmmxt_unpacklub_M0();
2025 break;
2026 case 1:
2027 if (insn & (1 << 21))
2028 gen_op_iwmmxt_unpacklsw_M0();
2029 else
2030 gen_op_iwmmxt_unpackluw_M0();
2031 break;
2032 case 2:
2033 if (insn & (1 << 21))
2034 gen_op_iwmmxt_unpacklsl_M0();
2035 else
2036 gen_op_iwmmxt_unpacklul_M0();
2037 break;
2038 case 3:
2039 return 1;
2040 }
2041 gen_op_iwmmxt_movq_wRn_M0(wrd);
2042 gen_op_iwmmxt_set_mup();
2043 gen_op_iwmmxt_set_cup();
2044 break;
2045 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2046 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2047 wrd = (insn >> 12) & 0xf;
2048 rd0 = (insn >> 16) & 0xf;
2049 gen_op_iwmmxt_movq_M0_wRn(rd0);
2050 switch ((insn >> 22) & 3) {
2051 case 0:
2052 if (insn & (1 << 21))
2053 gen_op_iwmmxt_unpackhsb_M0();
2054 else
2055 gen_op_iwmmxt_unpackhub_M0();
2056 break;
2057 case 1:
2058 if (insn & (1 << 21))
2059 gen_op_iwmmxt_unpackhsw_M0();
2060 else
2061 gen_op_iwmmxt_unpackhuw_M0();
2062 break;
2063 case 2:
2064 if (insn & (1 << 21))
2065 gen_op_iwmmxt_unpackhsl_M0();
2066 else
2067 gen_op_iwmmxt_unpackhul_M0();
2068 break;
2069 case 3:
2070 return 1;
2071 }
2072 gen_op_iwmmxt_movq_wRn_M0(wrd);
2073 gen_op_iwmmxt_set_mup();
2074 gen_op_iwmmxt_set_cup();
2075 break;
2076 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2077 case 0x214: case 0x614: case 0xa14: case 0xe14:
2078 if (((insn >> 22) & 3) == 0)
2079 return 1;
2080 wrd = (insn >> 12) & 0xf;
2081 rd0 = (insn >> 16) & 0xf;
2082 gen_op_iwmmxt_movq_M0_wRn(rd0);
2083 tmp = tcg_temp_new_i32();
2084 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2085 tcg_temp_free_i32(tmp);
2086 return 1;
2087 }
2088 switch ((insn >> 22) & 3) {
2089 case 1:
2090 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
2091 break;
2092 case 2:
2093 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
2094 break;
2095 case 3:
2096 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
2097 break;
2098 }
2099 tcg_temp_free_i32(tmp);
2100 gen_op_iwmmxt_movq_wRn_M0(wrd);
2101 gen_op_iwmmxt_set_mup();
2102 gen_op_iwmmxt_set_cup();
2103 break;
2104 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2105 case 0x014: case 0x414: case 0x814: case 0xc14:
2106 if (((insn >> 22) & 3) == 0)
2107 return 1;
2108 wrd = (insn >> 12) & 0xf;
2109 rd0 = (insn >> 16) & 0xf;
2110 gen_op_iwmmxt_movq_M0_wRn(rd0);
2111 tmp = tcg_temp_new_i32();
2112 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2113 tcg_temp_free_i32(tmp);
2114 return 1;
2115 }
2116 switch ((insn >> 22) & 3) {
2117 case 1:
2118 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
2119 break;
2120 case 2:
2121 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
2122 break;
2123 case 3:
2124 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
2125 break;
2126 }
2127 tcg_temp_free_i32(tmp);
2128 gen_op_iwmmxt_movq_wRn_M0(wrd);
2129 gen_op_iwmmxt_set_mup();
2130 gen_op_iwmmxt_set_cup();
2131 break;
2132 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2133 case 0x114: case 0x514: case 0x914: case 0xd14:
2134 if (((insn >> 22) & 3) == 0)
2135 return 1;
2136 wrd = (insn >> 12) & 0xf;
2137 rd0 = (insn >> 16) & 0xf;
2138 gen_op_iwmmxt_movq_M0_wRn(rd0);
2139 tmp = tcg_temp_new_i32();
2140 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2141 tcg_temp_free_i32(tmp);
2142 return 1;
2143 }
2144 switch ((insn >> 22) & 3) {
2145 case 1:
2146 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
2147 break;
2148 case 2:
2149 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
2150 break;
2151 case 3:
2152 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
2153 break;
2154 }
2155 tcg_temp_free_i32(tmp);
2156 gen_op_iwmmxt_movq_wRn_M0(wrd);
2157 gen_op_iwmmxt_set_mup();
2158 gen_op_iwmmxt_set_cup();
2159 break;
2160 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2161 case 0x314: case 0x714: case 0xb14: case 0xf14:
2162 if (((insn >> 22) & 3) == 0)
2163 return 1;
2164 wrd = (insn >> 12) & 0xf;
2165 rd0 = (insn >> 16) & 0xf;
2166 gen_op_iwmmxt_movq_M0_wRn(rd0);
2167 tmp = tcg_temp_new_i32();
2168 switch ((insn >> 22) & 3) {
2169 case 1:
2170 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2171 tcg_temp_free_i32(tmp);
2172 return 1;
2173 }
2174 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
2175 break;
2176 case 2:
2177 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2178 tcg_temp_free_i32(tmp);
2179 return 1;
2180 }
2181 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
2182 break;
2183 case 3:
2184 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2185 tcg_temp_free_i32(tmp);
2186 return 1;
2187 }
2188 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
2189 break;
2190 }
2191 tcg_temp_free_i32(tmp);
2192 gen_op_iwmmxt_movq_wRn_M0(wrd);
2193 gen_op_iwmmxt_set_mup();
2194 gen_op_iwmmxt_set_cup();
2195 break;
2196 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2197 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2198 wrd = (insn >> 12) & 0xf;
2199 rd0 = (insn >> 16) & 0xf;
2200 rd1 = (insn >> 0) & 0xf;
2201 gen_op_iwmmxt_movq_M0_wRn(rd0);
2202 switch ((insn >> 22) & 3) {
2203 case 0:
2204 if (insn & (1 << 21))
2205 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2206 else
2207 gen_op_iwmmxt_minub_M0_wRn(rd1);
2208 break;
2209 case 1:
2210 if (insn & (1 << 21))
2211 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2212 else
2213 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2214 break;
2215 case 2:
2216 if (insn & (1 << 21))
2217 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2218 else
2219 gen_op_iwmmxt_minul_M0_wRn(rd1);
2220 break;
2221 case 3:
2222 return 1;
2223 }
2224 gen_op_iwmmxt_movq_wRn_M0(wrd);
2225 gen_op_iwmmxt_set_mup();
2226 break;
2227 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2228 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2229 wrd = (insn >> 12) & 0xf;
2230 rd0 = (insn >> 16) & 0xf;
2231 rd1 = (insn >> 0) & 0xf;
2232 gen_op_iwmmxt_movq_M0_wRn(rd0);
2233 switch ((insn >> 22) & 3) {
2234 case 0:
2235 if (insn & (1 << 21))
2236 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2237 else
2238 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2239 break;
2240 case 1:
2241 if (insn & (1 << 21))
2242 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2243 else
2244 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2245 break;
2246 case 2:
2247 if (insn & (1 << 21))
2248 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2249 else
2250 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2251 break;
2252 case 3:
2253 return 1;
2254 }
2255 gen_op_iwmmxt_movq_wRn_M0(wrd);
2256 gen_op_iwmmxt_set_mup();
2257 break;
2258 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2259 case 0x402: case 0x502: case 0x602: case 0x702:
2260 wrd = (insn >> 12) & 0xf;
2261 rd0 = (insn >> 16) & 0xf;
2262 rd1 = (insn >> 0) & 0xf;
2263 gen_op_iwmmxt_movq_M0_wRn(rd0);
2264 tmp = tcg_const_i32((insn >> 20) & 3);
2265 iwmmxt_load_reg(cpu_V1, rd1);
2266 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2267 tcg_temp_free_i32(tmp);
2268 gen_op_iwmmxt_movq_wRn_M0(wrd);
2269 gen_op_iwmmxt_set_mup();
2270 break;
2271 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2272 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2273 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2274 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2275 wrd = (insn >> 12) & 0xf;
2276 rd0 = (insn >> 16) & 0xf;
2277 rd1 = (insn >> 0) & 0xf;
2278 gen_op_iwmmxt_movq_M0_wRn(rd0);
2279 switch ((insn >> 20) & 0xf) {
2280 case 0x0:
2281 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2282 break;
2283 case 0x1:
2284 gen_op_iwmmxt_subub_M0_wRn(rd1);
2285 break;
2286 case 0x3:
2287 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2288 break;
2289 case 0x4:
2290 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2291 break;
2292 case 0x5:
2293 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2294 break;
2295 case 0x7:
2296 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2297 break;
2298 case 0x8:
2299 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2300 break;
2301 case 0x9:
2302 gen_op_iwmmxt_subul_M0_wRn(rd1);
2303 break;
2304 case 0xb:
2305 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2306 break;
2307 default:
2308 return 1;
2309 }
2310 gen_op_iwmmxt_movq_wRn_M0(wrd);
2311 gen_op_iwmmxt_set_mup();
2312 gen_op_iwmmxt_set_cup();
2313 break;
2314 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2315 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2316 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2317 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2318 wrd = (insn >> 12) & 0xf;
2319 rd0 = (insn >> 16) & 0xf;
2320 gen_op_iwmmxt_movq_M0_wRn(rd0);
2321 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2322 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2323 tcg_temp_free_i32(tmp);
2324 gen_op_iwmmxt_movq_wRn_M0(wrd);
2325 gen_op_iwmmxt_set_mup();
2326 gen_op_iwmmxt_set_cup();
2327 break;
2328 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2329 case 0x418: case 0x518: case 0x618: case 0x718:
2330 case 0x818: case 0x918: case 0xa18: case 0xb18:
2331 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2332 wrd = (insn >> 12) & 0xf;
2333 rd0 = (insn >> 16) & 0xf;
2334 rd1 = (insn >> 0) & 0xf;
2335 gen_op_iwmmxt_movq_M0_wRn(rd0);
2336 switch ((insn >> 20) & 0xf) {
2337 case 0x0:
2338 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2339 break;
2340 case 0x1:
2341 gen_op_iwmmxt_addub_M0_wRn(rd1);
2342 break;
2343 case 0x3:
2344 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2345 break;
2346 case 0x4:
2347 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2348 break;
2349 case 0x5:
2350 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2351 break;
2352 case 0x7:
2353 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2354 break;
2355 case 0x8:
2356 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2357 break;
2358 case 0x9:
2359 gen_op_iwmmxt_addul_M0_wRn(rd1);
2360 break;
2361 case 0xb:
2362 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2363 break;
2364 default:
2365 return 1;
2366 }
2367 gen_op_iwmmxt_movq_wRn_M0(wrd);
2368 gen_op_iwmmxt_set_mup();
2369 gen_op_iwmmxt_set_cup();
2370 break;
2371 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2372 case 0x408: case 0x508: case 0x608: case 0x708:
2373 case 0x808: case 0x908: case 0xa08: case 0xb08:
2374 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2375 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2376 return 1;
2377 wrd = (insn >> 12) & 0xf;
2378 rd0 = (insn >> 16) & 0xf;
2379 rd1 = (insn >> 0) & 0xf;
2380 gen_op_iwmmxt_movq_M0_wRn(rd0);
2381 switch ((insn >> 22) & 3) {
2382 case 1:
2383 if (insn & (1 << 21))
2384 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2385 else
2386 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2387 break;
2388 case 2:
2389 if (insn & (1 << 21))
2390 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2391 else
2392 gen_op_iwmmxt_packul_M0_wRn(rd1);
2393 break;
2394 case 3:
2395 if (insn & (1 << 21))
2396 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2397 else
2398 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2399 break;
2400 }
2401 gen_op_iwmmxt_movq_wRn_M0(wrd);
2402 gen_op_iwmmxt_set_mup();
2403 gen_op_iwmmxt_set_cup();
2404 break;
2405 case 0x201: case 0x203: case 0x205: case 0x207:
2406 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2407 case 0x211: case 0x213: case 0x215: case 0x217:
2408 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2409 wrd = (insn >> 5) & 0xf;
2410 rd0 = (insn >> 12) & 0xf;
2411 rd1 = (insn >> 0) & 0xf;
2412 if (rd0 == 0xf || rd1 == 0xf)
2413 return 1;
2414 gen_op_iwmmxt_movq_M0_wRn(wrd);
2415 tmp = load_reg(s, rd0);
2416 tmp2 = load_reg(s, rd1);
2417 switch ((insn >> 16) & 0xf) {
2418 case 0x0: /* TMIA */
2419 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2420 break;
2421 case 0x8: /* TMIAPH */
2422 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2423 break;
2424 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2425 if (insn & (1 << 16))
2426 tcg_gen_shri_i32(tmp, tmp, 16);
2427 if (insn & (1 << 17))
2428 tcg_gen_shri_i32(tmp2, tmp2, 16);
2429 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2430 break;
2431 default:
2432 tcg_temp_free_i32(tmp2);
2433 tcg_temp_free_i32(tmp);
2434 return 1;
2435 }
2436 tcg_temp_free_i32(tmp2);
2437 tcg_temp_free_i32(tmp);
2438 gen_op_iwmmxt_movq_wRn_M0(wrd);
2439 gen_op_iwmmxt_set_mup();
2440 break;
2441 default:
2442 return 1;
2443 }
2444
2445 return 0;
2446 }
2447
2448 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
2449 (ie. an undefined instruction). */
2450 static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
2451 {
2452 int acc, rd0, rd1, rdhi, rdlo;
2453 TCGv_i32 tmp, tmp2;
2454
2455 if ((insn & 0x0ff00f10) == 0x0e200010) {
2456 /* Multiply with Internal Accumulate Format */
2457 rd0 = (insn >> 12) & 0xf;
2458 rd1 = insn & 0xf;
2459 acc = (insn >> 5) & 7;
2460
2461 if (acc != 0)
2462 return 1;
2463
2464 tmp = load_reg(s, rd0);
2465 tmp2 = load_reg(s, rd1);
2466 switch ((insn >> 16) & 0xf) {
2467 case 0x0: /* MIA */
2468 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2469 break;
2470 case 0x8: /* MIAPH */
2471 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2472 break;
2473 case 0xc: /* MIABB */
2474 case 0xd: /* MIABT */
2475 case 0xe: /* MIATB */
2476 case 0xf: /* MIATT */
2477 if (insn & (1 << 16))
2478 tcg_gen_shri_i32(tmp, tmp, 16);
2479 if (insn & (1 << 17))
2480 tcg_gen_shri_i32(tmp2, tmp2, 16);
2481 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2482 break;
2483 default:
2484 return 1;
2485 }
2486 tcg_temp_free_i32(tmp2);
2487 tcg_temp_free_i32(tmp);
2488
2489 gen_op_iwmmxt_movq_wRn_M0(acc);
2490 return 0;
2491 }
2492
2493 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2494 /* Internal Accumulator Access Format */
2495 rdhi = (insn >> 16) & 0xf;
2496 rdlo = (insn >> 12) & 0xf;
2497 acc = insn & 7;
2498
2499 if (acc != 0)
2500 return 1;
2501
2502 if (insn & ARM_CP_RW_BIT) { /* MRA */
2503 iwmmxt_load_reg(cpu_V0, acc);
2504 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2505 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2506 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2507 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2508 } else { /* MAR */
2509 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2510 iwmmxt_store_reg(cpu_V0, acc);
2511 }
2512 return 0;
2513 }
2514
2515 return 1;
2516 }
2517
2518 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2519 #define VFP_SREG(insn, bigbit, smallbit) \
2520 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2521 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2522 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2523 reg = (((insn) >> (bigbit)) & 0x0f) \
2524 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2525 } else { \
2526 if (insn & (1 << (smallbit))) \
2527 return 1; \
2528 reg = ((insn) >> (bigbit)) & 0x0f; \
2529 }} while (0)
2530
2531 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2532 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2533 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2534 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2535 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2536 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2537
2538 /* Move between integer and VFP cores. */
2539 static TCGv_i32 gen_vfp_mrs(void)
2540 {
2541 TCGv_i32 tmp = tcg_temp_new_i32();
2542 tcg_gen_mov_i32(tmp, cpu_F0s);
2543 return tmp;
2544 }
2545
2546 static void gen_vfp_msr(TCGv_i32 tmp)
2547 {
2548 tcg_gen_mov_i32(cpu_F0s, tmp);
2549 tcg_temp_free_i32(tmp);
2550 }
2551
2552 static void gen_neon_dup_u8(TCGv_i32 var, int shift)
2553 {
2554 TCGv_i32 tmp = tcg_temp_new_i32();
2555 if (shift)
2556 tcg_gen_shri_i32(var, var, shift);
2557 tcg_gen_ext8u_i32(var, var);
2558 tcg_gen_shli_i32(tmp, var, 8);
2559 tcg_gen_or_i32(var, var, tmp);
2560 tcg_gen_shli_i32(tmp, var, 16);
2561 tcg_gen_or_i32(var, var, tmp);
2562 tcg_temp_free_i32(tmp);
2563 }
2564
2565 static void gen_neon_dup_low16(TCGv_i32 var)
2566 {
2567 TCGv_i32 tmp = tcg_temp_new_i32();
2568 tcg_gen_ext16u_i32(var, var);
2569 tcg_gen_shli_i32(tmp, var, 16);
2570 tcg_gen_or_i32(var, var, tmp);
2571 tcg_temp_free_i32(tmp);
2572 }
2573
2574 static void gen_neon_dup_high16(TCGv_i32 var)
2575 {
2576 TCGv_i32 tmp = tcg_temp_new_i32();
2577 tcg_gen_andi_i32(var, var, 0xffff0000);
2578 tcg_gen_shri_i32(tmp, var, 16);
2579 tcg_gen_or_i32(var, var, tmp);
2580 tcg_temp_free_i32(tmp);
2581 }
2582
2583 static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int size)
2584 {
2585 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2586 TCGv_i32 tmp = tcg_temp_new_i32();
2587 switch (size) {
2588 case 0:
2589 gen_aa32_ld8u(tmp, addr, IS_USER(s));
2590 gen_neon_dup_u8(tmp, 0);
2591 break;
2592 case 1:
2593 gen_aa32_ld16u(tmp, addr, IS_USER(s));
2594 gen_neon_dup_low16(tmp);
2595 break;
2596 case 2:
2597 gen_aa32_ld32u(tmp, addr, IS_USER(s));
2598 break;
2599 default: /* Avoid compiler warnings. */
2600 abort();
2601 }
2602 return tmp;
2603 }
2604
2605 static int handle_vsel(uint32_t insn, uint32_t rd, uint32_t rn, uint32_t rm,
2606 uint32_t dp)
2607 {
2608 uint32_t cc = extract32(insn, 20, 2);
2609
2610 if (dp) {
2611 TCGv_i64 frn, frm, dest;
2612 TCGv_i64 tmp, zero, zf, nf, vf;
2613
2614 zero = tcg_const_i64(0);
2615
2616 frn = tcg_temp_new_i64();
2617 frm = tcg_temp_new_i64();
2618 dest = tcg_temp_new_i64();
2619
2620 zf = tcg_temp_new_i64();
2621 nf = tcg_temp_new_i64();
2622 vf = tcg_temp_new_i64();
2623
2624 tcg_gen_extu_i32_i64(zf, cpu_ZF);
2625 tcg_gen_ext_i32_i64(nf, cpu_NF);
2626 tcg_gen_ext_i32_i64(vf, cpu_VF);
2627
2628 tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn));
2629 tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm));
2630 switch (cc) {
2631 case 0: /* eq: Z */
2632 tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
2633 frn, frm);
2634 break;
2635 case 1: /* vs: V */
2636 tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero,
2637 frn, frm);
2638 break;
2639 case 2: /* ge: N == V -> N ^ V == 0 */
2640 tmp = tcg_temp_new_i64();
2641 tcg_gen_xor_i64(tmp, vf, nf);
2642 tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
2643 frn, frm);
2644 tcg_temp_free_i64(tmp);
2645 break;
2646 case 3: /* gt: !Z && N == V */
2647 tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero,
2648 frn, frm);
2649 tmp = tcg_temp_new_i64();
2650 tcg_gen_xor_i64(tmp, vf, nf);
2651 tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero,
2652 dest, frm);
2653 tcg_temp_free_i64(tmp);
2654 break;
2655 }
2656 tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd));
2657 tcg_temp_free_i64(frn);
2658 tcg_temp_free_i64(frm);
2659 tcg_temp_free_i64(dest);
2660
2661 tcg_temp_free_i64(zf);
2662 tcg_temp_free_i64(nf);
2663 tcg_temp_free_i64(vf);
2664
2665 tcg_temp_free_i64(zero);
2666 } else {
2667 TCGv_i32 frn, frm, dest;
2668 TCGv_i32 tmp, zero;
2669
2670 zero = tcg_const_i32(0);
2671
2672 frn = tcg_temp_new_i32();
2673 frm = tcg_temp_new_i32();
2674 dest = tcg_temp_new_i32();
2675 tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn));
2676 tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm));
2677 switch (cc) {
2678 case 0: /* eq: Z */
2679 tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
2680 frn, frm);
2681 break;
2682 case 1: /* vs: V */
2683 tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero,
2684 frn, frm);
2685 break;
2686 case 2: /* ge: N == V -> N ^ V == 0 */
2687 tmp = tcg_temp_new_i32();
2688 tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
2689 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
2690 frn, frm);
2691 tcg_temp_free_i32(tmp);
2692 break;
2693 case 3: /* gt: !Z && N == V */
2694 tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero,
2695 frn, frm);
2696 tmp = tcg_temp_new_i32();
2697 tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF);
2698 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero,
2699 dest, frm);
2700 tcg_temp_free_i32(tmp);
2701 break;
2702 }
2703 tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd));
2704 tcg_temp_free_i32(frn);
2705 tcg_temp_free_i32(frm);
2706 tcg_temp_free_i32(dest);
2707
2708 tcg_temp_free_i32(zero);
2709 }
2710
2711 return 0;
2712 }
2713
2714 static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn,
2715 uint32_t rm, uint32_t dp)
2716 {
2717 uint32_t vmin = extract32(insn, 6, 1);
2718 TCGv_ptr fpst = get_fpstatus_ptr(0);
2719
2720 if (dp) {
2721 TCGv_i64 frn, frm, dest;
2722
2723 frn = tcg_temp_new_i64();
2724 frm = tcg_temp_new_i64();
2725 dest = tcg_temp_new_i64();
2726
2727 tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn));
2728 tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm));
2729 if (vmin) {
2730 gen_helper_vfp_minnumd(dest, frn, frm, fpst);
2731 } else {
2732 gen_helper_vfp_maxnumd(dest, frn, frm, fpst);
2733 }
2734 tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd));
2735 tcg_temp_free_i64(frn);
2736 tcg_temp_free_i64(frm);
2737 tcg_temp_free_i64(dest);
2738 } else {
2739 TCGv_i32 frn, frm, dest;
2740
2741 frn = tcg_temp_new_i32();
2742 frm = tcg_temp_new_i32();
2743 dest = tcg_temp_new_i32();
2744
2745 tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn));
2746 tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm));
2747 if (vmin) {
2748 gen_helper_vfp_minnums(dest, frn, frm, fpst);
2749 } else {
2750 gen_helper_vfp_maxnums(dest, frn, frm, fpst);
2751 }
2752 tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd));
2753 tcg_temp_free_i32(frn);
2754 tcg_temp_free_i32(frm);
2755 tcg_temp_free_i32(dest);
2756 }
2757
2758 tcg_temp_free_ptr(fpst);
2759 return 0;
2760 }
2761
2762 static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
2763 int rounding)
2764 {
2765 TCGv_ptr fpst = get_fpstatus_ptr(0);
2766 TCGv_i32 tcg_rmode;
2767
2768 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
2769 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
2770
2771 if (dp) {
2772 TCGv_i64 tcg_op;
2773 TCGv_i64 tcg_res;
2774 tcg_op = tcg_temp_new_i64();
2775 tcg_res = tcg_temp_new_i64();
2776 tcg_gen_ld_f64(tcg_op, cpu_env, vfp_reg_offset(dp, rm));
2777 gen_helper_rintd(tcg_res, tcg_op, fpst);
2778 tcg_gen_st_f64(tcg_res, cpu_env, vfp_reg_offset(dp, rd));
2779 tcg_temp_free_i64(tcg_op);
2780 tcg_temp_free_i64(tcg_res);
2781 } else {
2782 TCGv_i32 tcg_op;
2783 TCGv_i32 tcg_res;
2784 tcg_op = tcg_temp_new_i32();
2785 tcg_res = tcg_temp_new_i32();
2786 tcg_gen_ld_f32(tcg_op, cpu_env, vfp_reg_offset(dp, rm));
2787 gen_helper_rints(tcg_res, tcg_op, fpst);
2788 tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(dp, rd));
2789 tcg_temp_free_i32(tcg_op);
2790 tcg_temp_free_i32(tcg_res);
2791 }
2792
2793 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
2794 tcg_temp_free_i32(tcg_rmode);
2795
2796 tcg_temp_free_ptr(fpst);
2797 return 0;
2798 }
2799
2800 static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
2801 int rounding)
2802 {
2803 bool is_signed = extract32(insn, 7, 1);
2804 TCGv_ptr fpst = get_fpstatus_ptr(0);
2805 TCGv_i32 tcg_rmode, tcg_shift;
2806
2807 tcg_shift = tcg_const_i32(0);
2808
2809 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
2810 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
2811
2812 if (dp) {
2813 TCGv_i64 tcg_double, tcg_res;
2814 TCGv_i32 tcg_tmp;
2815 /* Rd is encoded as a single precision register even when the source
2816 * is double precision.
2817 */
2818 rd = ((rd << 1) & 0x1e) | ((rd >> 4) & 0x1);
2819 tcg_double = tcg_temp_new_i64();
2820 tcg_res = tcg_temp_new_i64();
2821 tcg_tmp = tcg_temp_new_i32();
2822 tcg_gen_ld_f64(tcg_double, cpu_env, vfp_reg_offset(1, rm));
2823 if (is_signed) {
2824 gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
2825 } else {
2826 gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
2827 }
2828 tcg_gen_trunc_i64_i32(tcg_tmp, tcg_res);
2829 tcg_gen_st_f32(tcg_tmp, cpu_env, vfp_reg_offset(0, rd));
2830 tcg_temp_free_i32(tcg_tmp);
2831 tcg_temp_free_i64(tcg_res);
2832 tcg_temp_free_i64(tcg_double);
2833 } else {
2834 TCGv_i32 tcg_single, tcg_res;
2835 tcg_single = tcg_temp_new_i32();
2836 tcg_res = tcg_temp_new_i32();
2837 tcg_gen_ld_f32(tcg_single, cpu_env, vfp_reg_offset(0, rm));
2838 if (is_signed) {
2839 gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst);
2840 } else {
2841 gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
2842 }
2843 tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(0, rd));
2844 tcg_temp_free_i32(tcg_res);
2845 tcg_temp_free_i32(tcg_single);
2846 }
2847
2848 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
2849 tcg_temp_free_i32(tcg_rmode);
2850
2851 tcg_temp_free_i32(tcg_shift);
2852
2853 tcg_temp_free_ptr(fpst);
2854
2855 return 0;
2856 }
2857
2858 /* Table for converting the most common AArch32 encoding of
2859 * rounding mode to arm_fprounding order (which matches the
2860 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
2861 */
2862 static const uint8_t fp_decode_rm[] = {
2863 FPROUNDING_TIEAWAY,
2864 FPROUNDING_TIEEVEN,
2865 FPROUNDING_POSINF,
2866 FPROUNDING_NEGINF,
2867 };
2868
2869 static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
2870 {
2871 uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
2872
2873 if (!arm_feature(env, ARM_FEATURE_V8)) {
2874 return 1;
2875 }
2876
2877 if (dp) {
2878 VFP_DREG_D(rd, insn);
2879 VFP_DREG_N(rn, insn);
2880 VFP_DREG_M(rm, insn);
2881 } else {
2882 rd = VFP_SREG_D(insn);
2883 rn = VFP_SREG_N(insn);
2884 rm = VFP_SREG_M(insn);
2885 }
2886
2887 if ((insn & 0x0f800e50) == 0x0e000a00) {
2888 return handle_vsel(insn, rd, rn, rm, dp);
2889 } else if ((insn & 0x0fb00e10) == 0x0e800a00) {
2890 return handle_vminmaxnm(insn, rd, rn, rm, dp);
2891 } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40) {
2892 /* VRINTA, VRINTN, VRINTP, VRINTM */
2893 int rounding = fp_decode_rm[extract32(insn, 16, 2)];
2894 return handle_vrint(insn, rd, rm, dp, rounding);
2895 } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40) {
2896 /* VCVTA, VCVTN, VCVTP, VCVTM */
2897 int rounding = fp_decode_rm[extract32(insn, 16, 2)];
2898 return handle_vcvt(insn, rd, rm, dp, rounding);
2899 }
2900 return 1;
2901 }
2902
2903 /* Disassemble a VFP instruction. Returns nonzero if an error occurred
2904 (ie. an undefined instruction). */
2905 static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
2906 {
2907 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2908 int dp, veclen;
2909 TCGv_i32 addr;
2910 TCGv_i32 tmp;
2911 TCGv_i32 tmp2;
2912
2913 if (!arm_feature(env, ARM_FEATURE_VFP))
2914 return 1;
2915
2916 if (!s->vfp_enabled) {
2917 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2918 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2919 return 1;
2920 rn = (insn >> 16) & 0xf;
2921 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2922 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2923 return 1;
2924 }
2925
2926 if (extract32(insn, 28, 4) == 0xf) {
2927 /* Encodings with T=1 (Thumb) or unconditional (ARM):
2928 * only used in v8 and above.
2929 */
2930 return disas_vfp_v8_insn(env, s, insn);
2931 }
2932
2933 dp = ((insn & 0xf00) == 0xb00);
2934 switch ((insn >> 24) & 0xf) {
2935 case 0xe:
2936 if (insn & (1 << 4)) {
2937 /* single register transfer */
2938 rd = (insn >> 12) & 0xf;
2939 if (dp) {
2940 int size;
2941 int pass;
2942
2943 VFP_DREG_N(rn, insn);
2944 if (insn & 0xf)
2945 return 1;
2946 if (insn & 0x00c00060
2947 && !arm_feature(env, ARM_FEATURE_NEON))
2948 return 1;
2949
2950 pass = (insn >> 21) & 1;
2951 if (insn & (1 << 22)) {
2952 size = 0;
2953 offset = ((insn >> 5) & 3) * 8;
2954 } else if (insn & (1 << 5)) {
2955 size = 1;
2956 offset = (insn & (1 << 6)) ? 16 : 0;
2957 } else {
2958 size = 2;
2959 offset = 0;
2960 }
2961 if (insn & ARM_CP_RW_BIT) {
2962 /* vfp->arm */
2963 tmp = neon_load_reg(rn, pass);
2964 switch (size) {
2965 case 0:
2966 if (offset)
2967 tcg_gen_shri_i32(tmp, tmp, offset);
2968 if (insn & (1 << 23))
2969 gen_uxtb(tmp);
2970 else
2971 gen_sxtb(tmp);
2972 break;
2973 case 1:
2974 if (insn & (1 << 23)) {
2975 if (offset) {
2976 tcg_gen_shri_i32(tmp, tmp, 16);
2977 } else {
2978 gen_uxth(tmp);
2979 }
2980 } else {
2981 if (offset) {
2982 tcg_gen_sari_i32(tmp, tmp, 16);
2983 } else {
2984 gen_sxth(tmp);
2985 }
2986 }
2987 break;
2988 case 2:
2989 break;
2990 }
2991 store_reg(s, rd, tmp);
2992 } else {
2993 /* arm->vfp */
2994 tmp = load_reg(s, rd);
2995 if (insn & (1 << 23)) {
2996 /* VDUP */
2997 if (size == 0) {
2998 gen_neon_dup_u8(tmp, 0);
2999 } else if (size == 1) {
3000 gen_neon_dup_low16(tmp);
3001 }
3002 for (n = 0; n <= pass * 2; n++) {
3003 tmp2 = tcg_temp_new_i32();
3004 tcg_gen_mov_i32(tmp2, tmp);
3005 neon_store_reg(rn, n, tmp2);
3006 }
3007 neon_store_reg(rn, n, tmp);
3008 } else {
3009 /* VMOV */
3010 switch (size) {
3011 case 0:
3012 tmp2 = neon_load_reg(rn, pass);
3013 tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
3014 tcg_temp_free_i32(tmp2);
3015 break;
3016 case 1:
3017 tmp2 = neon_load_reg(rn, pass);
3018 tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
3019 tcg_temp_free_i32(tmp2);
3020 break;
3021 case 2:
3022 break;
3023 }
3024 neon_store_reg(rn, pass, tmp);
3025 }
3026 }
3027 } else { /* !dp */
3028 if ((insn & 0x6f) != 0x00)
3029 return 1;
3030 rn = VFP_SREG_N(insn);
3031 if (insn & ARM_CP_RW_BIT) {
3032 /* vfp->arm */
3033 if (insn & (1 << 21)) {
3034 /* system register */
3035 rn >>= 1;
3036
3037 switch (rn) {
3038 case ARM_VFP_FPSID:
3039 /* VFP2 allows access to FSID from userspace.
3040 VFP3 restricts all id registers to privileged
3041 accesses. */
3042 if (IS_USER(s)
3043 && arm_feature(env, ARM_FEATURE_VFP3))
3044 return 1;
3045 tmp = load_cpu_field(vfp.xregs[rn]);
3046 break;
3047 case ARM_VFP_FPEXC:
3048 if (IS_USER(s))
3049 return 1;
3050 tmp = load_cpu_field(vfp.xregs[rn]);
3051 break;
3052 case ARM_VFP_FPINST:
3053 case ARM_VFP_FPINST2:
3054 /* Not present in VFP3. */
3055 if (IS_USER(s)
3056 || arm_feature(env, ARM_FEATURE_VFP3))
3057 return 1;
3058 tmp = load_cpu_field(vfp.xregs[rn]);
3059 break;
3060 case ARM_VFP_FPSCR:
3061 if (rd == 15) {
3062 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
3063 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
3064 } else {
3065 tmp = tcg_temp_new_i32();
3066 gen_helper_vfp_get_fpscr(tmp, cpu_env);
3067 }
3068 break;
3069 case ARM_VFP_MVFR0:
3070 case ARM_VFP_MVFR1:
3071 if (IS_USER(s)
3072 || !arm_feature(env, ARM_FEATURE_MVFR))
3073 return 1;
3074 tmp = load_cpu_field(vfp.xregs[rn]);
3075 break;
3076 default:
3077 return 1;
3078 }
3079 } else {
3080 gen_mov_F0_vreg(0, rn);
3081 tmp = gen_vfp_mrs();
3082 }
3083 if (rd == 15) {
3084 /* Set the 4 flag bits in the CPSR. */
3085 gen_set_nzcv(tmp);
3086 tcg_temp_free_i32(tmp);
3087 } else {
3088 store_reg(s, rd, tmp);
3089 }
3090 } else {
3091 /* arm->vfp */
3092 if (insn & (1 << 21)) {
3093 rn >>= 1;
3094 /* system register */
3095 switch (rn) {
3096 case ARM_VFP_FPSID:
3097 case ARM_VFP_MVFR0:
3098 case ARM_VFP_MVFR1:
3099 /* Writes are ignored. */
3100 break;
3101 case ARM_VFP_FPSCR:
3102 tmp = load_reg(s, rd);
3103 gen_helper_vfp_set_fpscr(cpu_env, tmp);
3104 tcg_temp_free_i32(tmp);
3105 gen_lookup_tb(s);
3106 break;
3107 case ARM_VFP_FPEXC:
3108 if (IS_USER(s))
3109 return 1;
3110 /* TODO: VFP subarchitecture support.
3111 * For now, keep the EN bit only */
3112 tmp = load_reg(s, rd);
3113 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
3114 store_cpu_field(tmp, vfp.xregs[rn]);
3115 gen_lookup_tb(s);
3116 break;
3117 case ARM_VFP_FPINST:
3118 case ARM_VFP_FPINST2:
3119 tmp = load_reg(s, rd);
3120 store_cpu_field(tmp, vfp.xregs[rn]);
3121 break;
3122 default:
3123 return 1;
3124 }
3125 } else {
3126 tmp = load_reg(s, rd);
3127 gen_vfp_msr(tmp);
3128 gen_mov_vreg_F0(0, rn);
3129 }
3130 }
3131 }
3132 } else {
3133 /* data processing */
3134 /* The opcode is in bits 23, 21, 20 and 6. */
3135 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
3136 if (dp) {
3137 if (op == 15) {
3138 /* rn is opcode */
3139 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
3140 } else {
3141 /* rn is register number */
3142 VFP_DREG_N(rn, insn);
3143 }
3144
3145 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18) ||
3146 ((rn & 0x1e) == 0x6))) {
3147 /* Integer or single/half precision destination. */
3148 rd = VFP_SREG_D(insn);
3149 } else {
3150 VFP_DREG_D(rd, insn);
3151 }
3152 if (op == 15 &&
3153 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14) ||
3154 ((rn & 0x1e) == 0x4))) {
3155 /* VCVT from int or half precision is always from S reg
3156 * regardless of dp bit. VCVT with immediate frac_bits
3157 * has same format as SREG_M.
3158 */
3159 rm = VFP_SREG_M(insn);
3160 } else {
3161 VFP_DREG_M(rm, insn);
3162 }
3163 } else {
3164 rn = VFP_SREG_N(insn);
3165 if (op == 15 && rn == 15) {
3166 /* Double precision destination. */
3167 VFP_DREG_D(rd, insn);
3168 } else {
3169 rd = VFP_SREG_D(insn);
3170 }
3171 /* NB that we implicitly rely on the encoding for the frac_bits
3172 * in VCVT of fixed to float being the same as that of an SREG_M
3173 */
3174 rm = VFP_SREG_M(insn);
3175 }
3176
3177 veclen = s->vec_len;
3178 if (op == 15 && rn > 3)
3179 veclen = 0;
3180
3181 /* Shut up compiler warnings. */
3182 delta_m = 0;
3183 delta_d = 0;
3184 bank_mask = 0;
3185
3186 if (veclen > 0) {
3187 if (dp)
3188 bank_mask = 0xc;
3189 else
3190 bank_mask = 0x18;
3191
3192 /* Figure out what type of vector operation this is. */
3193 if ((rd & bank_mask) == 0) {
3194 /* scalar */
3195 veclen = 0;
3196 } else {
3197 if (dp)
3198 delta_d = (s->vec_stride >> 1) + 1;
3199 else
3200 delta_d = s->vec_stride + 1;
3201
3202 if ((rm & bank_mask) == 0) {
3203 /* mixed scalar/vector */
3204 delta_m = 0;
3205 } else {
3206 /* vector */
3207 delta_m = delta_d;
3208 }
3209 }
3210 }
3211
3212 /* Load the initial operands. */
3213 if (op == 15) {
3214 switch (rn) {
3215 case 16:
3216 case 17:
3217 /* Integer source */
3218 gen_mov_F0_vreg(0, rm);
3219 break;
3220 case 8:
3221 case 9:
3222 /* Compare */
3223 gen_mov_F0_vreg(dp, rd);
3224 gen_mov_F1_vreg(dp, rm);
3225 break;
3226 case 10:
3227 case 11:
3228 /* Compare with zero */
3229 gen_mov_F0_vreg(dp, rd);
3230 gen_vfp_F1_ld0(dp);
3231 break;
3232 case 20:
3233 case 21:
3234 case 22:
3235 case 23:
3236 case 28:
3237 case 29:
3238 case 30:
3239 case 31:
3240 /* Source and destination the same. */
3241 gen_mov_F0_vreg(dp, rd);
3242 break;
3243 case 4:
3244 case 5:
3245 case 6:
3246 case 7:
3247 /* VCVTB, VCVTT: only present with the halfprec extension
3248 * UNPREDICTABLE if bit 8 is set prior to ARMv8
3249 * (we choose to UNDEF)
3250 */
3251 if ((dp && !arm_feature(env, ARM_FEATURE_V8)) ||
3252 !arm_feature(env, ARM_FEATURE_VFP_FP16)) {
3253 return 1;
3254 }
3255 if (!extract32(rn, 1, 1)) {
3256 /* Half precision source. */
3257 gen_mov_F0_vreg(0, rm);
3258 break;
3259 }
3260 /* Otherwise fall through */
3261 default:
3262 /* One source operand. */
3263 gen_mov_F0_vreg(dp, rm);
3264 break;
3265 }
3266 } else {
3267 /* Two source operands. */
3268 gen_mov_F0_vreg(dp, rn);
3269 gen_mov_F1_vreg(dp, rm);
3270 }
3271
3272 for (;;) {
3273 /* Perform the calculation. */
3274 switch (op) {
3275 case 0: /* VMLA: fd + (fn * fm) */
3276 /* Note that order of inputs to the add matters for NaNs */
3277 gen_vfp_F1_mul(dp);
3278 gen_mov_F0_vreg(dp, rd);
3279 gen_vfp_add(dp);
3280 break;
3281 case 1: /* VMLS: fd + -(fn * fm) */
3282 gen_vfp_mul(dp);
3283 gen_vfp_F1_neg(dp);
3284 gen_mov_F0_vreg(dp, rd);
3285 gen_vfp_add(dp);
3286 break;
3287 case 2: /* VNMLS: -fd + (fn * fm) */
3288 /* Note that it isn't valid to replace (-A + B) with (B - A)
3289 * or similar plausible looking simplifications
3290 * because this will give wrong results for NaNs.
3291 */
3292 gen_vfp_F1_mul(dp);
3293 gen_mov_F0_vreg(dp, rd);
3294 gen_vfp_neg(dp);
3295 gen_vfp_add(dp);
3296 break;
3297 case 3: /* VNMLA: -fd + -(fn * fm) */
3298 gen_vfp_mul(dp);
3299 gen_vfp_F1_neg(dp);
3300 gen_mov_F0_vreg(dp, rd);
3301 gen_vfp_neg(dp);
3302 gen_vfp_add(dp);
3303 break;
3304 case 4: /* mul: fn * fm */
3305 gen_vfp_mul(dp);
3306 break;
3307 case 5: /* nmul: -(fn * fm) */
3308 gen_vfp_mul(dp);
3309 gen_vfp_neg(dp);
3310 break;
3311 case 6: /* add: fn + fm */
3312 gen_vfp_add(dp);
3313 break;
3314 case 7: /* sub: fn - fm */
3315 gen_vfp_sub(dp);
3316 break;
3317 case 8: /* div: fn / fm */
3318 gen_vfp_div(dp);
3319 break;
3320 case 10: /* VFNMA : fd = muladd(-fd, fn, fm) */
3321 case 11: /* VFNMS : fd = muladd(-fd, -fn, fm) */
3322 case 12: /* VFMA : fd = muladd( fd, fn, fm) */
3323 case 13: /* VFMS : fd = muladd( fd, -fn, fm) */
3324 /* These are fused multiply-add, and must be done as one
3325 * floating point operation with no rounding between the
3326 * multiplication and addition steps.
3327 * NB that doing the negations here as separate steps is
3328 * correct : an input NaN should come out with its sign bit
3329 * flipped if it is a negated-input.
3330 */
3331 if (!arm_feature(env, ARM_FEATURE_VFP4)) {
3332 return 1;
3333 }
3334 if (dp) {
3335 TCGv_ptr fpst;
3336 TCGv_i64 frd;
3337 if (op & 1) {
3338 /* VFNMS, VFMS */
3339 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
3340 }
3341 frd = tcg_temp_new_i64();
3342 tcg_gen_ld_f64(frd, cpu_env, vfp_reg_offset(dp, rd));
3343 if (op & 2) {
3344 /* VFNMA, VFNMS */
3345 gen_helper_vfp_negd(frd, frd);
3346 }
3347 fpst = get_fpstatus_ptr(0);
3348 gen_helper_vfp_muladdd(cpu_F0d, cpu_F0d,
3349 cpu_F1d, frd, fpst);
3350 tcg_temp_free_ptr(fpst);
3351 tcg_temp_free_i64(frd);
3352 } else {
3353 TCGv_ptr fpst;
3354 TCGv_i32 frd;
3355 if (op & 1) {
3356 /* VFNMS, VFMS */
3357 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
3358 }
3359 frd = tcg_temp_new_i32();
3360 tcg_gen_ld_f32(frd, cpu_env, vfp_reg_offset(dp, rd));
3361 if (op & 2) {
3362 gen_helper_vfp_negs(frd, frd);
3363 }
3364 fpst = get_fpstatus_ptr(0);
3365 gen_helper_vfp_muladds(cpu_F0s, cpu_F0s,
3366 cpu_F1s, frd, fpst);
3367 tcg_temp_free_ptr(fpst);
3368 tcg_temp_free_i32(frd);
3369 }
3370 break;
3371 case 14: /* fconst */
3372 if (!arm_feature(env, ARM_FEATURE_VFP3))
3373 return 1;
3374
3375 n = (insn << 12) & 0x80000000;
3376 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3377 if (dp) {
3378 if (i & 0x40)
3379 i |= 0x3f80;
3380 else
3381 i |= 0x4000;
3382 n |= i << 16;
3383 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3384 } else {
3385 if (i & 0x40)
3386 i |= 0x780;
3387 else
3388 i |= 0x800;
3389 n |= i << 19;
3390 tcg_gen_movi_i32(cpu_F0s, n);
3391 }
3392 break;
3393 case 15: /* extension space */
3394 switch (rn) {
3395 case 0: /* cpy */
3396 /* no-op */
3397 break;
3398 case 1: /* abs */
3399 gen_vfp_abs(dp);
3400 break;
3401 case 2: /* neg */
3402 gen_vfp_neg(dp);
3403 break;
3404 case 3: /* sqrt */
3405 gen_vfp_sqrt(dp);
3406 break;
3407 case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */
3408 tmp = gen_vfp_mrs();
3409 tcg_gen_ext16u_i32(tmp, tmp);
3410 if (dp) {
3411 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp,
3412 cpu_env);
3413 } else {
3414 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp,
3415 cpu_env);
3416 }
3417 tcg_temp_free_i32(tmp);
3418 break;
3419 case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */
3420 tmp = gen_vfp_mrs();
3421 tcg_gen_shri_i32(tmp, tmp, 16);
3422 if (dp) {
3423 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d, tmp,
3424 cpu_env);
3425 } else {
3426 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp,
3427 cpu_env);
3428 }
3429 tcg_temp_free_i32(tmp);
3430 break;
3431 case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */
3432 tmp = tcg_temp_new_i32();
3433 if (dp) {
3434 gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d,
3435 cpu_env);
3436 } else {
3437 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s,
3438 cpu_env);
3439 }
3440 gen_mov_F0_vreg(0, rd);
3441 tmp2 = gen_vfp_mrs();
3442 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3443 tcg_gen_or_i32(tmp, tmp, tmp2);
3444 tcg_temp_free_i32(tmp2);
3445 gen_vfp_msr(tmp);
3446 break;
3447 case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */
3448 tmp = tcg_temp_new_i32();
3449 if (dp) {
3450 gen_helper_vfp_fcvt_f64_to_f16(tmp, cpu_F0d,
3451 cpu_env);
3452 } else {
3453 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s,
3454 cpu_env);
3455 }
3456 tcg_gen_shli_i32(tmp, tmp, 16);
3457 gen_mov_F0_vreg(0, rd);
3458 tmp2 = gen_vfp_mrs();
3459 tcg_gen_ext16u_i32(tmp2, tmp2);
3460 tcg_gen_or_i32(tmp, tmp, tmp2);
3461 tcg_temp_free_i32(tmp2);
3462 gen_vfp_msr(tmp);
3463 break;
3464 case 8: /* cmp */
3465 gen_vfp_cmp(dp);
3466 break;
3467 case 9: /* cmpe */
3468 gen_vfp_cmpe(dp);
3469 break;
3470 case 10: /* cmpz */
3471 gen_vfp_cmp(dp);
3472 break;
3473 case 11: /* cmpez */
3474 gen_vfp_F1_ld0(dp);
3475 gen_vfp_cmpe(dp);
3476 break;
3477 case 12: /* vrintr */
3478 {
3479 TCGv_ptr fpst = get_fpstatus_ptr(0);
3480 if (dp) {
3481 gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
3482 } else {
3483 gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
3484 }
3485 tcg_temp_free_ptr(fpst);
3486 break;
3487 }
3488 case 13: /* vrintz */
3489 {
3490 TCGv_ptr fpst = get_fpstatus_ptr(0);
3491 TCGv_i32 tcg_rmode;
3492 tcg_rmode = tcg_const_i32(float_round_to_zero);
3493 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
3494 if (dp) {
3495 gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
3496 } else {
3497 gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
3498 }
3499 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
3500 tcg_temp_free_i32(tcg_rmode);
3501 tcg_temp_free_ptr(fpst);
3502 break;
3503 }
3504 case 14: /* vrintx */
3505 {
3506 TCGv_ptr fpst = get_fpstatus_ptr(0);
3507 if (dp) {
3508 gen_helper_rintd_exact(cpu_F0d, cpu_F0d, fpst);
3509 } else {
3510 gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpst);
3511 }
3512 tcg_temp_free_ptr(fpst);
3513 break;
3514 }
3515 case 15: /* single<->double conversion */
3516 if (dp)
3517 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3518 else
3519 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3520 break;
3521 case 16: /* fuito */
3522 gen_vfp_uito(dp, 0);
3523 break;
3524 case 17: /* fsito */
3525 gen_vfp_sito(dp, 0);
3526 break;
3527 case 20: /* fshto */
3528 if (!arm_feature(env, ARM_FEATURE_VFP3))
3529 return 1;
3530 gen_vfp_shto(dp, 16 - rm, 0);
3531 break;
3532 case 21: /* fslto */
3533 if (!arm_feature(env, ARM_FEATURE_VFP3))
3534 return 1;
3535 gen_vfp_slto(dp, 32 - rm, 0);
3536 break;
3537 case 22: /* fuhto */
3538 if (!arm_feature(env, ARM_FEATURE_VFP3))
3539 return 1;
3540 gen_vfp_uhto(dp, 16 - rm, 0);
3541 break;
3542 case 23: /* fulto */
3543 if (!arm_feature(env, ARM_FEATURE_VFP3))
3544 return 1;
3545 gen_vfp_ulto(dp, 32 - rm, 0);
3546 break;
3547 case 24: /* ftoui */
3548 gen_vfp_toui(dp, 0);
3549 break;
3550 case 25: /* ftouiz */
3551 gen_vfp_touiz(dp, 0);
3552 break;
3553 case 26: /* ftosi */
3554 gen_vfp_tosi(dp, 0);
3555 break;
3556 case 27: /* ftosiz */
3557 gen_vfp_tosiz(dp, 0);
3558 break;
3559 case 28: /* ftosh */
3560 if (!arm_feature(env, ARM_FEATURE_VFP3))
3561 return 1;
3562 gen_vfp_tosh(dp, 16 - rm, 0);
3563 break;
3564 case 29: /* ftosl */
3565 if (!arm_feature(env, ARM_FEATURE_VFP3))
3566 return 1;
3567 gen_vfp_tosl(dp, 32 - rm, 0);
3568 break;
3569 case 30: /* ftouh */
3570 if (!arm_feature(env, ARM_FEATURE_VFP3))
3571 return 1;
3572 gen_vfp_touh(dp, 16 - rm, 0);
3573 break;
3574 case 31: /* ftoul */
3575 if (!arm_feature(env, ARM_FEATURE_VFP3))
3576 return 1;
3577 gen_vfp_toul(dp, 32 - rm, 0);
3578 break;
3579 default: /* undefined */
3580 return 1;
3581 }
3582 break;
3583 default: /* undefined */
3584 return 1;
3585 }
3586
3587 /* Write back the result. */
3588 if (op == 15 && (rn >= 8 && rn <= 11)) {
3589 /* Comparison, do nothing. */
3590 } else if (op == 15 && dp && ((rn & 0x1c) == 0x18 ||
3591 (rn & 0x1e) == 0x6)) {
3592 /* VCVT double to int: always integer result.
3593 * VCVT double to half precision is always a single
3594 * precision result.
3595 */
3596 gen_mov_vreg_F0(0, rd);
3597 } else if (op == 15 && rn == 15) {
3598 /* conversion */
3599 gen_mov_vreg_F0(!dp, rd);
3600 } else {
3601 gen_mov_vreg_F0(dp, rd);
3602 }
3603
3604 /* break out of the loop if we have finished */
3605 if (veclen == 0)
3606 break;
3607
3608 if (op == 15 && delta_m == 0) {
3609 /* single source one-many */
3610 while (veclen--) {
3611 rd = ((rd + delta_d) & (bank_mask - 1))
3612 | (rd & bank_mask);
3613 gen_mov_vreg_F0(dp, rd);
3614 }
3615 break;
3616 }
3617 /* Setup the next operands. */
3618 veclen--;
3619 rd = ((rd + delta_d) & (bank_mask - 1))
3620 | (rd & bank_mask);
3621
3622 if (op == 15) {
3623 /* One source operand. */
3624 rm = ((rm + delta_m) & (bank_mask - 1))
3625 | (rm & bank_mask);
3626 gen_mov_F0_vreg(dp, rm);
3627 } else {
3628 /* Two source operands. */
3629 rn = ((rn + delta_d) & (bank_mask - 1))
3630 | (rn & bank_mask);
3631 gen_mov_F0_vreg(dp, rn);
3632 if (delta_m) {
3633 rm = ((rm + delta_m) & (bank_mask - 1))
3634 | (rm & bank_mask);
3635 gen_mov_F1_vreg(dp, rm);
3636 }
3637 }
3638 }
3639 }
3640 break;
3641 case 0xc:
3642 case 0xd:
3643 if ((insn & 0x03e00000) == 0x00400000) {
3644 /* two-register transfer */
3645 rn = (insn >> 16) & 0xf;
3646 rd = (insn >> 12) & 0xf;
3647 if (dp) {
3648 VFP_DREG_M(rm, insn);
3649 } else {
3650 rm = VFP_SREG_M(insn);
3651 }
3652
3653 if (insn & ARM_CP_RW_BIT) {
3654 /* vfp->arm */
3655 if (dp) {
3656 gen_mov_F0_vreg(0, rm * 2);
3657 tmp = gen_vfp_mrs();
3658 store_reg(s, rd, tmp);
3659 gen_mov_F0_vreg(0, rm * 2 + 1);
3660 tmp = gen_vfp_mrs();
3661 store_reg(s, rn, tmp);
3662 } else {
3663 gen_mov_F0_vreg(0, rm);
3664 tmp = gen_vfp_mrs();
3665 store_reg(s, rd, tmp);
3666 gen_mov_F0_vreg(0, rm + 1);
3667 tmp = gen_vfp_mrs();
3668 store_reg(s, rn, tmp);
3669 }
3670 } else {
3671 /* arm->vfp */
3672 if (dp) {
3673 tmp = load_reg(s, rd);
3674 gen_vfp_msr(tmp);
3675 gen_mov_vreg_F0(0, rm * 2);
3676 tmp = load_reg(s, rn);
3677 gen_vfp_msr(tmp);
3678 gen_mov_vreg_F0(0, rm * 2 + 1);
3679 } else {
3680 tmp = load_reg(s, rd);
3681 gen_vfp_msr(tmp);
3682 gen_mov_vreg_F0(0, rm);
3683 tmp = load_reg(s, rn);
3684 gen_vfp_msr(tmp);
3685 gen_mov_vreg_F0(0, rm + 1);
3686 }
3687 }
3688 } else {
3689 /* Load/store */
3690 rn = (insn >> 16) & 0xf;
3691 if (dp)
3692 VFP_DREG_D(rd, insn);
3693 else
3694 rd = VFP_SREG_D(insn);
3695 if ((insn & 0x01200000) == 0x01000000) {
3696 /* Single load/store */
3697 offset = (insn & 0xff) << 2;
3698 if ((insn & (1 << 23)) == 0)
3699 offset = -offset;
3700 if (s->thumb && rn == 15) {
3701 /* This is actually UNPREDICTABLE */
3702 addr = tcg_temp_new_i32();
3703 tcg_gen_movi_i32(addr, s->pc & ~2);
3704 } else {
3705 addr = load_reg(s, rn);
3706 }
3707 tcg_gen_addi_i32(addr, addr, offset);
3708 if (insn & (1 << 20)) {
3709 gen_vfp_ld(s, dp, addr);
3710 gen_mov_vreg_F0(dp, rd);
3711 } else {
3712 gen_mov_F0_vreg(dp, rd);
3713 gen_vfp_st(s, dp, addr);
3714 }
3715 tcg_temp_free_i32(addr);
3716 } else {
3717 /* load/store multiple */
3718 int w = insn & (1 << 21);
3719 if (dp)
3720 n = (insn >> 1) & 0x7f;
3721 else
3722 n = insn & 0xff;
3723
3724 if (w && !(((insn >> 23) ^ (insn >> 24)) & 1)) {
3725 /* P == U , W == 1 => UNDEF */
3726 return 1;
3727 }
3728 if (n == 0 || (rd + n) > 32 || (dp && n > 16)) {
3729 /* UNPREDICTABLE cases for bad immediates: we choose to
3730 * UNDEF to avoid generating huge numbers of TCG ops
3731 */
3732 return 1;
3733 }
3734 if (rn == 15 && w) {
3735 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
3736 return 1;
3737 }
3738
3739 if (s->thumb && rn == 15) {
3740 /* This is actually UNPREDICTABLE */
3741 addr = tcg_temp_new_i32();
3742 tcg_gen_movi_i32(addr, s->pc & ~2);
3743 } else {
3744 addr = load_reg(s, rn);
3745 }
3746 if (insn & (1 << 24)) /* pre-decrement */
3747 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
3748
3749 if (dp)
3750 offset = 8;
3751 else
3752 offset = 4;
3753 for (i = 0; i < n; i++) {
3754 if (insn & ARM_CP_RW_BIT) {
3755 /* load */
3756 gen_vfp_ld(s, dp, addr);
3757 gen_mov_vreg_F0(dp, rd + i);
3758 } else {
3759 /* store */
3760 gen_mov_F0_vreg(dp, rd + i);
3761 gen_vfp_st(s, dp, addr);
3762 }
3763 tcg_gen_addi_i32(addr, addr, offset);
3764 }
3765 if (w) {
3766 /* writeback */
3767 if (insn & (1 << 24))
3768 offset = -offset * n;
3769 else if (dp && (insn & 1))
3770 offset = 4;
3771 else
3772 offset = 0;
3773
3774 if (offset != 0)
3775 tcg_gen_addi_i32(addr, addr, offset);
3776 store_reg(s, rn, addr);
3777 } else {
3778 tcg_temp_free_i32(addr);
3779 }
3780 }
3781 }
3782 break;
3783 default:
3784 /* Should never happen. */
3785 return 1;
3786 }
3787 return 0;
3788 }
3789
3790 static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
3791 {
3792 TranslationBlock *tb;
3793
3794 tb = s->tb;
3795 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3796 tcg_gen_goto_tb(n);
3797 gen_set_pc_im(s, dest);
3798 tcg_gen_exit_tb((uintptr_t)tb + n);
3799 } else {
3800 gen_set_pc_im(s, dest);
3801 tcg_gen_exit_tb(0);
3802 }
3803 }
3804
3805 static inline void gen_jmp (DisasContext *s, uint32_t dest)
3806 {
3807 if (unlikely(s->singlestep_enabled)) {
3808 /* An indirect jump so that we still trigger the debug exception. */
3809 if (s->thumb)
3810 dest |= 1;
3811 gen_bx_im(s, dest);
3812 } else {
3813 gen_goto_tb(s, 0, dest);
3814 s->is_jmp = DISAS_TB_JUMP;
3815 }
3816 }
3817
3818 static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
3819 {
3820 if (x)
3821 tcg_gen_sari_i32(t0, t0, 16);
3822 else
3823 gen_sxth(t0);
3824 if (y)
3825 tcg_gen_sari_i32(t1, t1, 16);
3826 else
3827 gen_sxth(t1);
3828 tcg_gen_mul_i32(t0, t0, t1);
3829 }
3830
3831 /* Return the mask of PSR bits set by a MSR instruction. */
3832 static uint32_t msr_mask(CPUARMState *env, DisasContext *s, int flags, int spsr) {
3833 uint32_t mask;
3834
3835 mask = 0;
3836 if (flags & (1 << 0))
3837 mask |= 0xff;
3838 if (flags & (1 << 1))
3839 mask |= 0xff00;
3840 if (flags & (1 << 2))
3841 mask |= 0xff0000;
3842 if (flags & (1 << 3))
3843 mask |= 0xff000000;
3844
3845 /* Mask out undefined bits. */
3846 mask &= ~CPSR_RESERVED;
3847 if (!arm_feature(env, ARM_FEATURE_V4T))
3848 mask &= ~CPSR_T;
3849 if (!arm_feature(env, ARM_FEATURE_V5))
3850 mask &= ~CPSR_Q; /* V5TE in reality*/
3851 if (!arm_feature(env, ARM_FEATURE_V6))
3852 mask &= ~(CPSR_E | CPSR_GE);
3853 if (!arm_feature(env, ARM_FEATURE_THUMB2))
3854 mask &= ~CPSR_IT;
3855 /* Mask out execution state bits. */
3856 if (!spsr)
3857 mask &= ~CPSR_EXEC;
3858 /* Mask out privileged bits. */
3859 if (IS_USER(s))
3860 mask &= CPSR_USER;
3861 return mask;
3862 }
3863
3864 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3865 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv_i32 t0)
3866 {
3867 TCGv_i32 tmp;
3868 if (spsr) {
3869 /* ??? This is also undefined in system mode. */
3870 if (IS_USER(s))
3871 return 1;
3872
3873 tmp = load_cpu_field(spsr);
3874 tcg_gen_andi_i32(tmp, tmp, ~mask);
3875 tcg_gen_andi_i32(t0, t0, mask);
3876 tcg_gen_or_i32(tmp, tmp, t0);
3877 store_cpu_field(tmp, spsr);
3878 } else {
3879 gen_set_cpsr(t0, mask);
3880 }
3881 tcg_temp_free_i32(t0);
3882 gen_lookup_tb(s);
3883 return 0;
3884 }
3885
3886 /* Returns nonzero if access to the PSR is not permitted. */
3887 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3888 {
3889 TCGv_i32 tmp;
3890 tmp = tcg_temp_new_i32();
3891 tcg_gen_movi_i32(tmp, val);
3892 return gen_set_psr(s, mask, spsr, tmp);
3893 }
3894
3895 /* Generate an old-style exception return. Marks pc as dead. */
3896 static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
3897 {
3898 TCGv_i32 tmp;
3899 store_reg(s, 15, pc);
3900 tmp = load_cpu_field(spsr);
3901 gen_set_cpsr(tmp, 0xffffffff);
3902 tcg_temp_free_i32(tmp);
3903 s->is_jmp = DISAS_UPDATE;
3904 }
3905
3906 /* Generate a v6 exception return. Marks both values as dead. */
3907 static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
3908 {
3909 gen_set_cpsr(cpsr, 0xffffffff);
3910 tcg_temp_free_i32(cpsr);
3911 store_reg(s, 15, pc);
3912 s->is_jmp = DISAS_UPDATE;
3913 }
3914
3915 static inline void
3916 gen_set_condexec (DisasContext *s)
3917 {
3918 if (s->condexec_mask) {
3919 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3920 TCGv_i32 tmp = tcg_temp_new_i32();
3921 tcg_gen_movi_i32(tmp, val);
3922 store_cpu_field(tmp, condexec_bits);
3923 }
3924 }
3925
3926 static void gen_exception_insn(DisasContext *s, int offset, int excp)
3927 {
3928 gen_set_condexec(s);
3929 gen_set_pc_im(s, s->pc - offset);
3930 gen_exception(excp);
3931 s->is_jmp = DISAS_JUMP;
3932 }
3933
3934 static void gen_nop_hint(DisasContext *s, int val)
3935 {
3936 switch (val) {
3937 case 3: /* wfi */
3938 gen_set_pc_im(s, s->pc);
3939 s->is_jmp = DISAS_WFI;
3940 break;
3941 case 2: /* wfe */
3942 gen_set_pc_im(s, s->pc);
3943 s->is_jmp = DISAS_WFE;
3944 break;
3945 case 4: /* sev */
3946 case 5: /* sevl */
3947 /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */
3948 default: /* nop */
3949 break;
3950 }
3951 }
3952
3953 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3954
3955 static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1)
3956 {
3957 switch (size) {
3958 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3959 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3960 case 2: tcg_gen_add_i32(t0, t0, t1); break;
3961 default: abort();
3962 }
3963 }
3964
3965 static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
3966 {
3967 switch (size) {
3968 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3969 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3970 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
3971 default: return;
3972 }
3973 }
3974
3975 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3976 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3977 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3978 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3979 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3980
3981 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3982 switch ((size << 1) | u) { \
3983 case 0: \
3984 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3985 break; \
3986 case 1: \
3987 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3988 break; \
3989 case 2: \
3990 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3991 break; \
3992 case 3: \
3993 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3994 break; \
3995 case 4: \
3996 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3997 break; \
3998 case 5: \
3999 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
4000 break; \
4001 default: return 1; \
4002 }} while (0)
4003
4004 #define GEN_NEON_INTEGER_OP(name) do { \
4005 switch ((size << 1) | u) { \
4006 case 0: \
4007 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
4008 break; \
4009 case 1: \
4010 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
4011 break; \
4012 case 2: \
4013 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
4014 break; \
4015 case 3: \
4016 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
4017 break; \
4018 case 4: \
4019 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
4020 break; \
4021 case 5: \
4022 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
4023 break; \
4024 default: return 1; \
4025 }} while (0)
4026
4027 static TCGv_i32 neon_load_scratch(int scratch)
4028 {
4029 TCGv_i32 tmp = tcg_temp_new_i32();
4030 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
4031 return tmp;
4032 }
4033
4034 static void neon_store_scratch(int scratch, TCGv_i32 var)
4035 {
4036 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
4037 tcg_temp_free_i32(var);
4038 }
4039
4040 static inline TCGv_i32 neon_get_scalar(int size, int reg)
4041 {
4042 TCGv_i32 tmp;
4043 if (size == 1) {
4044 tmp = neon_load_reg(reg & 7, reg >> 4);
4045 if (reg & 8) {
4046 gen_neon_dup_high16(tmp);
4047 } else {
4048 gen_neon_dup_low16(tmp);
4049 }
4050 } else {
4051 tmp = neon_load_reg(reg & 15, reg >> 4);
4052 }
4053 return tmp;
4054 }
4055
4056 static int gen_neon_unzip(int rd, int rm, int size, int q)
4057 {
4058 TCGv_i32 tmp, tmp2;
4059 if (!q && size == 2) {
4060 return 1;
4061 }
4062 tmp = tcg_const_i32(rd);
4063 tmp2 = tcg_const_i32(rm);
4064 if (q) {
4065 switch (size) {
4066 case 0:
4067 gen_helper_neon_qunzip8(cpu_env, tmp, tmp2);
4068 break;
4069 case 1:
4070 gen_helper_neon_qunzip16(cpu_env, tmp, tmp2);
4071 break;
4072 case 2:
4073 gen_helper_neon_qunzip32(cpu_env, tmp, tmp2);
4074 break;
4075 default:
4076 abort();
4077 }
4078 } else {
4079 switch (size) {
4080 case 0:
4081 gen_helper_neon_unzip8(cpu_env, tmp, tmp2);
4082 break;
4083 case 1:
4084 gen_helper_neon_unzip16(cpu_env, tmp, tmp2);
4085 break;
4086 default:
4087 abort();
4088 }
4089 }
4090 tcg_temp_free_i32(tmp);
4091 tcg_temp_free_i32(tmp2);
4092 return 0;
4093 }
4094
4095 static int gen_neon_zip(int rd, int rm, int size, int q)
4096 {
4097 TCGv_i32 tmp, tmp2;
4098 if (!q && size == 2) {
4099 return 1;
4100 }
4101 tmp = tcg_const_i32(rd);
4102 tmp2 = tcg_const_i32(rm);
4103 if (q) {
4104 switch (size) {
4105 case 0:
4106 gen_helper_neon_qzip8(cpu_env, tmp, tmp2);
4107 break;
4108 case 1:
4109 gen_helper_neon_qzip16(cpu_env, tmp, tmp2);
4110 break;
4111 case 2:
4112 gen_helper_neon_qzip32(cpu_env, tmp, tmp2);
4113 break;
4114 default:
4115 abort();
4116 }
4117 } else {
4118 switch (size) {
4119 case 0:
4120 gen_helper_neon_zip8(cpu_env, tmp, tmp2);
4121 break;
4122 case 1:
4123 gen_helper_neon_zip16(cpu_env, tmp, tmp2);
4124 break;
4125 default:
4126 abort();
4127 }
4128 }
4129 tcg_temp_free_i32(tmp);
4130 tcg_temp_free_i32(tmp2);
4131 return 0;
4132 }
4133
4134 static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
4135 {
4136 TCGv_i32 rd, tmp;
4137
4138 rd = tcg_temp_new_i32();
4139 tmp = tcg_temp_new_i32();
4140
4141 tcg_gen_shli_i32(rd, t0, 8);
4142 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
4143 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
4144 tcg_gen_or_i32(rd, rd, tmp);
4145
4146 tcg_gen_shri_i32(t1, t1, 8);
4147 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
4148 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
4149 tcg_gen_or_i32(t1, t1, tmp);
4150 tcg_gen_mov_i32(t0, rd);
4151
4152 tcg_temp_free_i32(tmp);
4153 tcg_temp_free_i32(rd);
4154 }
4155
4156 static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
4157 {
4158 TCGv_i32 rd, tmp;
4159
4160 rd = tcg_temp_new_i32();
4161 tmp = tcg_temp_new_i32();
4162
4163 tcg_gen_shli_i32(rd, t0, 16);
4164 tcg_gen_andi_i32(tmp, t1, 0xffff);
4165 tcg_gen_or_i32(rd, rd, tmp);
4166 tcg_gen_shri_i32(t1, t1, 16);
4167 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
4168 tcg_gen_or_i32(t1, t1, tmp);
4169 tcg_gen_mov_i32(t0, rd);
4170
4171 tcg_temp_free_i32(tmp);
4172 tcg_temp_free_i32(rd);
4173 }
4174
4175
4176 static struct {
4177 int nregs;
4178 int interleave;
4179 int spacing;
4180 } neon_ls_element_type[11] = {
4181 {4, 4, 1},
4182 {4, 4, 2},
4183 {4, 1, 1},
4184 {4, 2, 1},
4185 {3, 3, 1},
4186 {3, 3, 2},
4187 {3, 1, 1},
4188 {1, 1, 1},
4189 {2, 2, 1},
4190 {2, 2, 2},
4191 {2, 1, 1}
4192 };
4193
4194 /* Translate a NEON load/store element instruction. Return nonzero if the
4195 instruction is invalid. */
4196 static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
4197 {
4198 int rd, rn, rm;
4199 int op;
4200 int nregs;
4201 int interleave;
4202 int spacing;
4203 int stride;
4204 int size;
4205 int reg;
4206 int pass;
4207 int load;
4208 int shift;
4209 int n;
4210 TCGv_i32 addr;
4211 TCGv_i32 tmp;
4212 TCGv_i32 tmp2;
4213 TCGv_i64 tmp64;
4214
4215 if (!s->vfp_enabled)
4216 return 1;
4217 VFP_DREG_D(rd, insn);
4218 rn = (insn >> 16) & 0xf;
4219 rm = insn & 0xf;
4220 load = (insn & (1 << 21)) != 0;
4221 if ((insn & (1 << 23)) == 0) {
4222 /* Load store all elements. */
4223 op = (insn >> 8) & 0xf;
4224 size = (insn >> 6) & 3;
4225 if (op > 10)
4226 return 1;
4227 /* Catch UNDEF cases for bad values of align field */
4228 switch (op & 0xc) {
4229 case 4:
4230 if (((insn >> 5) & 1) == 1) {
4231 return 1;
4232 }
4233 break;
4234 case 8:
4235 if (((insn >> 4) & 3) == 3) {
4236 return 1;
4237 }
4238 break;
4239 default:
4240 break;
4241 }
4242 nregs = neon_ls_element_type[op].nregs;
4243 interleave = neon_ls_element_type[op].interleave;
4244 spacing = neon_ls_element_type[op].spacing;
4245 if (size == 3 && (interleave | spacing) != 1)
4246 return 1;
4247 addr = tcg_temp_new_i32();
4248 load_reg_var(s, addr, rn);
4249 stride = (1 << size) * interleave;
4250 for (reg = 0; reg < nregs; reg++) {
4251 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
4252 load_reg_var(s, addr, rn);
4253 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
4254 } else if (interleave == 2 && nregs == 4 && reg == 2) {
4255 load_reg_var(s, addr, rn);
4256 tcg_gen_addi_i32(addr, addr, 1 << size);
4257 }
4258 if (size == 3) {
4259 tmp64 = tcg_temp_new_i64();
4260 if (load) {
4261 gen_aa32_ld64(tmp64, addr, IS_USER(s));
4262 neon_store_reg64(tmp64, rd);
4263 } else {
4264 neon_load_reg64(tmp64, rd);
4265 gen_aa32_st64(tmp64, addr, IS_USER(s));
4266 }
4267 tcg_temp_free_i64(tmp64);
4268 tcg_gen_addi_i32(addr, addr, stride);
4269 } else {
4270 for (pass = 0; pass < 2; pass++) {
4271 if (size == 2) {
4272 if (load) {
4273 tmp = tcg_temp_new_i32();
4274 gen_aa32_ld32u(tmp, addr, IS_USER(s));
4275 neon_store_reg(rd, pass, tmp);
4276 } else {
4277 tmp = neon_load_reg(rd, pass);
4278 gen_aa32_st32(tmp, addr, IS_USER(s));
4279 tcg_temp_free_i32(tmp);
4280 }
4281 tcg_gen_addi_i32(addr, addr, stride);
4282 } else if (size == 1) {
4283 if (load) {
4284 tmp = tcg_temp_new_i32();
4285 gen_aa32_ld16u(tmp, addr, IS_USER(s));
4286 tcg_gen_addi_i32(addr, addr, stride);
4287 tmp2 = tcg_temp_new_i32();
4288 gen_aa32_ld16u(tmp2, addr, IS_USER(s));
4289 tcg_gen_addi_i32(addr, addr, stride);
4290 tcg_gen_shli_i32(tmp2, tmp2, 16);
4291 tcg_gen_or_i32(tmp, tmp, tmp2);
4292 tcg_temp_free_i32(tmp2);
4293 neon_store_reg(rd, pass, tmp);
4294 } else {
4295 tmp = neon_load_reg(rd, pass);
4296 tmp2 = tcg_temp_new_i32();
4297 tcg_gen_shri_i32(tmp2, tmp, 16);
4298 gen_aa32_st16(tmp, addr, IS_USER(s));
4299 tcg_temp_free_i32(tmp);
4300 tcg_gen_addi_i32(addr, addr, stride);
4301 gen_aa32_st16(tmp2, addr, IS_USER(s));
4302 tcg_temp_free_i32(tmp2);
4303 tcg_gen_addi_i32(addr, addr, stride);
4304 }
4305 } else /* size == 0 */ {
4306 if (load) {
4307 TCGV_UNUSED_I32(tmp2);
4308 for (n = 0; n < 4; n++) {
4309 tmp = tcg_temp_new_i32();
4310 gen_aa32_ld8u(tmp, addr, IS_USER(s));
4311 tcg_gen_addi_i32(addr, addr, stride);
4312 if (n == 0) {
4313 tmp2 = tmp;
4314 } else {
4315 tcg_gen_shli_i32(tmp, tmp, n * 8);
4316 tcg_gen_or_i32(tmp2, tmp2, tmp);
4317 tcg_temp_free_i32(tmp);
4318 }
4319 }
4320 neon_store_reg(rd, pass, tmp2);
4321 } else {
4322 tmp2 = neon_load_reg(rd, pass);
4323 for (n = 0; n < 4; n++) {
4324 tmp = tcg_temp_new_i32();
4325 if (n == 0) {
4326 tcg_gen_mov_i32(tmp, tmp2);
4327 } else {
4328 tcg_gen_shri_i32(tmp, tmp2, n * 8);
4329 }
4330 gen_aa32_st8(tmp, addr, IS_USER(s));
4331 tcg_temp_free_i32(tmp);
4332 tcg_gen_addi_i32(addr, addr, stride);
4333 }
4334 tcg_temp_free_i32(tmp2);
4335 }
4336 }
4337 }
4338 }
4339 rd += spacing;
4340 }
4341 tcg_temp_free_i32(addr);
4342 stride = nregs * 8;
4343 } else {
4344 size = (insn >> 10) & 3;
4345 if (size == 3) {
4346 /* Load single element to all lanes. */
4347 int a = (insn >> 4) & 1;
4348 if (!load) {
4349 return 1;
4350 }
4351 size = (insn >> 6) & 3;
4352 nregs = ((insn >> 8) & 3) + 1;
4353
4354 if (size == 3) {
4355 if (nregs != 4 || a == 0) {
4356 return 1;
4357 }
4358 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
4359 size = 2;
4360 }
4361 if (nregs == 1 && a == 1 && size == 0) {
4362 return 1;
4363 }
4364 if (nregs == 3 && a == 1) {
4365 return 1;
4366 }
4367 addr = tcg_temp_new_i32();
4368 load_reg_var(s, addr, rn);
4369 if (nregs == 1) {
4370 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
4371 tmp = gen_load_and_replicate(s, addr, size);
4372 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
4373 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
4374 if (insn & (1 << 5)) {
4375 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
4376 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
4377 }
4378 tcg_temp_free_i32(tmp);
4379 } else {
4380 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
4381 stride = (insn & (1 << 5)) ? 2 : 1;
4382 for (reg = 0; reg < nregs; reg++) {
4383 tmp = gen_load_and_replicate(s, addr, size);
4384 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
4385 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
4386 tcg_temp_free_i32(tmp);
4387 tcg_gen_addi_i32(addr, addr, 1 << size);
4388 rd += stride;
4389 }
4390 }
4391 tcg_temp_free_i32(addr);
4392 stride = (1 << size) * nregs;
4393 } else {
4394 /* Single element. */
4395 int idx = (insn >> 4) & 0xf;
4396 pass = (insn >> 7) & 1;
4397 switch (size) {
4398 case 0:
4399 shift = ((insn >> 5) & 3) * 8;
4400 stride = 1;
4401 break;
4402 case 1:
4403 shift = ((insn >> 6) & 1) * 16;
4404 stride = (insn & (1 << 5)) ? 2 : 1;
4405 break;
4406 case 2:
4407 shift = 0;
4408 stride = (insn & (1 << 6)) ? 2 : 1;
4409 break;
4410 default:
4411 abort();
4412 }
4413 nregs = ((insn >> 8) & 3) + 1;
4414 /* Catch the UNDEF cases. This is unavoidably a bit messy. */
4415 switch (nregs) {
4416 case 1:
4417 if (((idx & (1 << size)) != 0) ||
4418 (size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) {
4419 return 1;
4420 }
4421 break;
4422 case 3:
4423 if ((idx & 1) != 0) {
4424 return 1;
4425 }
4426 /* fall through */
4427 case 2:
4428 if (size == 2 && (idx & 2) != 0) {
4429 return 1;
4430 }
4431 break;
4432 case 4:
4433 if ((size == 2) && ((idx & 3) == 3)) {
4434 return 1;
4435 }
4436 break;
4437 default:
4438 abort();
4439 }
4440 if ((rd + stride * (nregs - 1)) > 31) {
4441 /* Attempts to write off the end of the register file
4442 * are UNPREDICTABLE; we choose to UNDEF because otherwise
4443 * the neon_load_reg() would write off the end of the array.
4444 */
4445 return 1;
4446 }
4447 addr = tcg_temp_new_i32();
4448 load_reg_var(s, addr, rn);
4449 for (reg = 0; reg < nregs; reg++) {
4450 if (load) {
4451 tmp = tcg_temp_new_i32();
4452 switch (size) {
4453 case 0:
4454 gen_aa32_ld8u(tmp, addr, IS_USER(s));
4455 break;
4456 case 1:
4457 gen_aa32_ld16u(tmp, addr, IS_USER(s));
4458 break;
4459 case 2:
4460 gen_aa32_ld32u(tmp, addr, IS_USER(s));
4461 break;
4462 default: /* Avoid compiler warnings. */
4463 abort();
4464 }
4465 if (size != 2) {
4466 tmp2 = neon_load_reg(rd, pass);
4467 tcg_gen_deposit_i32(tmp, tmp2, tmp,
4468 shift, size ? 16 : 8);
4469 tcg_temp_free_i32(tmp2);
4470 }
4471 neon_store_reg(rd, pass, tmp);
4472 } else { /* Store */
4473 tmp = neon_load_reg(rd, pass);
4474 if (shift)
4475 tcg_gen_shri_i32(tmp, tmp, shift);
4476 switch (size) {
4477 case 0:
4478 gen_aa32_st8(tmp, addr, IS_USER(s));
4479 break;
4480 case 1:
4481 gen_aa32_st16(tmp, addr, IS_USER(s));
4482 break;
4483 case 2:
4484 gen_aa32_st32(tmp, addr, IS_USER(s));
4485 break;
4486 }
4487 tcg_temp_free_i32(tmp);
4488 }
4489 rd += stride;
4490 tcg_gen_addi_i32(addr, addr, 1 << size);
4491 }
4492 tcg_temp_free_i32(addr);
4493 stride = nregs * (1 << size);
4494 }
4495 }
4496 if (rm != 15) {
4497 TCGv_i32 base;
4498
4499 base = load_reg(s, rn);
4500 if (rm == 13) {
4501 tcg_gen_addi_i32(base, base, stride);
4502 } else {
4503 TCGv_i32 index;
4504 index = load_reg(s, rm);
4505 tcg_gen_add_i32(base, base, index);
4506 tcg_temp_free_i32(index);
4507 }
4508 store_reg(s, rn, base);
4509 }
4510 return 0;
4511 }
4512
4513 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4514 static void gen_neon_bsl(TCGv_i32 dest, TCGv_i32 t, TCGv_i32 f, TCGv_i32 c)
4515 {
4516 tcg_gen_and_i32(t, t, c);
4517 tcg_gen_andc_i32(f, f, c);
4518 tcg_gen_or_i32(dest, t, f);
4519 }
4520
4521 static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
4522 {
4523 switch (size) {
4524 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4525 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4526 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4527 default: abort();
4528 }
4529 }
4530
4531 static inline void gen_neon_narrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
4532 {
4533 switch (size) {
4534 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4535 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4536 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4537 default: abort();
4538 }
4539 }
4540
4541 static inline void gen_neon_narrow_satu(int size, TCGv_i32 dest, TCGv_i64 src)
4542 {
4543 switch (size) {
4544 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4545 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4546 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4547 default: abort();
4548 }
4549 }
4550
4551 static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src)
4552 {
4553 switch (size) {
4554 case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break;
4555 case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break;
4556 case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break;
4557 default: abort();
4558 }
4559 }
4560
4561 static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
4562 int q, int u)
4563 {
4564 if (q) {
4565 if (u) {
4566 switch (size) {
4567 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4568 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4569 default: abort();
4570 }
4571 } else {
4572 switch (size) {
4573 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4574 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4575 default: abort();
4576 }
4577 }
4578 } else {
4579 if (u) {
4580 switch (size) {
4581 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4582 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
4583 default: abort();
4584 }
4585 } else {
4586 switch (size) {
4587 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4588 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4589 default: abort();
4590 }
4591 }
4592 }
4593 }
4594
4595 static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
4596 {
4597 if (u) {
4598 switch (size) {
4599 case 0: gen_helper_neon_widen_u8(dest, src); break;
4600 case 1: gen_helper_neon_widen_u16(dest, src); break;
4601 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4602 default: abort();
4603 }
4604 } else {
4605 switch (size) {
4606 case 0: gen_helper_neon_widen_s8(dest, src); break;
4607 case 1: gen_helper_neon_widen_s16(dest, src); break;
4608 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4609 default: abort();
4610 }
4611 }
4612 tcg_temp_free_i32(src);
4613 }
4614
4615 static inline void gen_neon_addl(int size)
4616 {
4617 switch (size) {
4618 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4619 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4620 case 2: tcg_gen_add_i64(CPU_V001); break;
4621 default: abort();
4622 }
4623 }
4624
4625 static inline void gen_neon_subl(int size)
4626 {
4627 switch (size) {
4628 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4629 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4630 case 2: tcg_gen_sub_i64(CPU_V001); break;
4631 default: abort();
4632 }
4633 }
4634
4635 static inline void gen_neon_negl(TCGv_i64 var, int size)
4636 {
4637 switch (size) {
4638 case 0: gen_helper_neon_negl_u16(var, var); break;
4639 case 1: gen_helper_neon_negl_u32(var, var); break;
4640 case 2:
4641 tcg_gen_neg_i64(var, var);
4642 break;
4643 default: abort();
4644 }
4645 }
4646
4647 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4648 {
4649 switch (size) {
4650 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4651 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4652 default: abort();
4653 }
4654 }
4655
4656 static inline void gen_neon_mull(TCGv_i64 dest, TCGv_i32 a, TCGv_i32 b,
4657 int size, int u)
4658 {
4659 TCGv_i64 tmp;
4660
4661 switch ((size << 1) | u) {
4662 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4663 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4664 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4665 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4666 case 4:
4667 tmp = gen_muls_i64_i32(a, b);
4668 tcg_gen_mov_i64(dest, tmp);
4669 tcg_temp_free_i64(tmp);
4670 break;
4671 case 5:
4672 tmp = gen_mulu_i64_i32(a, b);
4673 tcg_gen_mov_i64(dest, tmp);
4674 tcg_temp_free_i64(tmp);
4675 break;
4676 default: abort();
4677 }
4678
4679 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4680 Don't forget to clean them now. */
4681 if (size < 2) {
4682 tcg_temp_free_i32(a);
4683 tcg_temp_free_i32(b);
4684 }
4685 }
4686
4687 static void gen_neon_narrow_op(int op, int u, int size,
4688 TCGv_i32 dest, TCGv_i64 src)
4689 {
4690 if (op) {
4691 if (u) {
4692 gen_neon_unarrow_sats(size, dest, src);
4693 } else {
4694 gen_neon_narrow(size, dest, src);
4695 }
4696 } else {
4697 if (u) {
4698 gen_neon_narrow_satu(size, dest, src);
4699 } else {
4700 gen_neon_narrow_sats(size, dest, src);
4701 }
4702 }
4703 }
4704
4705 /* Symbolic constants for op fields for Neon 3-register same-length.
4706 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
4707 * table A7-9.
4708 */
4709 #define NEON_3R_VHADD 0
4710 #define NEON_3R_VQADD 1
4711 #define NEON_3R_VRHADD 2
4712 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
4713 #define NEON_3R_VHSUB 4
4714 #define NEON_3R_VQSUB 5
4715 #define NEON_3R_VCGT 6
4716 #define NEON_3R_VCGE 7
4717 #define NEON_3R_VSHL 8
4718 #define NEON_3R_VQSHL 9
4719 #define NEON_3R_VRSHL 10
4720 #define NEON_3R_VQRSHL 11
4721 #define NEON_3R_VMAX 12
4722 #define NEON_3R_VMIN 13
4723 #define NEON_3R_VABD 14
4724 #define NEON_3R_VABA 15
4725 #define NEON_3R_VADD_VSUB 16
4726 #define NEON_3R_VTST_VCEQ 17
4727 #define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
4728 #define NEON_3R_VMUL 19
4729 #define NEON_3R_VPMAX 20
4730 #define NEON_3R_VPMIN 21
4731 #define NEON_3R_VQDMULH_VQRDMULH 22
4732 #define NEON_3R_VPADD 23
4733 #define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */
4734 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
4735 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
4736 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
4737 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
4738 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
4739 #define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
4740
4741 static const uint8_t neon_3r_sizes[] = {
4742 [NEON_3R_VHADD] = 0x7,
4743 [NEON_3R_VQADD] = 0xf,
4744 [NEON_3R_VRHADD] = 0x7,
4745 [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
4746 [NEON_3R_VHSUB] = 0x7,
4747 [NEON_3R_VQSUB] = 0xf,
4748 [NEON_3R_VCGT] = 0x7,
4749 [NEON_3R_VCGE] = 0x7,
4750 [NEON_3R_VSHL] = 0xf,
4751 [NEON_3R_VQSHL] = 0xf,
4752 [NEON_3R_VRSHL] = 0xf,
4753 [NEON_3R_VQRSHL] = 0xf,
4754 [NEON_3R_VMAX] = 0x7,
4755 [NEON_3R_VMIN] = 0x7,
4756 [NEON_3R_VABD] = 0x7,
4757 [NEON_3R_VABA] = 0x7,
4758 [NEON_3R_VADD_VSUB] = 0xf,
4759 [NEON_3R_VTST_VCEQ] = 0x7,
4760 [NEON_3R_VML] = 0x7,
4761 [NEON_3R_VMUL] = 0x7,
4762 [NEON_3R_VPMAX] = 0x7,
4763 [NEON_3R_VPMIN] = 0x7,
4764 [NEON_3R_VQDMULH_VQRDMULH] = 0x6,
4765 [NEON_3R_VPADD] = 0x7,
4766 [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */
4767 [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
4768 [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
4769 [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
4770 [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
4771 [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
4772 [NEON_3R_FLOAT_MISC] = 0x5, /* size bit 1 encodes op */
4773 };
4774
4775 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
4776 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
4777 * table A7-13.
4778 */
4779 #define NEON_2RM_VREV64 0
4780 #define NEON_2RM_VREV32 1
4781 #define NEON_2RM_VREV16 2
4782 #define NEON_2RM_VPADDL 4
4783 #define NEON_2RM_VPADDL_U 5
4784 #define NEON_2RM_AESE 6 /* Includes AESD */
4785 #define NEON_2RM_AESMC 7 /* Includes AESIMC */
4786 #define NEON_2RM_VCLS 8
4787 #define NEON_2RM_VCLZ 9
4788 #define NEON_2RM_VCNT 10
4789 #define NEON_2RM_VMVN 11
4790 #define NEON_2RM_VPADAL 12
4791 #define NEON_2RM_VPADAL_U 13
4792 #define NEON_2RM_VQABS 14
4793 #define NEON_2RM_VQNEG 15
4794 #define NEON_2RM_VCGT0 16
4795 #define NEON_2RM_VCGE0 17
4796 #define NEON_2RM_VCEQ0 18
4797 #define NEON_2RM_VCLE0 19
4798 #define NEON_2RM_VCLT0 20
4799 #define NEON_2RM_VABS 22
4800 #define NEON_2RM_VNEG 23
4801 #define NEON_2RM_VCGT0_F 24
4802 #define NEON_2RM_VCGE0_F 25
4803 #define NEON_2RM_VCEQ0_F 26
4804 #define NEON_2RM_VCLE0_F 27
4805 #define NEON_2RM_VCLT0_F 28
4806 #define NEON_2RM_VABS_F 30
4807 #define NEON_2RM_VNEG_F 31
4808 #define NEON_2RM_VSWP 32
4809 #define NEON_2RM_VTRN 33
4810 #define NEON_2RM_VUZP 34
4811 #define NEON_2RM_VZIP 35
4812 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
4813 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
4814 #define NEON_2RM_VSHLL 38
4815 #define NEON_2RM_VRINTN 40
4816 #define NEON_2RM_VRINTX 41
4817 #define NEON_2RM_VRINTA 42
4818 #define NEON_2RM_VRINTZ 43
4819 #define NEON_2RM_VCVT_F16_F32 44
4820 #define NEON_2RM_VRINTM 45
4821 #define NEON_2RM_VCVT_F32_F16 46
4822 #define NEON_2RM_VRINTP 47
4823 #define NEON_2RM_VCVTAU 48
4824 #define NEON_2RM_VCVTAS 49
4825 #define NEON_2RM_VCVTNU 50
4826 #define NEON_2RM_VCVTNS 51
4827 #define NEON_2RM_VCVTPU 52
4828 #define NEON_2RM_VCVTPS 53
4829 #define NEON_2RM_VCVTMU 54
4830 #define NEON_2RM_VCVTMS 55
4831 #define NEON_2RM_VRECPE 56
4832 #define NEON_2RM_VRSQRTE 57
4833 #define NEON_2RM_VRECPE_F 58
4834 #define NEON_2RM_VRSQRTE_F 59
4835 #define NEON_2RM_VCVT_FS 60
4836 #define NEON_2RM_VCVT_FU 61
4837 #define NEON_2RM_VCVT_SF 62
4838 #define NEON_2RM_VCVT_UF 63
4839
4840 static int neon_2rm_is_float_op(int op)
4841 {
4842 /* Return true if this neon 2reg-misc op is float-to-float */
4843 return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
4844 (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
4845 op == NEON_2RM_VRINTM ||
4846 (op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) ||
4847 op >= NEON_2RM_VRECPE_F);
4848 }
4849
4850 /* Each entry in this array has bit n set if the insn allows
4851 * size value n (otherwise it will UNDEF). Since unallocated
4852 * op values will have no bits set they always UNDEF.
4853 */
4854 static const uint8_t neon_2rm_sizes[] = {
4855 [NEON_2RM_VREV64] = 0x7,
4856 [NEON_2RM_VREV32] = 0x3,
4857 [NEON_2RM_VREV16] = 0x1,
4858 [NEON_2RM_VPADDL] = 0x7,
4859 [NEON_2RM_VPADDL_U] = 0x7,
4860 [NEON_2RM_AESE] = 0x1,
4861 [NEON_2RM_AESMC] = 0x1,
4862 [NEON_2RM_VCLS] = 0x7,
4863 [NEON_2RM_VCLZ] = 0x7,
4864 [NEON_2RM_VCNT] = 0x1,
4865 [NEON_2RM_VMVN] = 0x1,
4866 [NEON_2RM_VPADAL] = 0x7,
4867 [NEON_2RM_VPADAL_U] = 0x7,
4868 [NEON_2RM_VQABS] = 0x7,
4869 [NEON_2RM_VQNEG] = 0x7,
4870 [NEON_2RM_VCGT0] = 0x7,
4871 [NEON_2RM_VCGE0] = 0x7,
4872 [NEON_2RM_VCEQ0] = 0x7,
4873 [NEON_2RM_VCLE0] = 0x7,
4874 [NEON_2RM_VCLT0] = 0x7,
4875 [NEON_2RM_VABS] = 0x7,
4876 [NEON_2RM_VNEG] = 0x7,
4877 [NEON_2RM_VCGT0_F] = 0x4,
4878 [NEON_2RM_VCGE0_F] = 0x4,
4879 [NEON_2RM_VCEQ0_F] = 0x4,
4880 [NEON_2RM_VCLE0_F] = 0x4,
4881 [NEON_2RM_VCLT0_F] = 0x4,
4882 [NEON_2RM_VABS_F] = 0x4,
4883 [NEON_2RM_VNEG_F] = 0x4,
4884 [NEON_2RM_VSWP] = 0x1,
4885 [NEON_2RM_VTRN] = 0x7,
4886 [NEON_2RM_VUZP] = 0x7,
4887 [NEON_2RM_VZIP] = 0x7,
4888 [NEON_2RM_VMOVN] = 0x7,
4889 [NEON_2RM_VQMOVN] = 0x7,
4890 [NEON_2RM_VSHLL] = 0x7,
4891 [NEON_2RM_VRINTN] = 0x4,
4892 [NEON_2RM_VRINTX] = 0x4,
4893 [NEON_2RM_VRINTA] = 0x4,
4894 [NEON_2RM_VRINTZ] = 0x4,
4895 [NEON_2RM_VCVT_F16_F32] = 0x2,
4896 [NEON_2RM_VRINTM] = 0x4,
4897 [NEON_2RM_VCVT_F32_F16] = 0x2,
4898 [NEON_2RM_VRINTP] = 0x4,
4899 [NEON_2RM_VCVTAU] = 0x4,
4900 [NEON_2RM_VCVTAS] = 0x4,
4901 [NEON_2RM_VCVTNU] = 0x4,
4902 [NEON_2RM_VCVTNS] = 0x4,
4903 [NEON_2RM_VCVTPU] = 0x4,
4904 [NEON_2RM_VCVTPS] = 0x4,
4905 [NEON_2RM_VCVTMU] = 0x4,
4906 [NEON_2RM_VCVTMS] = 0x4,
4907 [NEON_2RM_VRECPE] = 0x4,
4908 [NEON_2RM_VRSQRTE] = 0x4,
4909 [NEON_2RM_VRECPE_F] = 0x4,
4910 [NEON_2RM_VRSQRTE_F] = 0x4,
4911 [NEON_2RM_VCVT_FS] = 0x4,
4912 [NEON_2RM_VCVT_FU] = 0x4,
4913 [NEON_2RM_VCVT_SF] = 0x4,
4914 [NEON_2RM_VCVT_UF] = 0x4,
4915 };
4916
4917 /* Translate a NEON data processing instruction. Return nonzero if the
4918 instruction is invalid.
4919 We process data in a mixture of 32-bit and 64-bit chunks.
4920 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4921
4922 static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
4923 {
4924 int op;
4925 int q;
4926 int rd, rn, rm;
4927 int size;
4928 int shift;
4929 int pass;
4930 int count;
4931 int pairwise;
4932 int u;
4933 uint32_t imm, mask;
4934 TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
4935 TCGv_i64 tmp64;
4936
4937 if (!s->vfp_enabled)
4938 return 1;
4939 q = (insn & (1 << 6)) != 0;
4940 u = (insn >> 24) & 1;
4941 VFP_DREG_D(rd, insn);
4942 VFP_DREG_N(rn, insn);
4943 VFP_DREG_M(rm, insn);
4944 size = (insn >> 20) & 3;
4945 if ((insn & (1 << 23)) == 0) {
4946 /* Three register same length. */
4947 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4948 /* Catch invalid op and bad size combinations: UNDEF */
4949 if ((neon_3r_sizes[op] & (1 << size)) == 0) {
4950 return 1;
4951 }
4952 /* All insns of this form UNDEF for either this condition or the
4953 * superset of cases "Q==1"; we catch the latter later.
4954 */
4955 if (q && ((rd | rn | rm) & 1)) {
4956 return 1;
4957 }
4958 if (size == 3 && op != NEON_3R_LOGIC) {
4959 /* 64-bit element instructions. */
4960 for (pass = 0; pass < (q ? 2 : 1); pass++) {
4961 neon_load_reg64(cpu_V0, rn + pass);
4962 neon_load_reg64(cpu_V1, rm + pass);
4963 switch (op) {
4964 case NEON_3R_VQADD:
4965 if (u) {
4966 gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
4967 cpu_V0, cpu_V1);
4968 } else {
4969 gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
4970 cpu_V0, cpu_V1);
4971 }
4972 break;
4973 case NEON_3R_VQSUB:
4974 if (u) {
4975 gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
4976 cpu_V0, cpu_V1);
4977 } else {
4978 gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
4979 cpu_V0, cpu_V1);
4980 }
4981 break;
4982 case NEON_3R_VSHL:
4983 if (u) {
4984 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4985 } else {
4986 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4987 }
4988 break;
4989 case NEON_3R_VQSHL:
4990 if (u) {
4991 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4992 cpu_V1, cpu_V0);
4993 } else {
4994 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4995 cpu_V1, cpu_V0);
4996 }
4997 break;
4998 case NEON_3R_VRSHL:
4999 if (u) {
5000 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
5001 } else {
5002 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
5003 }
5004 break;
5005 case NEON_3R_VQRSHL:
5006 if (u) {
5007 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
5008 cpu_V1, cpu_V0);
5009 } else {
5010 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
5011 cpu_V1, cpu_V0);
5012 }
5013 break;
5014 case NEON_3R_VADD_VSUB:
5015 if (u) {
5016 tcg_gen_sub_i64(CPU_V001);
5017 } else {
5018 tcg_gen_add_i64(CPU_V001);
5019 }
5020 break;
5021 default:
5022 abort();
5023 }
5024 neon_store_reg64(cpu_V0, rd + pass);
5025 }
5026 return 0;
5027 }
5028 pairwise = 0;
5029 switch (op) {
5030 case NEON_3R_VSHL:
5031 case NEON_3R_VQSHL:
5032 case NEON_3R_VRSHL:
5033 case NEON_3R_VQRSHL:
5034 {
5035 int rtmp;
5036 /* Shift instruction operands are reversed. */
5037 rtmp = rn;
5038 rn = rm;
5039 rm = rtmp;
5040 }
5041 break;
5042 case NEON_3R_VPADD:
5043 if (u) {
5044 return 1;
5045 }
5046 /* Fall through */
5047 case NEON_3R_VPMAX:
5048 case NEON_3R_VPMIN:
5049 pairwise = 1;
5050 break;
5051 case NEON_3R_FLOAT_ARITH:
5052 pairwise = (u && size < 2); /* if VPADD (float) */
5053 break;
5054 case NEON_3R_FLOAT_MINMAX:
5055 pairwise = u; /* if VPMIN/VPMAX (float) */
5056 break;
5057 case NEON_3R_FLOAT_CMP:
5058 if (!u && size) {
5059 /* no encoding for U=0 C=1x */
5060 return 1;
5061 }
5062 break;
5063 case NEON_3R_FLOAT_ACMP:
5064 if (!u) {
5065 return 1;
5066 }
5067 break;
5068 case NEON_3R_FLOAT_MISC:
5069 /* VMAXNM/VMINNM in ARMv8 */
5070 if (u && !arm_feature(env, ARM_FEATURE_V8)) {
5071 return 1;
5072 }
5073 break;
5074 case NEON_3R_VMUL:
5075 if (u && (size != 0)) {
5076 /* UNDEF on invalid size for polynomial subcase */
5077 return 1;
5078 }
5079 break;
5080 case NEON_3R_VFM:
5081 if (!arm_feature(env, ARM_FEATURE_VFP4) || u) {
5082 return 1;
5083 }
5084 break;
5085 default:
5086 break;
5087 }
5088
5089 if (pairwise && q) {
5090 /* All the pairwise insns UNDEF if Q is set */
5091 return 1;
5092 }
5093
5094 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5095
5096 if (pairwise) {
5097 /* Pairwise. */
5098 if (pass < 1) {
5099 tmp = neon_load_reg(rn, 0);
5100 tmp2 = neon_load_reg(rn, 1);
5101 } else {
5102 tmp = neon_load_reg(rm, 0);
5103 tmp2 = neon_load_reg(rm, 1);
5104 }
5105 } else {
5106 /* Elementwise. */
5107 tmp = neon_load_reg(rn, pass);
5108 tmp2 = neon_load_reg(rm, pass);
5109 }
5110 switch (op) {
5111 case NEON_3R_VHADD:
5112 GEN_NEON_INTEGER_OP(hadd);
5113 break;
5114 case NEON_3R_VQADD:
5115 GEN_NEON_INTEGER_OP_ENV(qadd);
5116 break;
5117 case NEON_3R_VRHADD:
5118 GEN_NEON_INTEGER_OP(rhadd);
5119 break;
5120 case NEON_3R_LOGIC: /* Logic ops. */
5121 switch ((u << 2) | size) {
5122 case 0: /* VAND */
5123 tcg_gen_and_i32(tmp, tmp, tmp2);
5124 break;
5125 case 1: /* BIC */
5126 tcg_gen_andc_i32(tmp, tmp, tmp2);
5127 break;
5128 case 2: /* VORR */
5129 tcg_gen_or_i32(tmp, tmp, tmp2);
5130 break;
5131 case 3: /* VORN */
5132 tcg_gen_orc_i32(tmp, tmp, tmp2);
5133 break;
5134 case 4: /* VEOR */
5135 tcg_gen_xor_i32(tmp, tmp, tmp2);
5136 break;
5137 case 5: /* VBSL */
5138 tmp3 = neon_load_reg(rd, pass);
5139 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
5140 tcg_temp_free_i32(tmp3);
5141 break;
5142 case 6: /* VBIT */
5143 tmp3 = neon_load_reg(rd, pass);
5144 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
5145 tcg_temp_free_i32(tmp3);
5146 break;
5147 case 7: /* VBIF */
5148 tmp3 = neon_load_reg(rd, pass);
5149 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
5150 tcg_temp_free_i32(tmp3);
5151 break;
5152 }
5153 break;
5154 case NEON_3R_VHSUB:
5155 GEN_NEON_INTEGER_OP(hsub);
5156 break;
5157 case NEON_3R_VQSUB:
5158 GEN_NEON_INTEGER_OP_ENV(qsub);
5159 break;
5160 case NEON_3R_VCGT:
5161 GEN_NEON_INTEGER_OP(cgt);
5162 break;
5163 case NEON_3R_VCGE:
5164 GEN_NEON_INTEGER_OP(cge);
5165 break;
5166 case NEON_3R_VSHL:
5167 GEN_NEON_INTEGER_OP(shl);
5168 break;
5169 case NEON_3R_VQSHL:
5170 GEN_NEON_INTEGER_OP_ENV(qshl);
5171 break;
5172 case NEON_3R_VRSHL:
5173 GEN_NEON_INTEGER_OP(rshl);
5174 break;
5175 case NEON_3R_VQRSHL:
5176 GEN_NEON_INTEGER_OP_ENV(qrshl);
5177 break;
5178 case NEON_3R_VMAX:
5179 GEN_NEON_INTEGER_OP(max);
5180 break;
5181 case NEON_3R_VMIN:
5182 GEN_NEON_INTEGER_OP(min);
5183 break;
5184 case NEON_3R_VABD:
5185 GEN_NEON_INTEGER_OP(abd);
5186 break;
5187 case NEON_3R_VABA:
5188 GEN_NEON_INTEGER_OP(abd);
5189 tcg_temp_free_i32(tmp2);
5190 tmp2 = neon_load_reg(rd, pass);
5191 gen_neon_add(size, tmp, tmp2);
5192 break;
5193 case NEON_3R_VADD_VSUB:
5194 if (!u) { /* VADD */
5195 gen_neon_add(size, tmp, tmp2);
5196 } else { /* VSUB */
5197 switch (size) {
5198 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
5199 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
5200 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
5201 default: abort();
5202 }
5203 }
5204 break;
5205 case NEON_3R_VTST_VCEQ:
5206 if (!u) { /* VTST */
5207 switch (size) {
5208 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
5209 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
5210 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
5211 default: abort();
5212 }
5213 } else { /* VCEQ */
5214 switch (size) {
5215 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5216 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5217 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
5218 default: abort();
5219 }
5220 }
5221 break;
5222 case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */
5223 switch (size) {
5224 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5225 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5226 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5227 default: abort();
5228 }
5229 tcg_temp_free_i32(tmp2);
5230 tmp2 = neon_load_reg(rd, pass);
5231 if (u) { /* VMLS */
5232 gen_neon_rsb(size, tmp, tmp2);
5233 } else { /* VMLA */
5234 gen_neon_add(size, tmp, tmp2);
5235 }
5236 break;
5237 case NEON_3R_VMUL:
5238 if (u) { /* polynomial */
5239 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
5240 } else { /* Integer */
5241 switch (size) {
5242 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5243 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5244 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5245 default: abort();
5246 }
5247 }
5248 break;
5249 case NEON_3R_VPMAX:
5250 GEN_NEON_INTEGER_OP(pmax);
5251 break;
5252 case NEON_3R_VPMIN:
5253 GEN_NEON_INTEGER_OP(pmin);
5254 break;
5255 case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
5256 if (!u) { /* VQDMULH */
5257 switch (size) {
5258 case 1:
5259 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
5260 break;
5261 case 2:
5262 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
5263 break;
5264 default: abort();
5265 }
5266 } else { /* VQRDMULH */
5267 switch (size) {
5268 case 1:
5269 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
5270 break;
5271 case 2:
5272 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
5273 break;
5274 default: abort();
5275 }
5276 }
5277 break;
5278 case NEON_3R_VPADD:
5279 switch (size) {
5280 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
5281 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
5282 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
5283 default: abort();
5284 }
5285 break;
5286 case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
5287 {
5288 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5289 switch ((u << 2) | size) {
5290 case 0: /* VADD */
5291 case 4: /* VPADD */
5292 gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
5293 break;
5294 case 2: /* VSUB */
5295 gen_helper_vfp_subs(tmp, tmp, tmp2, fpstatus);
5296 break;
5297 case 6: /* VABD */
5298 gen_helper_neon_abd_f32(tmp, tmp, tmp2, fpstatus);
5299 break;
5300 default:
5301 abort();
5302 }
5303 tcg_temp_free_ptr(fpstatus);
5304 break;
5305 }
5306 case NEON_3R_FLOAT_MULTIPLY:
5307 {
5308 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5309 gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus);
5310 if (!u) {
5311 tcg_temp_free_i32(tmp2);
5312 tmp2 = neon_load_reg(rd, pass);
5313 if (size == 0) {
5314 gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
5315 } else {
5316 gen_helper_vfp_subs(tmp, tmp2, tmp, fpstatus);
5317 }
5318 }
5319 tcg_temp_free_ptr(fpstatus);
5320 break;
5321 }
5322 case NEON_3R_FLOAT_CMP:
5323 {
5324 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5325 if (!u) {
5326 gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus);
5327 } else {
5328 if (size == 0) {
5329 gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus);
5330 } else {
5331 gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus);
5332 }
5333 }
5334 tcg_temp_free_ptr(fpstatus);
5335 break;
5336 }
5337 case NEON_3R_FLOAT_ACMP:
5338 {
5339 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5340 if (size == 0) {
5341 gen_helper_neon_acge_f32(tmp, tmp, tmp2, fpstatus);
5342 } else {
5343 gen_helper_neon_acgt_f32(tmp, tmp, tmp2, fpstatus);
5344 }
5345 tcg_temp_free_ptr(fpstatus);
5346 break;
5347 }
5348 case NEON_3R_FLOAT_MINMAX:
5349 {
5350 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5351 if (size == 0) {
5352 gen_helper_vfp_maxs(tmp, tmp, tmp2, fpstatus);
5353 } else {
5354 gen_helper_vfp_mins(tmp, tmp, tmp2, fpstatus);
5355 }
5356 tcg_temp_free_ptr(fpstatus);
5357 break;
5358 }
5359 case NEON_3R_FLOAT_MISC:
5360 if (u) {
5361 /* VMAXNM/VMINNM */
5362 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5363 if (size == 0) {
5364 gen_helper_vfp_maxnums(tmp, tmp, tmp2, fpstatus);
5365 } else {
5366 gen_helper_vfp_minnums(tmp, tmp, tmp2, fpstatus);
5367 }
5368 tcg_temp_free_ptr(fpstatus);
5369 } else {
5370 if (size == 0) {
5371 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
5372 } else {
5373 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
5374 }
5375 }
5376 break;
5377 case NEON_3R_VFM:
5378 {
5379 /* VFMA, VFMS: fused multiply-add */
5380 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
5381 TCGv_i32 tmp3 = neon_load_reg(rd, pass);
5382 if (size) {
5383 /* VFMS */
5384 gen_helper_vfp_negs(tmp, tmp);
5385 }
5386 gen_helper_vfp_muladds(tmp, tmp, tmp2, tmp3, fpstatus);
5387 tcg_temp_free_i32(tmp3);
5388 tcg_temp_free_ptr(fpstatus);
5389 break;
5390 }
5391 default:
5392 abort();
5393 }
5394 tcg_temp_free_i32(tmp2);
5395
5396 /* Save the result. For elementwise operations we can put it
5397 straight into the destination register. For pairwise operations
5398 we have to be careful to avoid clobbering the source operands. */
5399 if (pairwise && rd == rm) {
5400 neon_store_scratch(pass, tmp);
5401 } else {
5402 neon_store_reg(rd, pass, tmp);
5403 }
5404
5405 } /* for pass */
5406 if (pairwise && rd == rm) {
5407 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5408 tmp = neon_load_scratch(pass);
5409 neon_store_reg(rd, pass, tmp);
5410 }
5411 }
5412 /* End of 3 register same size operations. */
5413 } else if (insn & (1 << 4)) {
5414 if ((insn & 0x00380080) != 0) {
5415 /* Two registers and shift. */
5416 op = (insn >> 8) & 0xf;
5417 if (insn & (1 << 7)) {
5418 /* 64-bit shift. */
5419 if (op > 7) {
5420 return 1;
5421 }
5422 size = 3;
5423 } else {
5424 size = 2;
5425 while ((insn & (1 << (size + 19))) == 0)
5426 size--;
5427 }
5428 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
5429 /* To avoid excessive duplication of ops we implement shift
5430 by immediate using the variable shift operations. */
5431 if (op < 8) {
5432 /* Shift by immediate:
5433 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
5434 if (q && ((rd | rm) & 1)) {
5435 return 1;
5436 }
5437 if (!u && (op == 4 || op == 6)) {
5438 return 1;
5439 }
5440 /* Right shifts are encoded as N - shift, where N is the
5441 element size in bits. */
5442 if (op <= 4)
5443 shift = shift - (1 << (size + 3));
5444 if (size == 3) {
5445 count = q + 1;
5446 } else {
5447 count = q ? 4: 2;
5448 }
5449 switch (size) {
5450 case 0:
5451 imm = (uint8_t) shift;
5452 imm |= imm << 8;
5453 imm |= imm << 16;
5454 break;
5455 case 1:
5456 imm = (uint16_t) shift;
5457 imm |= imm << 16;
5458 break;
5459 case 2:
5460 case 3:
5461 imm = shift;
5462 break;
5463 default:
5464 abort();
5465 }
5466
5467 for (pass = 0; pass < count; pass++) {
5468 if (size == 3) {
5469 neon_load_reg64(cpu_V0, rm + pass);
5470 tcg_gen_movi_i64(cpu_V1, imm);
5471 switch (op) {
5472 case 0: /* VSHR */
5473 case 1: /* VSRA */
5474 if (u)
5475 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
5476 else
5477 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
5478 break;
5479 case 2: /* VRSHR */
5480 case 3: /* VRSRA */
5481 if (u)
5482 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
5483 else
5484 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
5485 break;
5486 case 4: /* VSRI */
5487 case 5: /* VSHL, VSLI */
5488 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
5489 break;
5490 case 6: /* VQSHLU */
5491 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
5492 cpu_V0, cpu_V1);
5493 break;
5494 case 7: /* VQSHL */
5495 if (u) {
5496 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
5497 cpu_V0, cpu_V1);
5498 } else {
5499 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
5500 cpu_V0, cpu_V1);
5501 }
5502 break;
5503 }
5504 if (op == 1 || op == 3) {
5505 /* Accumulate. */
5506 neon_load_reg64(cpu_V1, rd + pass);
5507 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
5508 } else if (op == 4 || (op == 5 && u)) {
5509 /* Insert */
5510 neon_load_reg64(cpu_V1, rd + pass);
5511 uint64_t mask;
5512 if (shift < -63 || shift > 63) {
5513 mask = 0;
5514 } else {
5515 if (op == 4) {
5516 mask = 0xffffffffffffffffull >> -shift;
5517 } else {
5518 mask = 0xffffffffffffffffull << shift;
5519 }
5520 }
5521 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
5522 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5523 }
5524 neon_store_reg64(cpu_V0, rd + pass);
5525 } else { /* size < 3 */
5526 /* Operands in T0 and T1. */
5527 tmp = neon_load_reg(rm, pass);
5528 tmp2 = tcg_temp_new_i32();
5529 tcg_gen_movi_i32(tmp2, imm);
5530 switch (op) {
5531 case 0: /* VSHR */
5532 case 1: /* VSRA */
5533 GEN_NEON_INTEGER_OP(shl);
5534 break;
5535 case 2: /* VRSHR */
5536 case 3: /* VRSRA */
5537 GEN_NEON_INTEGER_OP(rshl);
5538 break;
5539 case 4: /* VSRI */
5540 case 5: /* VSHL, VSLI */
5541 switch (size) {
5542 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
5543 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
5544 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
5545 default: abort();
5546 }
5547 break;
5548 case 6: /* VQSHLU */
5549 switch (size) {
5550 case 0:
5551 gen_helper_neon_qshlu_s8(tmp, cpu_env,
5552 tmp, tmp2);
5553 break;
5554 case 1:
5555 gen_helper_neon_qshlu_s16(tmp, cpu_env,
5556 tmp, tmp2);
5557 break;
5558 case 2:
5559 gen_helper_neon_qshlu_s32(tmp, cpu_env,
5560 tmp, tmp2);
5561 break;
5562 default:
5563 abort();
5564 }
5565 break;
5566 case 7: /* VQSHL */
5567 GEN_NEON_INTEGER_OP_ENV(qshl);
5568 break;
5569 }
5570 tcg_temp_free_i32(tmp2);
5571
5572 if (op == 1 || op == 3) {
5573 /* Accumulate. */
5574 tmp2 = neon_load_reg(rd, pass);
5575 gen_neon_add(size, tmp, tmp2);
5576 tcg_temp_free_i32(tmp2);
5577 } else if (op == 4 || (op == 5 && u)) {
5578 /* Insert */
5579 switch (size) {
5580 case 0:
5581 if (op == 4)
5582 mask = 0xff >> -shift;
5583 else
5584 mask = (uint8_t)(0xff << shift);
5585 mask |= mask << 8;
5586 mask |= mask << 16;
5587 break;
5588 case 1:
5589 if (op == 4)
5590 mask = 0xffff >> -shift;
5591 else
5592 mask = (uint16_t)(0xffff << shift);
5593 mask |= mask << 16;
5594 break;
5595 case 2:
5596 if (shift < -31 || shift > 31) {
5597 mask = 0;
5598 } else {
5599 if (op == 4)
5600 mask = 0xffffffffu >> -shift;
5601 else
5602 mask = 0xffffffffu << shift;
5603 }
5604 break;
5605 default:
5606 abort();
5607 }
5608 tmp2 = neon_load_reg(rd, pass);
5609 tcg_gen_andi_i32(tmp, tmp, mask);
5610 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
5611 tcg_gen_or_i32(tmp, tmp, tmp2);
5612 tcg_temp_free_i32(tmp2);
5613 }
5614 neon_store_reg(rd, pass, tmp);
5615 }
5616 } /* for pass */
5617 } else if (op < 10) {
5618 /* Shift by immediate and narrow:
5619 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
5620 int input_unsigned = (op == 8) ? !u : u;
5621 if (rm & 1) {
5622 return 1;
5623 }
5624 shift = shift - (1 << (size + 3));
5625 size++;
5626 if (size == 3) {
5627 tmp64 = tcg_const_i64(shift);
5628 neon_load_reg64(cpu_V0, rm);
5629 neon_load_reg64(cpu_V1, rm + 1);
5630 for (pass = 0; pass < 2; pass++) {
5631 TCGv_i64 in;
5632 if (pass == 0) {
5633 in = cpu_V0;
5634 } else {
5635 in = cpu_V1;
5636 }
5637 if (q) {
5638 if (input_unsigned) {
5639 gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
5640 } else {
5641 gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
5642 }
5643 } else {
5644 if (input_unsigned) {
5645 gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
5646 } else {
5647 gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
5648 }
5649 }
5650 tmp = tcg_temp_new_i32();
5651 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5652 neon_store_reg(rd, pass, tmp);
5653 } /* for pass */
5654 tcg_temp_free_i64(tmp64);
5655 } else {
5656 if (size == 1) {
5657 imm = (uint16_t)shift;
5658 imm |= imm << 16;
5659 } else {
5660 /* size == 2 */
5661 imm = (uint32_t)shift;
5662 }
5663 tmp2 = tcg_const_i32(imm);
5664 tmp4 = neon_load_reg(rm + 1, 0);
5665 tmp5 = neon_load_reg(rm + 1, 1);
5666 for (pass = 0; pass < 2; pass++) {
5667 if (pass == 0) {
5668 tmp = neon_load_reg(rm, 0);
5669 } else {
5670 tmp = tmp4;
5671 }
5672 gen_neon_shift_narrow(size, tmp, tmp2, q,
5673 input_unsigned);
5674 if (pass == 0) {
5675 tmp3 = neon_load_reg(rm, 1);
5676 } else {
5677 tmp3 = tmp5;
5678 }
5679 gen_neon_shift_narrow(size, tmp3, tmp2, q,
5680 input_unsigned);
5681 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
5682 tcg_temp_free_i32(tmp);
5683 tcg_temp_free_i32(tmp3);
5684 tmp = tcg_temp_new_i32();
5685 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5686 neon_store_reg(rd, pass, tmp);
5687 } /* for pass */
5688 tcg_temp_free_i32(tmp2);
5689 }
5690 } else if (op == 10) {
5691 /* VSHLL, VMOVL */
5692 if (q || (rd & 1)) {
5693 return 1;
5694 }
5695 tmp = neon_load_reg(rm, 0);
5696 tmp2 = neon_load_reg(rm, 1);
5697 for (pass = 0; pass < 2; pass++) {
5698 if (pass == 1)
5699 tmp = tmp2;
5700
5701 gen_neon_widen(cpu_V0, tmp, size, u);
5702
5703 if (shift != 0) {
5704 /* The shift is less than the width of the source
5705 type, so we can just shift the whole register. */
5706 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
5707 /* Widen the result of shift: we need to clear
5708 * the potential overflow bits resulting from
5709 * left bits of the narrow input appearing as
5710 * right bits of left the neighbour narrow
5711 * input. */
5712 if (size < 2 || !u) {
5713 uint64_t imm64;
5714 if (size == 0) {
5715 imm = (0xffu >> (8 - shift));
5716 imm |= imm << 16;
5717 } else if (size == 1) {
5718 imm = 0xffff >> (16 - shift);
5719 } else {
5720 /* size == 2 */
5721 imm = 0xffffffff >> (32 - shift);
5722 }
5723 if (size < 2) {
5724 imm64 = imm | (((uint64_t)imm) << 32);
5725 } else {
5726 imm64 = imm;
5727 }
5728 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
5729 }
5730 }
5731 neon_store_reg64(cpu_V0, rd + pass);
5732 }
5733 } else if (op >= 14) {
5734 /* VCVT fixed-point. */
5735 if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
5736 return 1;
5737 }
5738 /* We have already masked out the must-be-1 top bit of imm6,
5739 * hence this 32-shift where the ARM ARM has 64-imm6.
5740 */
5741 shift = 32 - shift;
5742 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5743 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
5744 if (!(op & 1)) {
5745 if (u)
5746 gen_vfp_ulto(0, shift, 1);
5747 else
5748 gen_vfp_slto(0, shift, 1);
5749 } else {
5750 if (u)
5751 gen_vfp_toul(0, shift, 1);
5752 else
5753 gen_vfp_tosl(0, shift, 1);
5754 }
5755 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
5756 }
5757 } else {
5758 return 1;
5759 }
5760 } else { /* (insn & 0x00380080) == 0 */
5761 int invert;
5762 if (q && (rd & 1)) {
5763 return 1;
5764 }
5765
5766 op = (insn >> 8) & 0xf;
5767 /* One register and immediate. */
5768 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
5769 invert = (insn & (1 << 5)) != 0;
5770 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
5771 * We choose to not special-case this and will behave as if a
5772 * valid constant encoding of 0 had been given.
5773 */
5774 switch (op) {
5775 case 0: case 1:
5776 /* no-op */
5777 break;
5778 case 2: case 3:
5779 imm <<= 8;
5780 break;
5781 case 4: case 5:
5782 imm <<= 16;
5783 break;
5784 case 6: case 7:
5785 imm <<= 24;
5786 break;
5787 case 8: case 9:
5788 imm |= imm << 16;
5789 break;
5790 case 10: case 11:
5791 imm = (imm << 8) | (imm << 24);
5792 break;
5793 case 12:
5794 imm = (imm << 8) | 0xff;
5795 break;
5796 case 13:
5797 imm = (imm << 16) | 0xffff;
5798 break;
5799 case 14:
5800 imm |= (imm << 8) | (imm << 16) | (imm << 24);
5801 if (invert)
5802 imm = ~imm;
5803 break;
5804 case 15:
5805 if (invert) {
5806 return 1;
5807 }
5808 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
5809 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
5810 break;
5811 }
5812 if (invert)
5813 imm = ~imm;
5814
5815 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5816 if (op & 1 && op < 12) {
5817 tmp = neon_load_reg(rd, pass);
5818 if (invert) {
5819 /* The immediate value has already been inverted, so
5820 BIC becomes AND. */
5821 tcg_gen_andi_i32(tmp, tmp, imm);
5822 } else {
5823 tcg_gen_ori_i32(tmp, tmp, imm);
5824 }
5825 } else {
5826 /* VMOV, VMVN. */
5827 tmp = tcg_temp_new_i32();
5828 if (op == 14 && invert) {
5829 int n;
5830 uint32_t val;
5831 val = 0;
5832 for (n = 0; n < 4; n++) {
5833 if (imm & (1 << (n + (pass & 1) * 4)))
5834 val |= 0xff << (n * 8);
5835 }
5836 tcg_gen_movi_i32(tmp, val);
5837 } else {
5838 tcg_gen_movi_i32(tmp, imm);
5839 }
5840 }
5841 neon_store_reg(rd, pass, tmp);
5842 }
5843 }
5844 } else { /* (insn & 0x00800010 == 0x00800000) */
5845 if (size != 3) {
5846 op = (insn >> 8) & 0xf;
5847 if ((insn & (1 << 6)) == 0) {
5848 /* Three registers of different lengths. */
5849 int src1_wide;
5850 int src2_wide;
5851 int prewiden;
5852 /* undefreq: bit 0 : UNDEF if size != 0
5853 * bit 1 : UNDEF if size == 0
5854 * bit 2 : UNDEF if U == 1
5855 * Note that [1:0] set implies 'always UNDEF'
5856 */
5857 int undefreq;
5858 /* prewiden, src1_wide, src2_wide, undefreq */
5859 static const int neon_3reg_wide[16][4] = {
5860 {1, 0, 0, 0}, /* VADDL */
5861 {1, 1, 0, 0}, /* VADDW */
5862 {1, 0, 0, 0}, /* VSUBL */
5863 {1, 1, 0, 0}, /* VSUBW */
5864 {0, 1, 1, 0}, /* VADDHN */
5865 {0, 0, 0, 0}, /* VABAL */
5866 {0, 1, 1, 0}, /* VSUBHN */
5867 {0, 0, 0, 0}, /* VABDL */
5868 {0, 0, 0, 0}, /* VMLAL */
5869 {0, 0, 0, 6}, /* VQDMLAL */
5870 {0, 0, 0, 0}, /* VMLSL */
5871 {0, 0, 0, 6}, /* VQDMLSL */
5872 {0, 0, 0, 0}, /* Integer VMULL */
5873 {0, 0, 0, 2}, /* VQDMULL */
5874 {0, 0, 0, 5}, /* Polynomial VMULL */
5875 {0, 0, 0, 3}, /* Reserved: always UNDEF */
5876 };
5877
5878 prewiden = neon_3reg_wide[op][0];
5879 src1_wide = neon_3reg_wide[op][1];
5880 src2_wide = neon_3reg_wide[op][2];
5881 undefreq = neon_3reg_wide[op][3];
5882
5883 if (((undefreq & 1) && (size != 0)) ||
5884 ((undefreq & 2) && (size == 0)) ||
5885 ((undefreq & 4) && u)) {
5886 return 1;
5887 }
5888 if ((src1_wide && (rn & 1)) ||
5889 (src2_wide && (rm & 1)) ||
5890 (!src2_wide && (rd & 1))) {
5891 return 1;
5892 }
5893
5894 /* Avoid overlapping operands. Wide source operands are
5895 always aligned so will never overlap with wide
5896 destinations in problematic ways. */
5897 if (rd == rm && !src2_wide) {
5898 tmp = neon_load_reg(rm, 1);
5899 neon_store_scratch(2, tmp);
5900 } else if (rd == rn && !src1_wide) {
5901 tmp = neon_load_reg(rn, 1);
5902 neon_store_scratch(2, tmp);
5903 }
5904 TCGV_UNUSED_I32(tmp3);
5905 for (pass = 0; pass < 2; pass++) {
5906 if (src1_wide) {
5907 neon_load_reg64(cpu_V0, rn + pass);
5908 TCGV_UNUSED_I32(tmp);
5909 } else {
5910 if (pass == 1 && rd == rn) {
5911 tmp = neon_load_scratch(2);
5912 } else {
5913 tmp = neon_load_reg(rn, pass);
5914 }
5915 if (prewiden) {
5916 gen_neon_widen(cpu_V0, tmp, size, u);
5917 }
5918 }
5919 if (src2_wide) {
5920 neon_load_reg64(cpu_V1, rm + pass);
5921 TCGV_UNUSED_I32(tmp2);
5922 } else {
5923 if (pass == 1 && rd == rm) {
5924 tmp2 = neon_load_scratch(2);
5925 } else {
5926 tmp2 = neon_load_reg(rm, pass);
5927 }
5928 if (prewiden) {
5929 gen_neon_widen(cpu_V1, tmp2, size, u);
5930 }
5931 }
5932 switch (op) {
5933 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5934 gen_neon_addl(size);
5935 break;
5936 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5937 gen_neon_subl(size);
5938 break;
5939 case 5: case 7: /* VABAL, VABDL */
5940 switch ((size << 1) | u) {
5941 case 0:
5942 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5943 break;
5944 case 1:
5945 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5946 break;
5947 case 2:
5948 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5949 break;
5950 case 3:
5951 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5952 break;
5953 case 4:
5954 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5955 break;
5956 case 5:
5957 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5958 break;
5959 default: abort();
5960 }
5961 tcg_temp_free_i32(tmp2);
5962 tcg_temp_free_i32(tmp);
5963 break;
5964 case 8: case 9: case 10: case 11: case 12: case 13:
5965 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5966 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5967 break;
5968 case 14: /* Polynomial VMULL */
5969 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
5970 tcg_temp_free_i32(tmp2);
5971 tcg_temp_free_i32(tmp);
5972 break;
5973 default: /* 15 is RESERVED: caught earlier */
5974 abort();
5975 }
5976 if (op == 13) {
5977 /* VQDMULL */
5978 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5979 neon_store_reg64(cpu_V0, rd + pass);
5980 } else if (op == 5 || (op >= 8 && op <= 11)) {
5981 /* Accumulate. */
5982 neon_load_reg64(cpu_V1, rd + pass);
5983 switch (op) {
5984 case 10: /* VMLSL */
5985 gen_neon_negl(cpu_V0, size);
5986 /* Fall through */
5987 case 5: case 8: /* VABAL, VMLAL */
5988 gen_neon_addl(size);
5989 break;
5990 case 9: case 11: /* VQDMLAL, VQDMLSL */
5991 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5992 if (op == 11) {
5993 gen_neon_negl(cpu_V0, size);
5994 }
5995 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5996 break;
5997 default:
5998 abort();
5999 }
6000 neon_store_reg64(cpu_V0, rd + pass);
6001 } else if (op == 4 || op == 6) {
6002 /* Narrowing operation. */
6003 tmp = tcg_temp_new_i32();
6004 if (!u) {
6005 switch (size) {
6006 case 0:
6007 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
6008 break;
6009 case 1:
6010 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
6011 break;
6012 case 2:
6013 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
6014 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
6015 break;
6016 default: abort();
6017 }
6018 } else {
6019 switch (size) {
6020 case 0:
6021 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
6022 break;
6023 case 1:
6024 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
6025 break;
6026 case 2:
6027 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
6028 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
6029 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
6030 break;
6031 default: abort();
6032 }
6033 }
6034 if (pass == 0) {
6035 tmp3 = tmp;
6036 } else {
6037 neon_store_reg(rd, 0, tmp3);
6038 neon_store_reg(rd, 1, tmp);
6039 }
6040 } else {
6041 /* Write back the result. */
6042 neon_store_reg64(cpu_V0, rd + pass);
6043 }
6044 }
6045 } else {
6046 /* Two registers and a scalar. NB that for ops of this form
6047 * the ARM ARM labels bit 24 as Q, but it is in our variable
6048 * 'u', not 'q'.
6049 */
6050 if (size == 0) {
6051 return 1;
6052 }
6053 switch (op) {
6054 case 1: /* Float VMLA scalar */
6055 case 5: /* Floating point VMLS scalar */
6056 case 9: /* Floating point VMUL scalar */
6057 if (size == 1) {
6058 return 1;
6059 }
6060 /* fall through */
6061 case 0: /* Integer VMLA scalar */
6062 case 4: /* Integer VMLS scalar */
6063 case 8: /* Integer VMUL scalar */
6064 case 12: /* VQDMULH scalar */
6065 case 13: /* VQRDMULH scalar */
6066 if (u && ((rd | rn) & 1)) {
6067 return 1;
6068 }
6069 tmp = neon_get_scalar(size, rm);
6070 neon_store_scratch(0, tmp);
6071 for (pass = 0; pass < (u ? 4 : 2); pass++) {
6072 tmp = neon_load_scratch(0);
6073 tmp2 = neon_load_reg(rn, pass);
6074 if (op == 12) {
6075 if (size == 1) {
6076 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
6077 } else {
6078 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
6079 }
6080 } else if (op == 13) {
6081 if (size == 1) {
6082 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
6083 } else {
6084 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
6085 }
6086 } else if (op & 1) {
6087 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6088 gen_helper_vfp_muls(tmp, tmp, tmp2, fpstatus);
6089 tcg_temp_free_ptr(fpstatus);
6090 } else {
6091 switch (size) {
6092 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
6093 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
6094 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
6095 default: abort();
6096 }
6097 }
6098 tcg_temp_free_i32(tmp2);
6099 if (op < 8) {
6100 /* Accumulate. */
6101 tmp2 = neon_load_reg(rd, pass);
6102 switch (op) {
6103 case 0:
6104 gen_neon_add(size, tmp, tmp2);
6105 break;
6106 case 1:
6107 {
6108 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6109 gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
6110 tcg_temp_free_ptr(fpstatus);
6111 break;
6112 }
6113 case 4:
6114 gen_neon_rsb(size, tmp, tmp2);
6115 break;
6116 case 5:
6117 {
6118 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6119 gen_helper_vfp_subs(tmp, tmp2, tmp, fpstatus);
6120 tcg_temp_free_ptr(fpstatus);
6121 break;
6122 }
6123 default:
6124 abort();
6125 }
6126 tcg_temp_free_i32(tmp2);
6127 }
6128 neon_store_reg(rd, pass, tmp);
6129 }
6130 break;
6131 case 3: /* VQDMLAL scalar */
6132 case 7: /* VQDMLSL scalar */
6133 case 11: /* VQDMULL scalar */
6134 if (u == 1) {
6135 return 1;
6136 }
6137 /* fall through */
6138 case 2: /* VMLAL sclar */
6139 case 6: /* VMLSL scalar */
6140 case 10: /* VMULL scalar */
6141 if (rd & 1) {
6142 return 1;
6143 }
6144 tmp2 = neon_get_scalar(size, rm);
6145 /* We need a copy of tmp2 because gen_neon_mull
6146 * deletes it during pass 0. */
6147 tmp4 = tcg_temp_new_i32();
6148 tcg_gen_mov_i32(tmp4, tmp2);
6149 tmp3 = neon_load_reg(rn, 1);
6150
6151 for (pass = 0; pass < 2; pass++) {
6152 if (pass == 0) {
6153 tmp = neon_load_reg(rn, 0);
6154 } else {
6155 tmp = tmp3;
6156 tmp2 = tmp4;
6157 }
6158 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
6159 if (op != 11) {
6160 neon_load_reg64(cpu_V1, rd + pass);
6161 }
6162 switch (op) {
6163 case 6:
6164 gen_neon_negl(cpu_V0, size);
6165 /* Fall through */
6166 case 2:
6167 gen_neon_addl(size);
6168 break;
6169 case 3: case 7:
6170 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
6171 if (op == 7) {
6172 gen_neon_negl(cpu_V0, size);
6173 }
6174 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
6175 break;
6176 case 10:
6177 /* no-op */
6178 break;
6179 case 11:
6180 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
6181 break;
6182 default:
6183 abort();
6184 }
6185 neon_store_reg64(cpu_V0, rd + pass);
6186 }
6187
6188
6189 break;
6190 default: /* 14 and 15 are RESERVED */
6191 return 1;
6192 }
6193 }
6194 } else { /* size == 3 */
6195 if (!u) {
6196 /* Extract. */
6197 imm = (insn >> 8) & 0xf;
6198
6199 if (imm > 7 && !q)
6200 return 1;
6201
6202 if (q && ((rd | rn | rm) & 1)) {
6203 return 1;
6204 }
6205
6206 if (imm == 0) {
6207 neon_load_reg64(cpu_V0, rn);
6208 if (q) {
6209 neon_load_reg64(cpu_V1, rn + 1);
6210 }
6211 } else if (imm == 8) {
6212 neon_load_reg64(cpu_V0, rn + 1);
6213 if (q) {
6214 neon_load_reg64(cpu_V1, rm);
6215 }
6216 } else if (q) {
6217 tmp64 = tcg_temp_new_i64();
6218 if (imm < 8) {
6219 neon_load_reg64(cpu_V0, rn);
6220 neon_load_reg64(tmp64, rn + 1);
6221 } else {
6222 neon_load_reg64(cpu_V0, rn + 1);
6223 neon_load_reg64(tmp64, rm);
6224 }
6225 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
6226 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
6227 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
6228 if (imm < 8) {
6229 neon_load_reg64(cpu_V1, rm);
6230 } else {
6231 neon_load_reg64(cpu_V1, rm + 1);
6232 imm -= 8;
6233 }
6234 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
6235 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
6236 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
6237 tcg_temp_free_i64(tmp64);
6238 } else {
6239 /* BUGFIX */
6240 neon_load_reg64(cpu_V0, rn);
6241 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
6242 neon_load_reg64(cpu_V1, rm);
6243 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
6244 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
6245 }
6246 neon_store_reg64(cpu_V0, rd);
6247 if (q) {
6248 neon_store_reg64(cpu_V1, rd + 1);
6249 }
6250 } else if ((insn & (1 << 11)) == 0) {
6251 /* Two register misc. */
6252 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
6253 size = (insn >> 18) & 3;
6254 /* UNDEF for unknown op values and bad op-size combinations */
6255 if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
6256 return 1;
6257 }
6258 if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
6259 q && ((rm | rd) & 1)) {
6260 return 1;
6261 }
6262 switch (op) {
6263 case NEON_2RM_VREV64:
6264 for (pass = 0; pass < (q ? 2 : 1); pass++) {
6265 tmp = neon_load_reg(rm, pass * 2);
6266 tmp2 = neon_load_reg(rm, pass * 2 + 1);
6267 switch (size) {
6268 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
6269 case 1: gen_swap_half(tmp); break;
6270 case 2: /* no-op */ break;
6271 default: abort();
6272 }
6273 neon_store_reg(rd, pass * 2 + 1, tmp);
6274 if (size == 2) {
6275 neon_store_reg(rd, pass * 2, tmp2);
6276 } else {
6277 switch (size) {
6278 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
6279 case 1: gen_swap_half(tmp2); break;
6280 default: abort();
6281 }
6282 neon_store_reg(rd, pass * 2, tmp2);
6283 }
6284 }
6285 break;
6286 case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
6287 case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
6288 for (pass = 0; pass < q + 1; pass++) {
6289 tmp = neon_load_reg(rm, pass * 2);
6290 gen_neon_widen(cpu_V0, tmp, size, op & 1);
6291 tmp = neon_load_reg(rm, pass * 2 + 1);
6292 gen_neon_widen(cpu_V1, tmp, size, op & 1);
6293 switch (size) {
6294 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
6295 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
6296 case 2: tcg_gen_add_i64(CPU_V001); break;
6297 default: abort();
6298 }
6299 if (op >= NEON_2RM_VPADAL) {
6300 /* Accumulate. */
6301 neon_load_reg64(cpu_V1, rd + pass);
6302 gen_neon_addl(size);
6303 }
6304 neon_store_reg64(cpu_V0, rd + pass);
6305 }
6306 break;
6307 case NEON_2RM_VTRN:
6308 if (size == 2) {
6309 int n;
6310 for (n = 0; n < (q ? 4 : 2); n += 2) {
6311 tmp = neon_load_reg(rm, n);
6312 tmp2 = neon_load_reg(rd, n + 1);
6313 neon_store_reg(rm, n, tmp2);
6314 neon_store_reg(rd, n + 1, tmp);
6315 }
6316 } else {
6317 goto elementwise;
6318 }
6319 break;
6320 case NEON_2RM_VUZP:
6321 if (gen_neon_unzip(rd, rm, size, q)) {
6322 return 1;
6323 }
6324 break;
6325 case NEON_2RM_VZIP:
6326 if (gen_neon_zip(rd, rm, size, q)) {
6327 return 1;
6328 }
6329 break;
6330 case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
6331 /* also VQMOVUN; op field and mnemonics don't line up */
6332 if (rm & 1) {
6333 return 1;
6334 }
6335 TCGV_UNUSED_I32(tmp2);
6336 for (pass = 0; pass < 2; pass++) {
6337 neon_load_reg64(cpu_V0, rm + pass);
6338 tmp = tcg_temp_new_i32();
6339 gen_neon_narrow_op(op == NEON_2RM_VMOVN, q, size,
6340 tmp, cpu_V0);
6341 if (pass == 0) {
6342 tmp2 = tmp;
6343 } else {
6344 neon_store_reg(rd, 0, tmp2);
6345 neon_store_reg(rd, 1, tmp);
6346 }
6347 }
6348 break;
6349 case NEON_2RM_VSHLL:
6350 if (q || (rd & 1)) {
6351 return 1;
6352 }
6353 tmp = neon_load_reg(rm, 0);
6354 tmp2 = neon_load_reg(rm, 1);
6355 for (pass = 0; pass < 2; pass++) {
6356 if (pass == 1)
6357 tmp = tmp2;
6358 gen_neon_widen(cpu_V0, tmp, size, 1);
6359 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
6360 neon_store_reg64(cpu_V0, rd + pass);
6361 }
6362 break;
6363 case NEON_2RM_VCVT_F16_F32:
6364 if (!arm_feature(env, ARM_FEATURE_VFP_FP16) ||
6365 q || (rm & 1)) {
6366 return 1;
6367 }
6368 tmp = tcg_temp_new_i32();
6369 tmp2 = tcg_temp_new_i32();
6370 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
6371 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
6372 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
6373 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
6374 tcg_gen_shli_i32(tmp2, tmp2, 16);
6375 tcg_gen_or_i32(tmp2, tmp2, tmp);
6376 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
6377 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
6378 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
6379 neon_store_reg(rd, 0, tmp2);
6380 tmp2 = tcg_temp_new_i32();
6381 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
6382 tcg_gen_shli_i32(tmp2, tmp2, 16);
6383 tcg_gen_or_i32(tmp2, tmp2, tmp);
6384 neon_store_reg(rd, 1, tmp2);
6385 tcg_temp_free_i32(tmp);
6386 break;
6387 case NEON_2RM_VCVT_F32_F16:
6388 if (!arm_feature(env, ARM_FEATURE_VFP_FP16) ||
6389 q || (rd & 1)) {
6390 return 1;
6391 }
6392 tmp3 = tcg_temp_new_i32();
6393 tmp = neon_load_reg(rm, 0);
6394 tmp2 = neon_load_reg(rm, 1);
6395 tcg_gen_ext16u_i32(tmp3, tmp);
6396 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
6397 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
6398 tcg_gen_shri_i32(tmp3, tmp, 16);
6399 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
6400 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
6401 tcg_temp_free_i32(tmp);
6402 tcg_gen_ext16u_i32(tmp3, tmp2);
6403 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
6404 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
6405 tcg_gen_shri_i32(tmp3, tmp2, 16);
6406 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
6407 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
6408 tcg_temp_free_i32(tmp2);
6409 tcg_temp_free_i32(tmp3);
6410 break;
6411 case NEON_2RM_AESE: case NEON_2RM_AESMC:
6412 if (!arm_feature(env, ARM_FEATURE_V8_AES)
6413 || ((rm | rd) & 1)) {
6414 return 1;
6415 }
6416 tmp = tcg_const_i32(rd);
6417 tmp2 = tcg_const_i32(rm);
6418
6419 /* Bit 6 is the lowest opcode bit; it distinguishes between
6420 * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
6421 */
6422 tmp3 = tcg_const_i32(extract32(insn, 6, 1));
6423
6424 if (op == NEON_2RM_AESE) {
6425 gen_helper_crypto_aese(cpu_env, tmp, tmp2, tmp3);
6426 } else {
6427 gen_helper_crypto_aesmc(cpu_env, tmp, tmp2, tmp3);
6428 }
6429 tcg_temp_free_i32(tmp);
6430 tcg_temp_free_i32(tmp2);
6431 tcg_temp_free_i32(tmp3);
6432 break;
6433 default:
6434 elementwise:
6435 for (pass = 0; pass < (q ? 4 : 2); pass++) {
6436 if (neon_2rm_is_float_op(op)) {
6437 tcg_gen_ld_f32(cpu_F0s, cpu_env,
6438 neon_reg_offset(rm, pass));
6439 TCGV_UNUSED_I32(tmp);
6440 } else {
6441 tmp = neon_load_reg(rm, pass);
6442 }
6443 switch (op) {
6444 case NEON_2RM_VREV32:
6445 switch (size) {
6446 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
6447 case 1: gen_swap_half(tmp); break;
6448 default: abort();
6449 }
6450 break;
6451 case NEON_2RM_VREV16:
6452 gen_rev16(tmp);
6453 break;
6454 case NEON_2RM_VCLS:
6455 switch (size) {
6456 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
6457 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
6458 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
6459 default: abort();
6460 }
6461 break;
6462 case NEON_2RM_VCLZ:
6463 switch (size) {
6464 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
6465 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
6466 case 2: gen_helper_clz(tmp, tmp); break;
6467 default: abort();
6468 }
6469 break;
6470 case NEON_2RM_VCNT:
6471 gen_helper_neon_cnt_u8(tmp, tmp);
6472 break;
6473 case NEON_2RM_VMVN:
6474 tcg_gen_not_i32(tmp, tmp);
6475 break;
6476 case NEON_2RM_VQABS:
6477 switch (size) {
6478 case 0:
6479 gen_helper_neon_qabs_s8(tmp, cpu_env, tmp);
6480 break;
6481 case 1:
6482 gen_helper_neon_qabs_s16(tmp, cpu_env, tmp);
6483 break;
6484 case 2:
6485 gen_helper_neon_qabs_s32(tmp, cpu_env, tmp);
6486 break;
6487 default: abort();
6488 }
6489 break;
6490 case NEON_2RM_VQNEG:
6491 switch (size) {
6492 case 0:
6493 gen_helper_neon_qneg_s8(tmp, cpu_env, tmp);
6494 break;
6495 case 1:
6496 gen_helper_neon_qneg_s16(tmp, cpu_env, tmp);
6497 break;
6498 case 2:
6499 gen_helper_neon_qneg_s32(tmp, cpu_env, tmp);
6500 break;
6501 default: abort();
6502 }
6503 break;
6504 case NEON_2RM_VCGT0: case NEON_2RM_VCLE0:
6505 tmp2 = tcg_const_i32(0);
6506 switch(size) {
6507 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
6508 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
6509 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
6510 default: abort();
6511 }
6512 tcg_temp_free_i32(tmp2);
6513 if (op == NEON_2RM_VCLE0) {
6514 tcg_gen_not_i32(tmp, tmp);
6515 }
6516 break;
6517 case NEON_2RM_VCGE0: case NEON_2RM_VCLT0:
6518 tmp2 = tcg_const_i32(0);
6519 switch(size) {
6520 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
6521 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
6522 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
6523 default: abort();
6524 }
6525 tcg_temp_free_i32(tmp2);
6526 if (op == NEON_2RM_VCLT0) {
6527 tcg_gen_not_i32(tmp, tmp);
6528 }
6529 break;
6530 case NEON_2RM_VCEQ0:
6531 tmp2 = tcg_const_i32(0);
6532 switch(size) {
6533 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
6534 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
6535 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
6536 default: abort();
6537 }
6538 tcg_temp_free_i32(tmp2);
6539 break;
6540 case NEON_2RM_VABS:
6541 switch(size) {
6542 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
6543 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
6544 case 2: tcg_gen_abs_i32(tmp, tmp); break;
6545 default: abort();
6546 }
6547 break;
6548 case NEON_2RM_VNEG:
6549 tmp2 = tcg_const_i32(0);
6550 gen_neon_rsb(size, tmp, tmp2);
6551 tcg_temp_free_i32(tmp2);
6552 break;
6553 case NEON_2RM_VCGT0_F:
6554 {
6555 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6556 tmp2 = tcg_const_i32(0);
6557 gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus);
6558 tcg_temp_free_i32(tmp2);
6559 tcg_temp_free_ptr(fpstatus);
6560 break;
6561 }
6562 case NEON_2RM_VCGE0_F:
6563 {
6564 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6565 tmp2 = tcg_const_i32(0);
6566 gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus);
6567 tcg_temp_free_i32(tmp2);
6568 tcg_temp_free_ptr(fpstatus);
6569 break;
6570 }
6571 case NEON_2RM_VCEQ0_F:
6572 {
6573 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6574 tmp2 = tcg_const_i32(0);
6575 gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus);
6576 tcg_temp_free_i32(tmp2);
6577 tcg_temp_free_ptr(fpstatus);
6578 break;
6579 }
6580 case NEON_2RM_VCLE0_F:
6581 {
6582 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6583 tmp2 = tcg_const_i32(0);
6584 gen_helper_neon_cge_f32(tmp, tmp2, tmp, fpstatus);
6585 tcg_temp_free_i32(tmp2);
6586 tcg_temp_free_ptr(fpstatus);
6587 break;
6588 }
6589 case NEON_2RM_VCLT0_F:
6590 {
6591 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6592 tmp2 = tcg_const_i32(0);
6593 gen_helper_neon_cgt_f32(tmp, tmp2, tmp, fpstatus);
6594 tcg_temp_free_i32(tmp2);
6595 tcg_temp_free_ptr(fpstatus);
6596 break;
6597 }
6598 case NEON_2RM_VABS_F:
6599 gen_vfp_abs(0);
6600 break;
6601 case NEON_2RM_VNEG_F:
6602 gen_vfp_neg(0);
6603 break;
6604 case NEON_2RM_VSWP:
6605 tmp2 = neon_load_reg(rd, pass);
6606 neon_store_reg(rm, pass, tmp2);
6607 break;
6608 case NEON_2RM_VTRN:
6609 tmp2 = neon_load_reg(rd, pass);
6610 switch (size) {
6611 case 0: gen_neon_trn_u8(tmp, tmp2); break;
6612 case 1: gen_neon_trn_u16(tmp, tmp2); break;
6613 default: abort();
6614 }
6615 neon_store_reg(rm, pass, tmp2);
6616 break;
6617 case NEON_2RM_VRINTN:
6618 case NEON_2RM_VRINTA:
6619 case NEON_2RM_VRINTM:
6620 case NEON_2RM_VRINTP:
6621 case NEON_2RM_VRINTZ:
6622 {
6623 TCGv_i32 tcg_rmode;
6624 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6625 int rmode;
6626
6627 if (op == NEON_2RM_VRINTZ) {
6628 rmode = FPROUNDING_ZERO;
6629 } else {
6630 rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
6631 }
6632
6633 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
6634 gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
6635 cpu_env);
6636 gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
6637 gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
6638 cpu_env);
6639 tcg_temp_free_ptr(fpstatus);
6640 tcg_temp_free_i32(tcg_rmode);
6641 break;
6642 }
6643 case NEON_2RM_VRINTX:
6644 {
6645 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6646 gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus);
6647 tcg_temp_free_ptr(fpstatus);
6648 break;
6649 }
6650 case NEON_2RM_VCVTAU:
6651 case NEON_2RM_VCVTAS:
6652 case NEON_2RM_VCVTNU:
6653 case NEON_2RM_VCVTNS:
6654 case NEON_2RM_VCVTPU:
6655 case NEON_2RM_VCVTPS:
6656 case NEON_2RM_VCVTMU:
6657 case NEON_2RM_VCVTMS:
6658 {
6659 bool is_signed = !extract32(insn, 7, 1);
6660 TCGv_ptr fpst = get_fpstatus_ptr(1);
6661 TCGv_i32 tcg_rmode, tcg_shift;
6662 int rmode = fp_decode_rm[extract32(insn, 8, 2)];
6663
6664 tcg_shift = tcg_const_i32(0);
6665 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
6666 gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
6667 cpu_env);
6668
6669 if (is_signed) {
6670 gen_helper_vfp_tosls(cpu_F0s, cpu_F0s,
6671 tcg_shift, fpst);
6672 } else {
6673 gen_helper_vfp_touls(cpu_F0s, cpu_F0s,
6674 tcg_shift, fpst);
6675 }
6676
6677 gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
6678 cpu_env);
6679 tcg_temp_free_i32(tcg_rmode);
6680 tcg_temp_free_i32(tcg_shift);
6681 tcg_temp_free_ptr(fpst);
6682 break;
6683 }
6684 case NEON_2RM_VRECPE:
6685 {
6686 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6687 gen_helper_recpe_u32(tmp, tmp, fpstatus);
6688 tcg_temp_free_ptr(fpstatus);
6689 break;
6690 }
6691 case NEON_2RM_VRSQRTE:
6692 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
6693 break;
6694 case NEON_2RM_VRECPE_F:
6695 {
6696 TCGv_ptr fpstatus = get_fpstatus_ptr(1);
6697 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, fpstatus);
6698 tcg_temp_free_ptr(fpstatus);
6699 break;
6700 }
6701 case NEON_2RM_VRSQRTE_F:
6702 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
6703 break;
6704 case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */
6705 gen_vfp_sito(0, 1);
6706 break;
6707 case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */
6708 gen_vfp_uito(0, 1);
6709 break;
6710 case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */
6711 gen_vfp_tosiz(0, 1);
6712 break;
6713 case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */
6714 gen_vfp_touiz(0, 1);
6715 break;
6716 default:
6717 /* Reserved op values were caught by the
6718 * neon_2rm_sizes[] check earlier.
6719 */
6720 abort();
6721 }
6722 if (neon_2rm_is_float_op(op)) {
6723 tcg_gen_st_f32(cpu_F0s, cpu_env,
6724 neon_reg_offset(rd, pass));
6725 } else {
6726 neon_store_reg(rd, pass, tmp);
6727 }
6728 }
6729 break;
6730 }
6731 } else if ((insn & (1 << 10)) == 0) {
6732 /* VTBL, VTBX. */
6733 int n = ((insn >> 8) & 3) + 1;
6734 if ((rn + n) > 32) {
6735 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
6736 * helper function running off the end of the register file.
6737 */
6738 return 1;
6739 }
6740 n <<= 3;
6741 if (insn & (1 << 6)) {
6742 tmp = neon_load_reg(rd, 0);
6743 } else {
6744 tmp = tcg_temp_new_i32();
6745 tcg_gen_movi_i32(tmp, 0);
6746 }
6747 tmp2 = neon_load_reg(rm, 0);
6748 tmp4 = tcg_const_i32(rn);
6749 tmp5 = tcg_const_i32(n);
6750 gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5);
6751 tcg_temp_free_i32(tmp);
6752 if (insn & (1 << 6)) {
6753 tmp = neon_load_reg(rd, 1);
6754 } else {
6755 tmp = tcg_temp_new_i32();
6756 tcg_gen_movi_i32(tmp, 0);
6757 }
6758 tmp3 = neon_load_reg(rm, 1);
6759 gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5);
6760 tcg_temp_free_i32(tmp5);
6761 tcg_temp_free_i32(tmp4);
6762 neon_store_reg(rd, 0, tmp2);
6763 neon_store_reg(rd, 1, tmp3);
6764 tcg_temp_free_i32(tmp);
6765 } else if ((insn & 0x380) == 0) {
6766 /* VDUP */
6767 if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) {
6768 return 1;
6769 }
6770 if (insn & (1 << 19)) {
6771 tmp = neon_load_reg(rm, 1);
6772 } else {
6773 tmp = neon_load_reg(rm, 0);
6774 }
6775 if (insn & (1 << 16)) {
6776 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
6777 } else if (insn & (1 << 17)) {
6778 if ((insn >> 18) & 1)
6779 gen_neon_dup_high16(tmp);
6780 else
6781 gen_neon_dup_low16(tmp);
6782 }
6783 for (pass = 0; pass < (q ? 4 : 2); pass++) {
6784 tmp2 = tcg_temp_new_i32();
6785 tcg_gen_mov_i32(tmp2, tmp);
6786 neon_store_reg(rd, pass, tmp2);
6787 }
6788 tcg_temp_free_i32(tmp);
6789 } else {
6790 return 1;
6791 }
6792 }
6793 }
6794 return 0;
6795 }
6796
6797 static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
6798 {
6799 int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
6800 const ARMCPRegInfo *ri;
6801
6802 cpnum = (insn >> 8) & 0xf;
6803 if (arm_feature(env, ARM_FEATURE_XSCALE)
6804 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
6805 return 1;
6806
6807 /* First check for coprocessor space used for actual instructions */
6808 switch (cpnum) {
6809 case 0:
6810 case 1:
6811 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6812 return disas_iwmmxt_insn(env, s, insn);
6813 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
6814 return disas_dsp_insn(env, s, insn);
6815 }
6816 return 1;
6817 default:
6818 break;
6819 }
6820
6821 /* Otherwise treat as a generic register access */
6822 is64 = (insn & (1 << 25)) == 0;
6823 if (!is64 && ((insn & (1 << 4)) == 0)) {
6824 /* cdp */
6825 return 1;
6826 }
6827
6828 crm = insn & 0xf;
6829 if (is64) {
6830 crn = 0;
6831 opc1 = (insn >> 4) & 0xf;
6832 opc2 = 0;
6833 rt2 = (insn >> 16) & 0xf;
6834 } else {
6835 crn = (insn >> 16) & 0xf;
6836 opc1 = (insn >> 21) & 7;
6837 opc2 = (insn >> 5) & 7;
6838 rt2 = 0;
6839 }
6840 isread = (insn >> 20) & 1;
6841 rt = (insn >> 12) & 0xf;
6842
6843 ri = get_arm_cp_reginfo(s->cp_regs,
6844 ENCODE_CP_REG(cpnum, is64, crn, crm, opc1, opc2));
6845 if (ri) {
6846 /* Check access permissions */
6847 if (!cp_access_ok(s->current_pl, ri, isread)) {
6848 return 1;
6849 }
6850
6851 if (ri->accessfn) {
6852 /* Emit code to perform further access permissions checks at
6853 * runtime; this may result in an exception.
6854 */
6855 TCGv_ptr tmpptr;
6856 gen_set_pc_im(s, s->pc);
6857 tmpptr = tcg_const_ptr(ri);
6858 gen_helper_access_check_cp_reg(cpu_env, tmpptr);
6859 tcg_temp_free_ptr(tmpptr);
6860 }
6861
6862 /* Handle special cases first */
6863 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
6864 case ARM_CP_NOP:
6865 return 0;
6866 case ARM_CP_WFI:
6867 if (isread) {
6868 return 1;
6869 }
6870 gen_set_pc_im(s, s->pc);
6871 s->is_jmp = DISAS_WFI;
6872 return 0;
6873 default:
6874 break;
6875 }
6876
6877 if (use_icount && (ri->type & ARM_CP_IO)) {
6878 gen_io_start();
6879 }
6880
6881 if (isread) {
6882 /* Read */
6883 if (is64) {
6884 TCGv_i64 tmp64;
6885 TCGv_i32 tmp;
6886 if (ri->type & ARM_CP_CONST) {
6887 tmp64 = tcg_const_i64(ri->resetvalue);
6888 } else if (ri->readfn) {
6889 TCGv_ptr tmpptr;
6890 tmp64 = tcg_temp_new_i64();
6891 tmpptr = tcg_const_ptr(ri);
6892 gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr);
6893 tcg_temp_free_ptr(tmpptr);
6894 } else {
6895 tmp64 = tcg_temp_new_i64();
6896 tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset);
6897 }
6898 tmp = tcg_temp_new_i32();
6899 tcg_gen_trunc_i64_i32(tmp, tmp64);
6900 store_reg(s, rt, tmp);
6901 tcg_gen_shri_i64(tmp64, tmp64, 32);
6902 tmp = tcg_temp_new_i32();
6903 tcg_gen_trunc_i64_i32(tmp, tmp64);
6904 tcg_temp_free_i64(tmp64);
6905 store_reg(s, rt2, tmp);
6906 } else {
6907 TCGv_i32 tmp;
6908 if (ri->type & ARM_CP_CONST) {
6909 tmp = tcg_const_i32(ri->resetvalue);
6910 } else if (ri->readfn) {
6911 TCGv_ptr tmpptr;
6912 tmp = tcg_temp_new_i32();
6913 tmpptr = tcg_const_ptr(ri);
6914 gen_helper_get_cp_reg(tmp, cpu_env, tmpptr);
6915 tcg_temp_free_ptr(tmpptr);
6916 } else {
6917 tmp = load_cpu_offset(ri->fieldoffset);
6918 }
6919 if (rt == 15) {
6920 /* Destination register of r15 for 32 bit loads sets
6921 * the condition codes from the high 4 bits of the value
6922 */
6923 gen_set_nzcv(tmp);
6924 tcg_temp_free_i32(tmp);
6925 } else {
6926 store_reg(s, rt, tmp);
6927 }
6928 }
6929 } else {
6930 /* Write */
6931 if (ri->type & ARM_CP_CONST) {
6932 /* If not forbidden by access permissions, treat as WI */
6933 return 0;
6934 }
6935
6936 if (is64) {
6937 TCGv_i32 tmplo, tmphi;
6938 TCGv_i64 tmp64 = tcg_temp_new_i64();
6939 tmplo = load_reg(s, rt);
6940 tmphi = load_reg(s, rt2);
6941 tcg_gen_concat_i32_i64(tmp64, tmplo, tmphi);
6942 tcg_temp_free_i32(tmplo);
6943 tcg_temp_free_i32(tmphi);
6944 if (ri->writefn) {
6945 TCGv_ptr tmpptr = tcg_const_ptr(ri);
6946 gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64);
6947 tcg_temp_free_ptr(tmpptr);
6948 } else {
6949 tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset);
6950 }
6951 tcg_temp_free_i64(tmp64);
6952 } else {
6953 if (ri->writefn) {
6954 TCGv_i32 tmp;
6955 TCGv_ptr tmpptr;
6956 tmp = load_reg(s, rt);
6957 tmpptr = tcg_const_ptr(ri);
6958 gen_helper_set_cp_reg(cpu_env, tmpptr, tmp);
6959 tcg_temp_free_ptr(tmpptr);
6960 tcg_temp_free_i32(tmp);
6961 } else {
6962 TCGv_i32 tmp = load_reg(s, rt);
6963 store_cpu_offset(tmp, ri->fieldoffset);
6964 }
6965 }
6966 }
6967
6968 if (use_icount && (ri->type & ARM_CP_IO)) {
6969 /* I/O operations must end the TB here (whether read or write) */
6970 gen_io_end();
6971 gen_lookup_tb(s);
6972 } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
6973 /* We default to ending the TB on a coprocessor register write,
6974 * but allow this to be suppressed by the register definition
6975 * (usually only necessary to work around guest bugs).
6976 */
6977 gen_lookup_tb(s);
6978 }
6979
6980 return 0;
6981 }
6982
6983 /* Unknown register; this might be a guest error or a QEMU
6984 * unimplemented feature.
6985 */
6986 if (is64) {
6987 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
6988 "64 bit system register cp:%d opc1: %d crm:%d\n",
6989 isread ? "read" : "write", cpnum, opc1, crm);
6990 } else {
6991 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
6992 "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d\n",
6993 isread ? "read" : "write", cpnum, opc1, crn, crm, opc2);
6994 }
6995
6996 return 1;
6997 }
6998
6999
7000 /* Store a 64-bit value to a register pair. Clobbers val. */
7001 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
7002 {
7003 TCGv_i32 tmp;
7004 tmp = tcg_temp_new_i32();
7005 tcg_gen_trunc_i64_i32(tmp, val);
7006 store_reg(s, rlow, tmp);
7007 tmp = tcg_temp_new_i32();
7008 tcg_gen_shri_i64(val, val, 32);
7009 tcg_gen_trunc_i64_i32(tmp, val);
7010 store_reg(s, rhigh, tmp);
7011 }
7012
7013 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
7014 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
7015 {
7016 TCGv_i64 tmp;
7017 TCGv_i32 tmp2;
7018
7019 /* Load value and extend to 64 bits. */
7020 tmp = tcg_temp_new_i64();
7021 tmp2 = load_reg(s, rlow);
7022 tcg_gen_extu_i32_i64(tmp, tmp2);
7023 tcg_temp_free_i32(tmp2);
7024 tcg_gen_add_i64(val, val, tmp);
7025 tcg_temp_free_i64(tmp);
7026 }
7027
7028 /* load and add a 64-bit value from a register pair. */
7029 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
7030 {
7031 TCGv_i64 tmp;
7032 TCGv_i32 tmpl;
7033 TCGv_i32 tmph;
7034
7035 /* Load 64-bit value rd:rn. */
7036 tmpl = load_reg(s, rlow);
7037 tmph = load_reg(s, rhigh);
7038 tmp = tcg_temp_new_i64();
7039 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
7040 tcg_temp_free_i32(tmpl);
7041 tcg_temp_free_i32(tmph);
7042 tcg_gen_add_i64(val, val, tmp);
7043 tcg_temp_free_i64(tmp);
7044 }
7045
7046 /* Set N and Z flags from hi|lo. */
7047 static void gen_logicq_cc(TCGv_i32 lo, TCGv_i32 hi)
7048 {
7049 tcg_gen_mov_i32(cpu_NF, hi);
7050 tcg_gen_or_i32(cpu_ZF, lo, hi);
7051 }
7052
7053 /* Load/Store exclusive instructions are implemented by remembering
7054 the value/address loaded, and seeing if these are the same
7055 when the store is performed. This should be sufficient to implement
7056 the architecturally mandated semantics, and avoids having to monitor
7057 regular stores.
7058
7059 In system emulation mode only one CPU will be running at once, so
7060 this sequence is effectively atomic. In user emulation mode we
7061 throw an exception and handle the atomic operation elsewhere. */
7062 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
7063 TCGv_i32 addr, int size)
7064 {
7065 TCGv_i32 tmp = tcg_temp_new_i32();
7066
7067 switch (size) {
7068 case 0:
7069 gen_aa32_ld8u(tmp, addr, IS_USER(s));
7070 break;
7071 case 1:
7072 gen_aa32_ld16u(tmp, addr, IS_USER(s));
7073 break;
7074 case 2:
7075 case 3:
7076 gen_aa32_ld32u(tmp, addr, IS_USER(s));
7077 break;
7078 default:
7079 abort();
7080 }
7081
7082 if (size == 3) {
7083 TCGv_i32 tmp2 = tcg_temp_new_i32();
7084 TCGv_i32 tmp3 = tcg_temp_new_i32();
7085
7086 tcg_gen_addi_i32(tmp2, addr, 4);
7087 gen_aa32_ld32u(tmp3, tmp2, IS_USER(s));
7088 tcg_temp_free_i32(tmp2);
7089 tcg_gen_concat_i32_i64(cpu_exclusive_val, tmp, tmp3);
7090 store_reg(s, rt2, tmp3);
7091 } else {
7092 tcg_gen_extu_i32_i64(cpu_exclusive_val, tmp);
7093 }
7094
7095 store_reg(s, rt, tmp);
7096 tcg_gen_extu_i32_i64(cpu_exclusive_addr, addr);
7097 }
7098
7099 static void gen_clrex(DisasContext *s)
7100 {
7101 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
7102 }
7103
7104 #ifdef CONFIG_USER_ONLY
7105 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
7106 TCGv_i32 addr, int size)
7107 {
7108 tcg_gen_extu_i32_i64(cpu_exclusive_test, addr);
7109 tcg_gen_movi_i32(cpu_exclusive_info,
7110 size | (rd << 4) | (rt << 8) | (rt2 << 12));
7111 gen_exception_insn(s, 4, EXCP_STREX);
7112 }
7113 #else
7114 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
7115 TCGv_i32 addr, int size)
7116 {
7117 TCGv_i32 tmp;
7118 TCGv_i64 val64, extaddr;
7119 int done_label;
7120 int fail_label;
7121
7122 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
7123 [addr] = {Rt};
7124 {Rd} = 0;
7125 } else {
7126 {Rd} = 1;
7127 } */
7128 fail_label = gen_new_label();
7129 done_label = gen_new_label();
7130 extaddr = tcg_temp_new_i64();
7131 tcg_gen_extu_i32_i64(extaddr, addr);
7132 tcg_gen_brcond_i64(TCG_COND_NE, extaddr, cpu_exclusive_addr, fail_label);
7133 tcg_temp_free_i64(extaddr);
7134
7135 tmp = tcg_temp_new_i32();
7136 switch (size) {
7137 case 0:
7138 gen_aa32_ld8u(tmp, addr, IS_USER(s));
7139 break;
7140 case 1:
7141 gen_aa32_ld16u(tmp, addr, IS_USER(s));
7142 break;
7143 case 2:
7144 case 3:
7145 gen_aa32_ld32u(tmp, addr, IS_USER(s));
7146 break;
7147 default:
7148 abort();
7149 }
7150
7151 val64 = tcg_temp_new_i64();
7152 if (size == 3) {
7153 TCGv_i32 tmp2 = tcg_temp_new_i32();
7154 TCGv_i32 tmp3 = tcg_temp_new_i32();
7155 tcg_gen_addi_i32(tmp2, addr, 4);
7156 gen_aa32_ld32u(tmp3, tmp2, IS_USER(s));
7157 tcg_temp_free_i32(tmp2);
7158 tcg_gen_concat_i32_i64(val64, tmp, tmp3);
7159 tcg_temp_free_i32(tmp3);
7160 } else {
7161 tcg_gen_extu_i32_i64(val64, tmp);
7162 }
7163 tcg_temp_free_i32(tmp);
7164
7165 tcg_gen_brcond_i64(TCG_COND_NE, val64, cpu_exclusive_val, fail_label);
7166 tcg_temp_free_i64(val64);
7167
7168 tmp = load_reg(s, rt);
7169 switch (size) {
7170 case 0:
7171 gen_aa32_st8(tmp, addr, IS_USER(s));
7172 break;
7173 case 1:
7174 gen_aa32_st16(tmp, addr, IS_USER(s));
7175 break;
7176 case 2:
7177 case 3:
7178 gen_aa32_st32(tmp, addr, IS_USER(s));
7179 break;
7180 default:
7181 abort();
7182 }
7183 tcg_temp_free_i32(tmp);
7184 if (size == 3) {
7185 tcg_gen_addi_i32(addr, addr, 4);
7186 tmp = load_reg(s, rt2);
7187 gen_aa32_st32(tmp, addr, IS_USER(s));
7188 tcg_temp_free_i32(tmp);
7189 }
7190 tcg_gen_movi_i32(cpu_R[rd], 0);
7191 tcg_gen_br(done_label);
7192 gen_set_label(fail_label);
7193 tcg_gen_movi_i32(cpu_R[rd], 1);
7194 gen_set_label(done_label);
7195 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
7196 }
7197 #endif
7198
7199 /* gen_srs:
7200 * @env: CPUARMState
7201 * @s: DisasContext
7202 * @mode: mode field from insn (which stack to store to)
7203 * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn
7204 * @writeback: true if writeback bit set
7205 *
7206 * Generate code for the SRS (Store Return State) insn.
7207 */
7208 static void gen_srs(DisasContext *s,
7209 uint32_t mode, uint32_t amode, bool writeback)
7210 {
7211 int32_t offset;
7212 TCGv_i32 addr = tcg_temp_new_i32();
7213 TCGv_i32 tmp = tcg_const_i32(mode);
7214 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7215 tcg_temp_free_i32(tmp);
7216 switch (amode) {
7217 case 0: /* DA */
7218 offset = -4;
7219 break;
7220 case 1: /* IA */
7221 offset = 0;
7222 break;
7223 case 2: /* DB */
7224 offset = -8;
7225 break;
7226 case 3: /* IB */
7227 offset = 4;
7228 break;
7229 default:
7230 abort();
7231 }
7232 tcg_gen_addi_i32(addr, addr, offset);
7233 tmp = load_reg(s, 14);
7234 gen_aa32_st32(tmp, addr, 0);
7235 tcg_temp_free_i32(tmp);
7236 tmp = load_cpu_field(spsr);
7237 tcg_gen_addi_i32(addr, addr, 4);
7238 gen_aa32_st32(tmp, addr, 0);
7239 tcg_temp_free_i32(tmp);
7240 if (writeback) {
7241 switch (amode) {
7242 case 0:
7243 offset = -8;
7244 break;
7245 case 1:
7246 offset = 4;
7247 break;
7248 case 2:
7249 offset = -4;
7250 break;
7251 case 3:
7252 offset = 0;
7253 break;
7254 default:
7255 abort();
7256 }
7257 tcg_gen_addi_i32(addr, addr, offset);
7258 tmp = tcg_const_i32(mode);
7259 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7260 tcg_temp_free_i32(tmp);
7261 }
7262 tcg_temp_free_i32(addr);
7263 }
7264
7265 static void disas_arm_insn(CPUARMState * env, DisasContext *s)
7266 {
7267 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
7268 TCGv_i32 tmp;
7269 TCGv_i32 tmp2;
7270 TCGv_i32 tmp3;
7271 TCGv_i32 addr;
7272 TCGv_i64 tmp64;
7273
7274 insn = arm_ldl_code(env, s->pc, s->bswap_code);
7275 s->pc += 4;
7276
7277 /* M variants do not implement ARM mode. */
7278 if (IS_M(env))
7279 goto illegal_op;
7280 cond = insn >> 28;
7281 if (cond == 0xf){
7282 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
7283 * choose to UNDEF. In ARMv5 and above the space is used
7284 * for miscellaneous unconditional instructions.
7285 */
7286 ARCH(5);
7287
7288 /* Unconditional instructions. */
7289 if (((insn >> 25) & 7) == 1) {
7290 /* NEON Data processing. */
7291 if (!arm_feature(env, ARM_FEATURE_NEON))
7292 goto illegal_op;
7293
7294 if (disas_neon_data_insn(env, s, insn))
7295 goto illegal_op;
7296 return;
7297 }
7298 if ((insn & 0x0f100000) == 0x04000000) {
7299 /* NEON load/store. */
7300 if (!arm_feature(env, ARM_FEATURE_NEON))
7301 goto illegal_op;
7302
7303 if (disas_neon_ls_insn(env, s, insn))
7304 goto illegal_op;
7305 return;
7306 }
7307 if ((insn & 0x0f000e10) == 0x0e000a00) {
7308 /* VFP. */
7309 if (disas_vfp_insn(env, s, insn)) {
7310 goto illegal_op;
7311 }
7312 return;
7313 }
7314 if (((insn & 0x0f30f000) == 0x0510f000) ||
7315 ((insn & 0x0f30f010) == 0x0710f000)) {
7316 if ((insn & (1 << 22)) == 0) {
7317 /* PLDW; v7MP */
7318 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
7319 goto illegal_op;
7320 }
7321 }
7322 /* Otherwise PLD; v5TE+ */
7323 ARCH(5TE);
7324 return;
7325 }
7326 if (((insn & 0x0f70f000) == 0x0450f000) ||
7327 ((insn & 0x0f70f010) == 0x0650f000)) {
7328 ARCH(7);
7329 return; /* PLI; V7 */
7330 }
7331 if (((insn & 0x0f700000) == 0x04100000) ||
7332 ((insn & 0x0f700010) == 0x06100000)) {
7333 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
7334 goto illegal_op;
7335 }
7336 return; /* v7MP: Unallocated memory hint: must NOP */
7337 }
7338
7339 if ((insn & 0x0ffffdff) == 0x01010000) {
7340 ARCH(6);
7341 /* setend */
7342 if (((insn >> 9) & 1) != s->bswap_code) {
7343 /* Dynamic endianness switching not implemented. */
7344 qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
7345 goto illegal_op;
7346 }
7347 return;
7348 } else if ((insn & 0x0fffff00) == 0x057ff000) {
7349 switch ((insn >> 4) & 0xf) {
7350 case 1: /* clrex */
7351 ARCH(6K);
7352 gen_clrex(s);
7353 return;
7354 case 4: /* dsb */
7355 case 5: /* dmb */
7356 case 6: /* isb */
7357 ARCH(7);
7358 /* We don't emulate caches so these are a no-op. */
7359 return;
7360 default:
7361 goto illegal_op;
7362 }
7363 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
7364 /* srs */
7365 if (IS_USER(s)) {
7366 goto illegal_op;
7367 }
7368 ARCH(6);
7369 gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21));
7370 return;
7371 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
7372 /* rfe */
7373 int32_t offset;
7374 if (IS_USER(s))
7375 goto illegal_op;
7376 ARCH(6);
7377 rn = (insn >> 16) & 0xf;
7378 addr = load_reg(s, rn);
7379 i = (insn >> 23) & 3;
7380 switch (i) {
7381 case 0: offset = -4; break; /* DA */
7382 case 1: offset = 0; break; /* IA */
7383 case 2: offset = -8; break; /* DB */
7384 case 3: offset = 4; break; /* IB */
7385 default: abort();
7386 }
7387 if (offset)
7388 tcg_gen_addi_i32(addr, addr, offset);
7389 /* Load PC into tmp and CPSR into tmp2. */
7390 tmp = tcg_temp_new_i32();
7391 gen_aa32_ld32u(tmp, addr, 0);
7392 tcg_gen_addi_i32(addr, addr, 4);
7393 tmp2 = tcg_temp_new_i32();
7394 gen_aa32_ld32u(tmp2, addr, 0);
7395 if (insn & (1 << 21)) {
7396 /* Base writeback. */
7397 switch (i) {
7398 case 0: offset = -8; break;
7399 case 1: offset = 4; break;
7400 case 2: offset = -4; break;
7401 case 3: offset = 0; break;
7402 default: abort();
7403 }
7404 if (offset)
7405 tcg_gen_addi_i32(addr, addr, offset);
7406 store_reg(s, rn, addr);
7407 } else {
7408 tcg_temp_free_i32(addr);
7409 }
7410 gen_rfe(s, tmp, tmp2);
7411 return;
7412 } else if ((insn & 0x0e000000) == 0x0a000000) {
7413 /* branch link and change to thumb (blx <offset>) */
7414 int32_t offset;
7415
7416 val = (uint32_t)s->pc;
7417 tmp = tcg_temp_new_i32();
7418 tcg_gen_movi_i32(tmp, val);
7419 store_reg(s, 14, tmp);
7420 /* Sign-extend the 24-bit offset */
7421 offset = (((int32_t)insn) << 8) >> 8;
7422 /* offset * 4 + bit24 * 2 + (thumb bit) */
7423 val += (offset << 2) | ((insn >> 23) & 2) | 1;
7424 /* pipeline offset */
7425 val += 4;
7426 /* protected by ARCH(5); above, near the start of uncond block */
7427 gen_bx_im(s, val);
7428 return;
7429 } else if ((insn & 0x0e000f00) == 0x0c000100) {
7430 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
7431 /* iWMMXt register transfer. */
7432 if (env->cp15.c15_cpar & (1 << 1))
7433 if (!disas_iwmmxt_insn(env, s, insn))
7434 return;
7435 }
7436 } else if ((insn & 0x0fe00000) == 0x0c400000) {
7437 /* Coprocessor double register transfer. */
7438 ARCH(5TE);
7439 } else if ((insn & 0x0f000010) == 0x0e000010) {
7440 /* Additional coprocessor register transfer. */
7441 } else if ((insn & 0x0ff10020) == 0x01000000) {
7442 uint32_t mask;
7443 uint32_t val;
7444 /* cps (privileged) */
7445 if (IS_USER(s))
7446 return;
7447 mask = val = 0;
7448 if (insn & (1 << 19)) {
7449 if (insn & (1 << 8))
7450 mask |= CPSR_A;
7451 if (insn & (1 << 7))
7452 mask |= CPSR_I;
7453 if (insn & (1 << 6))
7454 mask |= CPSR_F;
7455 if (insn & (1 << 18))
7456 val |= mask;
7457 }
7458 if (insn & (1 << 17)) {
7459 mask |= CPSR_M;
7460 val |= (insn & 0x1f);
7461 }
7462 if (mask) {
7463 gen_set_psr_im(s, mask, 0, val);
7464 }
7465 return;
7466 }
7467 goto illegal_op;
7468 }
7469 if (cond != 0xe) {
7470 /* if not always execute, we generate a conditional jump to
7471 next instruction */
7472 s->condlabel = gen_new_label();
7473 arm_gen_test_cc(cond ^ 1, s->condlabel);
7474 s->condjmp = 1;
7475 }
7476 if ((insn & 0x0f900000) == 0x03000000) {
7477 if ((insn & (1 << 21)) == 0) {
7478 ARCH(6T2);
7479 rd = (insn >> 12) & 0xf;
7480 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
7481 if ((insn & (1 << 22)) == 0) {
7482 /* MOVW */
7483 tmp = tcg_temp_new_i32();
7484 tcg_gen_movi_i32(tmp, val);
7485 } else {
7486 /* MOVT */
7487 tmp = load_reg(s, rd);
7488 tcg_gen_ext16u_i32(tmp, tmp);
7489 tcg_gen_ori_i32(tmp, tmp, val << 16);
7490 }
7491 store_reg(s, rd, tmp);
7492 } else {
7493 if (((insn >> 12) & 0xf) != 0xf)
7494 goto illegal_op;
7495 if (((insn >> 16) & 0xf) == 0) {
7496 gen_nop_hint(s, insn & 0xff);
7497 } else {
7498 /* CPSR = immediate */
7499 val = insn & 0xff;
7500 shift = ((insn >> 8) & 0xf) * 2;
7501 if (shift)
7502 val = (val >> shift) | (val << (32 - shift));
7503 i = ((insn & (1 << 22)) != 0);
7504 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
7505 goto illegal_op;
7506 }
7507 }
7508 } else if ((insn & 0x0f900000) == 0x01000000
7509 && (insn & 0x00000090) != 0x00000090) {
7510 /* miscellaneous instructions */
7511 op1 = (insn >> 21) & 3;
7512 sh = (insn >> 4) & 0xf;
7513 rm = insn & 0xf;
7514 switch (sh) {
7515 case 0x0: /* move program status register */
7516 if (op1 & 1) {
7517 /* PSR = reg */
7518 tmp = load_reg(s, rm);
7519 i = ((op1 & 2) != 0);
7520 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
7521 goto illegal_op;
7522 } else {
7523 /* reg = PSR */
7524 rd = (insn >> 12) & 0xf;
7525 if (op1 & 2) {
7526 if (IS_USER(s))
7527 goto illegal_op;
7528 tmp = load_cpu_field(spsr);
7529 } else {
7530 tmp = tcg_temp_new_i32();
7531 gen_helper_cpsr_read(tmp, cpu_env);
7532 }
7533 store_reg(s, rd, tmp);
7534 }
7535 break;
7536 case 0x1:
7537 if (op1 == 1) {
7538 /* branch/exchange thumb (bx). */
7539 ARCH(4T);
7540 tmp = load_reg(s, rm);
7541 gen_bx(s, tmp);
7542 } else if (op1 == 3) {
7543 /* clz */
7544 ARCH(5);
7545 rd = (insn >> 12) & 0xf;
7546 tmp = load_reg(s, rm);
7547 gen_helper_clz(tmp, tmp);
7548 store_reg(s, rd, tmp);
7549 } else {
7550 goto illegal_op;
7551 }
7552 break;
7553 case 0x2:
7554 if (op1 == 1) {
7555 ARCH(5J); /* bxj */
7556 /* Trivial implementation equivalent to bx. */
7557 tmp = load_reg(s, rm);
7558 gen_bx(s, tmp);
7559 } else {
7560 goto illegal_op;
7561 }
7562 break;
7563 case 0x3:
7564 if (op1 != 1)
7565 goto illegal_op;
7566
7567 ARCH(5);
7568 /* branch link/exchange thumb (blx) */
7569 tmp = load_reg(s, rm);
7570 tmp2 = tcg_temp_new_i32();
7571 tcg_gen_movi_i32(tmp2, s->pc);
7572 store_reg(s, 14, tmp2);
7573 gen_bx(s, tmp);
7574 break;
7575 case 0x4:
7576 {
7577 /* crc32/crc32c */
7578 uint32_t c = extract32(insn, 8, 4);
7579
7580 /* Check this CPU supports ARMv8 CRC instructions.
7581 * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
7582 * Bits 8, 10 and 11 should be zero.
7583 */
7584 if (!arm_feature(env, ARM_FEATURE_CRC) || op1 == 0x3 ||
7585 (c & 0xd) != 0) {
7586 goto illegal_op;
7587 }
7588
7589 rn = extract32(insn, 16, 4);
7590 rd = extract32(insn, 12, 4);
7591
7592 tmp = load_reg(s, rn);
7593 tmp2 = load_reg(s, rm);
7594 tmp3 = tcg_const_i32(1 << op1);
7595 if (c & 0x2) {
7596 gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
7597 } else {
7598 gen_helper_crc32(tmp, tmp, tmp2, tmp3);
7599 }
7600 tcg_temp_free_i32(tmp2);
7601 tcg_temp_free_i32(tmp3);
7602 store_reg(s, rd, tmp);
7603 break;
7604 }
7605 case 0x5: /* saturating add/subtract */
7606 ARCH(5TE);
7607 rd = (insn >> 12) & 0xf;
7608 rn = (insn >> 16) & 0xf;
7609 tmp = load_reg(s, rm);
7610 tmp2 = load_reg(s, rn);
7611 if (op1 & 2)
7612 gen_helper_double_saturate(tmp2, cpu_env, tmp2);
7613 if (op1 & 1)
7614 gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
7615 else
7616 gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
7617 tcg_temp_free_i32(tmp2);
7618 store_reg(s, rd, tmp);
7619 break;
7620 case 7:
7621 /* SMC instruction (op1 == 3)
7622 and undefined instructions (op1 == 0 || op1 == 2)
7623 will trap */
7624 if (op1 != 1) {
7625 goto illegal_op;
7626 }
7627 /* bkpt */
7628 ARCH(5);
7629 gen_exception_insn(s, 4, EXCP_BKPT);
7630 break;
7631 case 0x8: /* signed multiply */
7632 case 0xa:
7633 case 0xc:
7634 case 0xe:
7635 ARCH(5TE);
7636 rs = (insn >> 8) & 0xf;
7637 rn = (insn >> 12) & 0xf;
7638 rd = (insn >> 16) & 0xf;
7639 if (op1 == 1) {
7640 /* (32 * 16) >> 16 */
7641 tmp = load_reg(s, rm);
7642 tmp2 = load_reg(s, rs);
7643 if (sh & 4)
7644 tcg_gen_sari_i32(tmp2, tmp2, 16);
7645 else
7646 gen_sxth(tmp2);
7647 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7648 tcg_gen_shri_i64(tmp64, tmp64, 16);
7649 tmp = tcg_temp_new_i32();
7650 tcg_gen_trunc_i64_i32(tmp, tmp64);
7651 tcg_temp_free_i64(tmp64);
7652 if ((sh & 2) == 0) {
7653 tmp2 = load_reg(s, rn);
7654 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
7655 tcg_temp_free_i32(tmp2);
7656 }
7657 store_reg(s, rd, tmp);
7658 } else {
7659 /* 16 * 16 */
7660 tmp = load_reg(s, rm);
7661 tmp2 = load_reg(s, rs);
7662 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
7663 tcg_temp_free_i32(tmp2);
7664 if (op1 == 2) {
7665 tmp64 = tcg_temp_new_i64();
7666 tcg_gen_ext_i32_i64(tmp64, tmp);
7667 tcg_temp_free_i32(tmp);
7668 gen_addq(s, tmp64, rn, rd);
7669 gen_storeq_reg(s, rn, rd, tmp64);
7670 tcg_temp_free_i64(tmp64);
7671 } else {
7672 if (op1 == 0) {
7673 tmp2 = load_reg(s, rn);
7674 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
7675 tcg_temp_free_i32(tmp2);
7676 }
7677 store_reg(s, rd, tmp);
7678 }
7679 }
7680 break;
7681 default:
7682 goto illegal_op;
7683 }
7684 } else if (((insn & 0x0e000000) == 0 &&
7685 (insn & 0x00000090) != 0x90) ||
7686 ((insn & 0x0e000000) == (1 << 25))) {
7687 int set_cc, logic_cc, shiftop;
7688
7689 op1 = (insn >> 21) & 0xf;
7690 set_cc = (insn >> 20) & 1;
7691 logic_cc = table_logic_cc[op1] & set_cc;
7692
7693 /* data processing instruction */
7694 if (insn & (1 << 25)) {
7695 /* immediate operand */
7696 val = insn & 0xff;
7697 shift = ((insn >> 8) & 0xf) * 2;
7698 if (shift) {
7699 val = (val >> shift) | (val << (32 - shift));
7700 }
7701 tmp2 = tcg_temp_new_i32();
7702 tcg_gen_movi_i32(tmp2, val);
7703 if (logic_cc && shift) {
7704 gen_set_CF_bit31(tmp2);
7705 }
7706 } else {
7707 /* register */
7708 rm = (insn) & 0xf;
7709 tmp2 = load_reg(s, rm);
7710 shiftop = (insn >> 5) & 3;
7711 if (!(insn & (1 << 4))) {
7712 shift = (insn >> 7) & 0x1f;
7713 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7714 } else {
7715 rs = (insn >> 8) & 0xf;
7716 tmp = load_reg(s, rs);
7717 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
7718 }
7719 }
7720 if (op1 != 0x0f && op1 != 0x0d) {
7721 rn = (insn >> 16) & 0xf;
7722 tmp = load_reg(s, rn);
7723 } else {
7724 TCGV_UNUSED_I32(tmp);
7725 }
7726 rd = (insn >> 12) & 0xf;
7727 switch(op1) {
7728 case 0x00:
7729 tcg_gen_and_i32(tmp, tmp, tmp2);
7730 if (logic_cc) {
7731 gen_logic_CC(tmp);
7732 }
7733 store_reg_bx(env, s, rd, tmp);
7734 break;
7735 case 0x01:
7736 tcg_gen_xor_i32(tmp, tmp, tmp2);
7737 if (logic_cc) {
7738 gen_logic_CC(tmp);
7739 }
7740 store_reg_bx(env, s, rd, tmp);
7741 break;
7742 case 0x02:
7743 if (set_cc && rd == 15) {
7744 /* SUBS r15, ... is used for exception return. */
7745 if (IS_USER(s)) {
7746 goto illegal_op;
7747 }
7748 gen_sub_CC(tmp, tmp, tmp2);
7749 gen_exception_return(s, tmp);
7750 } else {
7751 if (set_cc) {
7752 gen_sub_CC(tmp, tmp, tmp2);
7753 } else {
7754 tcg_gen_sub_i32(tmp, tmp, tmp2);
7755 }
7756 store_reg_bx(env, s, rd, tmp);
7757 }
7758 break;
7759 case 0x03:
7760 if (set_cc) {
7761 gen_sub_CC(tmp, tmp2, tmp);
7762 } else {
7763 tcg_gen_sub_i32(tmp, tmp2, tmp);
7764 }
7765 store_reg_bx(env, s, rd, tmp);
7766 break;
7767 case 0x04:
7768 if (set_cc) {
7769 gen_add_CC(tmp, tmp, tmp2);
7770 } else {
7771 tcg_gen_add_i32(tmp, tmp, tmp2);
7772 }
7773 store_reg_bx(env, s, rd, tmp);
7774 break;
7775 case 0x05:
7776 if (set_cc) {
7777 gen_adc_CC(tmp, tmp, tmp2);
7778 } else {
7779 gen_add_carry(tmp, tmp, tmp2);
7780 }
7781 store_reg_bx(env, s, rd, tmp);
7782 break;
7783 case 0x06:
7784 if (set_cc) {
7785 gen_sbc_CC(tmp, tmp, tmp2);
7786 } else {
7787 gen_sub_carry(tmp, tmp, tmp2);
7788 }
7789 store_reg_bx(env, s, rd, tmp);
7790 break;
7791 case 0x07:
7792 if (set_cc) {
7793 gen_sbc_CC(tmp, tmp2, tmp);
7794 } else {
7795 gen_sub_carry(tmp, tmp2, tmp);
7796 }
7797 store_reg_bx(env, s, rd, tmp);
7798 break;
7799 case 0x08:
7800 if (set_cc) {
7801 tcg_gen_and_i32(tmp, tmp, tmp2);
7802 gen_logic_CC(tmp);
7803 }
7804 tcg_temp_free_i32(tmp);
7805 break;
7806 case 0x09:
7807 if (set_cc) {
7808 tcg_gen_xor_i32(tmp, tmp, tmp2);
7809 gen_logic_CC(tmp);
7810 }
7811 tcg_temp_free_i32(tmp);
7812 break;
7813 case 0x0a:
7814 if (set_cc) {
7815 gen_sub_CC(tmp, tmp, tmp2);
7816 }
7817 tcg_temp_free_i32(tmp);
7818 break;
7819 case 0x0b:
7820 if (set_cc) {
7821 gen_add_CC(tmp, tmp, tmp2);
7822 }
7823 tcg_temp_free_i32(tmp);
7824 break;
7825 case 0x0c:
7826 tcg_gen_or_i32(tmp, tmp, tmp2);
7827 if (logic_cc) {
7828 gen_logic_CC(tmp);
7829 }
7830 store_reg_bx(env, s, rd, tmp);
7831 break;
7832 case 0x0d:
7833 if (logic_cc && rd == 15) {
7834 /* MOVS r15, ... is used for exception return. */
7835 if (IS_USER(s)) {
7836 goto illegal_op;
7837 }
7838 gen_exception_return(s, tmp2);
7839 } else {
7840 if (logic_cc) {
7841 gen_logic_CC(tmp2);
7842 }
7843 store_reg_bx(env, s, rd, tmp2);
7844 }
7845 break;
7846 case 0x0e:
7847 tcg_gen_andc_i32(tmp, tmp, tmp2);
7848 if (logic_cc) {
7849 gen_logic_CC(tmp);
7850 }
7851 store_reg_bx(env, s, rd, tmp);
7852 break;
7853 default:
7854 case 0x0f:
7855 tcg_gen_not_i32(tmp2, tmp2);
7856 if (logic_cc) {
7857 gen_logic_CC(tmp2);
7858 }
7859 store_reg_bx(env, s, rd, tmp2);
7860 break;
7861 }
7862 if (op1 != 0x0f && op1 != 0x0d) {
7863 tcg_temp_free_i32(tmp2);
7864 }
7865 } else {
7866 /* other instructions */
7867 op1 = (insn >> 24) & 0xf;
7868 switch(op1) {
7869 case 0x0:
7870 case 0x1:
7871 /* multiplies, extra load/stores */
7872 sh = (insn >> 5) & 3;
7873 if (sh == 0) {
7874 if (op1 == 0x0) {
7875 rd = (insn >> 16) & 0xf;
7876 rn = (insn >> 12) & 0xf;
7877 rs = (insn >> 8) & 0xf;
7878 rm = (insn) & 0xf;
7879 op1 = (insn >> 20) & 0xf;
7880 switch (op1) {
7881 case 0: case 1: case 2: case 3: case 6:
7882 /* 32 bit mul */
7883 tmp = load_reg(s, rs);
7884 tmp2 = load_reg(s, rm);
7885 tcg_gen_mul_i32(tmp, tmp, tmp2);
7886 tcg_temp_free_i32(tmp2);
7887 if (insn & (1 << 22)) {
7888 /* Subtract (mls) */
7889 ARCH(6T2);
7890 tmp2 = load_reg(s, rn);
7891 tcg_gen_sub_i32(tmp, tmp2, tmp);
7892 tcg_temp_free_i32(tmp2);
7893 } else if (insn & (1 << 21)) {
7894 /* Add */
7895 tmp2 = load_reg(s, rn);
7896 tcg_gen_add_i32(tmp, tmp, tmp2);
7897 tcg_temp_free_i32(tmp2);
7898 }
7899 if (insn & (1 << 20))
7900 gen_logic_CC(tmp);
7901 store_reg(s, rd, tmp);
7902 break;
7903 case 4:
7904 /* 64 bit mul double accumulate (UMAAL) */
7905 ARCH(6);
7906 tmp = load_reg(s, rs);
7907 tmp2 = load_reg(s, rm);
7908 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
7909 gen_addq_lo(s, tmp64, rn);
7910 gen_addq_lo(s, tmp64, rd);
7911 gen_storeq_reg(s, rn, rd, tmp64);
7912 tcg_temp_free_i64(tmp64);
7913 break;
7914 case 8: case 9: case 10: case 11:
7915 case 12: case 13: case 14: case 15:
7916 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
7917 tmp = load_reg(s, rs);
7918 tmp2 = load_reg(s, rm);
7919 if (insn & (1 << 22)) {
7920 tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2);
7921 } else {
7922 tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2);
7923 }
7924 if (insn & (1 << 21)) { /* mult accumulate */
7925 TCGv_i32 al = load_reg(s, rn);
7926 TCGv_i32 ah = load_reg(s, rd);
7927 tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah);
7928 tcg_temp_free_i32(al);
7929 tcg_temp_free_i32(ah);
7930 }
7931 if (insn & (1 << 20)) {
7932 gen_logicq_cc(tmp, tmp2);
7933 }
7934 store_reg(s, rn, tmp);
7935 store_reg(s, rd, tmp2);
7936 break;
7937 default:
7938 goto illegal_op;
7939 }
7940 } else {
7941 rn = (insn >> 16) & 0xf;
7942 rd = (insn >> 12) & 0xf;
7943 if (insn & (1 << 23)) {
7944 /* load/store exclusive */
7945 int op2 = (insn >> 8) & 3;
7946 op1 = (insn >> 21) & 0x3;
7947
7948 switch (op2) {
7949 case 0: /* lda/stl */
7950 if (op1 == 1) {
7951 goto illegal_op;
7952 }
7953 ARCH(8);
7954 break;
7955 case 1: /* reserved */
7956 goto illegal_op;
7957 case 2: /* ldaex/stlex */
7958 ARCH(8);
7959 break;
7960 case 3: /* ldrex/strex */
7961 if (op1) {
7962 ARCH(6K);
7963 } else {
7964 ARCH(6);
7965 }
7966 break;
7967 }
7968
7969 addr = tcg_temp_local_new_i32();
7970 load_reg_var(s, addr, rn);
7971
7972 /* Since the emulation does not have barriers,
7973 the acquire/release semantics need no special
7974 handling */
7975 if (op2 == 0) {
7976 if (insn & (1 << 20)) {
7977 tmp = tcg_temp_new_i32();
7978 switch (op1) {
7979 case 0: /* lda */
7980 gen_aa32_ld32u(tmp, addr, IS_USER(s));
7981 break;
7982 case 2: /* ldab */
7983 gen_aa32_ld8u(tmp, addr, IS_USER(s));
7984 break;
7985 case 3: /* ldah */
7986 gen_aa32_ld16u(tmp, addr, IS_USER(s));
7987 break;
7988 default:
7989 abort();
7990 }
7991 store_reg(s, rd, tmp);
7992 } else {
7993 rm = insn & 0xf;
7994 tmp = load_reg(s, rm);
7995 switch (op1) {
7996 case 0: /* stl */
7997 gen_aa32_st32(tmp, addr, IS_USER(s));
7998 break;
7999 case 2: /* stlb */
8000 gen_aa32_st8(tmp, addr, IS_USER(s));
8001 break;
8002 case 3: /* stlh */
8003 gen_aa32_st16(tmp, addr, IS_USER(s));
8004 break;
8005 default:
8006 abort();
8007 }
8008 tcg_temp_free_i32(tmp);
8009 }
8010 } else if (insn & (1 << 20)) {
8011 switch (op1) {
8012 case 0: /* ldrex */
8013 gen_load_exclusive(s, rd, 15, addr, 2);
8014 break;
8015 case 1: /* ldrexd */
8016 gen_load_exclusive(s, rd, rd + 1, addr, 3);
8017 break;
8018 case 2: /* ldrexb */
8019 gen_load_exclusive(s, rd, 15, addr, 0);
8020 break;
8021 case 3: /* ldrexh */
8022 gen_load_exclusive(s, rd, 15, addr, 1);
8023 break;
8024 default:
8025 abort();
8026 }
8027 } else {
8028 rm = insn & 0xf;
8029 switch (op1) {
8030 case 0: /* strex */
8031 gen_store_exclusive(s, rd, rm, 15, addr, 2);
8032 break;
8033 case 1: /* strexd */
8034 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
8035 break;
8036 case 2: /* strexb */
8037 gen_store_exclusive(s, rd, rm, 15, addr, 0);
8038 break;
8039 case 3: /* strexh */
8040 gen_store_exclusive(s, rd, rm, 15, addr, 1);
8041 break;
8042 default:
8043 abort();
8044 }
8045 }
8046 tcg_temp_free_i32(addr);
8047 } else {
8048 /* SWP instruction */
8049 rm = (insn) & 0xf;
8050
8051 /* ??? This is not really atomic. However we know
8052 we never have multiple CPUs running in parallel,
8053 so it is good enough. */
8054 addr = load_reg(s, rn);
8055 tmp = load_reg(s, rm);
8056 tmp2 = tcg_temp_new_i32();
8057 if (insn & (1 << 22)) {
8058 gen_aa32_ld8u(tmp2, addr, IS_USER(s));
8059 gen_aa32_st8(tmp, addr, IS_USER(s));
8060 } else {
8061 gen_aa32_ld32u(tmp2, addr, IS_USER(s));
8062 gen_aa32_st32(tmp, addr, IS_USER(s));
8063 }
8064 tcg_temp_free_i32(tmp);
8065 tcg_temp_free_i32(addr);
8066 store_reg(s, rd, tmp2);
8067 }
8068 }
8069 } else {
8070 int address_offset;
8071 int load;
8072 /* Misc load/store */
8073 rn = (insn >> 16) & 0xf;
8074 rd = (insn >> 12) & 0xf;
8075 addr = load_reg(s, rn);
8076 if (insn & (1 << 24))
8077 gen_add_datah_offset(s, insn, 0, addr);
8078 address_offset = 0;
8079 if (insn & (1 << 20)) {
8080 /* load */
8081 tmp = tcg_temp_new_i32();
8082 switch(sh) {
8083 case 1:
8084 gen_aa32_ld16u(tmp, addr, IS_USER(s));
8085 break;
8086 case 2:
8087 gen_aa32_ld8s(tmp, addr, IS_USER(s));
8088 break;
8089 default:
8090 case 3:
8091 gen_aa32_ld16s(tmp, addr, IS_USER(s));
8092 break;
8093 }
8094 load = 1;
8095 } else if (sh & 2) {
8096 ARCH(5TE);
8097 /* doubleword */
8098 if (sh & 1) {
8099 /* store */
8100 tmp = load_reg(s, rd);
8101 gen_aa32_st32(tmp, addr, IS_USER(s));
8102 tcg_temp_free_i32(tmp);
8103 tcg_gen_addi_i32(addr, addr, 4);
8104 tmp = load_reg(s, rd + 1);
8105 gen_aa32_st32(tmp, addr, IS_USER(s));
8106 tcg_temp_free_i32(tmp);
8107 load = 0;
8108 } else {
8109 /* load */
8110 tmp = tcg_temp_new_i32();
8111 gen_aa32_ld32u(tmp, addr, IS_USER(s));
8112 store_reg(s, rd, tmp);
8113 tcg_gen_addi_i32(addr, addr, 4);
8114 tmp = tcg_temp_new_i32();
8115 gen_aa32_ld32u(tmp, addr, IS_USER(s));
8116 rd++;
8117 load = 1;
8118 }
8119 address_offset = -4;
8120 } else {
8121 /* store */
8122 tmp = load_reg(s, rd);
8123 gen_aa32_st16(tmp, addr, IS_USER(s));
8124 tcg_temp_free_i32(tmp);
8125 load = 0;
8126 }
8127 /* Perform base writeback before the loaded value to
8128 ensure correct behavior with overlapping index registers.
8129 ldrd with base writeback is is undefined if the
8130 destination and index registers overlap. */
8131 if (!(insn & (1 << 24))) {
8132 gen_add_datah_offset(s, insn, address_offset, addr);
8133 store_reg(s, rn, addr);
8134 } else if (insn & (1 << 21)) {
8135 if (address_offset)
8136 tcg_gen_addi_i32(addr, addr, address_offset);
8137 store_reg(s, rn, addr);
8138 } else {
8139 tcg_temp_free_i32(addr);
8140 }
8141 if (load) {
8142 /* Complete the load. */
8143 store_reg(s, rd, tmp);
8144 }
8145 }
8146 break;
8147 case 0x4:
8148 case 0x5:
8149 goto do_ldst;
8150 case 0x6:
8151 case 0x7:
8152 if (insn & (1 << 4)) {
8153 ARCH(6);
8154 /* Armv6 Media instructions. */
8155 rm = insn & 0xf;
8156 rn = (insn >> 16) & 0xf;
8157 rd = (insn >> 12) & 0xf;
8158 rs = (insn >> 8) & 0xf;
8159 switch ((insn >> 23) & 3) {
8160 case 0: /* Parallel add/subtract. */
8161 op1 = (insn >> 20) & 7;
8162 tmp = load_reg(s, rn);
8163 tmp2 = load_reg(s, rm);
8164 sh = (insn >> 5) & 7;
8165 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
8166 goto illegal_op;
8167 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
8168 tcg_temp_free_i32(tmp2);
8169 store_reg(s, rd, tmp);
8170 break;
8171 case 1:
8172 if ((insn & 0x00700020) == 0) {
8173 /* Halfword pack. */
8174 tmp = load_reg(s, rn);
8175 tmp2 = load_reg(s, rm);
8176 shift = (insn >> 7) & 0x1f;
8177 if (insn & (1 << 6)) {
8178 /* pkhtb */
8179 if (shift == 0)
8180 shift = 31;
8181 tcg_gen_sari_i32(tmp2, tmp2, shift);
8182 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
8183 tcg_gen_ext16u_i32(tmp2, tmp2);
8184 } else {
8185 /* pkhbt */
8186 if (shift)
8187 tcg_gen_shli_i32(tmp2, tmp2, shift);
8188 tcg_gen_ext16u_i32(tmp, tmp);
8189 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
8190 }
8191 tcg_gen_or_i32(tmp, tmp, tmp2);
8192 tcg_temp_free_i32(tmp2);
8193 store_reg(s, rd, tmp);
8194 } else if ((insn & 0x00200020) == 0x00200000) {
8195 /* [us]sat */
8196 tmp = load_reg(s, rm);
8197 shift = (insn >> 7) & 0x1f;
8198 if (insn & (1 << 6)) {
8199 if (shift == 0)
8200 shift = 31;
8201 tcg_gen_sari_i32(tmp, tmp, shift);
8202 } else {
8203 tcg_gen_shli_i32(tmp, tmp, shift);
8204 }
8205 sh = (insn >> 16) & 0x1f;
8206 tmp2 = tcg_const_i32(sh);
8207 if (insn & (1 << 22))
8208 gen_helper_usat(tmp, cpu_env, tmp, tmp2);
8209 else
8210 gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
8211 tcg_temp_free_i32(tmp2);
8212 store_reg(s, rd, tmp);
8213 } else if ((insn & 0x00300fe0) == 0x00200f20) {
8214 /* [us]sat16 */
8215 tmp = load_reg(s, rm);
8216 sh = (insn >> 16) & 0x1f;
8217 tmp2 = tcg_const_i32(sh);
8218 if (insn & (1 << 22))
8219 gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
8220 else
8221 gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
8222 tcg_temp_free_i32(tmp2);
8223 store_reg(s, rd, tmp);
8224 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
8225 /* Select bytes. */
8226 tmp = load_reg(s, rn);
8227 tmp2 = load_reg(s, rm);
8228 tmp3 = tcg_temp_new_i32();
8229 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
8230 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
8231 tcg_temp_free_i32(tmp3);
8232 tcg_temp_free_i32(tmp2);
8233 store_reg(s, rd, tmp);
8234 } else if ((insn & 0x000003e0) == 0x00000060) {
8235 tmp = load_reg(s, rm);
8236 shift = (insn >> 10) & 3;
8237 /* ??? In many cases it's not necessary to do a
8238 rotate, a shift is sufficient. */
8239 if (shift != 0)
8240 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
8241 op1 = (insn >> 20) & 7;
8242 switch (op1) {
8243 case 0: gen_sxtb16(tmp); break;
8244 case 2: gen_sxtb(tmp); break;
8245 case 3: gen_sxth(tmp); break;
8246 case 4: gen_uxtb16(tmp); break;
8247 case 6: gen_uxtb(tmp); break;
8248 case 7: gen_uxth(tmp); break;
8249 default: goto illegal_op;
8250 }
8251 if (rn != 15) {
8252 tmp2 = load_reg(s, rn);
8253 if ((op1 & 3) == 0) {
8254 gen_add16(tmp, tmp2);
8255 } else {
8256 tcg_gen_add_i32(tmp, tmp, tmp2);
8257 tcg_temp_free_i32(tmp2);
8258 }
8259 }
8260 store_reg(s, rd, tmp);
8261 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
8262 /* rev */
8263 tmp = load_reg(s, rm);
8264 if (insn & (1 << 22)) {
8265 if (insn & (1 << 7)) {
8266 gen_revsh(tmp);
8267 } else {
8268 ARCH(6T2);
8269 gen_helper_rbit(tmp, tmp);
8270 }
8271 } else {
8272 if (insn & (1 << 7))
8273 gen_rev16(tmp);
8274 else
8275 tcg_gen_bswap32_i32(tmp, tmp);
8276 }
8277 store_reg(s, rd, tmp);
8278 } else {
8279 goto illegal_op;
8280 }
8281 break;
8282 case 2: /* Multiplies (Type 3). */
8283 switch ((insn >> 20) & 0x7) {
8284 case 5:
8285 if (((insn >> 6) ^ (insn >> 7)) & 1) {
8286 /* op2 not 00x or 11x : UNDEF */
8287 goto illegal_op;
8288 }
8289 /* Signed multiply most significant [accumulate].
8290 (SMMUL, SMMLA, SMMLS) */
8291 tmp = load_reg(s, rm);
8292 tmp2 = load_reg(s, rs);
8293 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8294
8295 if (rd != 15) {
8296 tmp = load_reg(s, rd);
8297 if (insn & (1 << 6)) {
8298 tmp64 = gen_subq_msw(tmp64, tmp);
8299 } else {
8300 tmp64 = gen_addq_msw(tmp64, tmp);
8301 }
8302 }
8303 if (insn & (1 << 5)) {
8304 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
8305 }
8306 tcg_gen_shri_i64(tmp64, tmp64, 32);
8307 tmp = tcg_temp_new_i32();
8308 tcg_gen_trunc_i64_i32(tmp, tmp64);
8309 tcg_temp_free_i64(tmp64);
8310 store_reg(s, rn, tmp);
8311 break;
8312 case 0:
8313 case 4:
8314 /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */
8315 if (insn & (1 << 7)) {
8316 goto illegal_op;
8317 }
8318 tmp = load_reg(s, rm);
8319 tmp2 = load_reg(s, rs);
8320 if (insn & (1 << 5))
8321 gen_swap_half(tmp2);
8322 gen_smul_dual(tmp, tmp2);
8323 if (insn & (1 << 6)) {
8324 /* This subtraction cannot overflow. */
8325 tcg_gen_sub_i32(tmp, tmp, tmp2);
8326 } else {
8327 /* This addition cannot overflow 32 bits;
8328 * however it may overflow considered as a signed
8329 * operation, in which case we must set the Q flag.
8330 */
8331 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
8332 }
8333 tcg_temp_free_i32(tmp2);
8334 if (insn & (1 << 22)) {
8335 /* smlald, smlsld */
8336 tmp64 = tcg_temp_new_i64();
8337 tcg_gen_ext_i32_i64(tmp64, tmp);
8338 tcg_temp_free_i32(tmp);
8339 gen_addq(s, tmp64, rd, rn);
8340 gen_storeq_reg(s, rd, rn, tmp64);
8341 tcg_temp_free_i64(tmp64);
8342 } else {
8343 /* smuad, smusd, smlad, smlsd */
8344 if (rd != 15)
8345 {
8346 tmp2 = load_reg(s, rd);
8347 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
8348 tcg_temp_free_i32(tmp2);
8349 }
8350 store_reg(s, rn, tmp);
8351 }
8352 break;
8353 case 1:
8354 case 3:
8355 /* SDIV, UDIV */
8356 if (!arm_feature(env, ARM_FEATURE_ARM_DIV)) {
8357 goto illegal_op;
8358 }
8359 if (((insn >> 5) & 7) || (rd != 15)) {
8360 goto illegal_op;
8361 }
8362 tmp = load_reg(s, rm);
8363 tmp2 = load_reg(s, rs);
8364 if (insn & (1 << 21)) {
8365 gen_helper_udiv(tmp, tmp, tmp2);
8366 } else {
8367 gen_helper_sdiv(tmp, tmp, tmp2);
8368 }
8369 tcg_temp_free_i32(tmp2);
8370 store_reg(s, rn, tmp);
8371 break;
8372 default:
8373 goto illegal_op;
8374 }
8375 break;
8376 case 3:
8377 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
8378 switch (op1) {
8379 case 0: /* Unsigned sum of absolute differences. */
8380 ARCH(6);
8381 tmp = load_reg(s, rm);
8382 tmp2 = load_reg(s, rs);
8383 gen_helper_usad8(tmp, tmp, tmp2);
8384 tcg_temp_free_i32(tmp2);
8385 if (rd != 15) {
8386 tmp2 = load_reg(s, rd);
8387 tcg_gen_add_i32(tmp, tmp, tmp2);
8388 tcg_temp_free_i32(tmp2);
8389 }
8390 store_reg(s, rn, tmp);
8391 break;
8392 case 0x20: case 0x24: case 0x28: case 0x2c:
8393 /* Bitfield insert/clear. */
8394 ARCH(6T2);
8395 shift = (insn >> 7) & 0x1f;
8396 i = (insn >> 16) & 0x1f;
8397 i = i + 1 - shift;
8398 if (rm == 15) {
8399 tmp = tcg_temp_new_i32();
8400 tcg_gen_movi_i32(tmp, 0);
8401 } else {
8402 tmp = load_reg(s, rm);
8403 }
8404 if (i != 32) {
8405 tmp2 = load_reg(s, rd);
8406 tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i);
8407 tcg_temp_free_i32(tmp2);
8408 }
8409 store_reg(s, rd, tmp);
8410 break;
8411 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
8412 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
8413 ARCH(6T2);
8414 tmp = load_reg(s, rm);
8415 shift = (insn >> 7) & 0x1f;
8416 i = ((insn >> 16) & 0x1f) + 1;
8417 if (shift + i > 32)
8418 goto illegal_op;
8419 if (i < 32) {
8420 if (op1 & 0x20) {
8421 gen_ubfx(tmp, shift, (1u << i) - 1);
8422 } else {
8423 gen_sbfx(tmp, shift, i);
8424 }
8425 }
8426 store_reg(s, rd, tmp);
8427 break;
8428 default:
8429 goto illegal_op;
8430 }
8431 break;
8432 }
8433 break;
8434 }
8435 do_ldst:
8436 /* Check for undefined extension instructions
8437 * per the ARM Bible IE:
8438 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
8439 */
8440 sh = (0xf << 20) | (0xf << 4);
8441 if (op1 == 0x7 && ((insn & sh) == sh))
8442 {
8443 goto illegal_op;
8444 }
8445 /* load/store byte/word */
8446 rn = (insn >> 16) & 0xf;
8447 rd = (insn >> 12) & 0xf;
8448 tmp2 = load_reg(s, rn);
8449 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
8450 if (insn & (1 << 24))
8451 gen_add_data_offset(s, insn, tmp2);
8452 if (insn & (1 << 20)) {
8453 /* load */
8454 tmp = tcg_temp_new_i32();
8455 if (insn & (1 << 22)) {
8456 gen_aa32_ld8u(tmp, tmp2, i);
8457 } else {
8458 gen_aa32_ld32u(tmp, tmp2, i);
8459 }
8460 } else {
8461 /* store */
8462 tmp = load_reg(s, rd);
8463 if (insn & (1 << 22)) {
8464 gen_aa32_st8(tmp, tmp2, i);
8465 } else {
8466 gen_aa32_st32(tmp, tmp2, i);
8467 }
8468 tcg_temp_free_i32(tmp);
8469 }
8470 if (!(insn & (1 << 24))) {
8471 gen_add_data_offset(s, insn, tmp2);
8472 store_reg(s, rn, tmp2);
8473 } else if (insn & (1 << 21)) {
8474 store_reg(s, rn, tmp2);
8475 } else {
8476 tcg_temp_free_i32(tmp2);
8477 }
8478 if (insn & (1 << 20)) {
8479 /* Complete the load. */
8480 store_reg_from_load(env, s, rd, tmp);
8481 }
8482 break;
8483 case 0x08:
8484 case 0x09:
8485 {
8486 int j, n, user, loaded_base;
8487 TCGv_i32 loaded_var;
8488 /* load/store multiple words */
8489 /* XXX: store correct base if write back */
8490 user = 0;
8491 if (insn & (1 << 22)) {
8492 if (IS_USER(s))
8493 goto illegal_op; /* only usable in supervisor mode */
8494
8495 if ((insn & (1 << 15)) == 0)
8496 user = 1;
8497 }
8498 rn = (insn >> 16) & 0xf;
8499 addr = load_reg(s, rn);
8500
8501 /* compute total size */
8502 loaded_base = 0;
8503 TCGV_UNUSED_I32(loaded_var);
8504 n = 0;
8505 for(i=0;i<16;i++) {
8506 if (insn & (1 << i))
8507 n++;
8508 }
8509 /* XXX: test invalid n == 0 case ? */
8510 if (insn & (1 << 23)) {
8511 if (insn & (1 << 24)) {
8512 /* pre increment */
8513 tcg_gen_addi_i32(addr, addr, 4);
8514 } else {
8515 /* post increment */
8516 }
8517 } else {
8518 if (insn & (1 << 24)) {
8519 /* pre decrement */
8520 tcg_gen_addi_i32(addr, addr, -(n * 4));
8521 } else {
8522 /* post decrement */
8523 if (n != 1)
8524 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
8525 }
8526 }
8527 j = 0;
8528 for(i=0;i<16;i++) {
8529 if (insn & (1 << i)) {
8530 if (insn & (1 << 20)) {
8531 /* load */
8532 tmp = tcg_temp_new_i32();
8533 gen_aa32_ld32u(tmp, addr, IS_USER(s));
8534 if (user) {
8535 tmp2 = tcg_const_i32(i);
8536 gen_helper_set_user_reg(cpu_env, tmp2, tmp);
8537 tcg_temp_free_i32(tmp2);
8538 tcg_temp_free_i32(tmp);
8539 } else if (i == rn) {
8540 loaded_var = tmp;
8541 loaded_base = 1;
8542 } else {
8543 store_reg_from_load(env, s, i, tmp);
8544 }
8545 } else {
8546 /* store */
8547 if (i == 15) {
8548 /* special case: r15 = PC + 8 */
8549 val = (long)s->pc + 4;
8550 tmp = tcg_temp_new_i32();
8551 tcg_gen_movi_i32(tmp, val);
8552 } else if (user) {
8553 tmp = tcg_temp_new_i32();
8554 tmp2 = tcg_const_i32(i);
8555 gen_helper_get_user_reg(tmp, cpu_env, tmp2);
8556 tcg_temp_free_i32(tmp2);
8557 } else {
8558 tmp = load_reg(s, i);
8559 }
8560 gen_aa32_st32(tmp, addr, IS_USER(s));
8561 tcg_temp_free_i32(tmp);
8562 }
8563 j++;
8564 /* no need to add after the last transfer */
8565 if (j != n)
8566 tcg_gen_addi_i32(addr, addr, 4);
8567 }
8568 }
8569 if (insn & (1 << 21)) {
8570 /* write back */
8571 if (insn & (1 << 23)) {
8572 if (insn & (1 << 24)) {
8573 /* pre increment */
8574 } else {
8575 /* post increment */
8576 tcg_gen_addi_i32(addr, addr, 4);
8577 }
8578 } else {
8579 if (insn & (1 << 24)) {
8580 /* pre decrement */
8581 if (n != 1)
8582 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
8583 } else {
8584 /* post decrement */
8585 tcg_gen_addi_i32(addr, addr, -(n * 4));
8586 }
8587 }
8588 store_reg(s, rn, addr);
8589 } else {
8590 tcg_temp_free_i32(addr);
8591 }
8592 if (loaded_base) {
8593 store_reg(s, rn, loaded_var);
8594 }
8595 if ((insn & (1 << 22)) && !user) {
8596 /* Restore CPSR from SPSR. */
8597 tmp = load_cpu_field(spsr);
8598 gen_set_cpsr(tmp, 0xffffffff);
8599 tcg_temp_free_i32(tmp);
8600 s->is_jmp = DISAS_UPDATE;
8601 }
8602 }
8603 break;
8604 case 0xa:
8605 case 0xb:
8606 {
8607 int32_t offset;
8608
8609 /* branch (and link) */
8610 val = (int32_t)s->pc;
8611 if (insn & (1 << 24)) {
8612 tmp = tcg_temp_new_i32();
8613 tcg_gen_movi_i32(tmp, val);
8614 store_reg(s, 14, tmp);
8615 }
8616 offset = sextract32(insn << 2, 0, 26);
8617 val += offset + 4;
8618 gen_jmp(s, val);
8619 }
8620 break;
8621 case 0xc:
8622 case 0xd:
8623 case 0xe:
8624 if (((insn >> 8) & 0xe) == 10) {
8625 /* VFP. */
8626 if (disas_vfp_insn(env, s, insn)) {
8627 goto illegal_op;
8628 }
8629 } else if (disas_coproc_insn(env, s, insn)) {
8630 /* Coprocessor. */
8631 goto illegal_op;
8632 }
8633 break;
8634 case 0xf:
8635 /* swi */
8636 gen_set_pc_im(s, s->pc);
8637 s->is_jmp = DISAS_SWI;
8638 break;
8639 default:
8640 illegal_op:
8641 gen_exception_insn(s, 4, EXCP_UDEF);
8642 break;
8643 }
8644 }
8645 }
8646
8647 /* Return true if this is a Thumb-2 logical op. */
8648 static int
8649 thumb2_logic_op(int op)
8650 {
8651 return (op < 8);
8652 }
8653
8654 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
8655 then set condition code flags based on the result of the operation.
8656 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
8657 to the high bit of T1.
8658 Returns zero if the opcode is valid. */
8659
8660 static int
8661 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
8662 TCGv_i32 t0, TCGv_i32 t1)
8663 {
8664 int logic_cc;
8665
8666 logic_cc = 0;
8667 switch (op) {
8668 case 0: /* and */
8669 tcg_gen_and_i32(t0, t0, t1);
8670 logic_cc = conds;
8671 break;
8672 case 1: /* bic */
8673 tcg_gen_andc_i32(t0, t0, t1);
8674 logic_cc = conds;
8675 break;
8676 case 2: /* orr */
8677 tcg_gen_or_i32(t0, t0, t1);
8678 logic_cc = conds;
8679 break;
8680 case 3: /* orn */
8681 tcg_gen_orc_i32(t0, t0, t1);
8682 logic_cc = conds;
8683 break;
8684 case 4: /* eor */
8685 tcg_gen_xor_i32(t0, t0, t1);
8686 logic_cc = conds;
8687 break;
8688 case 8: /* add */
8689 if (conds)
8690 gen_add_CC(t0, t0, t1);
8691 else
8692 tcg_gen_add_i32(t0, t0, t1);
8693 break;
8694 case 10: /* adc */
8695 if (conds)
8696 gen_adc_CC(t0, t0, t1);
8697 else
8698 gen_adc(t0, t1);
8699 break;
8700 case 11: /* sbc */
8701 if (conds) {
8702 gen_sbc_CC(t0, t0, t1);
8703 } else {
8704 gen_sub_carry(t0, t0, t1);
8705 }
8706 break;
8707 case 13: /* sub */
8708 if (conds)
8709 gen_sub_CC(t0, t0, t1);
8710 else
8711 tcg_gen_sub_i32(t0, t0, t1);
8712 break;
8713 case 14: /* rsb */
8714 if (conds)
8715 gen_sub_CC(t0, t1, t0);
8716 else
8717 tcg_gen_sub_i32(t0, t1, t0);
8718 break;
8719 default: /* 5, 6, 7, 9, 12, 15. */
8720 return 1;
8721 }
8722 if (logic_cc) {
8723 gen_logic_CC(t0);
8724 if (shifter_out)
8725 gen_set_CF_bit31(t1);
8726 }
8727 return 0;
8728 }
8729
8730 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
8731 is not legal. */
8732 static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)
8733 {
8734 uint32_t insn, imm, shift, offset;
8735 uint32_t rd, rn, rm, rs;
8736 TCGv_i32 tmp;
8737 TCGv_i32 tmp2;
8738 TCGv_i32 tmp3;
8739 TCGv_i32 addr;
8740 TCGv_i64 tmp64;
8741 int op;
8742 int shiftop;
8743 int conds;
8744 int logic_cc;
8745
8746 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
8747 || arm_feature (env, ARM_FEATURE_M))) {
8748 /* Thumb-1 cores may need to treat bl and blx as a pair of
8749 16-bit instructions to get correct prefetch abort behavior. */
8750 insn = insn_hw1;
8751 if ((insn & (1 << 12)) == 0) {
8752 ARCH(5);
8753 /* Second half of blx. */
8754 offset = ((insn & 0x7ff) << 1);
8755 tmp = load_reg(s, 14);
8756 tcg_gen_addi_i32(tmp, tmp, offset);
8757 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
8758
8759 tmp2 = tcg_temp_new_i32();
8760 tcg_gen_movi_i32(tmp2, s->pc | 1);
8761 store_reg(s, 14, tmp2);
8762 gen_bx(s, tmp);
8763 return 0;
8764 }
8765 if (insn & (1 << 11)) {
8766 /* Second half of bl. */
8767 offset = ((insn & 0x7ff) << 1) | 1;
8768 tmp = load_reg(s, 14);
8769 tcg_gen_addi_i32(tmp, tmp, offset);
8770
8771 tmp2 = tcg_temp_new_i32();
8772 tcg_gen_movi_i32(tmp2, s->pc | 1);
8773 store_reg(s, 14, tmp2);
8774 gen_bx(s, tmp);
8775 return 0;
8776 }
8777 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
8778 /* Instruction spans a page boundary. Implement it as two
8779 16-bit instructions in case the second half causes an
8780 prefetch abort. */
8781 offset = ((int32_t)insn << 21) >> 9;
8782 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
8783 return 0;
8784 }
8785 /* Fall through to 32-bit decode. */
8786 }
8787
8788 insn = arm_lduw_code(env, s->pc, s->bswap_code);
8789 s->pc += 2;
8790 insn |= (uint32_t)insn_hw1 << 16;
8791
8792 if ((insn & 0xf800e800) != 0xf000e800) {
8793 ARCH(6T2);
8794 }
8795
8796 rn = (insn >> 16) & 0xf;
8797 rs = (insn >> 12) & 0xf;
8798 rd = (insn >> 8) & 0xf;
8799 rm = insn & 0xf;
8800 switch ((insn >> 25) & 0xf) {
8801 case 0: case 1: case 2: case 3:
8802 /* 16-bit instructions. Should never happen. */
8803 abort();
8804 case 4:
8805 if (insn & (1 << 22)) {
8806 /* Other load/store, table branch. */
8807 if (insn & 0x01200000) {
8808 /* Load/store doubleword. */
8809 if (rn == 15) {
8810 addr = tcg_temp_new_i32();
8811 tcg_gen_movi_i32(addr, s->pc & ~3);
8812 } else {
8813 addr = load_reg(s, rn);
8814 }
8815 offset = (insn & 0xff) * 4;
8816 if ((insn & (1 << 23)) == 0)
8817 offset = -offset;
8818 if (insn & (1 << 24)) {
8819 tcg_gen_addi_i32(addr, addr, offset);
8820 offset = 0;
8821 }
8822 if (insn & (1 << 20)) {
8823 /* ldrd */
8824 tmp = tcg_temp_new_i32();
8825 gen_aa32_ld32u(tmp, addr, IS_USER(s));
8826 store_reg(s, rs, tmp);
8827 tcg_gen_addi_i32(addr, addr, 4);
8828 tmp = tcg_temp_new_i32();
8829 gen_aa32_ld32u(tmp, addr, IS_USER(s));
8830 store_reg(s, rd, tmp);
8831 } else {
8832 /* strd */
8833 tmp = load_reg(s, rs);
8834 gen_aa32_st32(tmp, addr, IS_USER(s));
8835 tcg_temp_free_i32(tmp);
8836 tcg_gen_addi_i32(addr, addr, 4);
8837 tmp = load_reg(s, rd);
8838 gen_aa32_st32(tmp, addr, IS_USER(s));
8839 tcg_temp_free_i32(tmp);
8840 }
8841 if (insn & (1 << 21)) {
8842 /* Base writeback. */
8843 if (rn == 15)
8844 goto illegal_op;
8845 tcg_gen_addi_i32(addr, addr, offset - 4);
8846 store_reg(s, rn, addr);
8847 } else {
8848 tcg_temp_free_i32(addr);
8849 }
8850 } else if ((insn & (1 << 23)) == 0) {
8851 /* Load/store exclusive word. */
8852 addr = tcg_temp_local_new_i32();
8853 load_reg_var(s, addr, rn);
8854 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
8855 if (insn & (1 << 20)) {
8856 gen_load_exclusive(s, rs, 15, addr, 2);
8857 } else {
8858 gen_store_exclusive(s, rd, rs, 15, addr, 2);
8859 }
8860 tcg_temp_free_i32(addr);
8861 } else if ((insn & (7 << 5)) == 0) {
8862 /* Table Branch. */
8863 if (rn == 15) {
8864 addr = tcg_temp_new_i32();
8865 tcg_gen_movi_i32(addr, s->pc);
8866 } else {
8867 addr = load_reg(s, rn);
8868 }
8869 tmp = load_reg(s, rm);
8870 tcg_gen_add_i32(addr, addr, tmp);
8871 if (insn & (1 << 4)) {
8872 /* tbh */
8873 tcg_gen_add_i32(addr, addr, tmp);
8874 tcg_temp_free_i32(tmp);
8875 tmp = tcg_temp_new_i32();
8876 gen_aa32_ld16u(tmp, addr, IS_USER(s));
8877 } else { /* tbb */
8878 tcg_temp_free_i32(tmp);
8879 tmp = tcg_temp_new_i32();
8880 gen_aa32_ld8u(tmp, addr, IS_USER(s));
8881 }
8882 tcg_temp_free_i32(addr);
8883 tcg_gen_shli_i32(tmp, tmp, 1);
8884 tcg_gen_addi_i32(tmp, tmp, s->pc);
8885 store_reg(s, 15, tmp);
8886 } else {
8887 int op2 = (insn >> 6) & 0x3;
8888 op = (insn >> 4) & 0x3;
8889 switch (op2) {
8890 case 0:
8891 goto illegal_op;
8892 case 1:
8893 /* Load/store exclusive byte/halfword/doubleword */
8894 if (op == 2) {
8895 goto illegal_op;
8896 }
8897 ARCH(7);
8898 break;
8899 case 2:
8900 /* Load-acquire/store-release */
8901 if (op == 3) {
8902 goto illegal_op;
8903 }
8904 /* Fall through */
8905 case 3:
8906 /* Load-acquire/store-release exclusive */
8907 ARCH(8);
8908 break;
8909 }
8910 addr = tcg_temp_local_new_i32();
8911 load_reg_var(s, addr, rn);
8912 if (!(op2 & 1)) {
8913 if (insn & (1 << 20)) {
8914 tmp = tcg_temp_new_i32();
8915 switch (op) {
8916 case 0: /* ldab */
8917 gen_aa32_ld8u(tmp, addr, IS_USER(s));
8918 break;
8919 case 1: /* ldah */
8920 gen_aa32_ld16u(tmp, addr, IS_USER(s));
8921 break;
8922 case 2: /* lda */
8923 gen_aa32_ld32u(tmp, addr, IS_USER(s));
8924 break;
8925 default:
8926 abort();
8927 }
8928 store_reg(s, rs, tmp);
8929 } else {
8930 tmp = load_reg(s, rs);
8931 switch (op) {
8932 case 0: /* stlb */
8933 gen_aa32_st8(tmp, addr, IS_USER(s));
8934 break;
8935 case 1: /* stlh */
8936 gen_aa32_st16(tmp, addr, IS_USER(s));
8937 break;
8938 case 2: /* stl */
8939 gen_aa32_st32(tmp, addr, IS_USER(s));
8940 break;
8941 default:
8942 abort();
8943 }
8944 tcg_temp_free_i32(tmp);
8945 }
8946 } else if (insn & (1 << 20)) {
8947 gen_load_exclusive(s, rs, rd, addr, op);
8948 } else {
8949 gen_store_exclusive(s, rm, rs, rd, addr, op);
8950 }
8951 tcg_temp_free_i32(addr);
8952 }
8953 } else {
8954 /* Load/store multiple, RFE, SRS. */
8955 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
8956 /* RFE, SRS: not available in user mode or on M profile */
8957 if (IS_USER(s) || IS_M(env)) {
8958 goto illegal_op;
8959 }
8960 if (insn & (1 << 20)) {
8961 /* rfe */
8962 addr = load_reg(s, rn);
8963 if ((insn & (1 << 24)) == 0)
8964 tcg_gen_addi_i32(addr, addr, -8);
8965 /* Load PC into tmp and CPSR into tmp2. */
8966 tmp = tcg_temp_new_i32();
8967 gen_aa32_ld32u(tmp, addr, 0);
8968 tcg_gen_addi_i32(addr, addr, 4);
8969 tmp2 = tcg_temp_new_i32();
8970 gen_aa32_ld32u(tmp2, addr, 0);
8971 if (insn & (1 << 21)) {
8972 /* Base writeback. */
8973 if (insn & (1 << 24)) {
8974 tcg_gen_addi_i32(addr, addr, 4);
8975 } else {
8976 tcg_gen_addi_i32(addr, addr, -4);
8977 }
8978 store_reg(s, rn, addr);
8979 } else {
8980 tcg_temp_free_i32(addr);
8981 }
8982 gen_rfe(s, tmp, tmp2);
8983 } else {
8984 /* srs */
8985 gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2,
8986 insn & (1 << 21));
8987 }
8988 } else {
8989 int i, loaded_base = 0;
8990 TCGv_i32 loaded_var;
8991 /* Load/store multiple. */
8992 addr = load_reg(s, rn);
8993 offset = 0;
8994 for (i = 0; i < 16; i++) {
8995 if (insn & (1 << i))
8996 offset += 4;
8997 }
8998 if (insn & (1 << 24)) {
8999 tcg_gen_addi_i32(addr, addr, -offset);
9000 }
9001
9002 TCGV_UNUSED_I32(loaded_var);
9003 for (i = 0; i < 16; i++) {
9004 if ((insn & (1 << i)) == 0)
9005 continue;
9006 if (insn & (1 << 20)) {
9007 /* Load. */
9008 tmp = tcg_temp_new_i32();
9009 gen_aa32_ld32u(tmp, addr, IS_USER(s));
9010 if (i == 15) {
9011 gen_bx(s, tmp);
9012 } else if (i == rn) {
9013 loaded_var = tmp;
9014 loaded_base = 1;
9015 } else {
9016 store_reg(s, i, tmp);
9017 }
9018 } else {
9019 /* Store. */
9020 tmp = load_reg(s, i);
9021 gen_aa32_st32(tmp, addr, IS_USER(s));
9022 tcg_temp_free_i32(tmp);
9023 }
9024 tcg_gen_addi_i32(addr, addr, 4);
9025 }
9026 if (loaded_base) {
9027 store_reg(s, rn, loaded_var);
9028 }
9029 if (insn & (1 << 21)) {
9030 /* Base register writeback. */
9031 if (insn & (1 << 24)) {
9032 tcg_gen_addi_i32(addr, addr, -offset);
9033 }
9034 /* Fault if writeback register is in register list. */
9035 if (insn & (1 << rn))
9036 goto illegal_op;
9037 store_reg(s, rn, addr);
9038 } else {
9039 tcg_temp_free_i32(addr);
9040 }
9041 }
9042 }
9043 break;
9044 case 5:
9045
9046 op = (insn >> 21) & 0xf;
9047 if (op == 6) {
9048 /* Halfword pack. */
9049 tmp = load_reg(s, rn);
9050 tmp2 = load_reg(s, rm);
9051 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
9052 if (insn & (1 << 5)) {
9053 /* pkhtb */
9054 if (shift == 0)
9055 shift = 31;
9056 tcg_gen_sari_i32(tmp2, tmp2, shift);
9057 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
9058 tcg_gen_ext16u_i32(tmp2, tmp2);
9059 } else {
9060 /* pkhbt */
9061 if (shift)
9062 tcg_gen_shli_i32(tmp2, tmp2, shift);
9063 tcg_gen_ext16u_i32(tmp, tmp);
9064 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
9065 }
9066 tcg_gen_or_i32(tmp, tmp, tmp2);
9067 tcg_temp_free_i32(tmp2);
9068 store_reg(s, rd, tmp);
9069 } else {
9070 /* Data processing register constant shift. */
9071 if (rn == 15) {
9072 tmp = tcg_temp_new_i32();
9073 tcg_gen_movi_i32(tmp, 0);
9074 } else {
9075 tmp = load_reg(s, rn);
9076 }
9077 tmp2 = load_reg(s, rm);
9078
9079 shiftop = (insn >> 4) & 3;
9080 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
9081 conds = (insn & (1 << 20)) != 0;
9082 logic_cc = (conds && thumb2_logic_op(op));
9083 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
9084 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
9085 goto illegal_op;
9086 tcg_temp_free_i32(tmp2);
9087 if (rd != 15) {
9088 store_reg(s, rd, tmp);
9089 } else {
9090 tcg_temp_free_i32(tmp);
9091 }
9092 }
9093 break;
9094 case 13: /* Misc data processing. */
9095 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
9096 if (op < 4 && (insn & 0xf000) != 0xf000)
9097 goto illegal_op;
9098 switch (op) {
9099 case 0: /* Register controlled shift. */
9100 tmp = load_reg(s, rn);
9101 tmp2 = load_reg(s, rm);
9102 if ((insn & 0x70) != 0)
9103 goto illegal_op;
9104 op = (insn >> 21) & 3;
9105 logic_cc = (insn & (1 << 20)) != 0;
9106 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
9107 if (logic_cc)
9108 gen_logic_CC(tmp);
9109 store_reg_bx(env, s, rd, tmp);
9110 break;
9111 case 1: /* Sign/zero extend. */
9112 tmp = load_reg(s, rm);
9113 shift = (insn >> 4) & 3;
9114 /* ??? In many cases it's not necessary to do a
9115 rotate, a shift is sufficient. */
9116 if (shift != 0)
9117 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
9118 op = (insn >> 20) & 7;
9119 switch (op) {
9120 case 0: gen_sxth(tmp); break;
9121 case 1: gen_uxth(tmp); break;
9122 case 2: gen_sxtb16(tmp); break;
9123 case 3: gen_uxtb16(tmp); break;
9124 case 4: gen_sxtb(tmp); break;
9125 case 5: gen_uxtb(tmp); break;
9126 default: goto illegal_op;
9127 }
9128 if (rn != 15) {
9129 tmp2 = load_reg(s, rn);
9130 if ((op >> 1) == 1) {
9131 gen_add16(tmp, tmp2);
9132 } else {
9133 tcg_gen_add_i32(tmp, tmp, tmp2);
9134 tcg_temp_free_i32(tmp2);
9135 }
9136 }
9137 store_reg(s, rd, tmp);
9138 break;
9139 case 2: /* SIMD add/subtract. */
9140 op = (insn >> 20) & 7;
9141 shift = (insn >> 4) & 7;
9142 if ((op & 3) == 3 || (shift & 3) == 3)
9143 goto illegal_op;
9144 tmp = load_reg(s, rn);
9145 tmp2 = load_reg(s, rm);
9146 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
9147 tcg_temp_free_i32(tmp2);
9148 store_reg(s, rd, tmp);
9149 break;
9150 case 3: /* Other data processing. */
9151 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
9152 if (op < 4) {
9153 /* Saturating add/subtract. */
9154 tmp = load_reg(s, rn);
9155 tmp2 = load_reg(s, rm);
9156 if (op & 1)
9157 gen_helper_double_saturate(tmp, cpu_env, tmp);
9158 if (op & 2)
9159 gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
9160 else
9161 gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
9162 tcg_temp_free_i32(tmp2);
9163 } else {
9164 tmp = load_reg(s, rn);
9165 switch (op) {
9166 case 0x0a: /* rbit */
9167 gen_helper_rbit(tmp, tmp);
9168 break;
9169 case 0x08: /* rev */
9170 tcg_gen_bswap32_i32(tmp, tmp);
9171 break;
9172 case 0x09: /* rev16 */
9173 gen_rev16(tmp);
9174 break;
9175 case 0x0b: /* revsh */
9176 gen_revsh(tmp);
9177 break;
9178 case 0x10: /* sel */
9179 tmp2 = load_reg(s, rm);
9180 tmp3 = tcg_temp_new_i32();
9181 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
9182 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
9183 tcg_temp_free_i32(tmp3);
9184 tcg_temp_free_i32(tmp2);
9185 break;
9186 case 0x18: /* clz */
9187 gen_helper_clz(tmp, tmp);
9188 break;
9189 case 0x20:
9190 case 0x21:
9191 case 0x22:
9192 case 0x28:
9193 case 0x29:
9194 case 0x2a:
9195 {
9196 /* crc32/crc32c */
9197 uint32_t sz = op & 0x3;
9198 uint32_t c = op & 0x8;
9199
9200 if (!arm_feature(env, ARM_FEATURE_CRC)) {
9201 goto illegal_op;
9202 }
9203
9204 tmp2 = load_reg(s, rm);
9205 tmp3 = tcg_const_i32(1 << sz);
9206 if (c) {
9207 gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
9208 } else {
9209 gen_helper_crc32(tmp, tmp, tmp2, tmp3);
9210 }
9211 tcg_temp_free_i32(tmp2);
9212 tcg_temp_free_i32(tmp3);
9213 break;
9214 }
9215 default:
9216 goto illegal_op;
9217 }
9218 }
9219 store_reg(s, rd, tmp);
9220 break;
9221 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
9222 op = (insn >> 4) & 0xf;
9223 tmp = load_reg(s, rn);
9224 tmp2 = load_reg(s, rm);
9225 switch ((insn >> 20) & 7) {
9226 case 0: /* 32 x 32 -> 32 */
9227 tcg_gen_mul_i32(tmp, tmp, tmp2);
9228 tcg_temp_free_i32(tmp2);
9229 if (rs != 15) {
9230 tmp2 = load_reg(s, rs);
9231 if (op)
9232 tcg_gen_sub_i32(tmp, tmp2, tmp);
9233 else
9234 tcg_gen_add_i32(tmp, tmp, tmp2);
9235 tcg_temp_free_i32(tmp2);
9236 }
9237 break;
9238 case 1: /* 16 x 16 -> 32 */
9239 gen_mulxy(tmp, tmp2, op & 2, op & 1);
9240 tcg_temp_free_i32(tmp2);
9241 if (rs != 15) {
9242 tmp2 = load_reg(s, rs);
9243 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
9244 tcg_temp_free_i32(tmp2);
9245 }
9246 break;
9247 case 2: /* Dual multiply add. */
9248 case 4: /* Dual multiply subtract. */
9249 if (op)
9250 gen_swap_half(tmp2);
9251 gen_smul_dual(tmp, tmp2);
9252 if (insn & (1 << 22)) {
9253 /* This subtraction cannot overflow. */
9254 tcg_gen_sub_i32(tmp, tmp, tmp2);
9255 } else {
9256 /* This addition cannot overflow 32 bits;
9257 * however it may overflow considered as a signed
9258 * operation, in which case we must set the Q flag.
9259 */
9260 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
9261 }
9262 tcg_temp_free_i32(tmp2);
9263 if (rs != 15)
9264 {
9265 tmp2 = load_reg(s, rs);
9266 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
9267 tcg_temp_free_i32(tmp2);
9268 }
9269 break;
9270 case 3: /* 32 * 16 -> 32msb */
9271 if (op)
9272 tcg_gen_sari_i32(tmp2, tmp2, 16);
9273 else
9274 gen_sxth(tmp2);
9275 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9276 tcg_gen_shri_i64(tmp64, tmp64, 16);
9277 tmp = tcg_temp_new_i32();
9278 tcg_gen_trunc_i64_i32(tmp, tmp64);
9279 tcg_temp_free_i64(tmp64);
9280 if (rs != 15)
9281 {
9282 tmp2 = load_reg(s, rs);
9283 gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
9284 tcg_temp_free_i32(tmp2);
9285 }
9286 break;
9287 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
9288 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9289 if (rs != 15) {
9290 tmp = load_reg(s, rs);
9291 if (insn & (1 << 20)) {
9292 tmp64 = gen_addq_msw(tmp64, tmp);
9293 } else {
9294 tmp64 = gen_subq_msw(tmp64, tmp);
9295 }
9296 }
9297 if (insn & (1 << 4)) {
9298 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
9299 }
9300 tcg_gen_shri_i64(tmp64, tmp64, 32);
9301 tmp = tcg_temp_new_i32();
9302 tcg_gen_trunc_i64_i32(tmp, tmp64);
9303 tcg_temp_free_i64(tmp64);
9304 break;
9305 case 7: /* Unsigned sum of absolute differences. */
9306 gen_helper_usad8(tmp, tmp, tmp2);
9307 tcg_temp_free_i32(tmp2);
9308 if (rs != 15) {
9309 tmp2 = load_reg(s, rs);
9310 tcg_gen_add_i32(tmp, tmp, tmp2);
9311 tcg_temp_free_i32(tmp2);
9312 }
9313 break;
9314 }
9315 store_reg(s, rd, tmp);
9316 break;
9317 case 6: case 7: /* 64-bit multiply, Divide. */
9318 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
9319 tmp = load_reg(s, rn);
9320 tmp2 = load_reg(s, rm);
9321 if ((op & 0x50) == 0x10) {
9322 /* sdiv, udiv */
9323 if (!arm_feature(env, ARM_FEATURE_THUMB_DIV)) {
9324 goto illegal_op;
9325 }
9326 if (op & 0x20)
9327 gen_helper_udiv(tmp, tmp, tmp2);
9328 else
9329 gen_helper_sdiv(tmp, tmp, tmp2);
9330 tcg_temp_free_i32(tmp2);
9331 store_reg(s, rd, tmp);
9332 } else if ((op & 0xe) == 0xc) {
9333 /* Dual multiply accumulate long. */
9334 if (op & 1)
9335 gen_swap_half(tmp2);
9336 gen_smul_dual(tmp, tmp2);
9337 if (op & 0x10) {
9338 tcg_gen_sub_i32(tmp, tmp, tmp2);
9339 } else {
9340 tcg_gen_add_i32(tmp, tmp, tmp2);
9341 }
9342 tcg_temp_free_i32(tmp2);
9343 /* BUGFIX */
9344 tmp64 = tcg_temp_new_i64();
9345 tcg_gen_ext_i32_i64(tmp64, tmp);
9346 tcg_temp_free_i32(tmp);
9347 gen_addq(s, tmp64, rs, rd);
9348 gen_storeq_reg(s, rs, rd, tmp64);
9349 tcg_temp_free_i64(tmp64);
9350 } else {
9351 if (op & 0x20) {
9352 /* Unsigned 64-bit multiply */
9353 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
9354 } else {
9355 if (op & 8) {
9356 /* smlalxy */
9357 gen_mulxy(tmp, tmp2, op & 2, op & 1);
9358 tcg_temp_free_i32(tmp2);
9359 tmp64 = tcg_temp_new_i64();
9360 tcg_gen_ext_i32_i64(tmp64, tmp);
9361 tcg_temp_free_i32(tmp);
9362 } else {
9363 /* Signed 64-bit multiply */
9364 tmp64 = gen_muls_i64_i32(tmp, tmp2);
9365 }
9366 }
9367 if (op & 4) {
9368 /* umaal */
9369 gen_addq_lo(s, tmp64, rs);
9370 gen_addq_lo(s, tmp64, rd);
9371 } else if (op & 0x40) {
9372 /* 64-bit accumulate. */
9373 gen_addq(s, tmp64, rs, rd);
9374 }
9375 gen_storeq_reg(s, rs, rd, tmp64);
9376 tcg_temp_free_i64(tmp64);
9377 }
9378 break;
9379 }
9380 break;
9381 case 6: case 7: case 14: case 15:
9382 /* Coprocessor. */
9383 if (((insn >> 24) & 3) == 3) {
9384 /* Translate into the equivalent ARM encoding. */
9385 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
9386 if (disas_neon_data_insn(env, s, insn))
9387 goto illegal_op;
9388 } else if (((insn >> 8) & 0xe) == 10) {
9389 if (disas_vfp_insn(env, s, insn)) {
9390 goto illegal_op;
9391 }
9392 } else {
9393 if (insn & (1 << 28))
9394 goto illegal_op;
9395 if (disas_coproc_insn (env, s, insn))
9396 goto illegal_op;
9397 }
9398 break;
9399 case 8: case 9: case 10: case 11:
9400 if (insn & (1 << 15)) {
9401 /* Branches, misc control. */
9402 if (insn & 0x5000) {
9403 /* Unconditional branch. */
9404 /* signextend(hw1[10:0]) -> offset[:12]. */
9405 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
9406 /* hw1[10:0] -> offset[11:1]. */
9407 offset |= (insn & 0x7ff) << 1;
9408 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
9409 offset[24:22] already have the same value because of the
9410 sign extension above. */
9411 offset ^= ((~insn) & (1 << 13)) << 10;
9412 offset ^= ((~insn) & (1 << 11)) << 11;
9413
9414 if (insn & (1 << 14)) {
9415 /* Branch and link. */
9416 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
9417 }
9418
9419 offset += s->pc;
9420 if (insn & (1 << 12)) {
9421 /* b/bl */
9422 gen_jmp(s, offset);
9423 } else {
9424 /* blx */
9425 offset &= ~(uint32_t)2;
9426 /* thumb2 bx, no need to check */
9427 gen_bx_im(s, offset);
9428 }
9429 } else if (((insn >> 23) & 7) == 7) {
9430 /* Misc control */
9431 if (insn & (1 << 13))
9432 goto illegal_op;
9433
9434 if (insn & (1 << 26)) {
9435 /* Secure monitor call (v6Z) */
9436 qemu_log_mask(LOG_UNIMP,
9437 "arm: unimplemented secure monitor call\n");
9438 goto illegal_op; /* not implemented. */
9439 } else {
9440 op = (insn >> 20) & 7;
9441 switch (op) {
9442 case 0: /* msr cpsr. */
9443 if (IS_M(env)) {
9444 tmp = load_reg(s, rn);
9445 addr = tcg_const_i32(insn & 0xff);
9446 gen_helper_v7m_msr(cpu_env, addr, tmp);
9447 tcg_temp_free_i32(addr);
9448 tcg_temp_free_i32(tmp);
9449 gen_lookup_tb(s);
9450 break;
9451 }
9452 /* fall through */
9453 case 1: /* msr spsr. */
9454 if (IS_M(env))
9455 goto illegal_op;
9456 tmp = load_reg(s, rn);
9457 if (gen_set_psr(s,
9458 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
9459 op == 1, tmp))
9460 goto illegal_op;
9461 break;
9462 case 2: /* cps, nop-hint. */
9463 if (((insn >> 8) & 7) == 0) {
9464 gen_nop_hint(s, insn & 0xff);
9465 }
9466 /* Implemented as NOP in user mode. */
9467 if (IS_USER(s))
9468 break;
9469 offset = 0;
9470 imm = 0;
9471 if (insn & (1 << 10)) {
9472 if (insn & (1 << 7))
9473 offset |= CPSR_A;
9474 if (insn & (1 << 6))
9475 offset |= CPSR_I;
9476 if (insn & (1 << 5))
9477 offset |= CPSR_F;
9478 if (insn & (1 << 9))
9479 imm = CPSR_A | CPSR_I | CPSR_F;
9480 }
9481 if (insn & (1 << 8)) {
9482 offset |= 0x1f;
9483 imm |= (insn & 0x1f);
9484 }
9485 if (offset) {
9486 gen_set_psr_im(s, offset, 0, imm);
9487 }
9488 break;
9489 case 3: /* Special control operations. */
9490 ARCH(7);
9491 op = (insn >> 4) & 0xf;
9492 switch (op) {
9493 case 2: /* clrex */
9494 gen_clrex(s);
9495 break;
9496 case 4: /* dsb */
9497 case 5: /* dmb */
9498 case 6: /* isb */
9499 /* These execute as NOPs. */
9500 break;
9501 default:
9502 goto illegal_op;
9503 }
9504 break;
9505 case 4: /* bxj */
9506 /* Trivial implementation equivalent to bx. */
9507 tmp = load_reg(s, rn);
9508 gen_bx(s, tmp);
9509 break;
9510 case 5: /* Exception return. */
9511 if (IS_USER(s)) {
9512 goto illegal_op;
9513 }
9514 if (rn != 14 || rd != 15) {
9515 goto illegal_op;
9516 }
9517 tmp = load_reg(s, rn);
9518 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
9519 gen_exception_return(s, tmp);
9520 break;
9521 case 6: /* mrs cpsr. */
9522 tmp = tcg_temp_new_i32();
9523 if (IS_M(env)) {
9524 addr = tcg_const_i32(insn & 0xff);
9525 gen_helper_v7m_mrs(tmp, cpu_env, addr);
9526 tcg_temp_free_i32(addr);
9527 } else {
9528 gen_helper_cpsr_read(tmp, cpu_env);
9529 }
9530 store_reg(s, rd, tmp);
9531 break;
9532 case 7: /* mrs spsr. */
9533 /* Not accessible in user mode. */
9534 if (IS_USER(s) || IS_M(env))
9535 goto illegal_op;
9536 tmp = load_cpu_field(spsr);
9537 store_reg(s, rd, tmp);
9538 break;
9539 }
9540 }
9541 } else {
9542 /* Conditional branch. */
9543 op = (insn >> 22) & 0xf;
9544 /* Generate a conditional jump to next instruction. */
9545 s->condlabel = gen_new_label();
9546 arm_gen_test_cc(op ^ 1, s->condlabel);
9547 s->condjmp = 1;
9548
9549 /* offset[11:1] = insn[10:0] */
9550 offset = (insn & 0x7ff) << 1;
9551 /* offset[17:12] = insn[21:16]. */
9552 offset |= (insn & 0x003f0000) >> 4;
9553 /* offset[31:20] = insn[26]. */
9554 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
9555 /* offset[18] = insn[13]. */
9556 offset |= (insn & (1 << 13)) << 5;
9557 /* offset[19] = insn[11]. */
9558 offset |= (insn & (1 << 11)) << 8;
9559
9560 /* jump to the offset */
9561 gen_jmp(s, s->pc + offset);
9562 }
9563 } else {
9564 /* Data processing immediate. */
9565 if (insn & (1 << 25)) {
9566 if (insn & (1 << 24)) {
9567 if (insn & (1 << 20))
9568 goto illegal_op;
9569 /* Bitfield/Saturate. */
9570 op = (insn >> 21) & 7;
9571 imm = insn & 0x1f;
9572 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
9573 if (rn == 15) {
9574 tmp = tcg_temp_new_i32();
9575 tcg_gen_movi_i32(tmp, 0);
9576 } else {
9577 tmp = load_reg(s, rn);
9578 }
9579 switch (op) {
9580 case 2: /* Signed bitfield extract. */
9581 imm++;
9582 if (shift + imm > 32)
9583 goto illegal_op;
9584 if (imm < 32)
9585 gen_sbfx(tmp, shift, imm);
9586 break;
9587 case 6: /* Unsigned bitfield extract. */
9588 imm++;
9589 if (shift + imm > 32)
9590 goto illegal_op;
9591 if (imm < 32)
9592 gen_ubfx(tmp, shift, (1u << imm) - 1);
9593 break;
9594 case 3: /* Bitfield insert/clear. */
9595 if (imm < shift)
9596 goto illegal_op;
9597 imm = imm + 1 - shift;
9598 if (imm != 32) {
9599 tmp2 = load_reg(s, rd);
9600 tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm);
9601 tcg_temp_free_i32(tmp2);
9602 }
9603 break;
9604 case 7:
9605 goto illegal_op;
9606 default: /* Saturate. */
9607 if (shift) {
9608 if (op & 1)
9609 tcg_gen_sari_i32(tmp, tmp, shift);
9610 else
9611 tcg_gen_shli_i32(tmp, tmp, shift);
9612 }
9613 tmp2 = tcg_const_i32(imm);
9614 if (op & 4) {
9615 /* Unsigned. */
9616 if ((op & 1) && shift == 0)
9617 gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
9618 else
9619 gen_helper_usat(tmp, cpu_env, tmp, tmp2);
9620 } else {
9621 /* Signed. */
9622 if ((op & 1) && shift == 0)
9623 gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
9624 else
9625 gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
9626 }
9627 tcg_temp_free_i32(tmp2);
9628 break;
9629 }
9630 store_reg(s, rd, tmp);
9631 } else {
9632 imm = ((insn & 0x04000000) >> 15)
9633 | ((insn & 0x7000) >> 4) | (insn & 0xff);
9634 if (insn & (1 << 22)) {
9635 /* 16-bit immediate. */
9636 imm |= (insn >> 4) & 0xf000;
9637 if (insn & (1 << 23)) {
9638 /* movt */
9639 tmp = load_reg(s, rd);
9640 tcg_gen_ext16u_i32(tmp, tmp);
9641 tcg_gen_ori_i32(tmp, tmp, imm << 16);
9642 } else {
9643 /* movw */
9644 tmp = tcg_temp_new_i32();
9645 tcg_gen_movi_i32(tmp, imm);
9646 }
9647 } else {
9648 /* Add/sub 12-bit immediate. */
9649 if (rn == 15) {
9650 offset = s->pc & ~(uint32_t)3;
9651 if (insn & (1 << 23))
9652 offset -= imm;
9653 else
9654 offset += imm;
9655 tmp = tcg_temp_new_i32();
9656 tcg_gen_movi_i32(tmp, offset);
9657 } else {
9658 tmp = load_reg(s, rn);
9659 if (insn & (1 << 23))
9660 tcg_gen_subi_i32(tmp, tmp, imm);
9661 else
9662 tcg_gen_addi_i32(tmp, tmp, imm);
9663 }
9664 }
9665 store_reg(s, rd, tmp);
9666 }
9667 } else {
9668 int shifter_out = 0;
9669 /* modified 12-bit immediate. */
9670 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
9671 imm = (insn & 0xff);
9672 switch (shift) {
9673 case 0: /* XY */
9674 /* Nothing to do. */
9675 break;
9676 case 1: /* 00XY00XY */
9677 imm |= imm << 16;
9678 break;
9679 case 2: /* XY00XY00 */
9680 imm |= imm << 16;
9681 imm <<= 8;
9682 break;
9683 case 3: /* XYXYXYXY */
9684 imm |= imm << 16;
9685 imm |= imm << 8;
9686 break;
9687 default: /* Rotated constant. */
9688 shift = (shift << 1) | (imm >> 7);
9689 imm |= 0x80;
9690 imm = imm << (32 - shift);
9691 shifter_out = 1;
9692 break;
9693 }
9694 tmp2 = tcg_temp_new_i32();
9695 tcg_gen_movi_i32(tmp2, imm);
9696 rn = (insn >> 16) & 0xf;
9697 if (rn == 15) {
9698 tmp = tcg_temp_new_i32();
9699 tcg_gen_movi_i32(tmp, 0);
9700 } else {
9701 tmp = load_reg(s, rn);
9702 }
9703 op = (insn >> 21) & 0xf;
9704 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
9705 shifter_out, tmp, tmp2))
9706 goto illegal_op;
9707 tcg_temp_free_i32(tmp2);
9708 rd = (insn >> 8) & 0xf;
9709 if (rd != 15) {
9710 store_reg(s, rd, tmp);
9711 } else {
9712 tcg_temp_free_i32(tmp);
9713 }
9714 }
9715 }
9716 break;
9717 case 12: /* Load/store single data item. */
9718 {
9719 int postinc = 0;
9720 int writeback = 0;
9721 int user;
9722 if ((insn & 0x01100000) == 0x01000000) {
9723 if (disas_neon_ls_insn(env, s, insn))
9724 goto illegal_op;
9725 break;
9726 }
9727 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
9728 if (rs == 15) {
9729 if (!(insn & (1 << 20))) {
9730 goto illegal_op;
9731 }
9732 if (op != 2) {
9733 /* Byte or halfword load space with dest == r15 : memory hints.
9734 * Catch them early so we don't emit pointless addressing code.
9735 * This space is a mix of:
9736 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
9737 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
9738 * cores)
9739 * unallocated hints, which must be treated as NOPs
9740 * UNPREDICTABLE space, which we NOP or UNDEF depending on
9741 * which is easiest for the decoding logic
9742 * Some space which must UNDEF
9743 */
9744 int op1 = (insn >> 23) & 3;
9745 int op2 = (insn >> 6) & 0x3f;
9746 if (op & 2) {
9747 goto illegal_op;
9748 }
9749 if (rn == 15) {
9750 /* UNPREDICTABLE, unallocated hint or
9751 * PLD/PLDW/PLI (literal)
9752 */
9753 return 0;
9754 }
9755 if (op1 & 1) {
9756 return 0; /* PLD/PLDW/PLI or unallocated hint */
9757 }
9758 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
9759 return 0; /* PLD/PLDW/PLI or unallocated hint */
9760 }
9761 /* UNDEF space, or an UNPREDICTABLE */
9762 return 1;
9763 }
9764 }
9765 user = IS_USER(s);
9766 if (rn == 15) {
9767 addr = tcg_temp_new_i32();
9768 /* PC relative. */
9769 /* s->pc has already been incremented by 4. */
9770 imm = s->pc & 0xfffffffc;
9771 if (insn & (1 << 23))
9772 imm += insn & 0xfff;
9773 else
9774 imm -= insn & 0xfff;
9775 tcg_gen_movi_i32(addr, imm);
9776 } else {
9777 addr = load_reg(s, rn);
9778 if (insn & (1 << 23)) {
9779 /* Positive offset. */
9780 imm = insn & 0xfff;
9781 tcg_gen_addi_i32(addr, addr, imm);
9782 } else {
9783 imm = insn & 0xff;
9784 switch ((insn >> 8) & 0xf) {
9785 case 0x0: /* Shifted Register. */
9786 shift = (insn >> 4) & 0xf;
9787 if (shift > 3) {
9788 tcg_temp_free_i32(addr);
9789 goto illegal_op;
9790 }
9791 tmp = load_reg(s, rm);
9792 if (shift)
9793 tcg_gen_shli_i32(tmp, tmp, shift);
9794 tcg_gen_add_i32(addr, addr, tmp);
9795 tcg_temp_free_i32(tmp);
9796 break;
9797 case 0xc: /* Negative offset. */
9798 tcg_gen_addi_i32(addr, addr, -imm);
9799 break;
9800 case 0xe: /* User privilege. */
9801 tcg_gen_addi_i32(addr, addr, imm);
9802 user = 1;
9803 break;
9804 case 0x9: /* Post-decrement. */
9805 imm = -imm;
9806 /* Fall through. */
9807 case 0xb: /* Post-increment. */
9808 postinc = 1;
9809 writeback = 1;
9810 break;
9811 case 0xd: /* Pre-decrement. */
9812 imm = -imm;
9813 /* Fall through. */
9814 case 0xf: /* Pre-increment. */
9815 tcg_gen_addi_i32(addr, addr, imm);
9816 writeback = 1;
9817 break;
9818 default:
9819 tcg_temp_free_i32(addr);
9820 goto illegal_op;
9821 }
9822 }
9823 }
9824 if (insn & (1 << 20)) {
9825 /* Load. */
9826 tmp = tcg_temp_new_i32();
9827 switch (op) {
9828 case 0:
9829 gen_aa32_ld8u(tmp, addr, user);
9830 break;
9831 case 4:
9832 gen_aa32_ld8s(tmp, addr, user);
9833 break;
9834 case 1:
9835 gen_aa32_ld16u(tmp, addr, user);
9836 break;
9837 case 5:
9838 gen_aa32_ld16s(tmp, addr, user);
9839 break;
9840 case 2:
9841 gen_aa32_ld32u(tmp, addr, user);
9842 break;
9843 default:
9844 tcg_temp_free_i32(tmp);
9845 tcg_temp_free_i32(addr);
9846 goto illegal_op;
9847 }
9848 if (rs == 15) {
9849 gen_bx(s, tmp);
9850 } else {
9851 store_reg(s, rs, tmp);
9852 }
9853 } else {
9854 /* Store. */
9855 tmp = load_reg(s, rs);
9856 switch (op) {
9857 case 0:
9858 gen_aa32_st8(tmp, addr, user);
9859 break;
9860 case 1:
9861 gen_aa32_st16(tmp, addr, user);
9862 break;
9863 case 2:
9864 gen_aa32_st32(tmp, addr, user);
9865 break;
9866 default:
9867 tcg_temp_free_i32(tmp);
9868 tcg_temp_free_i32(addr);
9869 goto illegal_op;
9870 }
9871 tcg_temp_free_i32(tmp);
9872 }
9873 if (postinc)
9874 tcg_gen_addi_i32(addr, addr, imm);
9875 if (writeback) {
9876 store_reg(s, rn, addr);
9877 } else {
9878 tcg_temp_free_i32(addr);
9879 }
9880 }
9881 break;
9882 default:
9883 goto illegal_op;
9884 }
9885 return 0;
9886 illegal_op:
9887 return 1;
9888 }
9889
9890 static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
9891 {
9892 uint32_t val, insn, op, rm, rn, rd, shift, cond;
9893 int32_t offset;
9894 int i;
9895 TCGv_i32 tmp;
9896 TCGv_i32 tmp2;
9897 TCGv_i32 addr;
9898
9899 if (s->condexec_mask) {
9900 cond = s->condexec_cond;
9901 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
9902 s->condlabel = gen_new_label();
9903 arm_gen_test_cc(cond ^ 1, s->condlabel);
9904 s->condjmp = 1;
9905 }
9906 }
9907
9908 insn = arm_lduw_code(env, s->pc, s->bswap_code);
9909 s->pc += 2;
9910
9911 switch (insn >> 12) {
9912 case 0: case 1:
9913
9914 rd = insn & 7;
9915 op = (insn >> 11) & 3;
9916 if (op == 3) {
9917 /* add/subtract */
9918 rn = (insn >> 3) & 7;
9919 tmp = load_reg(s, rn);
9920 if (insn & (1 << 10)) {
9921 /* immediate */
9922 tmp2 = tcg_temp_new_i32();
9923 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
9924 } else {
9925 /* reg */
9926 rm = (insn >> 6) & 7;
9927 tmp2 = load_reg(s, rm);
9928 }
9929 if (insn & (1 << 9)) {
9930 if (s->condexec_mask)
9931 tcg_gen_sub_i32(tmp, tmp, tmp2);
9932 else
9933 gen_sub_CC(tmp, tmp, tmp2);
9934 } else {
9935 if (s->condexec_mask)
9936 tcg_gen_add_i32(tmp, tmp, tmp2);
9937 else
9938 gen_add_CC(tmp, tmp, tmp2);
9939 }
9940 tcg_temp_free_i32(tmp2);
9941 store_reg(s, rd, tmp);
9942 } else {
9943 /* shift immediate */
9944 rm = (insn >> 3) & 7;
9945 shift = (insn >> 6) & 0x1f;
9946 tmp = load_reg(s, rm);
9947 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
9948 if (!s->condexec_mask)
9949 gen_logic_CC(tmp);
9950 store_reg(s, rd, tmp);
9951 }
9952 break;
9953 case 2: case 3:
9954 /* arithmetic large immediate */
9955 op = (insn >> 11) & 3;
9956 rd = (insn >> 8) & 0x7;
9957 if (op == 0) { /* mov */
9958 tmp = tcg_temp_new_i32();
9959 tcg_gen_movi_i32(tmp, insn & 0xff);
9960 if (!s->condexec_mask)
9961 gen_logic_CC(tmp);
9962 store_reg(s, rd, tmp);
9963 } else {
9964 tmp = load_reg(s, rd);
9965 tmp2 = tcg_temp_new_i32();
9966 tcg_gen_movi_i32(tmp2, insn & 0xff);
9967 switch (op) {
9968 case 1: /* cmp */
9969 gen_sub_CC(tmp, tmp, tmp2);
9970 tcg_temp_free_i32(tmp);
9971 tcg_temp_free_i32(tmp2);
9972 break;
9973 case 2: /* add */
9974 if (s->condexec_mask)
9975 tcg_gen_add_i32(tmp, tmp, tmp2);
9976 else
9977 gen_add_CC(tmp, tmp, tmp2);
9978 tcg_temp_free_i32(tmp2);
9979 store_reg(s, rd, tmp);
9980 break;
9981 case 3: /* sub */
9982 if (s->condexec_mask)
9983 tcg_gen_sub_i32(tmp, tmp, tmp2);
9984 else
9985 gen_sub_CC(tmp, tmp, tmp2);
9986 tcg_temp_free_i32(tmp2);
9987 store_reg(s, rd, tmp);
9988 break;
9989 }
9990 }
9991 break;
9992 case 4:
9993 if (insn & (1 << 11)) {
9994 rd = (insn >> 8) & 7;
9995 /* load pc-relative. Bit 1 of PC is ignored. */
9996 val = s->pc + 2 + ((insn & 0xff) * 4);
9997 val &= ~(uint32_t)2;
9998 addr = tcg_temp_new_i32();
9999 tcg_gen_movi_i32(addr, val);
10000 tmp = tcg_temp_new_i32();
10001 gen_aa32_ld32u(tmp, addr, IS_USER(s));
10002 tcg_temp_free_i32(addr);
10003 store_reg(s, rd, tmp);
10004 break;
10005 }
10006 if (insn & (1 << 10)) {
10007 /* data processing extended or blx */
10008 rd = (insn & 7) | ((insn >> 4) & 8);
10009 rm = (insn >> 3) & 0xf;
10010 op = (insn >> 8) & 3;
10011 switch (op) {
10012 case 0: /* add */
10013 tmp = load_reg(s, rd);
10014 tmp2 = load_reg(s, rm);
10015 tcg_gen_add_i32(tmp, tmp, tmp2);
10016 tcg_temp_free_i32(tmp2);
10017 store_reg(s, rd, tmp);
10018 break;
10019 case 1: /* cmp */
10020 tmp = load_reg(s, rd);
10021 tmp2 = load_reg(s, rm);
10022 gen_sub_CC(tmp, tmp, tmp2);
10023 tcg_temp_free_i32(tmp2);
10024 tcg_temp_free_i32(tmp);
10025 break;
10026 case 2: /* mov/cpy */
10027 tmp = load_reg(s, rm);
10028 store_reg(s, rd, tmp);
10029 break;
10030 case 3:/* branch [and link] exchange thumb register */
10031 tmp = load_reg(s, rm);
10032 if (insn & (1 << 7)) {
10033 ARCH(5);
10034 val = (uint32_t)s->pc | 1;
10035 tmp2 = tcg_temp_new_i32();
10036 tcg_gen_movi_i32(tmp2, val);
10037 store_reg(s, 14, tmp2);
10038 }
10039 /* already thumb, no need to check */
10040 gen_bx(s, tmp);
10041 break;
10042 }
10043 break;
10044 }
10045
10046 /* data processing register */
10047 rd = insn & 7;
10048 rm = (insn >> 3) & 7;
10049 op = (insn >> 6) & 0xf;
10050 if (op == 2 || op == 3 || op == 4 || op == 7) {
10051 /* the shift/rotate ops want the operands backwards */
10052 val = rm;
10053 rm = rd;
10054 rd = val;
10055 val = 1;
10056 } else {
10057 val = 0;
10058 }
10059
10060 if (op == 9) { /* neg */
10061 tmp = tcg_temp_new_i32();
10062 tcg_gen_movi_i32(tmp, 0);
10063 } else if (op != 0xf) { /* mvn doesn't read its first operand */
10064 tmp = load_reg(s, rd);
10065 } else {
10066 TCGV_UNUSED_I32(tmp);
10067 }
10068
10069 tmp2 = load_reg(s, rm);
10070 switch (op) {
10071 case 0x0: /* and */
10072 tcg_gen_and_i32(tmp, tmp, tmp2);
10073 if (!s->condexec_mask)
10074 gen_logic_CC(tmp);
10075 break;
10076 case 0x1: /* eor */
10077 tcg_gen_xor_i32(tmp, tmp, tmp2);
10078 if (!s->condexec_mask)
10079 gen_logic_CC(tmp);
10080 break;
10081 case 0x2: /* lsl */
10082 if (s->condexec_mask) {
10083 gen_shl(tmp2, tmp2, tmp);
10084 } else {
10085 gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
10086 gen_logic_CC(tmp2);
10087 }
10088 break;
10089 case 0x3: /* lsr */
10090 if (s->condexec_mask) {
10091 gen_shr(tmp2, tmp2, tmp);
10092 } else {
10093 gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
10094 gen_logic_CC(tmp2);
10095 }
10096 break;
10097 case 0x4: /* asr */
10098 if (s->condexec_mask) {
10099 gen_sar(tmp2, tmp2, tmp);
10100 } else {
10101 gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
10102 gen_logic_CC(tmp2);
10103 }
10104 break;
10105 case 0x5: /* adc */
10106 if (s->condexec_mask) {
10107 gen_adc(tmp, tmp2);
10108 } else {
10109 gen_adc_CC(tmp, tmp, tmp2);
10110 }
10111 break;
10112 case 0x6: /* sbc */
10113 if (s->condexec_mask) {
10114 gen_sub_carry(tmp, tmp, tmp2);
10115 } else {
10116 gen_sbc_CC(tmp, tmp, tmp2);
10117 }
10118 break;
10119 case 0x7: /* ror */
10120 if (s->condexec_mask) {
10121 tcg_gen_andi_i32(tmp, tmp, 0x1f);
10122 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
10123 } else {
10124 gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
10125 gen_logic_CC(tmp2);
10126 }
10127 break;
10128 case 0x8: /* tst */
10129 tcg_gen_and_i32(tmp, tmp, tmp2);
10130 gen_logic_CC(tmp);
10131 rd = 16;
10132 break;
10133 case 0x9: /* neg */
10134 if (s->condexec_mask)
10135 tcg_gen_neg_i32(tmp, tmp2);
10136 else
10137 gen_sub_CC(tmp, tmp, tmp2);
10138 break;
10139 case 0xa: /* cmp */
10140 gen_sub_CC(tmp, tmp, tmp2);
10141 rd = 16;
10142 break;
10143 case 0xb: /* cmn */
10144 gen_add_CC(tmp, tmp, tmp2);
10145 rd = 16;
10146 break;
10147 case 0xc: /* orr */
10148 tcg_gen_or_i32(tmp, tmp, tmp2);
10149 if (!s->condexec_mask)
10150 gen_logic_CC(tmp);
10151 break;
10152 case 0xd: /* mul */
10153 tcg_gen_mul_i32(tmp, tmp, tmp2);
10154 if (!s->condexec_mask)
10155 gen_logic_CC(tmp);
10156 break;
10157 case 0xe: /* bic */
10158 tcg_gen_andc_i32(tmp, tmp, tmp2);
10159 if (!s->condexec_mask)
10160 gen_logic_CC(tmp);
10161 break;
10162 case 0xf: /* mvn */
10163 tcg_gen_not_i32(tmp2, tmp2);
10164 if (!s->condexec_mask)
10165 gen_logic_CC(tmp2);
10166 val = 1;
10167 rm = rd;
10168 break;
10169 }
10170 if (rd != 16) {
10171 if (val) {
10172 store_reg(s, rm, tmp2);
10173 if (op != 0xf)
10174 tcg_temp_free_i32(tmp);
10175 } else {
10176 store_reg(s, rd, tmp);
10177 tcg_temp_free_i32(tmp2);
10178 }
10179 } else {
10180 tcg_temp_free_i32(tmp);
10181 tcg_temp_free_i32(tmp2);
10182 }
10183 break;
10184
10185 case 5:
10186 /* load/store register offset. */
10187 rd = insn & 7;
10188 rn = (insn >> 3) & 7;
10189 rm = (insn >> 6) & 7;
10190 op = (insn >> 9) & 7;
10191 addr = load_reg(s, rn);
10192 tmp = load_reg(s, rm);
10193 tcg_gen_add_i32(addr, addr, tmp);
10194 tcg_temp_free_i32(tmp);
10195
10196 if (op < 3) { /* store */
10197 tmp = load_reg(s, rd);
10198 } else {
10199 tmp = tcg_temp_new_i32();
10200 }
10201
10202 switch (op) {
10203 case 0: /* str */
10204 gen_aa32_st32(tmp, addr, IS_USER(s));
10205 break;
10206 case 1: /* strh */
10207 gen_aa32_st16(tmp, addr, IS_USER(s));
10208 break;
10209 case 2: /* strb */
10210 gen_aa32_st8(tmp, addr, IS_USER(s));
10211 break;
10212 case 3: /* ldrsb */
10213 gen_aa32_ld8s(tmp, addr, IS_USER(s));
10214 break;
10215 case 4: /* ldr */
10216 gen_aa32_ld32u(tmp, addr, IS_USER(s));
10217 break;
10218 case 5: /* ldrh */
10219 gen_aa32_ld16u(tmp, addr, IS_USER(s));
10220 break;
10221 case 6: /* ldrb */
10222 gen_aa32_ld8u(tmp, addr, IS_USER(s));
10223 break;
10224 case 7: /* ldrsh */
10225 gen_aa32_ld16s(tmp, addr, IS_USER(s));
10226 break;
10227 }
10228 if (op >= 3) { /* load */
10229 store_reg(s, rd, tmp);
10230 } else {
10231 tcg_temp_free_i32(tmp);
10232 }
10233 tcg_temp_free_i32(addr);
10234 break;
10235
10236 case 6:
10237 /* load/store word immediate offset */
10238 rd = insn & 7;
10239 rn = (insn >> 3) & 7;
10240 addr = load_reg(s, rn);
10241 val = (insn >> 4) & 0x7c;
10242 tcg_gen_addi_i32(addr, addr, val);
10243
10244 if (insn & (1 << 11)) {
10245 /* load */
10246 tmp = tcg_temp_new_i32();
10247 gen_aa32_ld32u(tmp, addr, IS_USER(s));
10248 store_reg(s, rd, tmp);
10249 } else {
10250 /* store */
10251 tmp = load_reg(s, rd);
10252 gen_aa32_st32(tmp, addr, IS_USER(s));
10253 tcg_temp_free_i32(tmp);
10254 }
10255 tcg_temp_free_i32(addr);
10256 break;
10257
10258 case 7:
10259 /* load/store byte immediate offset */
10260 rd = insn & 7;
10261 rn = (insn >> 3) & 7;
10262 addr = load_reg(s, rn);
10263 val = (insn >> 6) & 0x1f;
10264 tcg_gen_addi_i32(addr, addr, val);
10265
10266 if (insn & (1 << 11)) {
10267 /* load */
10268 tmp = tcg_temp_new_i32();
10269 gen_aa32_ld8u(tmp, addr, IS_USER(s));
10270 store_reg(s, rd, tmp);
10271 } else {
10272 /* store */
10273 tmp = load_reg(s, rd);
10274 gen_aa32_st8(tmp, addr, IS_USER(s));
10275 tcg_temp_free_i32(tmp);
10276 }
10277 tcg_temp_free_i32(addr);
10278 break;
10279
10280 case 8:
10281 /* load/store halfword immediate offset */
10282 rd = insn & 7;
10283 rn = (insn >> 3) & 7;
10284 addr = load_reg(s, rn);
10285 val = (insn >> 5) & 0x3e;
10286 tcg_gen_addi_i32(addr, addr, val);
10287
10288 if (insn & (1 << 11)) {
10289 /* load */
10290 tmp = tcg_temp_new_i32();
10291 gen_aa32_ld16u(tmp, addr, IS_USER(s));
10292 store_reg(s, rd, tmp);
10293 } else {
10294 /* store */
10295 tmp = load_reg(s, rd);
10296 gen_aa32_st16(tmp, addr, IS_USER(s));
10297 tcg_temp_free_i32(tmp);
10298 }
10299 tcg_temp_free_i32(addr);
10300 break;
10301
10302 case 9:
10303 /* load/store from stack */
10304 rd = (insn >> 8) & 7;
10305 addr = load_reg(s, 13);
10306 val = (insn & 0xff) * 4;
10307 tcg_gen_addi_i32(addr, addr, val);
10308
10309 if (insn & (1 << 11)) {
10310 /* load */
10311 tmp = tcg_temp_new_i32();
10312 gen_aa32_ld32u(tmp, addr, IS_USER(s));
10313 store_reg(s, rd, tmp);
10314 } else {
10315 /* store */
10316 tmp = load_reg(s, rd);
10317 gen_aa32_st32(tmp, addr, IS_USER(s));
10318 tcg_temp_free_i32(tmp);
10319 }
10320 tcg_temp_free_i32(addr);
10321 break;
10322
10323 case 10:
10324 /* add to high reg */
10325 rd = (insn >> 8) & 7;
10326 if (insn & (1 << 11)) {
10327 /* SP */
10328 tmp = load_reg(s, 13);
10329 } else {
10330 /* PC. bit 1 is ignored. */
10331 tmp = tcg_temp_new_i32();
10332 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
10333 }
10334 val = (insn & 0xff) * 4;
10335 tcg_gen_addi_i32(tmp, tmp, val);
10336 store_reg(s, rd, tmp);
10337 break;
10338
10339 case 11:
10340 /* misc */
10341 op = (insn >> 8) & 0xf;
10342 switch (op) {
10343 case 0:
10344 /* adjust stack pointer */
10345 tmp = load_reg(s, 13);
10346 val = (insn & 0x7f) * 4;
10347 if (insn & (1 << 7))
10348 val = -(int32_t)val;
10349 tcg_gen_addi_i32(tmp, tmp, val);
10350 store_reg(s, 13, tmp);
10351 break;
10352
10353 case 2: /* sign/zero extend. */
10354 ARCH(6);
10355 rd = insn & 7;
10356 rm = (insn >> 3) & 7;
10357 tmp = load_reg(s, rm);
10358 switch ((insn >> 6) & 3) {
10359 case 0: gen_sxth(tmp); break;
10360 case 1: gen_sxtb(tmp); break;
10361 case 2: gen_uxth(tmp); break;
10362 case 3: gen_uxtb(tmp); break;
10363 }
10364 store_reg(s, rd, tmp);
10365 break;
10366 case 4: case 5: case 0xc: case 0xd:
10367 /* push/pop */
10368 addr = load_reg(s, 13);
10369 if (insn & (1 << 8))
10370 offset = 4;
10371 else
10372 offset = 0;
10373 for (i = 0; i < 8; i++) {
10374 if (insn & (1 << i))
10375 offset += 4;
10376 }
10377 if ((insn & (1 << 11)) == 0) {
10378 tcg_gen_addi_i32(addr, addr, -offset);
10379 }
10380 for (i = 0; i < 8; i++) {
10381 if (insn & (1 << i)) {
10382 if (insn & (1 << 11)) {
10383 /* pop */
10384 tmp = tcg_temp_new_i32();
10385 gen_aa32_ld32u(tmp, addr, IS_USER(s));
10386 store_reg(s, i, tmp);
10387 } else {
10388 /* push */
10389 tmp = load_reg(s, i);
10390 gen_aa32_st32(tmp, addr, IS_USER(s));
10391 tcg_temp_free_i32(tmp);
10392 }
10393 /* advance to the next address. */
10394 tcg_gen_addi_i32(addr, addr, 4);
10395 }
10396 }
10397 TCGV_UNUSED_I32(tmp);
10398 if (insn & (1 << 8)) {
10399 if (insn & (1 << 11)) {
10400 /* pop pc */
10401 tmp = tcg_temp_new_i32();
10402 gen_aa32_ld32u(tmp, addr, IS_USER(s));
10403 /* don't set the pc until the rest of the instruction
10404 has completed */
10405 } else {
10406 /* push lr */
10407 tmp = load_reg(s, 14);
10408 gen_aa32_st32(tmp, addr, IS_USER(s));
10409 tcg_temp_free_i32(tmp);
10410 }
10411 tcg_gen_addi_i32(addr, addr, 4);
10412 }
10413 if ((insn & (1 << 11)) == 0) {
10414 tcg_gen_addi_i32(addr, addr, -offset);
10415 }
10416 /* write back the new stack pointer */
10417 store_reg(s, 13, addr);
10418 /* set the new PC value */
10419 if ((insn & 0x0900) == 0x0900) {
10420 store_reg_from_load(env, s, 15, tmp);
10421 }
10422 break;
10423
10424 case 1: case 3: case 9: case 11: /* czb */
10425 rm = insn & 7;
10426 tmp = load_reg(s, rm);
10427 s->condlabel = gen_new_label();
10428 s->condjmp = 1;
10429 if (insn & (1 << 11))
10430 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
10431 else
10432 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
10433 tcg_temp_free_i32(tmp);
10434 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
10435 val = (uint32_t)s->pc + 2;
10436 val += offset;
10437 gen_jmp(s, val);
10438 break;
10439
10440 case 15: /* IT, nop-hint. */
10441 if ((insn & 0xf) == 0) {
10442 gen_nop_hint(s, (insn >> 4) & 0xf);
10443 break;
10444 }
10445 /* If Then. */
10446 s->condexec_cond = (insn >> 4) & 0xe;
10447 s->condexec_mask = insn & 0x1f;
10448 /* No actual code generated for this insn, just setup state. */
10449 break;
10450
10451 case 0xe: /* bkpt */
10452 ARCH(5);
10453 gen_exception_insn(s, 2, EXCP_BKPT);
10454 break;
10455
10456 case 0xa: /* rev */
10457 ARCH(6);
10458 rn = (insn >> 3) & 0x7;
10459 rd = insn & 0x7;
10460 tmp = load_reg(s, rn);
10461 switch ((insn >> 6) & 3) {
10462 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
10463 case 1: gen_rev16(tmp); break;
10464 case 3: gen_revsh(tmp); break;
10465 default: goto illegal_op;
10466 }
10467 store_reg(s, rd, tmp);
10468 break;
10469
10470 case 6:
10471 switch ((insn >> 5) & 7) {
10472 case 2:
10473 /* setend */
10474 ARCH(6);
10475 if (((insn >> 3) & 1) != s->bswap_code) {
10476 /* Dynamic endianness switching not implemented. */
10477 qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
10478 goto illegal_op;
10479 }
10480 break;
10481 case 3:
10482 /* cps */
10483 ARCH(6);
10484 if (IS_USER(s)) {
10485 break;
10486 }
10487 if (IS_M(env)) {
10488 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
10489 /* FAULTMASK */
10490 if (insn & 1) {
10491 addr = tcg_const_i32(19);
10492 gen_helper_v7m_msr(cpu_env, addr, tmp);
10493 tcg_temp_free_i32(addr);
10494 }
10495 /* PRIMASK */
10496 if (insn & 2) {
10497 addr = tcg_const_i32(16);
10498 gen_helper_v7m_msr(cpu_env, addr, tmp);
10499 tcg_temp_free_i32(addr);
10500 }
10501 tcg_temp_free_i32(tmp);
10502 gen_lookup_tb(s);
10503 } else {
10504 if (insn & (1 << 4)) {
10505 shift = CPSR_A | CPSR_I | CPSR_F;
10506 } else {
10507 shift = 0;
10508 }
10509 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
10510 }
10511 break;
10512 default:
10513 goto undef;
10514 }
10515 break;
10516
10517 default:
10518 goto undef;
10519 }
10520 break;
10521
10522 case 12:
10523 {
10524 /* load/store multiple */
10525 TCGv_i32 loaded_var;
10526 TCGV_UNUSED_I32(loaded_var);
10527 rn = (insn >> 8) & 0x7;
10528 addr = load_reg(s, rn);
10529 for (i = 0; i < 8; i++) {
10530 if (insn & (1 << i)) {
10531 if (insn & (1 << 11)) {
10532 /* load */
10533 tmp = tcg_temp_new_i32();
10534 gen_aa32_ld32u(tmp, addr, IS_USER(s));
10535 if (i == rn) {
10536 loaded_var = tmp;
10537 } else {
10538 store_reg(s, i, tmp);
10539 }
10540 } else {
10541 /* store */
10542 tmp = load_reg(s, i);
10543 gen_aa32_st32(tmp, addr, IS_USER(s));
10544 tcg_temp_free_i32(tmp);
10545 }
10546 /* advance to the next address */
10547 tcg_gen_addi_i32(addr, addr, 4);
10548 }
10549 }
10550 if ((insn & (1 << rn)) == 0) {
10551 /* base reg not in list: base register writeback */
10552 store_reg(s, rn, addr);
10553 } else {
10554 /* base reg in list: if load, complete it now */
10555 if (insn & (1 << 11)) {
10556 store_reg(s, rn, loaded_var);
10557 }
10558 tcg_temp_free_i32(addr);
10559 }
10560 break;
10561 }
10562 case 13:
10563 /* conditional branch or swi */
10564 cond = (insn >> 8) & 0xf;
10565 if (cond == 0xe)
10566 goto undef;
10567
10568 if (cond == 0xf) {
10569 /* swi */
10570 gen_set_pc_im(s, s->pc);
10571 s->is_jmp = DISAS_SWI;
10572 break;
10573 }
10574 /* generate a conditional jump to next instruction */
10575 s->condlabel = gen_new_label();
10576 arm_gen_test_cc(cond ^ 1, s->condlabel);
10577 s->condjmp = 1;
10578
10579 /* jump to the offset */
10580 val = (uint32_t)s->pc + 2;
10581 offset = ((int32_t)insn << 24) >> 24;
10582 val += offset << 1;
10583 gen_jmp(s, val);
10584 break;
10585
10586 case 14:
10587 if (insn & (1 << 11)) {
10588 if (disas_thumb2_insn(env, s, insn))
10589 goto undef32;
10590 break;
10591 }
10592 /* unconditional branch */
10593 val = (uint32_t)s->pc;
10594 offset = ((int32_t)insn << 21) >> 21;
10595 val += (offset << 1) + 2;
10596 gen_jmp(s, val);
10597 break;
10598
10599 case 15:
10600 if (disas_thumb2_insn(env, s, insn))
10601 goto undef32;
10602 break;
10603 }
10604 return;
10605 undef32:
10606 gen_exception_insn(s, 4, EXCP_UDEF);
10607 return;
10608 illegal_op:
10609 undef:
10610 gen_exception_insn(s, 2, EXCP_UDEF);
10611 }
10612
10613 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
10614 basic block 'tb'. If search_pc is TRUE, also generate PC
10615 information for each intermediate instruction. */
10616 static inline void gen_intermediate_code_internal(ARMCPU *cpu,
10617 TranslationBlock *tb,
10618 bool search_pc)
10619 {
10620 CPUState *cs = CPU(cpu);
10621 CPUARMState *env = &cpu->env;
10622 DisasContext dc1, *dc = &dc1;
10623 CPUBreakpoint *bp;
10624 uint16_t *gen_opc_end;
10625 int j, lj;
10626 target_ulong pc_start;
10627 target_ulong next_page_start;
10628 int num_insns;
10629 int max_insns;
10630
10631 /* generate intermediate code */
10632
10633 /* The A64 decoder has its own top level loop, because it doesn't need
10634 * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
10635 */
10636 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
10637 gen_intermediate_code_internal_a64(cpu, tb, search_pc);
10638 return;
10639 }
10640
10641 pc_start = tb->pc;
10642
10643 dc->tb = tb;
10644
10645 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
10646
10647 dc->is_jmp = DISAS_NEXT;
10648 dc->pc = pc_start;
10649 dc->singlestep_enabled = cs->singlestep_enabled;
10650 dc->condjmp = 0;
10651
10652 dc->aarch64 = 0;
10653 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
10654 dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
10655 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
10656 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
10657 #if !defined(CONFIG_USER_ONLY)
10658 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
10659 #endif
10660 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
10661 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
10662 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
10663 dc->cp_regs = cpu->cp_regs;
10664 dc->current_pl = arm_current_pl(env);
10665 dc->features = env->features;
10666
10667 cpu_F0s = tcg_temp_new_i32();
10668 cpu_F1s = tcg_temp_new_i32();
10669 cpu_F0d = tcg_temp_new_i64();
10670 cpu_F1d = tcg_temp_new_i64();
10671 cpu_V0 = cpu_F0d;
10672 cpu_V1 = cpu_F1d;
10673 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
10674 cpu_M0 = tcg_temp_new_i64();
10675 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
10676 lj = -1;
10677 num_insns = 0;
10678 max_insns = tb->cflags & CF_COUNT_MASK;
10679 if (max_insns == 0)
10680 max_insns = CF_COUNT_MASK;
10681
10682 gen_tb_start();
10683
10684 tcg_clear_temp_count();
10685
10686 /* A note on handling of the condexec (IT) bits:
10687 *
10688 * We want to avoid the overhead of having to write the updated condexec
10689 * bits back to the CPUARMState for every instruction in an IT block. So:
10690 * (1) if the condexec bits are not already zero then we write
10691 * zero back into the CPUARMState now. This avoids complications trying
10692 * to do it at the end of the block. (For example if we don't do this
10693 * it's hard to identify whether we can safely skip writing condexec
10694 * at the end of the TB, which we definitely want to do for the case
10695 * where a TB doesn't do anything with the IT state at all.)
10696 * (2) if we are going to leave the TB then we call gen_set_condexec()
10697 * which will write the correct value into CPUARMState if zero is wrong.
10698 * This is done both for leaving the TB at the end, and for leaving
10699 * it because of an exception we know will happen, which is done in
10700 * gen_exception_insn(). The latter is necessary because we need to
10701 * leave the TB with the PC/IT state just prior to execution of the
10702 * instruction which caused the exception.
10703 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
10704 * then the CPUARMState will be wrong and we need to reset it.
10705 * This is handled in the same way as restoration of the
10706 * PC in these situations: we will be called again with search_pc=1
10707 * and generate a mapping of the condexec bits for each PC in
10708 * gen_opc_condexec_bits[]. restore_state_to_opc() then uses
10709 * this to restore the condexec bits.
10710 *
10711 * Note that there are no instructions which can read the condexec
10712 * bits, and none which can write non-static values to them, so
10713 * we don't need to care about whether CPUARMState is correct in the
10714 * middle of a TB.
10715 */
10716
10717 /* Reset the conditional execution bits immediately. This avoids
10718 complications trying to do it at the end of the block. */
10719 if (dc->condexec_mask || dc->condexec_cond)
10720 {
10721 TCGv_i32 tmp = tcg_temp_new_i32();
10722 tcg_gen_movi_i32(tmp, 0);
10723 store_cpu_field(tmp, condexec_bits);
10724 }
10725 do {
10726 #ifdef CONFIG_USER_ONLY
10727 /* Intercept jump to the magic kernel page. */
10728 if (dc->pc >= 0xffff0000) {
10729 /* We always get here via a jump, so know we are not in a
10730 conditional execution block. */
10731 gen_exception(EXCP_KERNEL_TRAP);
10732 dc->is_jmp = DISAS_UPDATE;
10733 break;
10734 }
10735 #else
10736 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
10737 /* We always get here via a jump, so know we are not in a
10738 conditional execution block. */
10739 gen_exception(EXCP_EXCEPTION_EXIT);
10740 dc->is_jmp = DISAS_UPDATE;
10741 break;
10742 }
10743 #endif
10744
10745 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
10746 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
10747 if (bp->pc == dc->pc) {
10748 gen_exception_insn(dc, 0, EXCP_DEBUG);
10749 /* Advance PC so that clearing the breakpoint will
10750 invalidate this TB. */
10751 dc->pc += 2;
10752 goto done_generating;
10753 }
10754 }
10755 }
10756 if (search_pc) {
10757 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10758 if (lj < j) {
10759 lj++;
10760 while (lj < j)
10761 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10762 }
10763 tcg_ctx.gen_opc_pc[lj] = dc->pc;
10764 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
10765 tcg_ctx.gen_opc_instr_start[lj] = 1;
10766 tcg_ctx.gen_opc_icount[lj] = num_insns;
10767 }
10768
10769 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
10770 gen_io_start();
10771
10772 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
10773 tcg_gen_debug_insn_start(dc->pc);
10774 }
10775
10776 if (dc->thumb) {
10777 disas_thumb_insn(env, dc);
10778 if (dc->condexec_mask) {
10779 dc->condexec_cond = (dc->condexec_cond & 0xe)
10780 | ((dc->condexec_mask >> 4) & 1);
10781 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
10782 if (dc->condexec_mask == 0) {
10783 dc->condexec_cond = 0;
10784 }
10785 }
10786 } else {
10787 disas_arm_insn(env, dc);
10788 }
10789
10790 if (dc->condjmp && !dc->is_jmp) {
10791 gen_set_label(dc->condlabel);
10792 dc->condjmp = 0;
10793 }
10794
10795 if (tcg_check_temp_count()) {
10796 fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
10797 dc->pc);
10798 }
10799
10800 /* Translation stops when a conditional branch is encountered.
10801 * Otherwise the subsequent code could get translated several times.
10802 * Also stop translation when a page boundary is reached. This
10803 * ensures prefetch aborts occur at the right place. */
10804 num_insns ++;
10805 } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
10806 !cs->singlestep_enabled &&
10807 !singlestep &&
10808 dc->pc < next_page_start &&
10809 num_insns < max_insns);
10810
10811 if (tb->cflags & CF_LAST_IO) {
10812 if (dc->condjmp) {
10813 /* FIXME: This can theoretically happen with self-modifying
10814 code. */
10815 cpu_abort(cs, "IO on conditional branch instruction");
10816 }
10817 gen_io_end();
10818 }
10819
10820 /* At this stage dc->condjmp will only be set when the skipped
10821 instruction was a conditional branch or trap, and the PC has
10822 already been written. */
10823 if (unlikely(cs->singlestep_enabled)) {
10824 /* Make sure the pc is updated, and raise a debug exception. */
10825 if (dc->condjmp) {
10826 gen_set_condexec(dc);
10827 if (dc->is_jmp == DISAS_SWI) {
10828 gen_exception(EXCP_SWI);
10829 } else {
10830 gen_exception(EXCP_DEBUG);
10831 }
10832 gen_set_label(dc->condlabel);
10833 }
10834 if (dc->condjmp || !dc->is_jmp) {
10835 gen_set_pc_im(dc, dc->pc);
10836 dc->condjmp = 0;
10837 }
10838 gen_set_condexec(dc);
10839 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
10840 gen_exception(EXCP_SWI);
10841 } else {
10842 /* FIXME: Single stepping a WFI insn will not halt
10843 the CPU. */
10844 gen_exception(EXCP_DEBUG);
10845 }
10846 } else {
10847 /* While branches must always occur at the end of an IT block,
10848 there are a few other things that can cause us to terminate
10849 the TB in the middle of an IT block:
10850 - Exception generating instructions (bkpt, swi, undefined).
10851 - Page boundaries.
10852 - Hardware watchpoints.
10853 Hardware breakpoints have already been handled and skip this code.
10854 */
10855 gen_set_condexec(dc);
10856 switch(dc->is_jmp) {
10857 case DISAS_NEXT:
10858 gen_goto_tb(dc, 1, dc->pc);
10859 break;
10860 default:
10861 case DISAS_JUMP:
10862 case DISAS_UPDATE:
10863 /* indicate that the hash table must be used to find the next TB */
10864 tcg_gen_exit_tb(0);
10865 break;
10866 case DISAS_TB_JUMP:
10867 /* nothing more to generate */
10868 break;
10869 case DISAS_WFI:
10870 gen_helper_wfi(cpu_env);
10871 break;
10872 case DISAS_WFE:
10873 gen_helper_wfe(cpu_env);
10874 break;
10875 case DISAS_SWI:
10876 gen_exception(EXCP_SWI);
10877 break;
10878 }
10879 if (dc->condjmp) {
10880 gen_set_label(dc->condlabel);
10881 gen_set_condexec(dc);
10882 gen_goto_tb(dc, 1, dc->pc);
10883 dc->condjmp = 0;
10884 }
10885 }
10886
10887 done_generating:
10888 gen_tb_end(tb, num_insns);
10889 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
10890
10891 #ifdef DEBUG_DISAS
10892 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
10893 qemu_log("----------------\n");
10894 qemu_log("IN: %s\n", lookup_symbol(pc_start));
10895 log_target_disas(env, pc_start, dc->pc - pc_start,
10896 dc->thumb | (dc->bswap_code << 1));
10897 qemu_log("\n");
10898 }
10899 #endif
10900 if (search_pc) {
10901 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10902 lj++;
10903 while (lj <= j)
10904 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10905 } else {
10906 tb->size = dc->pc - pc_start;
10907 tb->icount = num_insns;
10908 }
10909 }
10910
10911 void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
10912 {
10913 gen_intermediate_code_internal(arm_env_get_cpu(env), tb, false);
10914 }
10915
10916 void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb)
10917 {
10918 gen_intermediate_code_internal(arm_env_get_cpu(env), tb, true);
10919 }
10920
10921 static const char *cpu_mode_names[16] = {
10922 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
10923 "???", "???", "???", "und", "???", "???", "???", "sys"
10924 };
10925
10926 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
10927 int flags)
10928 {
10929 ARMCPU *cpu = ARM_CPU(cs);
10930 CPUARMState *env = &cpu->env;
10931 int i;
10932 uint32_t psr;
10933
10934 for(i=0;i<16;i++) {
10935 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
10936 if ((i % 4) == 3)
10937 cpu_fprintf(f, "\n");
10938 else
10939 cpu_fprintf(f, " ");
10940 }
10941 psr = cpsr_read(env);
10942 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
10943 psr,
10944 psr & (1 << 31) ? 'N' : '-',
10945 psr & (1 << 30) ? 'Z' : '-',
10946 psr & (1 << 29) ? 'C' : '-',
10947 psr & (1 << 28) ? 'V' : '-',
10948 psr & CPSR_T ? 'T' : 'A',
10949 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
10950
10951 if (flags & CPU_DUMP_FPU) {
10952 int numvfpregs = 0;
10953 if (arm_feature(env, ARM_FEATURE_VFP)) {
10954 numvfpregs += 16;
10955 }
10956 if (arm_feature(env, ARM_FEATURE_VFP3)) {
10957 numvfpregs += 16;
10958 }
10959 for (i = 0; i < numvfpregs; i++) {
10960 uint64_t v = float64_val(env->vfp.regs[i]);
10961 cpu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
10962 i * 2, (uint32_t)v,
10963 i * 2 + 1, (uint32_t)(v >> 32),
10964 i, v);
10965 }
10966 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
10967 }
10968 }
10969
10970 void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos)
10971 {
10972 if (is_a64(env)) {
10973 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
10974 env->condexec_bits = 0;
10975 } else {
10976 env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos];
10977 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
10978 }
10979 }
AR7 emulation for QEMU