target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "hw/qdev-properties.h"
  24 #include "qapi/qmp/qerror.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31
  32 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  33 {
  34     ARMCPU *cpu = ARM_CPU(cs);
  35
  36     cpu->env.regs[15] = value;
  37 }
  38
  39 static bool arm_cpu_has_work(CPUState *cs)
  40 {
  41     return cs->interrupt_request &
  42         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
  43 }
  44
  45 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  46 {
  47     /* Reset a single ARMCPRegInfo register */
  48     ARMCPRegInfo *ri = value;
  49     ARMCPU *cpu = opaque;
  50
  51     if (ri->type & ARM_CP_SPECIAL) {
  52         return;
  53     }
  54
  55     if (ri->resetfn) {
  56         ri->resetfn(&cpu->env, ri);
  57         return;
  58     }
  59
  60     /* A zero offset is never possible as it would be regs[0]
  61      * so we use it to indicate that reset is being handled elsewhere.
  62      * This is basically only used for fields in non-core coprocessors
  63      * (like the pxa2xx ones).
  64      */
  65     if (!ri->fieldoffset) {
  66         return;
  67     }
  68
  69     if (cpreg_field_is_64bit(ri)) {
  70         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  71     } else {
  72         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  73     }
  74 }
  75
  76 /* CPUClass::reset() */
  77 static void arm_cpu_reset(CPUState *s)
  78 {
  79     ARMCPU *cpu = ARM_CPU(s);
  80     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  81     CPUARMState *env = &cpu->env;
  82
  83     acc->parent_reset(s);
  84
  85     memset(env, 0, offsetof(CPUARMState, features));
  86     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  87     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  88     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  89     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  90
  91     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  92         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  93     }
  94
  95     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  96         /* 64 bit CPUs always start in 64 bit mode */
  97         env->aarch64 = 1;
  98 #if defined(CONFIG_USER_ONLY)
  99         env->pstate = PSTATE_MODE_EL0t;
 100         /* Userspace expects access to CTL_EL0 and the cache ops */
 101         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 102 #else
 103         env->pstate = PSTATE_MODE_EL1h;
 104 #endif
 105     }
 106
 107 #if defined(CONFIG_USER_ONLY)
 108     env->uncached_cpsr = ARM_CPU_MODE_USR;
 109     /* For user mode we must enable access to coprocessors */
 110     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 111     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 112         env->cp15.c15_cpar = 3;
 113     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 114         env->cp15.c15_cpar = 1;
 115     }
 116 #else
 117     /* SVC mode with interrupts disabled.  */
 118     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 119     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 120     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 121        clear at reset.  Initial SP and PC are loaded from ROM.  */
 122     if (IS_M(env)) {
 123         uint32_t pc;
 124         uint8_t *rom;
 125         env->daif &= ~PSTATE_I;
 126         rom = rom_ptr(0);
 127         if (rom) {
 128             /* We should really use ldl_phys here, in case the guest
 129                modified flash and reset itself.  However images
 130                loaded via -kernel have not been copied yet, so load the
 131                values directly from there.  */
 132             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 133             pc = ldl_p(rom + 4);
 134             env->thumb = pc & 1;
 135             env->regs[15] = pc & ~1;
 136         }
 137     }
 138
 139     if (env->cp15.c1_sys & SCTLR_V) {
 140             env->regs[15] = 0xFFFF0000;
 141     }
 142
 143     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 144 #endif
 145     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 146     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 147     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 148     set_float_detect_tininess(float_tininess_before_rounding,
 149                               &env->vfp.fp_status);
 150     set_float_detect_tininess(float_tininess_before_rounding,
 151                               &env->vfp.standard_fp_status);
 152     tlb_flush(s, 1);
 153     /* Reset is a state change for some CPUARMState fields which we
 154      * bake assumptions about into translated code, so we need to
 155      * tb_flush().
 156      */
 157     tb_flush(env);
 158 }
 159
 160 #ifndef CONFIG_USER_ONLY
 161 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 162 {
 163     ARMCPU *cpu = opaque;
 164     CPUState *cs = CPU(cpu);
 165
 166     switch (irq) {
 167     case ARM_CPU_IRQ:
 168         if (level) {
 169             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 170         } else {
 171             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 172         }
 173         break;
 174     case ARM_CPU_FIQ:
 175         if (level) {
 176             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 177         } else {
 178             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 179         }
 180         break;
 181     default:
 182         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 183     }
 184 }
 185
 186 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 187 {
 188 #ifdef CONFIG_KVM
 189     ARMCPU *cpu = opaque;
 190     CPUState *cs = CPU(cpu);
 191     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 192
 193     switch (irq) {
 194     case ARM_CPU_IRQ:
 195         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 196         break;
 197     case ARM_CPU_FIQ:
 198         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 199         break;
 200     default:
 201         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 202     }
 203     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 204     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 205 #endif
 206 }
 207 #endif
 208
 209 static inline void set_feature(CPUARMState *env, int feature)
 210 {
 211     env->features |= 1ULL << feature;
 212 }
 213
 214 static void arm_cpu_initfn(Object *obj)
 215 {
 216     CPUState *cs = CPU(obj);
 217     ARMCPU *cpu = ARM_CPU(obj);
 218     static bool inited;
 219
 220     cs->env_ptr = &cpu->env;
 221     cpu_exec_init(&cpu->env);
 222     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 223                                          g_free, g_free);
 224
 225 #ifndef CONFIG_USER_ONLY
 226     /* Our inbound IRQ and FIQ lines */
 227     if (kvm_enabled()) {
 228         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 229     } else {
 230         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 231     }
 232
 233     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 234                                                 arm_gt_ptimer_cb, cpu);
 235     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 236                                                 arm_gt_vtimer_cb, cpu);
 237     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 238                        ARRAY_SIZE(cpu->gt_timer_outputs));
 239 #endif
 240
 241     /* DTB consumers generally don't in fact care what the 'compatible'
 242      * string is, so always provide some string and trust that a hypothetical
 243      * picky DTB consumer will also provide a helpful error message.
 244      */
 245     cpu->dtb_compatible = "qemu,unknown";
 246     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 247
 248     if (tcg_enabled() && !inited) {
 249         inited = true;
 250         arm_translate_init();
 251     }
 252 }
 253
 254 static Property arm_cpu_reset_cbar_property =
 255             DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
 256
 257 static Property arm_cpu_reset_hivecs_property =
 258             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 259
 260 static void arm_cpu_post_init(Object *obj)
 261 {
 262     ARMCPU *cpu = ARM_CPU(obj);
 263
 264     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
 265         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 266                                  &error_abort);
 267     }
 268
 269     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 270         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 271                                  &error_abort);
 272     }
 273 }
 274
 275 static void arm_cpu_finalizefn(Object *obj)
 276 {
 277     ARMCPU *cpu = ARM_CPU(obj);
 278     g_hash_table_destroy(cpu->cp_regs);
 279 }
 280
 281 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 282 {
 283     CPUState *cs = CPU(dev);
 284     ARMCPU *cpu = ARM_CPU(dev);
 285     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 286     CPUARMState *env = &cpu->env;
 287
 288     /* Some features automatically imply others: */
 289     if (arm_feature(env, ARM_FEATURE_V8)) {
 290         set_feature(env, ARM_FEATURE_V7);
 291         set_feature(env, ARM_FEATURE_ARM_DIV);
 292         set_feature(env, ARM_FEATURE_LPAE);
 293         set_feature(env, ARM_FEATURE_V8_AES);
 294     }
 295     if (arm_feature(env, ARM_FEATURE_V7)) {
 296         set_feature(env, ARM_FEATURE_VAPA);
 297         set_feature(env, ARM_FEATURE_THUMB2);
 298         set_feature(env, ARM_FEATURE_MPIDR);
 299         if (!arm_feature(env, ARM_FEATURE_M)) {
 300             set_feature(env, ARM_FEATURE_V6K);
 301         } else {
 302             set_feature(env, ARM_FEATURE_V6);
 303         }
 304     }
 305     if (arm_feature(env, ARM_FEATURE_V6K)) {
 306         set_feature(env, ARM_FEATURE_V6);
 307         set_feature(env, ARM_FEATURE_MVFR);
 308     }
 309     if (arm_feature(env, ARM_FEATURE_V6)) {
 310         set_feature(env, ARM_FEATURE_V5);
 311         if (!arm_feature(env, ARM_FEATURE_M)) {
 312             set_feature(env, ARM_FEATURE_AUXCR);
 313         }
 314     }
 315     if (arm_feature(env, ARM_FEATURE_V5)) {
 316         set_feature(env, ARM_FEATURE_V4T);
 317     }
 318     if (arm_feature(env, ARM_FEATURE_M)) {
 319         set_feature(env, ARM_FEATURE_THUMB_DIV);
 320     }
 321     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 322         set_feature(env, ARM_FEATURE_THUMB_DIV);
 323     }
 324     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 325         set_feature(env, ARM_FEATURE_VFP3);
 326     }
 327     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 328         set_feature(env, ARM_FEATURE_VFP);
 329     }
 330     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 331         set_feature(env, ARM_FEATURE_V7MP);
 332         set_feature(env, ARM_FEATURE_PXN);
 333     }
 334
 335     if (cpu->reset_hivecs) {
 336             cpu->reset_sctlr |= (1 << 13);
 337     }
 338
 339     register_cp_regs_for_features(cpu);
 340     arm_cpu_register_gdb_regs_for_features(cpu);
 341
 342     init_cpreg_list(cpu);
 343
 344     cpu_reset(cs);
 345     qemu_init_vcpu(cs);
 346
 347     acc->parent_realize(dev, errp);
 348 }
 349
 350 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 351 {
 352     ObjectClass *oc;
 353     char *typename;
 354
 355     if (!cpu_model) {
 356         return NULL;
 357     }
 358
 359     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 360     oc = object_class_by_name(typename);
 361     g_free(typename);
 362     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 363         object_class_is_abstract(oc)) {
 364         return NULL;
 365     }
 366     return oc;
 367 }
 368
 369 /* CPU models. These are not needed for the AArch64 linux-user build. */
 370 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 371
 372 static void arm926_initfn(Object *obj)
 373 {
 374     ARMCPU *cpu = ARM_CPU(obj);
 375
 376     cpu->dtb_compatible = "arm,arm926";
 377     set_feature(&cpu->env, ARM_FEATURE_V5);
 378     set_feature(&cpu->env, ARM_FEATURE_VFP);
 379     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 380     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 381     cpu->midr = 0x41069265;
 382     cpu->reset_fpsid = 0x41011090;
 383     cpu->ctr = 0x1dd20d2;
 384     cpu->reset_sctlr = 0x00090078;
 385 }
 386
 387 static void arm946_initfn(Object *obj)
 388 {
 389     ARMCPU *cpu = ARM_CPU(obj);
 390
 391     cpu->dtb_compatible = "arm,arm946";
 392     set_feature(&cpu->env, ARM_FEATURE_V5);
 393     set_feature(&cpu->env, ARM_FEATURE_MPU);
 394     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 395     cpu->midr = 0x41059461;
 396     cpu->ctr = 0x0f004006;
 397     cpu->reset_sctlr = 0x00000078;
 398 }
 399
 400 static void arm1026_initfn(Object *obj)
 401 {
 402     ARMCPU *cpu = ARM_CPU(obj);
 403
 404     cpu->dtb_compatible = "arm,arm1026";
 405     set_feature(&cpu->env, ARM_FEATURE_V5);
 406     set_feature(&cpu->env, ARM_FEATURE_VFP);
 407     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 408     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 409     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 410     cpu->midr = 0x4106a262;
 411     cpu->reset_fpsid = 0x410110a0;
 412     cpu->ctr = 0x1dd20d2;
 413     cpu->reset_sctlr = 0x00090078;
 414     cpu->reset_auxcr = 1;
 415     {
 416         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 417         ARMCPRegInfo ifar = {
 418             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 419             .access = PL1_RW,
 420             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 421             .resetvalue = 0
 422         };
 423         define_one_arm_cp_reg(cpu, &ifar);
 424     }
 425 }
 426
 427 static void arm1136_r2_initfn(Object *obj)
 428 {
 429     ARMCPU *cpu = ARM_CPU(obj);
 430     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 431      * older core than plain "arm1136". In particular this does not
 432      * have the v6K features.
 433      * These ID register values are correct for 1136 but may be wrong
 434      * for 1136_r2 (in particular r0p2 does not actually implement most
 435      * of the ID registers).
 436      */
 437
 438     cpu->dtb_compatible = "arm,arm1136";
 439     set_feature(&cpu->env, ARM_FEATURE_V6);
 440     set_feature(&cpu->env, ARM_FEATURE_VFP);
 441     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 442     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 443     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 444     cpu->midr = 0x4107b362;
 445     cpu->reset_fpsid = 0x410120b4;
 446     cpu->mvfr0 = 0x11111111;
 447     cpu->mvfr1 = 0x00000000;
 448     cpu->ctr = 0x1dd20d2;
 449     cpu->reset_sctlr = 0x00050078;
 450     cpu->id_pfr0 = 0x111;
 451     cpu->id_pfr1 = 0x1;
 452     cpu->id_dfr0 = 0x2;
 453     cpu->id_afr0 = 0x3;
 454     cpu->id_mmfr0 = 0x01130003;
 455     cpu->id_mmfr1 = 0x10030302;
 456     cpu->id_mmfr2 = 0x01222110;
 457     cpu->id_isar0 = 0x00140011;
 458     cpu->id_isar1 = 0x12002111;
 459     cpu->id_isar2 = 0x11231111;
 460     cpu->id_isar3 = 0x01102131;
 461     cpu->id_isar4 = 0x141;
 462     cpu->reset_auxcr = 7;
 463 }
 464
 465 static void arm1136_initfn(Object *obj)
 466 {
 467     ARMCPU *cpu = ARM_CPU(obj);
 468
 469     cpu->dtb_compatible = "arm,arm1136";
 470     set_feature(&cpu->env, ARM_FEATURE_V6K);
 471     set_feature(&cpu->env, ARM_FEATURE_V6);
 472     set_feature(&cpu->env, ARM_FEATURE_VFP);
 473     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 474     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 475     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 476     cpu->midr = 0x4117b363;
 477     cpu->reset_fpsid = 0x410120b4;
 478     cpu->mvfr0 = 0x11111111;
 479     cpu->mvfr1 = 0x00000000;
 480     cpu->ctr = 0x1dd20d2;
 481     cpu->reset_sctlr = 0x00050078;
 482     cpu->id_pfr0 = 0x111;
 483     cpu->id_pfr1 = 0x1;
 484     cpu->id_dfr0 = 0x2;
 485     cpu->id_afr0 = 0x3;
 486     cpu->id_mmfr0 = 0x01130003;
 487     cpu->id_mmfr1 = 0x10030302;
 488     cpu->id_mmfr2 = 0x01222110;
 489     cpu->id_isar0 = 0x00140011;
 490     cpu->id_isar1 = 0x12002111;
 491     cpu->id_isar2 = 0x11231111;
 492     cpu->id_isar3 = 0x01102131;
 493     cpu->id_isar4 = 0x141;
 494     cpu->reset_auxcr = 7;
 495 }
 496
 497 static void arm1176_initfn(Object *obj)
 498 {
 499     ARMCPU *cpu = ARM_CPU(obj);
 500
 501     cpu->dtb_compatible = "arm,arm1176";
 502     set_feature(&cpu->env, ARM_FEATURE_V6K);
 503     set_feature(&cpu->env, ARM_FEATURE_VFP);
 504     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 505     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 506     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 507     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 508     cpu->midr = 0x410fb767;
 509     cpu->reset_fpsid = 0x410120b5;
 510     cpu->mvfr0 = 0x11111111;
 511     cpu->mvfr1 = 0x00000000;
 512     cpu->ctr = 0x1dd20d2;
 513     cpu->reset_sctlr = 0x00050078;
 514     cpu->id_pfr0 = 0x111;
 515     cpu->id_pfr1 = 0x11;
 516     cpu->id_dfr0 = 0x33;
 517     cpu->id_afr0 = 0;
 518     cpu->id_mmfr0 = 0x01130003;
 519     cpu->id_mmfr1 = 0x10030302;
 520     cpu->id_mmfr2 = 0x01222100;
 521     cpu->id_isar0 = 0x0140011;
 522     cpu->id_isar1 = 0x12002111;
 523     cpu->id_isar2 = 0x11231121;
 524     cpu->id_isar3 = 0x01102131;
 525     cpu->id_isar4 = 0x01141;
 526     cpu->reset_auxcr = 7;
 527 }
 528
 529 static void arm11mpcore_initfn(Object *obj)
 530 {
 531     ARMCPU *cpu = ARM_CPU(obj);
 532
 533     cpu->dtb_compatible = "arm,arm11mpcore";
 534     set_feature(&cpu->env, ARM_FEATURE_V6K);
 535     set_feature(&cpu->env, ARM_FEATURE_VFP);
 536     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 537     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 538     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 539     cpu->midr = 0x410fb022;
 540     cpu->reset_fpsid = 0x410120b4;
 541     cpu->mvfr0 = 0x11111111;
 542     cpu->mvfr1 = 0x00000000;
 543     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 544     cpu->id_pfr0 = 0x111;
 545     cpu->id_pfr1 = 0x1;
 546     cpu->id_dfr0 = 0;
 547     cpu->id_afr0 = 0x2;
 548     cpu->id_mmfr0 = 0x01100103;
 549     cpu->id_mmfr1 = 0x10020302;
 550     cpu->id_mmfr2 = 0x01222000;
 551     cpu->id_isar0 = 0x00100011;
 552     cpu->id_isar1 = 0x12002111;
 553     cpu->id_isar2 = 0x11221011;
 554     cpu->id_isar3 = 0x01102131;
 555     cpu->id_isar4 = 0x141;
 556     cpu->reset_auxcr = 1;
 557 }
 558
 559 static void cortex_m3_initfn(Object *obj)
 560 {
 561     ARMCPU *cpu = ARM_CPU(obj);
 562     set_feature(&cpu->env, ARM_FEATURE_V7);
 563     set_feature(&cpu->env, ARM_FEATURE_M);
 564     cpu->midr = 0x410fc231;
 565 }
 566
 567 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 568 {
 569 #ifndef CONFIG_USER_ONLY
 570     CPUClass *cc = CPU_CLASS(oc);
 571
 572     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 573 #endif
 574 }
 575
 576 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 577     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 578       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 579     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 580       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 581     REGINFO_SENTINEL
 582 };
 583
 584 static void cortex_a8_initfn(Object *obj)
 585 {
 586     ARMCPU *cpu = ARM_CPU(obj);
 587
 588     cpu->dtb_compatible = "arm,cortex-a8";
 589     set_feature(&cpu->env, ARM_FEATURE_V7);
 590     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 591     set_feature(&cpu->env, ARM_FEATURE_NEON);
 592     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 593     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 594     cpu->midr = 0x410fc080;
 595     cpu->reset_fpsid = 0x410330c0;
 596     cpu->mvfr0 = 0x11110222;
 597     cpu->mvfr1 = 0x00011100;
 598     cpu->ctr = 0x82048004;
 599     cpu->reset_sctlr = 0x00c50078;
 600     cpu->id_pfr0 = 0x1031;
 601     cpu->id_pfr1 = 0x11;
 602     cpu->id_dfr0 = 0x400;
 603     cpu->id_afr0 = 0;
 604     cpu->id_mmfr0 = 0x31100003;
 605     cpu->id_mmfr1 = 0x20000000;
 606     cpu->id_mmfr2 = 0x01202000;
 607     cpu->id_mmfr3 = 0x11;
 608     cpu->id_isar0 = 0x00101111;
 609     cpu->id_isar1 = 0x12112111;
 610     cpu->id_isar2 = 0x21232031;
 611     cpu->id_isar3 = 0x11112131;
 612     cpu->id_isar4 = 0x00111142;
 613     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 614     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 615     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 616     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 617     cpu->reset_auxcr = 2;
 618     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 619 }
 620
 621 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 622     /* power_control should be set to maximum latency. Again,
 623      * default to 0 and set by private hook
 624      */
 625     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 626       .access = PL1_RW, .resetvalue = 0,
 627       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 628     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 629       .access = PL1_RW, .resetvalue = 0,
 630       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 631     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 632       .access = PL1_RW, .resetvalue = 0,
 633       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 634     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 635       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 636     /* TLB lockdown control */
 637     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 638       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 639     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 640       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 641     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 642       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 643     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 644       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 645     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 646       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 647     REGINFO_SENTINEL
 648 };
 649
 650 static void cortex_a9_initfn(Object *obj)
 651 {
 652     ARMCPU *cpu = ARM_CPU(obj);
 653
 654     cpu->dtb_compatible = "arm,cortex-a9";
 655     set_feature(&cpu->env, ARM_FEATURE_V7);
 656     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 657     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 658     set_feature(&cpu->env, ARM_FEATURE_NEON);
 659     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 660     /* Note that A9 supports the MP extensions even for
 661      * A9UP and single-core A9MP (which are both different
 662      * and valid configurations; we don't model A9UP).
 663      */
 664     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 665     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 666     cpu->midr = 0x410fc090;
 667     cpu->reset_fpsid = 0x41033090;
 668     cpu->mvfr0 = 0x11110222;
 669     cpu->mvfr1 = 0x01111111;
 670     cpu->ctr = 0x80038003;
 671     cpu->reset_sctlr = 0x00c50078;
 672     cpu->id_pfr0 = 0x1031;
 673     cpu->id_pfr1 = 0x11;
 674     cpu->id_dfr0 = 0x000;
 675     cpu->id_afr0 = 0;
 676     cpu->id_mmfr0 = 0x00100103;
 677     cpu->id_mmfr1 = 0x20000000;
 678     cpu->id_mmfr2 = 0x01230000;
 679     cpu->id_mmfr3 = 0x00002111;
 680     cpu->id_isar0 = 0x00101111;
 681     cpu->id_isar1 = 0x13112111;
 682     cpu->id_isar2 = 0x21232041;
 683     cpu->id_isar3 = 0x11112131;
 684     cpu->id_isar4 = 0x00111142;
 685     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 686     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 687     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 688     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 689 }
 690
 691 #ifndef CONFIG_USER_ONLY
 692 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 693 {
 694     /* Linux wants the number of processors from here.
 695      * Might as well set the interrupt-controller bit too.
 696      */
 697     return ((smp_cpus - 1) << 24) | (1 << 23);
 698 }
 699 #endif
 700
 701 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 702 #ifndef CONFIG_USER_ONLY
 703     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 704       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 705       .writefn = arm_cp_write_ignore, },
 706 #endif
 707     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 708       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 709     REGINFO_SENTINEL
 710 };
 711
 712 static void cortex_a15_initfn(Object *obj)
 713 {
 714     ARMCPU *cpu = ARM_CPU(obj);
 715
 716     cpu->dtb_compatible = "arm,cortex-a15";
 717     set_feature(&cpu->env, ARM_FEATURE_V7);
 718     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 719     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 720     set_feature(&cpu->env, ARM_FEATURE_NEON);
 721     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 722     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 723     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 724     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 725     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 726     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 727     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 728     cpu->midr = 0x412fc0f1;
 729     cpu->reset_fpsid = 0x410430f0;
 730     cpu->mvfr0 = 0x10110222;
 731     cpu->mvfr1 = 0x11111111;
 732     cpu->ctr = 0x8444c004;
 733     cpu->reset_sctlr = 0x00c50078;
 734     cpu->id_pfr0 = 0x00001131;
 735     cpu->id_pfr1 = 0x00011011;
 736     cpu->id_dfr0 = 0x02010555;
 737     cpu->id_afr0 = 0x00000000;
 738     cpu->id_mmfr0 = 0x10201105;
 739     cpu->id_mmfr1 = 0x20000000;
 740     cpu->id_mmfr2 = 0x01240000;
 741     cpu->id_mmfr3 = 0x02102211;
 742     cpu->id_isar0 = 0x02101110;
 743     cpu->id_isar1 = 0x13112111;
 744     cpu->id_isar2 = 0x21232041;
 745     cpu->id_isar3 = 0x11112131;
 746     cpu->id_isar4 = 0x10011142;
 747     cpu->clidr = 0x0a200023;
 748     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 749     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 750     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 751     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 752 }
 753
 754 static void ti925t_initfn(Object *obj)
 755 {
 756     ARMCPU *cpu = ARM_CPU(obj);
 757     set_feature(&cpu->env, ARM_FEATURE_V4T);
 758     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 759     cpu->midr = ARM_CPUID_TI925T;
 760     cpu->ctr = 0x5109149;
 761     cpu->reset_sctlr = 0x00000070;
 762 }
 763
 764 static void sa1100_initfn(Object *obj)
 765 {
 766     ARMCPU *cpu = ARM_CPU(obj);
 767
 768     cpu->dtb_compatible = "intel,sa1100";
 769     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 770     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 771     cpu->midr = 0x4401A11B;
 772     cpu->reset_sctlr = 0x00000070;
 773 }
 774
 775 static void sa1110_initfn(Object *obj)
 776 {
 777     ARMCPU *cpu = ARM_CPU(obj);
 778     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 779     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 780     cpu->midr = 0x6901B119;
 781     cpu->reset_sctlr = 0x00000070;
 782 }
 783
 784 static void pxa250_initfn(Object *obj)
 785 {
 786     ARMCPU *cpu = ARM_CPU(obj);
 787
 788     cpu->dtb_compatible = "marvell,xscale";
 789     set_feature(&cpu->env, ARM_FEATURE_V5);
 790     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 791     cpu->midr = 0x69052100;
 792     cpu->ctr = 0xd172172;
 793     cpu->reset_sctlr = 0x00000078;
 794 }
 795
 796 static void pxa255_initfn(Object *obj)
 797 {
 798     ARMCPU *cpu = ARM_CPU(obj);
 799
 800     cpu->dtb_compatible = "marvell,xscale";
 801     set_feature(&cpu->env, ARM_FEATURE_V5);
 802     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 803     cpu->midr = 0x69052d00;
 804     cpu->ctr = 0xd172172;
 805     cpu->reset_sctlr = 0x00000078;
 806 }
 807
 808 static void pxa260_initfn(Object *obj)
 809 {
 810     ARMCPU *cpu = ARM_CPU(obj);
 811
 812     cpu->dtb_compatible = "marvell,xscale";
 813     set_feature(&cpu->env, ARM_FEATURE_V5);
 814     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 815     cpu->midr = 0x69052903;
 816     cpu->ctr = 0xd172172;
 817     cpu->reset_sctlr = 0x00000078;
 818 }
 819
 820 static void pxa261_initfn(Object *obj)
 821 {
 822     ARMCPU *cpu = ARM_CPU(obj);
 823
 824     cpu->dtb_compatible = "marvell,xscale";
 825     set_feature(&cpu->env, ARM_FEATURE_V5);
 826     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 827     cpu->midr = 0x69052d05;
 828     cpu->ctr = 0xd172172;
 829     cpu->reset_sctlr = 0x00000078;
 830 }
 831
 832 static void pxa262_initfn(Object *obj)
 833 {
 834     ARMCPU *cpu = ARM_CPU(obj);
 835
 836     cpu->dtb_compatible = "marvell,xscale";
 837     set_feature(&cpu->env, ARM_FEATURE_V5);
 838     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 839     cpu->midr = 0x69052d06;
 840     cpu->ctr = 0xd172172;
 841     cpu->reset_sctlr = 0x00000078;
 842 }
 843
 844 static void pxa270a0_initfn(Object *obj)
 845 {
 846     ARMCPU *cpu = ARM_CPU(obj);
 847
 848     cpu->dtb_compatible = "marvell,xscale";
 849     set_feature(&cpu->env, ARM_FEATURE_V5);
 850     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 851     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 852     cpu->midr = 0x69054110;
 853     cpu->ctr = 0xd172172;
 854     cpu->reset_sctlr = 0x00000078;
 855 }
 856
 857 static void pxa270a1_initfn(Object *obj)
 858 {
 859     ARMCPU *cpu = ARM_CPU(obj);
 860
 861     cpu->dtb_compatible = "marvell,xscale";
 862     set_feature(&cpu->env, ARM_FEATURE_V5);
 863     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 864     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 865     cpu->midr = 0x69054111;
 866     cpu->ctr = 0xd172172;
 867     cpu->reset_sctlr = 0x00000078;
 868 }
 869
 870 static void pxa270b0_initfn(Object *obj)
 871 {
 872     ARMCPU *cpu = ARM_CPU(obj);
 873
 874     cpu->dtb_compatible = "marvell,xscale";
 875     set_feature(&cpu->env, ARM_FEATURE_V5);
 876     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 877     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 878     cpu->midr = 0x69054112;
 879     cpu->ctr = 0xd172172;
 880     cpu->reset_sctlr = 0x00000078;
 881 }
 882
 883 static void pxa270b1_initfn(Object *obj)
 884 {
 885     ARMCPU *cpu = ARM_CPU(obj);
 886
 887     cpu->dtb_compatible = "marvell,xscale";
 888     set_feature(&cpu->env, ARM_FEATURE_V5);
 889     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 890     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 891     cpu->midr = 0x69054113;
 892     cpu->ctr = 0xd172172;
 893     cpu->reset_sctlr = 0x00000078;
 894 }
 895
 896 static void pxa270c0_initfn(Object *obj)
 897 {
 898     ARMCPU *cpu = ARM_CPU(obj);
 899
 900     cpu->dtb_compatible = "marvell,xscale";
 901     set_feature(&cpu->env, ARM_FEATURE_V5);
 902     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 903     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 904     cpu->midr = 0x69054114;
 905     cpu->ctr = 0xd172172;
 906     cpu->reset_sctlr = 0x00000078;
 907 }
 908
 909 static void pxa270c5_initfn(Object *obj)
 910 {
 911     ARMCPU *cpu = ARM_CPU(obj);
 912
 913     cpu->dtb_compatible = "marvell,xscale";
 914     set_feature(&cpu->env, ARM_FEATURE_V5);
 915     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 916     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 917     cpu->midr = 0x69054117;
 918     cpu->ctr = 0xd172172;
 919     cpu->reset_sctlr = 0x00000078;
 920 }
 921
 922 #ifdef CONFIG_USER_ONLY
 923 static void arm_any_initfn(Object *obj)
 924 {
 925     ARMCPU *cpu = ARM_CPU(obj);
 926     set_feature(&cpu->env, ARM_FEATURE_V8);
 927     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 928     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 929     set_feature(&cpu->env, ARM_FEATURE_NEON);
 930     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 931     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 932     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 933     set_feature(&cpu->env, ARM_FEATURE_CRC);
 934 #ifdef TARGET_AARCH64
 935     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 936 #endif
 937     cpu->midr = 0xffffffff;
 938 }
 939 #endif
 940
 941 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 942
 943 typedef struct ARMCPUInfo {
 944     const char *name;
 945     void (*initfn)(Object *obj);
 946     void (*class_init)(ObjectClass *oc, void *data);
 947 } ARMCPUInfo;
 948
 949 static const ARMCPUInfo arm_cpus[] = {
 950 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 951     { .name = "arm926",      .initfn = arm926_initfn },
 952     { .name = "arm946",      .initfn = arm946_initfn },
 953     { .name = "arm1026",     .initfn = arm1026_initfn },
 954     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 955      * older core than plain "arm1136". In particular this does not
 956      * have the v6K features.
 957      */
 958     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 959     { .name = "arm1136",     .initfn = arm1136_initfn },
 960     { .name = "arm1176",     .initfn = arm1176_initfn },
 961     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 962     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 963                              .class_init = arm_v7m_class_init },
 964     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 965     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 966     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 967     { .name = "ti925t",      .initfn = ti925t_initfn },
 968     { .name = "sa1100",      .initfn = sa1100_initfn },
 969     { .name = "sa1110",      .initfn = sa1110_initfn },
 970     { .name = "pxa250",      .initfn = pxa250_initfn },
 971     { .name = "pxa255",      .initfn = pxa255_initfn },
 972     { .name = "pxa260",      .initfn = pxa260_initfn },
 973     { .name = "pxa261",      .initfn = pxa261_initfn },
 974     { .name = "pxa262",      .initfn = pxa262_initfn },
 975     /* "pxa270" is an alias for "pxa270-a0" */
 976     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 977     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 978     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 979     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 980     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 981     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 982     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 983 #ifdef CONFIG_USER_ONLY
 984     { .name = "any",         .initfn = arm_any_initfn },
 985 #endif
 986 #endif
 987     { .name = NULL }
 988 };
 989
 990 static Property arm_cpu_properties[] = {
 991     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
 992     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
 993     DEFINE_PROP_END_OF_LIST()
 994 };
 995
 996 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 997 {
 998     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 999     CPUClass *cc = CPU_CLASS(acc);
1000     DeviceClass *dc = DEVICE_CLASS(oc);
1001
1002     acc->parent_realize = dc->realize;
1003     dc->realize = arm_cpu_realizefn;
1004     dc->props = arm_cpu_properties;
1005
1006     acc->parent_reset = cc->reset;
1007     cc->reset = arm_cpu_reset;
1008
1009     cc->class_by_name = arm_cpu_class_by_name;
1010     cc->has_work = arm_cpu_has_work;
1011     cc->do_interrupt = arm_cpu_do_interrupt;
1012     cc->dump_state = arm_cpu_dump_state;
1013     cc->set_pc = arm_cpu_set_pc;
1014     cc->gdb_read_register = arm_cpu_gdb_read_register;
1015     cc->gdb_write_register = arm_cpu_gdb_write_register;
1016 #ifdef CONFIG_USER_ONLY
1017     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1018 #else
1019     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1020     cc->vmsd = &vmstate_arm_cpu;
1021 #endif
1022     cc->gdb_num_core_regs = 26;
1023     cc->gdb_core_xml_file = "arm-core.xml";
1024 }
1025
1026 static void cpu_register(const ARMCPUInfo *info)
1027 {
1028     TypeInfo type_info = {
1029         .parent = TYPE_ARM_CPU,
1030         .instance_size = sizeof(ARMCPU),
1031         .instance_init = info->initfn,
1032         .class_size = sizeof(ARMCPUClass),
1033         .class_init = info->class_init,
1034     };
1035
1036     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1037     type_register(&type_info);
1038     g_free((void *)type_info.name);
1039 }
1040
1041 static const TypeInfo arm_cpu_type_info = {
1042     .name = TYPE_ARM_CPU,
1043     .parent = TYPE_CPU,
1044     .instance_size = sizeof(ARMCPU),
1045     .instance_init = arm_cpu_initfn,
1046     .instance_post_init = arm_cpu_post_init,
1047     .instance_finalize = arm_cpu_finalizefn,
1048     .abstract = true,
1049     .class_size = sizeof(ARMCPUClass),
1050     .class_init = arm_cpu_class_init,
1051 };
1052
1053 static void arm_cpu_register_types(void)
1054 {
1055     const ARMCPUInfo *info = arm_cpus;
1056
1057     type_register_static(&arm_cpu_type_info);
1058
1059     while (info->name) {
1060         cpu_register(info);
1061         info++;
1062     }
1063 }
1064
1065 type_init(arm_cpu_register_types)