hw/core/ptimer.c

   1 /*
   2  * General purpose implementation of a simple periodic countdown timer.
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  *
   6  * This code is licensed under the GNU LGPL.
   7  */
   8 #include "qemu/osdep.h"
   9 #include "hw/hw.h"
  10 #include "qemu/timer.h"
  11 #include "hw/ptimer.h"
  12 #include "qemu/host-utils.h"
  13 #include "sysemu/replay.h"
  14
  15 struct ptimer_state
  16 {
  17     uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot.  */
  18     uint64_t limit;
  19     uint64_t delta;
  20     uint32_t period_frac;
  21     int64_t period;
  22     int64_t last_event;
  23     int64_t next_event;
  24     QEMUBH *bh;
  25     QEMUTimer *timer;
  26 };
  27
  28 /* Use a bottom-half routine to avoid reentrancy issues.  */
  29 static void ptimer_trigger(ptimer_state *s)
  30 {
  31     if (s->bh) {
  32         replay_bh_schedule_event(s->bh);
  33     }
  34 }
  35
  36 static void ptimer_reload(ptimer_state *s)
  37 {
  38     uint32_t period_frac = s->period_frac;
  39     uint64_t period = s->period;
  40
  41     if (s->delta == 0) {
  42         ptimer_trigger(s);
  43         s->delta = s->limit;
  44     }
  45     if (s->delta == 0 || s->period == 0) {
  46         fprintf(stderr, "Timer with period zero, disabling\n");
  47         s->enabled = 0;
  48         return;
  49     }
  50
  51     /*
  52      * Artificially limit timeout rate to something
  53      * achievable under QEMU.  Otherwise, QEMU spends all
  54      * its time generating timer interrupts, and there
  55      * is no forward progress.
  56      * About ten microseconds is the fastest that really works
  57      * on the current generation of host machines.
  58      */
  59
  60     if (s->enabled == 1 && (s->delta * period < 10000) && !use_icount) {
  61         period = 10000 / s->delta;
  62         period_frac = 0;
  63     }
  64
  65     s->last_event = s->next_event;
  66     s->next_event = s->last_event + s->delta * period;
  67     if (period_frac) {
  68         s->next_event += ((int64_t)period_frac * s->delta) >> 32;
  69     }
  70     timer_mod(s->timer, s->next_event);
  71 }
  72
  73 static void ptimer_tick(void *opaque)
  74 {
  75     ptimer_state *s = (ptimer_state *)opaque;
  76     ptimer_trigger(s);
  77     s->delta = 0;
  78     if (s->enabled == 2) {
  79         s->enabled = 0;
  80     } else {
  81         ptimer_reload(s);
  82     }
  83 }
  84
  85 uint64_t ptimer_get_count(ptimer_state *s)
  86 {
  87     uint64_t counter;
  88
  89     if (s->enabled) {
  90         int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  91         int64_t next = s->next_event;
  92         bool expired = (now - next >= 0);
  93         bool oneshot = (s->enabled == 2);
  94
  95         /* Figure out the current counter value.  */
  96         if (expired) {
  97             /* Prevent timer underflowing if it should already have
  98                triggered.  */
  99             counter = 0;
 100         } else {
 101             uint64_t rem;
 102             uint64_t div;
 103             int clz1, clz2;
 104             int shift;
 105             uint32_t period_frac = s->period_frac;
 106             uint64_t period = s->period;
 107
 108             if (!oneshot && (s->delta * period < 10000) && !use_icount) {
 109                 period = 10000 / s->delta;
 110                 period_frac = 0;
 111             }
 112
 113             /* We need to divide time by period, where time is stored in
 114                rem (64-bit integer) and period is stored in period/period_frac
 115                (64.32 fixed point).
 116
 117                Doing full precision division is hard, so scale values and
 118                do a 64-bit division.  The result should be rounded down,
 119                so that the rounding error never causes the timer to go
 120                backwards.
 121             */
 122
 123             rem = next - now;
 124             div = period;
 125
 126             clz1 = clz64(rem);
 127             clz2 = clz64(div);
 128             shift = clz1 < clz2 ? clz1 : clz2;
 129
 130             rem <<= shift;
 131             div <<= shift;
 132             if (shift >= 32) {
 133                 div |= ((uint64_t)period_frac << (shift - 32));
 134             } else {
 135                 if (shift != 0)
 136                     div |= (period_frac >> (32 - shift));
 137                 /* Look at remaining bits of period_frac and round div up if
 138                    necessary.  */
 139                 if ((uint32_t)(period_frac << shift))
 140                     div += 1;
 141             }
 142             counter = rem / div;
 143         }
 144     } else {
 145         counter = s->delta;
 146     }
 147     return counter;
 148 }
 149
 150 void ptimer_set_count(ptimer_state *s, uint64_t count)
 151 {
 152     s->delta = count;
 153     if (s->enabled) {
 154         s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 155         ptimer_reload(s);
 156     }
 157 }
 158
 159 void ptimer_run(ptimer_state *s, int oneshot)
 160 {
 161     bool was_disabled = !s->enabled;
 162
 163     if (was_disabled && s->period == 0) {
 164         fprintf(stderr, "Timer with period zero, disabling\n");
 165         return;
 166     }
 167     s->enabled = oneshot ? 2 : 1;
 168     if (was_disabled) {
 169         s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 170         ptimer_reload(s);
 171     }
 172 }
 173
 174 /* Pause a timer.  Note that this may cause it to "lose" time, even if it
 175    is immediately restarted.  */
 176 void ptimer_stop(ptimer_state *s)
 177 {
 178     if (!s->enabled)
 179         return;
 180
 181     s->delta = ptimer_get_count(s);
 182     timer_del(s->timer);
 183     s->enabled = 0;
 184 }
 185
 186 /* Set counter increment interval in nanoseconds.  */
 187 void ptimer_set_period(ptimer_state *s, int64_t period)
 188 {
 189     s->delta = ptimer_get_count(s);
 190     s->period = period;
 191     s->period_frac = 0;
 192     if (s->enabled) {
 193         s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 194         ptimer_reload(s);
 195     }
 196 }
 197
 198 /* Set counter frequency in Hz.  */
 199 void ptimer_set_freq(ptimer_state *s, uint32_t freq)
 200 {
 201     s->delta = ptimer_get_count(s);
 202     s->period = 1000000000ll / freq;
 203     s->period_frac = (1000000000ll << 32) / freq;
 204     if (s->enabled) {
 205         s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 206         ptimer_reload(s);
 207     }
 208 }
 209
 210 /* Set the initial countdown value.  If reload is nonzero then also set
 211    count = limit.  */
 212 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload)
 213 {
 214     s->limit = limit;
 215     if (reload)
 216         s->delta = limit;
 217     if (s->enabled && reload) {
 218         s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 219         ptimer_reload(s);
 220     }
 221 }
 222
 223 uint64_t ptimer_get_limit(ptimer_state *s)
 224 {
 225     return s->limit;
 226 }
 227
 228 const VMStateDescription vmstate_ptimer = {
 229     .name = "ptimer",
 230     .version_id = 1,
 231     .minimum_version_id = 1,
 232     .fields = (VMStateField[]) {
 233         VMSTATE_UINT8(enabled, ptimer_state),
 234         VMSTATE_UINT64(limit, ptimer_state),
 235         VMSTATE_UINT64(delta, ptimer_state),
 236         VMSTATE_UINT32(period_frac, ptimer_state),
 237         VMSTATE_INT64(period, ptimer_state),
 238         VMSTATE_INT64(last_event, ptimer_state),
 239         VMSTATE_INT64(next_event, ptimer_state),
 240         VMSTATE_TIMER_PTR(timer, ptimer_state),
 241         VMSTATE_END_OF_LIST()
 242     }
 243 };
 244
 245 ptimer_state *ptimer_init(QEMUBH *bh)
 246 {
 247     ptimer_state *s;
 248
 249     s = (ptimer_state *)g_malloc0(sizeof(ptimer_state));
 250     s->bh = bh;
 251     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
 252     return s;
 253 }