include/hw/riscv/sifive_u_prci.h

   1 /*
   2  * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
   3  *
   4  * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_SIFIVE_U_PRCI_H
  20 #define HW_SIFIVE_U_PRCI_H
  21
  22 #define SIFIVE_U_PRCI_HFXOSCCFG     0x00
  23 #define SIFIVE_U_PRCI_COREPLLCFG0   0x04
  24 #define SIFIVE_U_PRCI_DDRPLLCFG0    0x0C
  25 #define SIFIVE_U_PRCI_DDRPLLCFG1    0x10
  26 #define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
  27 #define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
  28 #define SIFIVE_U_PRCI_CORECLKSEL    0x24
  29 #define SIFIVE_U_PRCI_DEVICESRESET  0x28
  30 #define SIFIVE_U_PRCI_CLKMUXSTATUS  0x2C
  31
  32 /*
  33  * Current FU540-C000 manual says ready bit is at bit 29, but
  34  * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
  35  * We have to trust the actual code that works.
  36  *
  37  * see https://github.com/sifive/freedom-u540-c000-bootloader
  38  */
  39
  40 #define SIFIVE_U_PRCI_HFXOSCCFG_EN  (1 << 30)
  41 #define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
  42
  43 /* xxxPLLCFG0 register bits */
  44 #define SIFIVE_U_PRCI_PLLCFG0_DIVR  (1 << 0)
  45 #define SIFIVE_U_PRCI_PLLCFG0_DIVF  (31 << 6)
  46 #define SIFIVE_U_PRCI_PLLCFG0_DIVQ  (3 << 15)
  47 #define SIFIVE_U_PRCI_PLLCFG0_FSE   (1 << 25)
  48 #define SIFIVE_U_PRCI_PLLCFG0_LOCK  (1 << 31)
  49
  50 /* xxxPLLCFG1 register bits */
  51 #define SIFIVE_U_PRCI_PLLCFG1_CKE   (1 << 24)
  52
  53 /* coreclksel register bits */
  54 #define SIFIVE_U_PRCI_CORECLKSEL_HFCLK  (1 << 0)
  55
  56
  57 #define SIFIVE_U_PRCI_REG_SIZE  0x1000
  58
  59 #define TYPE_SIFIVE_U_PRCI      "riscv.sifive.u.prci"
  60
  61 #define SIFIVE_U_PRCI(obj) \
  62     OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI)
  63
  64 typedef struct SiFiveUPRCIState {
  65     /*< private >*/
  66     SysBusDevice parent_obj;
  67
  68     /*< public >*/
  69     MemoryRegion mmio;
  70     uint32_t hfxosccfg;
  71     uint32_t corepllcfg0;
  72     uint32_t ddrpllcfg0;
  73     uint32_t ddrpllcfg1;
  74     uint32_t gemgxlpllcfg0;
  75     uint32_t gemgxlpllcfg1;
  76     uint32_t coreclksel;
  77     uint32_t devicesreset;
  78     uint32_t clkmuxstatus;
  79 } SiFiveUPRCIState;
  80
  81 /*
  82  * Clock indexes for use by Device Tree data and the PRCI driver.
  83  *
  84  * These values are from sifive-fu540-prci.h in the Linux kernel.
  85  */
  86 #define PRCI_CLK_COREPLL        0
  87 #define PRCI_CLK_DDRPLL         1
  88 #define PRCI_CLK_GEMGXLPLL      2
  89 #define PRCI_CLK_TLCLK          3
  90
  91 #endif /* HW_SIFIVE_U_PRCI_H */