hw/arm/mps2.c

   1 /*
   2  * ARM V2M MPS2 board emulation.
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * We model the following FPGA images:
  17  *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
  18  *  "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
  19  *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
  20  *
  21  * Links to the TRM for the board itself and to the various Application
  22  * Notes which document the FPGA images can be found here:
  23  *   https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu/units.h"
  28 #include "qemu/cutils.h"
  29 #include "qapi/error.h"
  30 #include "qemu/error-report.h"
  31 #include "hw/arm/boot.h"
  32 #include "hw/arm/armv7m.h"
  33 #include "hw/or-irq.h"
  34 #include "hw/boards.h"
  35 #include "exec/address-spaces.h"
  36 #include "sysemu/sysemu.h"
  37 #include "hw/misc/unimp.h"
  38 #include "hw/char/cmsdk-apb-uart.h"
  39 #include "hw/timer/cmsdk-apb-timer.h"
  40 #include "hw/timer/cmsdk-apb-dualtimer.h"
  41 #include "hw/misc/mps2-scc.h"
  42 #include "hw/misc/mps2-fpgaio.h"
  43 #include "hw/ssi/pl022.h"
  44 #include "hw/i2c/arm_sbcon_i2c.h"
  45 #include "hw/net/lan9118.h"
  46 #include "net/net.h"
  47 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  48 #include "qom/object.h"
  49
  50 typedef enum MPS2FPGAType {
  51     FPGA_AN385,
  52     FPGA_AN386,
  53     FPGA_AN511,
  54 } MPS2FPGAType;
  55
  56 struct MPS2MachineClass {
  57     MachineClass parent;
  58     MPS2FPGAType fpga_type;
  59     uint32_t scc_id;
  60 };
  61 typedef struct MPS2MachineClass MPS2MachineClass;
  62
  63 struct MPS2MachineState {
  64     MachineState parent;
  65
  66     ARMv7MState armv7m;
  67     MemoryRegion ssram1;
  68     MemoryRegion ssram1_m;
  69     MemoryRegion ssram23;
  70     MemoryRegion ssram23_m;
  71     MemoryRegion blockram;
  72     MemoryRegion blockram_m1;
  73     MemoryRegion blockram_m2;
  74     MemoryRegion blockram_m3;
  75     MemoryRegion sram;
  76     /* FPGA APB subsystem */
  77     MPS2SCC scc;
  78     MPS2FPGAIO fpgaio;
  79     /* CMSDK APB subsystem */
  80     CMSDKAPBDualTimer dualtimer;
  81     CMSDKAPBWatchdog watchdog;
  82 };
  83 typedef struct MPS2MachineState MPS2MachineState;
  84
  85 #define TYPE_MPS2_MACHINE "mps2"
  86 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
  87 #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
  88 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
  89
  90 DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass,
  91                      MPS2_MACHINE, TYPE_MPS2_MACHINE)
  92
  93 /* Main SYSCLK frequency in Hz */
  94 #define SYSCLK_FRQ 25000000
  95
  96 /* Initialize the auxiliary RAM region @mr and map it into
  97  * the memory map at @base.
  98  */
  99 static void make_ram(MemoryRegion *mr, const char *name,
 100                      hwaddr base, hwaddr size)
 101 {
 102     memory_region_init_ram(mr, NULL, name, size, &error_fatal);
 103     memory_region_add_subregion(get_system_memory(), base, mr);
 104 }
 105
 106 /* Create an alias of an entire original MemoryRegion @orig
 107  * located at @base in the memory map.
 108  */
 109 static void make_ram_alias(MemoryRegion *mr, const char *name,
 110                            MemoryRegion *orig, hwaddr base)
 111 {
 112     memory_region_init_alias(mr, NULL, name, orig, 0,
 113                              memory_region_size(orig));
 114     memory_region_add_subregion(get_system_memory(), base, mr);
 115 }
 116
 117 static void mps2_common_init(MachineState *machine)
 118 {
 119     MPS2MachineState *mms = MPS2_MACHINE(machine);
 120     MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
 121     MemoryRegion *system_memory = get_system_memory();
 122     MachineClass *mc = MACHINE_GET_CLASS(machine);
 123     DeviceState *armv7m, *sccdev;
 124     int i;
 125
 126     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 127         error_report("This board can only be used with CPU %s",
 128                      mc->default_cpu_type);
 129         exit(1);
 130     }
 131
 132     if (machine->ram_size != mc->default_ram_size) {
 133         char *sz = size_to_str(mc->default_ram_size);
 134         error_report("Invalid RAM size, should be %s", sz);
 135         g_free(sz);
 136         exit(EXIT_FAILURE);
 137     }
 138
 139     /* The FPGA images have an odd combination of different RAMs,
 140      * because in hardware they are different implementations and
 141      * connected to different buses, giving varying performance/size
 142      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 143      * call the 16MB our "system memory", as it's the largest lump.
 144      *
 145      * AN385/AN386/AN511:
 146      *  0x21000000 .. 0x21ffffff : PSRAM (16MB)
 147      * AN385/AN386 only:
 148      *  0x00000000 .. 0x003fffff : ZBT SSRAM1
 149      *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
 150      *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
 151      *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
 152      *  0x01000000 .. 0x01003fff : block RAM (16K)
 153      *  0x01004000 .. 0x01007fff : mirror of above
 154      *  0x01008000 .. 0x0100bfff : mirror of above
 155      *  0x0100c000 .. 0x0100ffff : mirror of above
 156      * AN511 only:
 157      *  0x00000000 .. 0x0003ffff : FPGA block RAM
 158      *  0x00400000 .. 0x007fffff : ZBT SSRAM1
 159      *  0x20000000 .. 0x2001ffff : SRAM
 160      *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
 161      *
 162      * The AN385/AN386 has a feature where the lowest 16K can be mapped
 163      * either to the bottom of the ZBT SSRAM1 or to the block RAM.
 164      * This is of no use for QEMU so we don't implement it (as if
 165      * zbt_boot_ctrl is always zero).
 166      */
 167     memory_region_add_subregion(system_memory, 0x21000000, machine->ram);
 168
 169     switch (mmc->fpga_type) {
 170     case FPGA_AN385:
 171     case FPGA_AN386:
 172         make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
 173         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
 174         make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
 175         make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
 176                        &mms->ssram23, 0x20400000);
 177         make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
 178         make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
 179                        &mms->blockram, 0x01004000);
 180         make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
 181                        &mms->blockram, 0x01008000);
 182         make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
 183                        &mms->blockram, 0x0100c000);
 184         break;
 185     case FPGA_AN511:
 186         make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
 187         make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
 188         make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
 189         make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
 190         break;
 191     default:
 192         g_assert_not_reached();
 193     }
 194
 195     object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M);
 196     armv7m = DEVICE(&mms->armv7m);
 197     switch (mmc->fpga_type) {
 198     case FPGA_AN385:
 199     case FPGA_AN386:
 200         qdev_prop_set_uint32(armv7m, "num-irq", 32);
 201         break;
 202     case FPGA_AN511:
 203         qdev_prop_set_uint32(armv7m, "num-irq", 64);
 204         break;
 205     default:
 206         g_assert_not_reached();
 207     }
 208     qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
 209     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 210     object_property_set_link(OBJECT(&mms->armv7m), "memory",
 211                              OBJECT(system_memory), &error_abort);
 212     sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal);
 213
 214     create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
 215     create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
 216     create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
 217     create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
 218     create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
 219     create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
 220     /* These three ranges all cover multiple devices; we may implement
 221      * some of them below (in which case the real device takes precedence
 222      * over the unimplemented-region mapping).
 223      */
 224     create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
 225                                 0x40000000, 0x00010000);
 226     create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
 227                                 0x40010000, 0x00010000);
 228     create_unimplemented_device("Extra peripheral region @0x40020000",
 229                                 0x40020000, 0x00010000);
 230
 231     create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
 232     create_unimplemented_device("VGA", 0x41000000, 0x0200000);
 233
 234     switch (mmc->fpga_type) {
 235     case FPGA_AN385:
 236     case FPGA_AN386:
 237     {
 238         /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
 239          * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
 240          */
 241         Object *orgate;
 242         DeviceState *orgate_dev;
 243
 244         orgate = object_new(TYPE_OR_IRQ);
 245         object_property_set_int(orgate, "num-lines", 6, &error_fatal);
 246         qdev_realize(DEVICE(orgate), NULL, &error_fatal);
 247         orgate_dev = DEVICE(orgate);
 248         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 249
 250         for (i = 0; i < 5; i++) {
 251             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 252                                               0x40006000, 0x40007000,
 253                                               0x40009000};
 254             /* RX irq number; TX irq is always one greater */
 255             static const int uartirq[] = {0, 2, 4, 18, 20};
 256             qemu_irq txovrint = NULL, rxovrint = NULL;
 257
 258             if (i < 3) {
 259                 txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
 260                 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
 261             }
 262
 263             cmsdk_apb_uart_create(uartbase[i],
 264                                   qdev_get_gpio_in(armv7m, uartirq[i] + 1),
 265                                   qdev_get_gpio_in(armv7m, uartirq[i]),
 266                                   txovrint, rxovrint,
 267                                   NULL,
 268                                   serial_hd(i), SYSCLK_FRQ);
 269         }
 270         break;
 271     }
 272     case FPGA_AN511:
 273     {
 274         /* The overflow IRQs for all UARTs are ORed together.
 275          * Tx and Rx IRQs for each UART are ORed together.
 276          */
 277         Object *orgate;
 278         DeviceState *orgate_dev;
 279
 280         orgate = object_new(TYPE_OR_IRQ);
 281         object_property_set_int(orgate, "num-lines", 10, &error_fatal);
 282         qdev_realize(DEVICE(orgate), NULL, &error_fatal);
 283         orgate_dev = DEVICE(orgate);
 284         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 285
 286         for (i = 0; i < 5; i++) {
 287             /* system irq numbers for the combined tx/rx for each UART */
 288             static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
 289             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 290                                               0x4002c000, 0x4002d000,
 291                                               0x4002e000};
 292             Object *txrx_orgate;
 293             DeviceState *txrx_orgate_dev;
 294
 295             txrx_orgate = object_new(TYPE_OR_IRQ);
 296             object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal);
 297             qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal);
 298             txrx_orgate_dev = DEVICE(txrx_orgate);
 299             qdev_connect_gpio_out(txrx_orgate_dev, 0,
 300                                   qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
 301             cmsdk_apb_uart_create(uartbase[i],
 302                                   qdev_get_gpio_in(txrx_orgate_dev, 0),
 303                                   qdev_get_gpio_in(txrx_orgate_dev, 1),
 304                                   qdev_get_gpio_in(orgate_dev, i * 2),
 305                                   qdev_get_gpio_in(orgate_dev, i * 2 + 1),
 306                                   NULL,
 307                                   serial_hd(i), SYSCLK_FRQ);
 308         }
 309         break;
 310     }
 311     default:
 312         g_assert_not_reached();
 313     }
 314     for (i = 0; i < 4; i++) {
 315         static const hwaddr gpiobase[] = {0x40010000, 0x40011000,
 316                                           0x40012000, 0x40013000};
 317         create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000);
 318     }
 319
 320     /* CMSDK APB subsystem */
 321     cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
 322     cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
 323     object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
 324                             TYPE_CMSDK_APB_DUALTIMER);
 325     qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
 326     sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
 327     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
 328                        qdev_get_gpio_in(armv7m, 10));
 329     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
 330     object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
 331                             TYPE_CMSDK_APB_WATCHDOG);
 332     qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
 333     sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
 334     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
 335                        qdev_get_gpio_in_named(armv7m, "NMI", 0));
 336     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000);
 337
 338     /* FPGA APB subsystem */
 339     object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
 340     sccdev = DEVICE(&mms->scc);
 341     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 342     qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
 343     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 344     sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
 345     sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
 346     object_initialize_child(OBJECT(mms), "fpgaio",
 347                             &mms->fpgaio, TYPE_MPS2_FPGAIO);
 348     qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
 349     sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
 350     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
 351     sysbus_create_simple(TYPE_PL022, 0x40025000,        /* External ADC */
 352                          qdev_get_gpio_in(armv7m, 22));
 353     for (i = 0; i < 2; i++) {
 354         static const int spi_irqno[] = {11, 24};
 355         static const hwaddr spibase[] = {0x40020000,    /* APB */
 356                                          0x40021000,    /* LCD */
 357                                          0x40026000,    /* Shield0 */
 358                                          0x40027000};   /* Shield1 */
 359         DeviceState *orgate_dev;
 360         Object *orgate;
 361         int j;
 362
 363         orgate = object_new(TYPE_OR_IRQ);
 364         object_property_set_int(orgate, "num-lines", 2, &error_fatal);
 365         orgate_dev = DEVICE(orgate);
 366         qdev_realize(orgate_dev, NULL, &error_fatal);
 367         qdev_connect_gpio_out(orgate_dev, 0,
 368                               qdev_get_gpio_in(armv7m, spi_irqno[i]));
 369         for (j = 0; j < 2; j++) {
 370             sysbus_create_simple(TYPE_PL022, spibase[2 * i + j],
 371                                  qdev_get_gpio_in(orgate_dev, j));
 372         }
 373     }
 374     for (i = 0; i < 4; i++) {
 375         static const hwaddr i2cbase[] = {0x40022000,    /* Touch */
 376                                          0x40023000,    /* Audio */
 377                                          0x40029000,    /* Shield0 */
 378                                          0x4002a000};   /* Shield1 */
 379         sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
 380     }
 381     create_unimplemented_device("i2s", 0x40024000, 0x400);
 382
 383     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 384      * except that it doesn't support the checksum-offload feature.
 385      */
 386     lan9118_init(&nd_table[0], 0x40200000,
 387                  qdev_get_gpio_in(armv7m,
 388                                   mmc->fpga_type == FPGA_AN511 ? 47 : 13));
 389
 390     system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
 391
 392     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
 393                        0x400000);
 394 }
 395
 396 static void mps2_class_init(ObjectClass *oc, void *data)
 397 {
 398     MachineClass *mc = MACHINE_CLASS(oc);
 399
 400     mc->init = mps2_common_init;
 401     mc->max_cpus = 1;
 402     mc->default_ram_size = 16 * MiB;
 403     mc->default_ram_id = "mps.ram";
 404 }
 405
 406 static void mps2_an385_class_init(ObjectClass *oc, void *data)
 407 {
 408     MachineClass *mc = MACHINE_CLASS(oc);
 409     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 410
 411     mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
 412     mmc->fpga_type = FPGA_AN385;
 413     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 414     mmc->scc_id = 0x41043850;
 415 }
 416
 417 static void mps2_an386_class_init(ObjectClass *oc, void *data)
 418 {
 419     MachineClass *mc = MACHINE_CLASS(oc);
 420     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 421
 422     mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
 423     mmc->fpga_type = FPGA_AN386;
 424     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
 425     mmc->scc_id = 0x41043860;
 426 }
 427
 428 static void mps2_an511_class_init(ObjectClass *oc, void *data)
 429 {
 430     MachineClass *mc = MACHINE_CLASS(oc);
 431     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 432
 433     mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
 434     mmc->fpga_type = FPGA_AN511;
 435     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 436     mmc->scc_id = 0x41045110;
 437 }
 438
 439 static const TypeInfo mps2_info = {
 440     .name = TYPE_MPS2_MACHINE,
 441     .parent = TYPE_MACHINE,
 442     .abstract = true,
 443     .instance_size = sizeof(MPS2MachineState),
 444     .class_size = sizeof(MPS2MachineClass),
 445     .class_init = mps2_class_init,
 446 };
 447
 448 static const TypeInfo mps2_an385_info = {
 449     .name = TYPE_MPS2_AN385_MACHINE,
 450     .parent = TYPE_MPS2_MACHINE,
 451     .class_init = mps2_an385_class_init,
 452 };
 453
 454 static const TypeInfo mps2_an386_info = {
 455     .name = TYPE_MPS2_AN386_MACHINE,
 456     .parent = TYPE_MPS2_MACHINE,
 457     .class_init = mps2_an386_class_init,
 458 };
 459
 460 static const TypeInfo mps2_an511_info = {
 461     .name = TYPE_MPS2_AN511_MACHINE,
 462     .parent = TYPE_MPS2_MACHINE,
 463     .class_init = mps2_an511_class_init,
 464 };
 465
 466 static void mps2_machine_init(void)
 467 {
 468     type_register_static(&mps2_info);
 469     type_register_static(&mps2_an385_info);
 470     type_register_static(&mps2_an386_info);
 471     type_register_static(&mps2_an511_info);
 472 }
 473
 474 type_init(mps2_machine_init);