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spapr: Adjust default VSMT value for better migration compatibility
[qemu/ar7.git] / hw / ppc / spapr.c
blob499ab647d8829dad32dea7988b06cb33df7ed864
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
32 #include "hw/hw.h"
33 #include "qemu/log.h"
34 #include "hw/fw-path-provider.h"
35 #include "elf.h"
36 #include "net/net.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/cpus.h"
40 #include "sysemu/hw_accel.h"
41 #include "kvm_ppc.h"
42 #include "migration/misc.h"
43 #include "migration/global_state.h"
44 #include "migration/register.h"
45 #include "mmu-hash64.h"
46 #include "mmu-book3s-v3.h"
47 #include "cpu-models.h"
48 #include "qom/cpu.h"
49
50 #include "hw/boards.h"
51 #include "hw/ppc/ppc.h"
52 #include "hw/loader.h"
53
54 #include "hw/ppc/fdt.h"
55 #include "hw/ppc/spapr.h"
56 #include "hw/ppc/spapr_vio.h"
57 #include "hw/pci-host/spapr.h"
58 #include "hw/ppc/xics.h"
59 #include "hw/pci/msi.h"
60
61 #include "hw/pci/pci.h"
62 #include "hw/scsi/scsi.h"
63 #include "hw/virtio/virtio-scsi.h"
64 #include "hw/virtio/vhost-scsi-common.h"
65
66 #include "exec/address-spaces.h"
67 #include "hw/usb.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
70 #include "trace.h"
71 #include "hw/nmi.h"
72 #include "hw/intc/intc.h"
73
74 #include "hw/compat.h"
75 #include "qemu/cutils.h"
76 #include "hw/ppc/spapr_cpu_core.h"
77 #include "qmp-commands.h"
78
79 #include <libfdt.h>
80
81 /* SLOF memory layout:
82 *
83 * SLOF raw image loaded at 0, copies its romfs right below the flat
84 * device-tree, then position SLOF itself 31M below that
85 *
86 * So we set FW_OVERHEAD to 40MB which should account for all of that
87 * and more
88 *
89 * We load our kernel at 4M, leaving space for SLOF initial image
90 */
91 #define FDT_MAX_SIZE 0x100000
92 #define RTAS_MAX_SIZE 0x10000
93 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
94 #define FW_MAX_SIZE 0x400000
95 #define FW_FILE_NAME "slof.bin"
96 #define FW_OVERHEAD 0x2800000
97 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
98
99 #define MIN_RMA_SLOF 128UL
100
101 #define PHANDLE_XICP 0x00001111
102
103 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
104 const char *type_ics,
105 int nr_irqs, Error **errp)
106 {
107 Error *local_err = NULL;
108 Object *obj;
109
110 obj = object_new(type_ics);
111 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
112 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
113 &error_abort);
114 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
115 if (local_err) {
116 goto error;
117 }
118 object_property_set_bool(obj, true, "realized", &local_err);
119 if (local_err) {
120 goto error;
121 }
122
123 return ICS_SIMPLE(obj);
124
125 error:
126 error_propagate(errp, local_err);
127 return NULL;
128 }
129
130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
131 {
132 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
133 * and newer QEMUs don't even have them. In both cases, we don't want
134 * to send anything on the wire.
135 */
136 return false;
137 }
138
139 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
140 .name = "icp/server",
141 .version_id = 1,
142 .minimum_version_id = 1,
143 .needed = pre_2_10_vmstate_dummy_icp_needed,
144 .fields = (VMStateField[]) {
145 VMSTATE_UNUSED(4), /* uint32_t xirr */
146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
147 VMSTATE_UNUSED(1), /* uint8_t mfrr */
148 VMSTATE_END_OF_LIST()
149 },
150 };
151
152 static void pre_2_10_vmstate_register_dummy_icp(int i)
153 {
154 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
155 (void *)(uintptr_t) i);
156 }
157
158 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
159 {
160 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
161 (void *)(uintptr_t) i);
162 }
163
164 static inline int xics_max_server_number(void)
165 {
166 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads);
167 }
168
169 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
170 {
171 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
172 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
173
174 if (kvm_enabled()) {
175 if (machine_kernel_irqchip_allowed(machine) &&
176 !xics_kvm_init(spapr, errp)) {
177 spapr->icp_type = TYPE_KVM_ICP;
178 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
179 }
180 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
181 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
182 return;
183 }
184 }
185
186 if (!spapr->ics) {
187 xics_spapr_init(spapr);
188 spapr->icp_type = TYPE_ICP;
189 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
190 if (!spapr->ics) {
191 return;
192 }
193 }
194
195 if (smc->pre_2_10_has_unused_icps) {
196 int i;
197
198 for (i = 0; i < xics_max_server_number(); i++) {
199 /* Dummy entries get deregistered when real ICPState objects
200 * are registered during CPU core hotplug.
201 */
202 pre_2_10_vmstate_register_dummy_icp(i);
203 }
204 }
205 }
206
207 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
208 int smt_threads)
209 {
210 int i, ret = 0;
211 uint32_t servers_prop[smt_threads];
212 uint32_t gservers_prop[smt_threads * 2];
213 int index = spapr_vcpu_id(cpu);
214
215 if (cpu->compat_pvr) {
216 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
217 if (ret < 0) {
218 return ret;
219 }
220 }
221
222 /* Build interrupt servers and gservers properties */
223 for (i = 0; i < smt_threads; i++) {
224 servers_prop[i] = cpu_to_be32(index + i);
225 /* Hack, direct the group queues back to cpu 0 */
226 gservers_prop[i*2] = cpu_to_be32(index + i);
227 gservers_prop[i*2 + 1] = 0;
228 }
229 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
230 servers_prop, sizeof(servers_prop));
231 if (ret < 0) {
232 return ret;
233 }
234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
235 gservers_prop, sizeof(gservers_prop));
236
237 return ret;
238 }
239
240 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
241 {
242 int index = spapr_vcpu_id(cpu);
243 uint32_t associativity[] = {cpu_to_be32(0x5),
244 cpu_to_be32(0x0),
245 cpu_to_be32(0x0),
246 cpu_to_be32(0x0),
247 cpu_to_be32(cpu->node_id),
248 cpu_to_be32(index)};
249
250 /* Advertise NUMA via ibm,associativity */
251 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
252 sizeof(associativity));
253 }
254
255 /* Populate the "ibm,pa-features" property */
256 static void spapr_populate_pa_features(sPAPRMachineState *spapr,
257 PowerPCCPU *cpu,
258 void *fdt, int offset,
259 bool legacy_guest)
260 {
261 CPUPPCState *env = &cpu->env;
262 uint8_t pa_features_206[] = { 6, 0,
263 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
264 uint8_t pa_features_207[] = { 24, 0,
265 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
266 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
267 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
268 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
269 uint8_t pa_features_300[] = { 66, 0,
270 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
271 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
272 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
273 /* 6: DS207 */
274 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
275 /* 16: Vector */
276 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
277 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
278 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
279 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
280 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
281 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
282 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
283 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
285 /* 42: PM, 44: PC RA, 46: SC vec'd */
286 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
287 /* 48: SIMD, 50: QP BFP, 52: String */
288 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
289 /* 54: DecFP, 56: DecI, 58: SHA */
290 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
291 /* 60: NM atomic, 62: RNG */
292 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
293 };
294 uint8_t *pa_features = NULL;
295 size_t pa_size;
296
297 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
298 pa_features = pa_features_206;
299 pa_size = sizeof(pa_features_206);
300 }
301 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
302 pa_features = pa_features_207;
303 pa_size = sizeof(pa_features_207);
304 }
305 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
306 pa_features = pa_features_300;
307 pa_size = sizeof(pa_features_300);
308 }
309 if (!pa_features) {
310 return;
311 }
312
313 if (env->ci_large_pages) {
314 /*
315 * Note: we keep CI large pages off by default because a 64K capable
316 * guest provisioned with large pages might otherwise try to map a qemu
317 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
318 * even if that qemu runs on a 4k host.
319 * We dd this bit back here if we are confident this is not an issue
320 */
321 pa_features[3] |= 0x20;
322 }
323 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
324 pa_features[24] |= 0x80; /* Transactional memory support */
325 }
326 if (legacy_guest && pa_size > 40) {
327 /* Workaround for broken kernels that attempt (guest) radix
328 * mode when they can't handle it, if they see the radix bit set
329 * in pa-features. So hide it from them. */
330 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
331 }
332
333 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
334 }
335
336 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
337 {
338 int ret = 0, offset, cpus_offset;
339 CPUState *cs;
340 char cpu_model[32];
341 int smt = kvmppc_smt_threads();
342 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
343
344 CPU_FOREACH(cs) {
345 PowerPCCPU *cpu = POWERPC_CPU(cs);
346 DeviceClass *dc = DEVICE_GET_CLASS(cs);
347 int index = spapr_vcpu_id(cpu);
348 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
349
350 if ((index % smt) != 0) {
351 continue;
352 }
353
354 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
355
356 cpus_offset = fdt_path_offset(fdt, "/cpus");
357 if (cpus_offset < 0) {
358 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
359 if (cpus_offset < 0) {
360 return cpus_offset;
361 }
362 }
363 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
364 if (offset < 0) {
365 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
366 if (offset < 0) {
367 return offset;
368 }
369 }
370
371 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
372 pft_size_prop, sizeof(pft_size_prop));
373 if (ret < 0) {
374 return ret;
375 }
376
377 if (nb_numa_nodes > 1) {
378 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
379 if (ret < 0) {
380 return ret;
381 }
382 }
383
384 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
385 if (ret < 0) {
386 return ret;
387 }
388
389 spapr_populate_pa_features(spapr, cpu, fdt, offset,
390 spapr->cas_legacy_guest_workaround);
391 }
392 return ret;
393 }
394
395 static hwaddr spapr_node0_size(MachineState *machine)
396 {
397 if (nb_numa_nodes) {
398 int i;
399 for (i = 0; i < nb_numa_nodes; ++i) {
400 if (numa_info[i].node_mem) {
401 return MIN(pow2floor(numa_info[i].node_mem),
402 machine->ram_size);
403 }
404 }
405 }
406 return machine->ram_size;
407 }
408
409 static void add_str(GString *s, const gchar *s1)
410 {
411 g_string_append_len(s, s1, strlen(s1) + 1);
412 }
413
414 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
415 hwaddr size)
416 {
417 uint32_t associativity[] = {
418 cpu_to_be32(0x4), /* length */
419 cpu_to_be32(0x0), cpu_to_be32(0x0),
420 cpu_to_be32(0x0), cpu_to_be32(nodeid)
421 };
422 char mem_name[32];
423 uint64_t mem_reg_property[2];
424 int off;
425
426 mem_reg_property[0] = cpu_to_be64(start);
427 mem_reg_property[1] = cpu_to_be64(size);
428
429 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
430 off = fdt_add_subnode(fdt, 0, mem_name);
431 _FDT(off);
432 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
433 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
434 sizeof(mem_reg_property))));
435 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
436 sizeof(associativity))));
437 return off;
438 }
439
440 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
441 {
442 MachineState *machine = MACHINE(spapr);
443 hwaddr mem_start, node_size;
444 int i, nb_nodes = nb_numa_nodes;
445 NodeInfo *nodes = numa_info;
446 NodeInfo ramnode;
447
448 /* No NUMA nodes, assume there is just one node with whole RAM */
449 if (!nb_numa_nodes) {
450 nb_nodes = 1;
451 ramnode.node_mem = machine->ram_size;
452 nodes = &ramnode;
453 }
454
455 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
456 if (!nodes[i].node_mem) {
457 continue;
458 }
459 if (mem_start >= machine->ram_size) {
460 node_size = 0;
461 } else {
462 node_size = nodes[i].node_mem;
463 if (node_size > machine->ram_size - mem_start) {
464 node_size = machine->ram_size - mem_start;
465 }
466 }
467 if (!mem_start) {
468 /* ppc_spapr_init() checks for rma_size <= node0_size already */
469 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
470 mem_start += spapr->rma_size;
471 node_size -= spapr->rma_size;
472 }
473 for ( ; node_size; ) {
474 hwaddr sizetmp = pow2floor(node_size);
475
476 /* mem_start != 0 here */
477 if (ctzl(mem_start) < ctzl(sizetmp)) {
478 sizetmp = 1ULL << ctzl(mem_start);
479 }
480
481 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
482 node_size -= sizetmp;
483 mem_start += sizetmp;
484 }
485 }
486
487 return 0;
488 }
489
490 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
491 sPAPRMachineState *spapr)
492 {
493 PowerPCCPU *cpu = POWERPC_CPU(cs);
494 CPUPPCState *env = &cpu->env;
495 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
496 int index = spapr_vcpu_id(cpu);
497 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
498 0xffffffff, 0xffffffff};
499 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
500 : SPAPR_TIMEBASE_FREQ;
501 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
502 uint32_t page_sizes_prop[64];
503 size_t page_sizes_prop_size;
504 uint32_t vcpus_per_socket = smp_threads * smp_cores;
505 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
506 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
507 sPAPRDRConnector *drc;
508 int drc_index;
509 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
510 int i;
511
512 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
513 if (drc) {
514 drc_index = spapr_drc_index(drc);
515 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
516 }
517
518 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
519 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
520
521 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
522 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
523 env->dcache_line_size)));
524 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
525 env->dcache_line_size)));
526 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
527 env->icache_line_size)));
528 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
529 env->icache_line_size)));
530
531 if (pcc->l1_dcache_size) {
532 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
533 pcc->l1_dcache_size)));
534 } else {
535 warn_report("Unknown L1 dcache size for cpu");
536 }
537 if (pcc->l1_icache_size) {
538 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
539 pcc->l1_icache_size)));
540 } else {
541 warn_report("Unknown L1 icache size for cpu");
542 }
543
544 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
545 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
546 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
547 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
548 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
549 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
550
551 if (env->spr_cb[SPR_PURR].oea_read) {
552 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
553 }
554
555 if (env->mmu_model & POWERPC_MMU_1TSEG) {
556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
557 segs, sizeof(segs))));
558 }
559
560 /* Advertise VSX (vector extensions) if available
561 * 1 == VMX / Altivec available
562 * 2 == VSX available
563 *
564 * Only CPUs for which we create core types in spapr_cpu_core.c
565 * are possible, and all of those have VMX */
566 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
567 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
568 } else {
569 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
570 }
571
572 /* Advertise DFP (Decimal Floating Point) if available
573 * 0 / no property == no DFP
574 * 1 == DFP available */
575 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
576 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
577 }
578
579 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
580 sizeof(page_sizes_prop));
581 if (page_sizes_prop_size) {
582 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
583 page_sizes_prop, page_sizes_prop_size)));
584 }
585
586 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
587
588 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
589 cs->cpu_index / vcpus_per_socket)));
590
591 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
592 pft_size_prop, sizeof(pft_size_prop))));
593
594 if (nb_numa_nodes > 1) {
595 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
596 }
597
598 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
599
600 if (pcc->radix_page_info) {
601 for (i = 0; i < pcc->radix_page_info->count; i++) {
602 radix_AP_encodings[i] =
603 cpu_to_be32(pcc->radix_page_info->entries[i]);
604 }
605 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
606 radix_AP_encodings,
607 pcc->radix_page_info->count *
608 sizeof(radix_AP_encodings[0]))));
609 }
610 }
611
612 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
613 {
614 CPUState *cs;
615 int cpus_offset;
616 char *nodename;
617 int smt = kvmppc_smt_threads();
618
619 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
620 _FDT(cpus_offset);
621 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
622 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
623
624 /*
625 * We walk the CPUs in reverse order to ensure that CPU DT nodes
626 * created by fdt_add_subnode() end up in the right order in FDT
627 * for the guest kernel the enumerate the CPUs correctly.
628 */
629 CPU_FOREACH_REVERSE(cs) {
630 PowerPCCPU *cpu = POWERPC_CPU(cs);
631 int index = spapr_vcpu_id(cpu);
632 DeviceClass *dc = DEVICE_GET_CLASS(cs);
633 int offset;
634
635 if ((index % smt) != 0) {
636 continue;
637 }
638
639 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
640 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
641 g_free(nodename);
642 _FDT(offset);
643 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
644 }
645
646 }
647
648 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
649 {
650 MemoryDeviceInfoList *info;
651
652 for (info = list; info; info = info->next) {
653 MemoryDeviceInfo *value = info->value;
654
655 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
656 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
657
658 if (pcdimm_info->addr >= addr &&
659 addr < (pcdimm_info->addr + pcdimm_info->size)) {
660 return pcdimm_info->node;
661 }
662 }
663 }
664
665 return -1;
666 }
667
668 /*
669 * Adds ibm,dynamic-reconfiguration-memory node.
670 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
671 * of this device tree node.
672 */
673 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
674 {
675 MachineState *machine = MACHINE(spapr);
676 int ret, i, offset;
677 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
678 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
679 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
680 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
681 memory_region_size(&spapr->hotplug_memory.mr)) /
682 lmb_size;
683 uint32_t *int_buf, *cur_index, buf_len;
684 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
685 MemoryDeviceInfoList *dimms = NULL;
686
687 /*
688 * Don't create the node if there is no hotpluggable memory
689 */
690 if (machine->ram_size == machine->maxram_size) {
691 return 0;
692 }
693
694 /*
695 * Allocate enough buffer size to fit in ibm,dynamic-memory
696 * or ibm,associativity-lookup-arrays
697 */
698 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
699 * sizeof(uint32_t);
700 cur_index = int_buf = g_malloc0(buf_len);
701
702 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
703
704 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
705 sizeof(prop_lmb_size));
706 if (ret < 0) {
707 goto out;
708 }
709
710 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
711 if (ret < 0) {
712 goto out;
713 }
714
715 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
716 if (ret < 0) {
717 goto out;
718 }
719
720 if (hotplug_lmb_start) {
721 MemoryDeviceInfoList **prev = &dimms;
722 qmp_pc_dimm_device_list(qdev_get_machine(), &prev);
723 }
724
725 /* ibm,dynamic-memory */
726 int_buf[0] = cpu_to_be32(nr_lmbs);
727 cur_index++;
728 for (i = 0; i < nr_lmbs; i++) {
729 uint64_t addr = i * lmb_size;
730 uint32_t *dynamic_memory = cur_index;
731
732 if (i >= hotplug_lmb_start) {
733 sPAPRDRConnector *drc;
734
735 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
736 g_assert(drc);
737
738 dynamic_memory[0] = cpu_to_be32(addr >> 32);
739 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
740 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
741 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
742 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
743 if (memory_region_present(get_system_memory(), addr)) {
744 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
745 } else {
746 dynamic_memory[5] = cpu_to_be32(0);
747 }
748 } else {
749 /*
750 * LMB information for RMA, boot time RAM and gap b/n RAM and
751 * hotplug memory region -- all these are marked as reserved
752 * and as having no valid DRC.
753 */
754 dynamic_memory[0] = cpu_to_be32(addr >> 32);
755 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
756 dynamic_memory[2] = cpu_to_be32(0);
757 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
758 dynamic_memory[4] = cpu_to_be32(-1);
759 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
760 SPAPR_LMB_FLAGS_DRC_INVALID);
761 }
762
763 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
764 }
765 qapi_free_MemoryDeviceInfoList(dimms);
766 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
767 if (ret < 0) {
768 goto out;
769 }
770
771 /* ibm,associativity-lookup-arrays */
772 cur_index = int_buf;
773 int_buf[0] = cpu_to_be32(nr_nodes);
774 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
775 cur_index += 2;
776 for (i = 0; i < nr_nodes; i++) {
777 uint32_t associativity[] = {
778 cpu_to_be32(0x0),
779 cpu_to_be32(0x0),
780 cpu_to_be32(0x0),
781 cpu_to_be32(i)
782 };
783 memcpy(cur_index, associativity, sizeof(associativity));
784 cur_index += 4;
785 }
786 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
787 (cur_index - int_buf) * sizeof(uint32_t));
788 out:
789 g_free(int_buf);
790 return ret;
791 }
792
793 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
794 sPAPROptionVector *ov5_updates)
795 {
796 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
797 int ret = 0, offset;
798
799 /* Generate ibm,dynamic-reconfiguration-memory node if required */
800 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
801 g_assert(smc->dr_lmb_enabled);
802 ret = spapr_populate_drconf_memory(spapr, fdt);
803 if (ret) {
804 goto out;
805 }
806 }
807
808 offset = fdt_path_offset(fdt, "/chosen");
809 if (offset < 0) {
810 offset = fdt_add_subnode(fdt, 0, "chosen");
811 if (offset < 0) {
812 return offset;
813 }
814 }
815 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
816 "ibm,architecture-vec-5");
817
818 out:
819 return ret;
820 }
821
822 static bool spapr_hotplugged_dev_before_cas(void)
823 {
824 Object *drc_container, *obj;
825 ObjectProperty *prop;
826 ObjectPropertyIterator iter;
827
828 drc_container = container_get(object_get_root(), "/dr-connector");
829 object_property_iter_init(&iter, drc_container);
830 while ((prop = object_property_iter_next(&iter))) {
831 if (!strstart(prop->type, "link<", NULL)) {
832 continue;
833 }
834 obj = object_property_get_link(drc_container, prop->name, NULL);
835 if (spapr_drc_needed(obj)) {
836 return true;
837 }
838 }
839 return false;
840 }
841
842 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
843 target_ulong addr, target_ulong size,
844 sPAPROptionVector *ov5_updates)
845 {
846 void *fdt, *fdt_skel;
847 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
848
849 if (spapr_hotplugged_dev_before_cas()) {
850 return 1;
851 }
852
853 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
854 error_report("SLOF provided an unexpected CAS buffer size "
855 TARGET_FMT_lu " (min: %zu, max: %u)",
856 size, sizeof(hdr), FW_MAX_SIZE);
857 exit(EXIT_FAILURE);
858 }
859
860 size -= sizeof(hdr);
861
862 /* Create skeleton */
863 fdt_skel = g_malloc0(size);
864 _FDT((fdt_create(fdt_skel, size)));
865 _FDT((fdt_begin_node(fdt_skel, "")));
866 _FDT((fdt_end_node(fdt_skel)));
867 _FDT((fdt_finish(fdt_skel)));
868 fdt = g_malloc0(size);
869 _FDT((fdt_open_into(fdt_skel, fdt, size)));
870 g_free(fdt_skel);
871
872 /* Fixup cpu nodes */
873 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
874
875 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
876 return -1;
877 }
878
879 /* Pack resulting tree */
880 _FDT((fdt_pack(fdt)));
881
882 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
883 trace_spapr_cas_failed(size);
884 return -1;
885 }
886
887 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
888 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
889 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
890 g_free(fdt);
891
892 return 0;
893 }
894
895 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
896 {
897 int rtas;
898 GString *hypertas = g_string_sized_new(256);
899 GString *qemu_hypertas = g_string_sized_new(256);
900 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
901 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
902 memory_region_size(&spapr->hotplug_memory.mr);
903 uint32_t lrdr_capacity[] = {
904 cpu_to_be32(max_hotplug_addr >> 32),
905 cpu_to_be32(max_hotplug_addr & 0xffffffff),
906 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
907 cpu_to_be32(max_cpus / smp_threads),
908 };
909
910 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
911
912 /* hypertas */
913 add_str(hypertas, "hcall-pft");
914 add_str(hypertas, "hcall-term");
915 add_str(hypertas, "hcall-dabr");
916 add_str(hypertas, "hcall-interrupt");
917 add_str(hypertas, "hcall-tce");
918 add_str(hypertas, "hcall-vio");
919 add_str(hypertas, "hcall-splpar");
920 add_str(hypertas, "hcall-bulk");
921 add_str(hypertas, "hcall-set-mode");
922 add_str(hypertas, "hcall-sprg0");
923 add_str(hypertas, "hcall-copy");
924 add_str(hypertas, "hcall-debug");
925 add_str(qemu_hypertas, "hcall-memop1");
926
927 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
928 add_str(hypertas, "hcall-multi-tce");
929 }
930
931 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
932 add_str(hypertas, "hcall-hpt-resize");
933 }
934
935 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
936 hypertas->str, hypertas->len));
937 g_string_free(hypertas, TRUE);
938 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
939 qemu_hypertas->str, qemu_hypertas->len));
940 g_string_free(qemu_hypertas, TRUE);
941
942 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
943 refpoints, sizeof(refpoints)));
944
945 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
946 RTAS_ERROR_LOG_MAX));
947 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
948 RTAS_EVENT_SCAN_RATE));
949
950 g_assert(msi_nonbroken);
951 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
952
953 /*
954 * According to PAPR, rtas ibm,os-term does not guarantee a return
955 * back to the guest cpu.
956 *
957 * While an additional ibm,extended-os-term property indicates
958 * that rtas call return will always occur. Set this property.
959 */
960 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
961
962 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
963 lrdr_capacity, sizeof(lrdr_capacity)));
964
965 spapr_dt_rtas_tokens(fdt, rtas);
966 }
967
968 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
969 * that the guest may request and thus the valid values for bytes 24..26 of
970 * option vector 5: */
971 static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
972 {
973 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
974
975 char val[2 * 4] = {
976 23, 0x00, /* Xive mode, filled in below. */
977 24, 0x00, /* Hash/Radix, filled in below. */
978 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
979 26, 0x40, /* Radix options: GTSE == yes. */
980 };
981
982 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
983 first_ppc_cpu->compat_pvr)) {
984 /* If we're in a pre POWER9 compat mode then the guest should do hash */
985 val[3] = 0x00; /* Hash */
986 } else if (kvm_enabled()) {
987 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
988 val[3] = 0x80; /* OV5_MMU_BOTH */
989 } else if (kvmppc_has_cap_mmu_radix()) {
990 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
991 } else {
992 val[3] = 0x00; /* Hash */
993 }
994 } else {
995 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
996 val[3] = 0xC0;
997 }
998 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
999 val, sizeof(val)));
1000 }
1001
1002 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
1003 {
1004 MachineState *machine = MACHINE(spapr);
1005 int chosen;
1006 const char *boot_device = machine->boot_order;
1007 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1008 size_t cb = 0;
1009 char *bootlist = get_boot_devices_list(&cb, true);
1010
1011 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1012
1013 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1014 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1015 spapr->initrd_base));
1016 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1017 spapr->initrd_base + spapr->initrd_size));
1018
1019 if (spapr->kernel_size) {
1020 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1021 cpu_to_be64(spapr->kernel_size) };
1022
1023 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1024 &kprop, sizeof(kprop)));
1025 if (spapr->kernel_le) {
1026 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1027 }
1028 }
1029 if (boot_menu) {
1030 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1031 }
1032 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1033 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1034 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1035
1036 if (cb && bootlist) {
1037 int i;
1038
1039 for (i = 0; i < cb; i++) {
1040 if (bootlist[i] == '\n') {
1041 bootlist[i] = ' ';
1042 }
1043 }
1044 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1045 }
1046
1047 if (boot_device && strlen(boot_device)) {
1048 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1049 }
1050
1051 if (!spapr->has_graphics && stdout_path) {
1052 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1053 }
1054
1055 spapr_dt_ov5_platform_support(fdt, chosen);
1056
1057 g_free(stdout_path);
1058 g_free(bootlist);
1059 }
1060
1061 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1062 {
1063 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1064 * KVM to work under pHyp with some guest co-operation */
1065 int hypervisor;
1066 uint8_t hypercall[16];
1067
1068 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1069 /* indicate KVM hypercall interface */
1070 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1071 if (kvmppc_has_cap_fixup_hcalls()) {
1072 /*
1073 * Older KVM versions with older guest kernels were broken
1074 * with the magic page, don't allow the guest to map it.
1075 */
1076 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1077 sizeof(hypercall))) {
1078 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1079 hypercall, sizeof(hypercall)));
1080 }
1081 }
1082 }
1083
1084 static void *spapr_build_fdt(sPAPRMachineState *spapr,
1085 hwaddr rtas_addr,
1086 hwaddr rtas_size)
1087 {
1088 MachineState *machine = MACHINE(spapr);
1089 MachineClass *mc = MACHINE_GET_CLASS(machine);
1090 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1091 int ret;
1092 void *fdt;
1093 sPAPRPHBState *phb;
1094 char *buf;
1095
1096 fdt = g_malloc0(FDT_MAX_SIZE);
1097 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1098
1099 /* Root node */
1100 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1101 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1102 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1103
1104 /*
1105 * Add info to guest to indentify which host is it being run on
1106 * and what is the uuid of the guest
1107 */
1108 if (kvmppc_get_host_model(&buf)) {
1109 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1110 g_free(buf);
1111 }
1112 if (kvmppc_get_host_serial(&buf)) {
1113 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1114 g_free(buf);
1115 }
1116
1117 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1118
1119 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1120 if (qemu_uuid_set) {
1121 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1122 }
1123 g_free(buf);
1124
1125 if (qemu_get_vm_name()) {
1126 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1127 qemu_get_vm_name()));
1128 }
1129
1130 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1131 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1132
1133 /* /interrupt controller */
1134 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);
1135
1136 ret = spapr_populate_memory(spapr, fdt);
1137 if (ret < 0) {
1138 error_report("couldn't setup memory nodes in fdt");
1139 exit(1);
1140 }
1141
1142 /* /vdevice */
1143 spapr_dt_vdevice(spapr->vio_bus, fdt);
1144
1145 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1146 ret = spapr_rng_populate_dt(fdt);
1147 if (ret < 0) {
1148 error_report("could not set up rng device in the fdt");
1149 exit(1);
1150 }
1151 }
1152
1153 QLIST_FOREACH(phb, &spapr->phbs, list) {
1154 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1155 if (ret < 0) {
1156 error_report("couldn't setup PCI devices in fdt");
1157 exit(1);
1158 }
1159 }
1160
1161 /* cpus */
1162 spapr_populate_cpus_dt_node(fdt, spapr);
1163
1164 if (smc->dr_lmb_enabled) {
1165 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1166 }
1167
1168 if (mc->has_hotpluggable_cpus) {
1169 int offset = fdt_path_offset(fdt, "/cpus");
1170 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1171 SPAPR_DR_CONNECTOR_TYPE_CPU);
1172 if (ret < 0) {
1173 error_report("Couldn't set up CPU DR device tree properties");
1174 exit(1);
1175 }
1176 }
1177
1178 /* /event-sources */
1179 spapr_dt_events(spapr, fdt);
1180
1181 /* /rtas */
1182 spapr_dt_rtas(spapr, fdt);
1183
1184 /* /chosen */
1185 spapr_dt_chosen(spapr, fdt);
1186
1187 /* /hypervisor */
1188 if (kvm_enabled()) {
1189 spapr_dt_hypervisor(spapr, fdt);
1190 }
1191
1192 /* Build memory reserve map */
1193 if (spapr->kernel_size) {
1194 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1195 }
1196 if (spapr->initrd_size) {
1197 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1198 }
1199
1200 /* ibm,client-architecture-support updates */
1201 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1202 if (ret < 0) {
1203 error_report("couldn't setup CAS properties fdt");
1204 exit(1);
1205 }
1206
1207 return fdt;
1208 }
1209
1210 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1211 {
1212 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1213 }
1214
1215 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1216 PowerPCCPU *cpu)
1217 {
1218 CPUPPCState *env = &cpu->env;
1219
1220 /* The TCG path should also be holding the BQL at this point */
1221 g_assert(qemu_mutex_iothread_locked());
1222
1223 if (msr_pr) {
1224 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1225 env->gpr[3] = H_PRIVILEGE;
1226 } else {
1227 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1228 }
1229 }
1230
1231 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1232 {
1233 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1234
1235 return spapr->patb_entry;
1236 }
1237
1238 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1239 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1240 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1241 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1242 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1243
1244 /*
1245 * Get the fd to access the kernel htab, re-opening it if necessary
1246 */
1247 static int get_htab_fd(sPAPRMachineState *spapr)
1248 {
1249 Error *local_err = NULL;
1250
1251 if (spapr->htab_fd >= 0) {
1252 return spapr->htab_fd;
1253 }
1254
1255 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1256 if (spapr->htab_fd < 0) {
1257 error_report_err(local_err);
1258 }
1259
1260 return spapr->htab_fd;
1261 }
1262
1263 void close_htab_fd(sPAPRMachineState *spapr)
1264 {
1265 if (spapr->htab_fd >= 0) {
1266 close(spapr->htab_fd);
1267 }
1268 spapr->htab_fd = -1;
1269 }
1270
1271 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1272 {
1273 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1274
1275 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1276 }
1277
1278 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1279 {
1280 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1281
1282 assert(kvm_enabled());
1283
1284 if (!spapr->htab) {
1285 return 0;
1286 }
1287
1288 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1289 }
1290
1291 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1292 hwaddr ptex, int n)
1293 {
1294 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1295 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1296
1297 if (!spapr->htab) {
1298 /*
1299 * HTAB is controlled by KVM. Fetch into temporary buffer
1300 */
1301 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1302 kvmppc_read_hptes(hptes, ptex, n);
1303 return hptes;
1304 }
1305
1306 /*
1307 * HTAB is controlled by QEMU. Just point to the internally
1308 * accessible PTEG.
1309 */
1310 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1311 }
1312
1313 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1314 const ppc_hash_pte64_t *hptes,
1315 hwaddr ptex, int n)
1316 {
1317 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1318
1319 if (!spapr->htab) {
1320 g_free((void *)hptes);
1321 }
1322
1323 /* Nothing to do for qemu managed HPT */
1324 }
1325
1326 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1327 uint64_t pte0, uint64_t pte1)
1328 {
1329 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1330 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1331
1332 if (!spapr->htab) {
1333 kvmppc_write_hpte(ptex, pte0, pte1);
1334 } else {
1335 stq_p(spapr->htab + offset, pte0);
1336 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1337 }
1338 }
1339
1340 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1341 {
1342 int shift;
1343
1344 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1345 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1346 * that's much more than is needed for Linux guests */
1347 shift = ctz64(pow2ceil(ramsize)) - 7;
1348 shift = MAX(shift, 18); /* Minimum architected size */
1349 shift = MIN(shift, 46); /* Maximum architected size */
1350 return shift;
1351 }
1352
1353 void spapr_free_hpt(sPAPRMachineState *spapr)
1354 {
1355 g_free(spapr->htab);
1356 spapr->htab = NULL;
1357 spapr->htab_shift = 0;
1358 close_htab_fd(spapr);
1359 }
1360
1361 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1362 Error **errp)
1363 {
1364 long rc;
1365
1366 /* Clean up any HPT info from a previous boot */
1367 spapr_free_hpt(spapr);
1368
1369 rc = kvmppc_reset_htab(shift);
1370 if (rc < 0) {
1371 /* kernel-side HPT needed, but couldn't allocate one */
1372 error_setg_errno(errp, errno,
1373 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1374 shift);
1375 /* This is almost certainly fatal, but if the caller really
1376 * wants to carry on with shift == 0, it's welcome to try */
1377 } else if (rc > 0) {
1378 /* kernel-side HPT allocated */
1379 if (rc != shift) {
1380 error_setg(errp,
1381 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1382 shift, rc);
1383 }
1384
1385 spapr->htab_shift = shift;
1386 spapr->htab = NULL;
1387 } else {
1388 /* kernel-side HPT not needed, allocate in userspace instead */
1389 size_t size = 1ULL << shift;
1390 int i;
1391
1392 spapr->htab = qemu_memalign(size, size);
1393 if (!spapr->htab) {
1394 error_setg_errno(errp, errno,
1395 "Could not allocate HPT of order %d", shift);
1396 return;
1397 }
1398
1399 memset(spapr->htab, 0, size);
1400 spapr->htab_shift = shift;
1401
1402 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1403 DIRTY_HPTE(HPTE(spapr->htab, i));
1404 }
1405 }
1406 /* We're setting up a hash table, so that means we're not radix */
1407 spapr->patb_entry = 0;
1408 }
1409
1410 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1411 {
1412 int hpt_shift;
1413
1414 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1415 || (spapr->cas_reboot
1416 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1417 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1418 } else {
1419 uint64_t current_ram_size;
1420
1421 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1422 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1423 }
1424 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1425
1426 if (spapr->vrma_adjust) {
1427 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1428 spapr->htab_shift);
1429 }
1430 }
1431
1432 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1433 {
1434 bool matched = false;
1435
1436 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1437 matched = true;
1438 }
1439
1440 if (!matched) {
1441 error_report("Device %s is not supported by this machine yet.",
1442 qdev_fw_name(DEVICE(sbdev)));
1443 exit(1);
1444 }
1445 }
1446
1447 static int spapr_reset_drcs(Object *child, void *opaque)
1448 {
1449 sPAPRDRConnector *drc =
1450 (sPAPRDRConnector *) object_dynamic_cast(child,
1451 TYPE_SPAPR_DR_CONNECTOR);
1452
1453 if (drc) {
1454 spapr_drc_reset(drc);
1455 }
1456
1457 return 0;
1458 }
1459
1460 static void spapr_machine_reset(void)
1461 {
1462 MachineState *machine = MACHINE(qdev_get_machine());
1463 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1464 PowerPCCPU *first_ppc_cpu;
1465 uint32_t rtas_limit;
1466 hwaddr rtas_addr, fdt_addr;
1467 void *fdt;
1468 int rc;
1469
1470 /* Check for unknown sysbus devices */
1471 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1472
1473 spapr_caps_reset(spapr);
1474
1475 first_ppc_cpu = POWERPC_CPU(first_cpu);
1476 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1477 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1478 spapr->max_compat_pvr)) {
1479 /* If using KVM with radix mode available, VCPUs can be started
1480 * without a HPT because KVM will start them in radix mode.
1481 * Set the GR bit in PATB so that we know there is no HPT. */
1482 spapr->patb_entry = PATBE1_GR;
1483 } else {
1484 spapr_setup_hpt_and_vrma(spapr);
1485 }
1486
1487 qemu_devices_reset();
1488
1489 /* DRC reset may cause a device to be unplugged. This will cause troubles
1490 * if this device is used by another device (eg, a running vhost backend
1491 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1492 * situations, we reset DRCs after all devices have been reset.
1493 */
1494 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1495
1496 spapr_clear_pending_events(spapr);
1497
1498 /*
1499 * We place the device tree and RTAS just below either the top of the RMA,
1500 * or just below 2GB, whichever is lowere, so that it can be
1501 * processed with 32-bit real mode code if necessary
1502 */
1503 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1504 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1505 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1506
1507 /* if this reset wasn't generated by CAS, we should reset our
1508 * negotiated options and start from scratch */
1509 if (!spapr->cas_reboot) {
1510 spapr_ovec_cleanup(spapr->ov5_cas);
1511 spapr->ov5_cas = spapr_ovec_new();
1512
1513 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1514 }
1515
1516 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1517
1518 spapr_load_rtas(spapr, fdt, rtas_addr);
1519
1520 rc = fdt_pack(fdt);
1521
1522 /* Should only fail if we've built a corrupted tree */
1523 assert(rc == 0);
1524
1525 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1526 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1527 fdt_totalsize(fdt), FDT_MAX_SIZE);
1528 exit(1);
1529 }
1530
1531 /* Load the fdt */
1532 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1533 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1534 g_free(fdt);
1535
1536 /* Set up the entry state */
1537 first_ppc_cpu->env.gpr[3] = fdt_addr;
1538 first_ppc_cpu->env.gpr[5] = 0;
1539 first_cpu->halted = 0;
1540 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1541
1542 spapr->cas_reboot = false;
1543 }
1544
1545 static void spapr_create_nvram(sPAPRMachineState *spapr)
1546 {
1547 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1548 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1549
1550 if (dinfo) {
1551 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1552 &error_fatal);
1553 }
1554
1555 qdev_init_nofail(dev);
1556
1557 spapr->nvram = (struct sPAPRNVRAM *)dev;
1558 }
1559
1560 static void spapr_rtc_create(sPAPRMachineState *spapr)
1561 {
1562 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1563 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1564 &error_fatal);
1565 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1566 &error_fatal);
1567 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1568 "date", &error_fatal);
1569 }
1570
1571 /* Returns whether we want to use VGA or not */
1572 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1573 {
1574 switch (vga_interface_type) {
1575 case VGA_NONE:
1576 return false;
1577 case VGA_DEVICE:
1578 return true;
1579 case VGA_STD:
1580 case VGA_VIRTIO:
1581 return pci_vga_init(pci_bus) != NULL;
1582 default:
1583 error_setg(errp,
1584 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1585 return false;
1586 }
1587 }
1588
1589 static int spapr_pre_load(void *opaque)
1590 {
1591 int rc;
1592
1593 rc = spapr_caps_pre_load(opaque);
1594 if (rc) {
1595 return rc;
1596 }
1597
1598 return 0;
1599 }
1600
1601 static int spapr_post_load(void *opaque, int version_id)
1602 {
1603 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1604 int err = 0;
1605
1606 err = spapr_caps_post_migration(spapr);
1607 if (err) {
1608 return err;
1609 }
1610
1611 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1612 CPUState *cs;
1613 CPU_FOREACH(cs) {
1614 PowerPCCPU *cpu = POWERPC_CPU(cs);
1615 icp_resend(ICP(cpu->intc));
1616 }
1617 }
1618
1619 /* In earlier versions, there was no separate qdev for the PAPR
1620 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1621 * So when migrating from those versions, poke the incoming offset
1622 * value into the RTC device */
1623 if (version_id < 3) {
1624 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1625 }
1626
1627 if (kvm_enabled() && spapr->patb_entry) {
1628 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1629 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1630 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1631
1632 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1633 if (err) {
1634 error_report("Process table config unsupported by the host");
1635 return -EINVAL;
1636 }
1637 }
1638
1639 return err;
1640 }
1641
1642 static int spapr_pre_save(void *opaque)
1643 {
1644 int rc;
1645
1646 rc = spapr_caps_pre_save(opaque);
1647 if (rc) {
1648 return rc;
1649 }
1650
1651 return 0;
1652 }
1653
1654 static bool version_before_3(void *opaque, int version_id)
1655 {
1656 return version_id < 3;
1657 }
1658
1659 static bool spapr_pending_events_needed(void *opaque)
1660 {
1661 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1662 return !QTAILQ_EMPTY(&spapr->pending_events);
1663 }
1664
1665 static const VMStateDescription vmstate_spapr_event_entry = {
1666 .name = "spapr_event_log_entry",
1667 .version_id = 1,
1668 .minimum_version_id = 1,
1669 .fields = (VMStateField[]) {
1670 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1671 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1672 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1673 NULL, extended_length),
1674 VMSTATE_END_OF_LIST()
1675 },
1676 };
1677
1678 static const VMStateDescription vmstate_spapr_pending_events = {
1679 .name = "spapr_pending_events",
1680 .version_id = 1,
1681 .minimum_version_id = 1,
1682 .needed = spapr_pending_events_needed,
1683 .fields = (VMStateField[]) {
1684 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1685 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1686 VMSTATE_END_OF_LIST()
1687 },
1688 };
1689
1690 static bool spapr_ov5_cas_needed(void *opaque)
1691 {
1692 sPAPRMachineState *spapr = opaque;
1693 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1694 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1695 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1696 bool cas_needed;
1697
1698 /* Prior to the introduction of sPAPROptionVector, we had two option
1699 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1700 * Both of these options encode machine topology into the device-tree
1701 * in such a way that the now-booted OS should still be able to interact
1702 * appropriately with QEMU regardless of what options were actually
1703 * negotiatied on the source side.
1704 *
1705 * As such, we can avoid migrating the CAS-negotiated options if these
1706 * are the only options available on the current machine/platform.
1707 * Since these are the only options available for pseries-2.7 and
1708 * earlier, this allows us to maintain old->new/new->old migration
1709 * compatibility.
1710 *
1711 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1712 * via default pseries-2.8 machines and explicit command-line parameters.
1713 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1714 * of the actual CAS-negotiated values to continue working properly. For
1715 * example, availability of memory unplug depends on knowing whether
1716 * OV5_HP_EVT was negotiated via CAS.
1717 *
1718 * Thus, for any cases where the set of available CAS-negotiatable
1719 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1720 * include the CAS-negotiated options in the migration stream.
1721 */
1722 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1723 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1724
1725 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1726 * the mask itself since in the future it's possible "legacy" bits may be
1727 * removed via machine options, which could generate a false positive
1728 * that breaks migration.
1729 */
1730 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1731 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1732
1733 spapr_ovec_cleanup(ov5_mask);
1734 spapr_ovec_cleanup(ov5_legacy);
1735 spapr_ovec_cleanup(ov5_removed);
1736
1737 return cas_needed;
1738 }
1739
1740 static const VMStateDescription vmstate_spapr_ov5_cas = {
1741 .name = "spapr_option_vector_ov5_cas",
1742 .version_id = 1,
1743 .minimum_version_id = 1,
1744 .needed = spapr_ov5_cas_needed,
1745 .fields = (VMStateField[]) {
1746 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1747 vmstate_spapr_ovec, sPAPROptionVector),
1748 VMSTATE_END_OF_LIST()
1749 },
1750 };
1751
1752 static bool spapr_patb_entry_needed(void *opaque)
1753 {
1754 sPAPRMachineState *spapr = opaque;
1755
1756 return !!spapr->patb_entry;
1757 }
1758
1759 static const VMStateDescription vmstate_spapr_patb_entry = {
1760 .name = "spapr_patb_entry",
1761 .version_id = 1,
1762 .minimum_version_id = 1,
1763 .needed = spapr_patb_entry_needed,
1764 .fields = (VMStateField[]) {
1765 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1766 VMSTATE_END_OF_LIST()
1767 },
1768 };
1769
1770 static const VMStateDescription vmstate_spapr = {
1771 .name = "spapr",
1772 .version_id = 3,
1773 .minimum_version_id = 1,
1774 .pre_load = spapr_pre_load,
1775 .post_load = spapr_post_load,
1776 .pre_save = spapr_pre_save,
1777 .fields = (VMStateField[]) {
1778 /* used to be @next_irq */
1779 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1780
1781 /* RTC offset */
1782 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1783
1784 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1785 VMSTATE_END_OF_LIST()
1786 },
1787 .subsections = (const VMStateDescription*[]) {
1788 &vmstate_spapr_ov5_cas,
1789 &vmstate_spapr_patb_entry,
1790 &vmstate_spapr_pending_events,
1791 &vmstate_spapr_cap_htm,
1792 &vmstate_spapr_cap_vsx,
1793 &vmstate_spapr_cap_dfp,
1794 NULL
1795 }
1796 };
1797
1798 static int htab_save_setup(QEMUFile *f, void *opaque)
1799 {
1800 sPAPRMachineState *spapr = opaque;
1801
1802 /* "Iteration" header */
1803 if (!spapr->htab_shift) {
1804 qemu_put_be32(f, -1);
1805 } else {
1806 qemu_put_be32(f, spapr->htab_shift);
1807 }
1808
1809 if (spapr->htab) {
1810 spapr->htab_save_index = 0;
1811 spapr->htab_first_pass = true;
1812 } else {
1813 if (spapr->htab_shift) {
1814 assert(kvm_enabled());
1815 }
1816 }
1817
1818
1819 return 0;
1820 }
1821
1822 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1823 int chunkstart, int n_valid, int n_invalid)
1824 {
1825 qemu_put_be32(f, chunkstart);
1826 qemu_put_be16(f, n_valid);
1827 qemu_put_be16(f, n_invalid);
1828 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1829 HASH_PTE_SIZE_64 * n_valid);
1830 }
1831
1832 static void htab_save_end_marker(QEMUFile *f)
1833 {
1834 qemu_put_be32(f, 0);
1835 qemu_put_be16(f, 0);
1836 qemu_put_be16(f, 0);
1837 }
1838
1839 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1840 int64_t max_ns)
1841 {
1842 bool has_timeout = max_ns != -1;
1843 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1844 int index = spapr->htab_save_index;
1845 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1846
1847 assert(spapr->htab_first_pass);
1848
1849 do {
1850 int chunkstart;
1851
1852 /* Consume invalid HPTEs */
1853 while ((index < htabslots)
1854 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1855 CLEAN_HPTE(HPTE(spapr->htab, index));
1856 index++;
1857 }
1858
1859 /* Consume valid HPTEs */
1860 chunkstart = index;
1861 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1862 && HPTE_VALID(HPTE(spapr->htab, index))) {
1863 CLEAN_HPTE(HPTE(spapr->htab, index));
1864 index++;
1865 }
1866
1867 if (index > chunkstart) {
1868 int n_valid = index - chunkstart;
1869
1870 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
1871
1872 if (has_timeout &&
1873 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1874 break;
1875 }
1876 }
1877 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1878
1879 if (index >= htabslots) {
1880 assert(index == htabslots);
1881 index = 0;
1882 spapr->htab_first_pass = false;
1883 }
1884 spapr->htab_save_index = index;
1885 }
1886
1887 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1888 int64_t max_ns)
1889 {
1890 bool final = max_ns < 0;
1891 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1892 int examined = 0, sent = 0;
1893 int index = spapr->htab_save_index;
1894 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1895
1896 assert(!spapr->htab_first_pass);
1897
1898 do {
1899 int chunkstart, invalidstart;
1900
1901 /* Consume non-dirty HPTEs */
1902 while ((index < htabslots)
1903 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1904 index++;
1905 examined++;
1906 }
1907
1908 chunkstart = index;
1909 /* Consume valid dirty HPTEs */
1910 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1911 && HPTE_DIRTY(HPTE(spapr->htab, index))
1912 && HPTE_VALID(HPTE(spapr->htab, index))) {
1913 CLEAN_HPTE(HPTE(spapr->htab, index));
1914 index++;
1915 examined++;
1916 }
1917
1918 invalidstart = index;
1919 /* Consume invalid dirty HPTEs */
1920 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1921 && HPTE_DIRTY(HPTE(spapr->htab, index))
1922 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1923 CLEAN_HPTE(HPTE(spapr->htab, index));
1924 index++;
1925 examined++;
1926 }
1927
1928 if (index > chunkstart) {
1929 int n_valid = invalidstart - chunkstart;
1930 int n_invalid = index - invalidstart;
1931
1932 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
1933 sent += index - chunkstart;
1934
1935 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1936 break;
1937 }
1938 }
1939
1940 if (examined >= htabslots) {
1941 break;
1942 }
1943
1944 if (index >= htabslots) {
1945 assert(index == htabslots);
1946 index = 0;
1947 }
1948 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1949
1950 if (index >= htabslots) {
1951 assert(index == htabslots);
1952 index = 0;
1953 }
1954
1955 spapr->htab_save_index = index;
1956
1957 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1958 }
1959
1960 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1961 #define MAX_KVM_BUF_SIZE 2048
1962
1963 static int htab_save_iterate(QEMUFile *f, void *opaque)
1964 {
1965 sPAPRMachineState *spapr = opaque;
1966 int fd;
1967 int rc = 0;
1968
1969 /* Iteration header */
1970 if (!spapr->htab_shift) {
1971 qemu_put_be32(f, -1);
1972 return 1;
1973 } else {
1974 qemu_put_be32(f, 0);
1975 }
1976
1977 if (!spapr->htab) {
1978 assert(kvm_enabled());
1979
1980 fd = get_htab_fd(spapr);
1981 if (fd < 0) {
1982 return fd;
1983 }
1984
1985 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1986 if (rc < 0) {
1987 return rc;
1988 }
1989 } else if (spapr->htab_first_pass) {
1990 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1991 } else {
1992 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1993 }
1994
1995 htab_save_end_marker(f);
1996
1997 return rc;
1998 }
1999
2000 static int htab_save_complete(QEMUFile *f, void *opaque)
2001 {
2002 sPAPRMachineState *spapr = opaque;
2003 int fd;
2004
2005 /* Iteration header */
2006 if (!spapr->htab_shift) {
2007 qemu_put_be32(f, -1);
2008 return 0;
2009 } else {
2010 qemu_put_be32(f, 0);
2011 }
2012
2013 if (!spapr->htab) {
2014 int rc;
2015
2016 assert(kvm_enabled());
2017
2018 fd = get_htab_fd(spapr);
2019 if (fd < 0) {
2020 return fd;
2021 }
2022
2023 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2024 if (rc < 0) {
2025 return rc;
2026 }
2027 } else {
2028 if (spapr->htab_first_pass) {
2029 htab_save_first_pass(f, spapr, -1);
2030 }
2031 htab_save_later_pass(f, spapr, -1);
2032 }
2033
2034 /* End marker */
2035 htab_save_end_marker(f);
2036
2037 return 0;
2038 }
2039
2040 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2041 {
2042 sPAPRMachineState *spapr = opaque;
2043 uint32_t section_hdr;
2044 int fd = -1;
2045 Error *local_err = NULL;
2046
2047 if (version_id < 1 || version_id > 1) {
2048 error_report("htab_load() bad version");
2049 return -EINVAL;
2050 }
2051
2052 section_hdr = qemu_get_be32(f);
2053
2054 if (section_hdr == -1) {
2055 spapr_free_hpt(spapr);
2056 return 0;
2057 }
2058
2059 if (section_hdr) {
2060 /* First section gives the htab size */
2061 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2062 if (local_err) {
2063 error_report_err(local_err);
2064 return -EINVAL;
2065 }
2066 return 0;
2067 }
2068
2069 if (!spapr->htab) {
2070 assert(kvm_enabled());
2071
2072 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2073 if (fd < 0) {
2074 error_report_err(local_err);
2075 return fd;
2076 }
2077 }
2078
2079 while (true) {
2080 uint32_t index;
2081 uint16_t n_valid, n_invalid;
2082
2083 index = qemu_get_be32(f);
2084 n_valid = qemu_get_be16(f);
2085 n_invalid = qemu_get_be16(f);
2086
2087 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2088 /* End of Stream */
2089 break;
2090 }
2091
2092 if ((index + n_valid + n_invalid) >
2093 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2094 /* Bad index in stream */
2095 error_report(
2096 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2097 index, n_valid, n_invalid, spapr->htab_shift);
2098 return -EINVAL;
2099 }
2100
2101 if (spapr->htab) {
2102 if (n_valid) {
2103 qemu_get_buffer(f, HPTE(spapr->htab, index),
2104 HASH_PTE_SIZE_64 * n_valid);
2105 }
2106 if (n_invalid) {
2107 memset(HPTE(spapr->htab, index + n_valid), 0,
2108 HASH_PTE_SIZE_64 * n_invalid);
2109 }
2110 } else {
2111 int rc;
2112
2113 assert(fd >= 0);
2114
2115 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2116 if (rc < 0) {
2117 return rc;
2118 }
2119 }
2120 }
2121
2122 if (!spapr->htab) {
2123 assert(fd >= 0);
2124 close(fd);
2125 }
2126
2127 return 0;
2128 }
2129
2130 static void htab_save_cleanup(void *opaque)
2131 {
2132 sPAPRMachineState *spapr = opaque;
2133
2134 close_htab_fd(spapr);
2135 }
2136
2137 static SaveVMHandlers savevm_htab_handlers = {
2138 .save_setup = htab_save_setup,
2139 .save_live_iterate = htab_save_iterate,
2140 .save_live_complete_precopy = htab_save_complete,
2141 .save_cleanup = htab_save_cleanup,
2142 .load_state = htab_load,
2143 };
2144
2145 static void spapr_boot_set(void *opaque, const char *boot_device,
2146 Error **errp)
2147 {
2148 MachineState *machine = MACHINE(opaque);
2149 machine->boot_order = g_strdup(boot_device);
2150 }
2151
2152 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2153 {
2154 MachineState *machine = MACHINE(spapr);
2155 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2156 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2157 int i;
2158
2159 for (i = 0; i < nr_lmbs; i++) {
2160 uint64_t addr;
2161
2162 addr = i * lmb_size + spapr->hotplug_memory.base;
2163 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2164 addr / lmb_size);
2165 }
2166 }
2167
2168 /*
2169 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2170 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2171 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2172 */
2173 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2174 {
2175 int i;
2176
2177 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2178 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2179 " is not aligned to %llu MiB",
2180 machine->ram_size,
2181 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2182 return;
2183 }
2184
2185 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2186 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2187 " is not aligned to %llu MiB",
2188 machine->ram_size,
2189 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2190 return;
2191 }
2192
2193 for (i = 0; i < nb_numa_nodes; i++) {
2194 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2195 error_setg(errp,
2196 "Node %d memory size 0x%" PRIx64
2197 " is not aligned to %llu MiB",
2198 i, numa_info[i].node_mem,
2199 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2200 return;
2201 }
2202 }
2203 }
2204
2205 /* find cpu slot in machine->possible_cpus by core_id */
2206 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2207 {
2208 int index = id / smp_threads;
2209
2210 if (index >= ms->possible_cpus->len) {
2211 return NULL;
2212 }
2213 if (idx) {
2214 *idx = index;
2215 }
2216 return &ms->possible_cpus->cpus[index];
2217 }
2218
2219 static void spapr_init_cpus(sPAPRMachineState *spapr)
2220 {
2221 MachineState *machine = MACHINE(spapr);
2222 MachineClass *mc = MACHINE_GET_CLASS(machine);
2223 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2224 int smt = kvmppc_smt_threads();
2225 const CPUArchIdList *possible_cpus;
2226 int boot_cores_nr = smp_cpus / smp_threads;
2227 int i;
2228
2229 if (!type) {
2230 error_report("Unable to find sPAPR CPU Core definition");
2231 exit(1);
2232 }
2233
2234 possible_cpus = mc->possible_cpu_arch_ids(machine);
2235 if (mc->has_hotpluggable_cpus) {
2236 if (smp_cpus % smp_threads) {
2237 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2238 smp_cpus, smp_threads);
2239 exit(1);
2240 }
2241 if (max_cpus % smp_threads) {
2242 error_report("max_cpus (%u) must be multiple of threads (%u)",
2243 max_cpus, smp_threads);
2244 exit(1);
2245 }
2246 } else {
2247 if (max_cpus != smp_cpus) {
2248 error_report("This machine version does not support CPU hotplug");
2249 exit(1);
2250 }
2251 boot_cores_nr = possible_cpus->len;
2252 }
2253
2254 for (i = 0; i < possible_cpus->len; i++) {
2255 int core_id = i * smp_threads;
2256
2257 if (mc->has_hotpluggable_cpus) {
2258 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2259 (core_id / smp_threads) * smt);
2260 }
2261
2262 if (i < boot_cores_nr) {
2263 Object *core = object_new(type);
2264 int nr_threads = smp_threads;
2265
2266 /* Handle the partially filled core for older machine types */
2267 if ((i + 1) * smp_threads >= smp_cpus) {
2268 nr_threads = smp_cpus - i * smp_threads;
2269 }
2270
2271 object_property_set_int(core, nr_threads, "nr-threads",
2272 &error_fatal);
2273 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2274 &error_fatal);
2275 object_property_set_bool(core, true, "realized", &error_fatal);
2276 }
2277 }
2278 }
2279
2280 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2281 {
2282 Error *local_err = NULL;
2283 bool vsmt_user = !!spapr->vsmt;
2284 int kvm_smt = kvmppc_smt_threads();
2285 int ret;
2286
2287 if (!kvm_enabled() && (smp_threads > 1)) {
2288 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2289 "on a pseries machine");
2290 goto out;
2291 }
2292 if (!is_power_of_2(smp_threads)) {
2293 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2294 "machine because it must be a power of 2", smp_threads);
2295 goto out;
2296 }
2297
2298 /* Detemine the VSMT mode to use: */
2299 if (vsmt_user) {
2300 if (spapr->vsmt < smp_threads) {
2301 error_setg(&local_err, "Cannot support VSMT mode %d"
2302 " because it must be >= threads/core (%d)",
2303 spapr->vsmt, smp_threads);
2304 goto out;
2305 }
2306 /* In this case, spapr->vsmt has been set by the command line */
2307 } else {
2308 /*
2309 * Default VSMT value is tricky, because we need it to be as
2310 * consistent as possible (for migration), but this requires
2311 * changing it for at least some existing cases. We pick 8 as
2312 * the value that we'd get with KVM on POWER8, the
2313 * overwhelmingly common case in production systems.
2314 */
2315 spapr->vsmt = 8;
2316 }
2317
2318 /* KVM: If necessary, set the SMT mode: */
2319 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2320 ret = kvmppc_set_smt_threads(spapr->vsmt);
2321 if (ret) {
2322 /* Looks like KVM isn't able to change VSMT mode */
2323 error_setg(&local_err,
2324 "Failed to set KVM's VSMT mode to %d (errno %d)",
2325 spapr->vsmt, ret);
2326 /* We can live with that if the default one is big enough
2327 * for the number of threads, and a submultiple of the one
2328 * we want. In this case we'll waste some vcpu ids, but
2329 * behaviour will be correct */
2330 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2331 warn_report_err(local_err);
2332 local_err = NULL;
2333 goto out;
2334 } else {
2335 if (!vsmt_user) {
2336 error_append_hint(&local_err,
2337 "On PPC, a VM with %d threads/core"
2338 " on a host with %d threads/core"
2339 " requires the use of VSMT mode %d.\n",
2340 smp_threads, kvm_smt, spapr->vsmt);
2341 }
2342 kvmppc_hint_smt_possible(&local_err);
2343 goto out;
2344 }
2345 }
2346 }
2347 /* else TCG: nothing to do currently */
2348 out:
2349 error_propagate(errp, local_err);
2350 }
2351
2352 /* pSeries LPAR / sPAPR hardware init */
2353 static void spapr_machine_init(MachineState *machine)
2354 {
2355 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2356 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2357 const char *kernel_filename = machine->kernel_filename;
2358 const char *initrd_filename = machine->initrd_filename;
2359 PCIHostState *phb;
2360 int i;
2361 MemoryRegion *sysmem = get_system_memory();
2362 MemoryRegion *ram = g_new(MemoryRegion, 1);
2363 MemoryRegion *rma_region;
2364 void *rma = NULL;
2365 hwaddr rma_alloc_size;
2366 hwaddr node0_size = spapr_node0_size(machine);
2367 long load_limit, fw_size;
2368 char *filename;
2369 Error *resize_hpt_err = NULL;
2370
2371 msi_nonbroken = true;
2372
2373 QLIST_INIT(&spapr->phbs);
2374 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2375
2376 /* Check HPT resizing availability */
2377 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2378 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2379 /*
2380 * If the user explicitly requested a mode we should either
2381 * supply it, or fail completely (which we do below). But if
2382 * it's not set explicitly, we reset our mode to something
2383 * that works
2384 */
2385 if (resize_hpt_err) {
2386 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2387 error_free(resize_hpt_err);
2388 resize_hpt_err = NULL;
2389 } else {
2390 spapr->resize_hpt = smc->resize_hpt_default;
2391 }
2392 }
2393
2394 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2395
2396 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2397 /*
2398 * User requested HPT resize, but this host can't supply it. Bail out
2399 */
2400 error_report_err(resize_hpt_err);
2401 exit(1);
2402 }
2403
2404 /* Allocate RMA if necessary */
2405 rma_alloc_size = kvmppc_alloc_rma(&rma);
2406
2407 if (rma_alloc_size == -1) {
2408 error_report("Unable to create RMA");
2409 exit(1);
2410 }
2411
2412 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2413 spapr->rma_size = rma_alloc_size;
2414 } else {
2415 spapr->rma_size = node0_size;
2416
2417 /* With KVM, we don't actually know whether KVM supports an
2418 * unbounded RMA (PR KVM) or is limited by the hash table size
2419 * (HV KVM using VRMA), so we always assume the latter
2420 *
2421 * In that case, we also limit the initial allocations for RTAS
2422 * etc... to 256M since we have no way to know what the VRMA size
2423 * is going to be as it depends on the size of the hash table
2424 * isn't determined yet.
2425 */
2426 if (kvm_enabled()) {
2427 spapr->vrma_adjust = 1;
2428 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2429 }
2430
2431 /* Actually we don't support unbounded RMA anymore since we
2432 * added proper emulation of HV mode. The max we can get is
2433 * 16G which also happens to be what we configure for PAPR
2434 * mode so make sure we don't do anything bigger than that
2435 */
2436 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2437 }
2438
2439 if (spapr->rma_size > node0_size) {
2440 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2441 spapr->rma_size);
2442 exit(1);
2443 }
2444
2445 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2446 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2447
2448 /* Set up Interrupt Controller before we create the VCPUs */
2449 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2450
2451 /* Set up containers for ibm,client-architecture-support negotiated options
2452 */
2453 spapr->ov5 = spapr_ovec_new();
2454 spapr->ov5_cas = spapr_ovec_new();
2455
2456 if (smc->dr_lmb_enabled) {
2457 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2458 spapr_validate_node_memory(machine, &error_fatal);
2459 }
2460
2461 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2462 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2463 /* KVM and TCG always allow GTSE with radix... */
2464 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2465 }
2466 /* ... but not with hash (currently). */
2467
2468 /* advertise support for dedicated HP event source to guests */
2469 if (spapr->use_hotplug_event_source) {
2470 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2471 }
2472
2473 /* advertise support for HPT resizing */
2474 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2475 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2476 }
2477
2478 /* init CPUs */
2479 spapr_set_vsmt_mode(spapr, &error_fatal);
2480
2481 spapr_init_cpus(spapr);
2482
2483 if (kvm_enabled()) {
2484 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2485 kvmppc_enable_logical_ci_hcalls();
2486 kvmppc_enable_set_mode_hcall();
2487
2488 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2489 kvmppc_enable_clear_ref_mod_hcalls();
2490 }
2491
2492 /* allocate RAM */
2493 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2494 machine->ram_size);
2495 memory_region_add_subregion(sysmem, 0, ram);
2496
2497 if (rma_alloc_size && rma) {
2498 rma_region = g_new(MemoryRegion, 1);
2499 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2500 rma_alloc_size, rma);
2501 vmstate_register_ram_global(rma_region);
2502 memory_region_add_subregion(sysmem, 0, rma_region);
2503 }
2504
2505 /* initialize hotplug memory address space */
2506 if (machine->ram_size < machine->maxram_size) {
2507 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2508 /*
2509 * Limit the number of hotpluggable memory slots to half the number
2510 * slots that KVM supports, leaving the other half for PCI and other
2511 * devices. However ensure that number of slots doesn't drop below 32.
2512 */
2513 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2514 SPAPR_MAX_RAM_SLOTS;
2515
2516 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2517 max_memslots = SPAPR_MAX_RAM_SLOTS;
2518 }
2519 if (machine->ram_slots > max_memslots) {
2520 error_report("Specified number of memory slots %"
2521 PRIu64" exceeds max supported %d",
2522 machine->ram_slots, max_memslots);
2523 exit(1);
2524 }
2525
2526 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2527 SPAPR_HOTPLUG_MEM_ALIGN);
2528 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2529 "hotplug-memory", hotplug_mem_size);
2530 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2531 &spapr->hotplug_memory.mr);
2532 }
2533
2534 if (smc->dr_lmb_enabled) {
2535 spapr_create_lmb_dr_connectors(spapr);
2536 }
2537
2538 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2539 if (!filename) {
2540 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2541 exit(1);
2542 }
2543 spapr->rtas_size = get_image_size(filename);
2544 if (spapr->rtas_size < 0) {
2545 error_report("Could not get size of LPAR rtas '%s'", filename);
2546 exit(1);
2547 }
2548 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2549 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2550 error_report("Could not load LPAR rtas '%s'", filename);
2551 exit(1);
2552 }
2553 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2554 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2555 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2556 exit(1);
2557 }
2558 g_free(filename);
2559
2560 /* Set up RTAS event infrastructure */
2561 spapr_events_init(spapr);
2562
2563 /* Set up the RTC RTAS interfaces */
2564 spapr_rtc_create(spapr);
2565
2566 /* Set up VIO bus */
2567 spapr->vio_bus = spapr_vio_bus_init();
2568
2569 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2570 if (serial_hds[i]) {
2571 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2572 }
2573 }
2574
2575 /* We always have at least the nvram device on VIO */
2576 spapr_create_nvram(spapr);
2577
2578 /* Set up PCI */
2579 spapr_pci_rtas_init();
2580
2581 phb = spapr_create_phb(spapr, 0);
2582
2583 for (i = 0; i < nb_nics; i++) {
2584 NICInfo *nd = &nd_table[i];
2585
2586 if (!nd->model) {
2587 nd->model = g_strdup("ibmveth");
2588 }
2589
2590 if (strcmp(nd->model, "ibmveth") == 0) {
2591 spapr_vlan_create(spapr->vio_bus, nd);
2592 } else {
2593 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2594 }
2595 }
2596
2597 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2598 spapr_vscsi_create(spapr->vio_bus);
2599 }
2600
2601 /* Graphics */
2602 if (spapr_vga_init(phb->bus, &error_fatal)) {
2603 spapr->has_graphics = true;
2604 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2605 }
2606
2607 if (machine->usb) {
2608 if (smc->use_ohci_by_default) {
2609 pci_create_simple(phb->bus, -1, "pci-ohci");
2610 } else {
2611 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2612 }
2613
2614 if (spapr->has_graphics) {
2615 USBBus *usb_bus = usb_bus_find(-1);
2616
2617 usb_create_simple(usb_bus, "usb-kbd");
2618 usb_create_simple(usb_bus, "usb-mouse");
2619 }
2620 }
2621
2622 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2623 error_report(
2624 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2625 MIN_RMA_SLOF);
2626 exit(1);
2627 }
2628
2629 if (kernel_filename) {
2630 uint64_t lowaddr = 0;
2631
2632 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2633 NULL, NULL, &lowaddr, NULL, 1,
2634 PPC_ELF_MACHINE, 0, 0);
2635 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2636 spapr->kernel_size = load_elf(kernel_filename,
2637 translate_kernel_address, NULL, NULL,
2638 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2639 0, 0);
2640 spapr->kernel_le = spapr->kernel_size > 0;
2641 }
2642 if (spapr->kernel_size < 0) {
2643 error_report("error loading %s: %s", kernel_filename,
2644 load_elf_strerror(spapr->kernel_size));
2645 exit(1);
2646 }
2647
2648 /* load initrd */
2649 if (initrd_filename) {
2650 /* Try to locate the initrd in the gap between the kernel
2651 * and the firmware. Add a bit of space just in case
2652 */
2653 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2654 + 0x1ffff) & ~0xffff;
2655 spapr->initrd_size = load_image_targphys(initrd_filename,
2656 spapr->initrd_base,
2657 load_limit
2658 - spapr->initrd_base);
2659 if (spapr->initrd_size < 0) {
2660 error_report("could not load initial ram disk '%s'",
2661 initrd_filename);
2662 exit(1);
2663 }
2664 }
2665 }
2666
2667 if (bios_name == NULL) {
2668 bios_name = FW_FILE_NAME;
2669 }
2670 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2671 if (!filename) {
2672 error_report("Could not find LPAR firmware '%s'", bios_name);
2673 exit(1);
2674 }
2675 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2676 if (fw_size <= 0) {
2677 error_report("Could not load LPAR firmware '%s'", filename);
2678 exit(1);
2679 }
2680 g_free(filename);
2681
2682 /* FIXME: Should register things through the MachineState's qdev
2683 * interface, this is a legacy from the sPAPREnvironment structure
2684 * which predated MachineState but had a similar function */
2685 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2686 register_savevm_live(NULL, "spapr/htab", -1, 1,
2687 &savevm_htab_handlers, spapr);
2688
2689 qemu_register_boot_set(spapr_boot_set, spapr);
2690
2691 if (kvm_enabled()) {
2692 /* to stop and start vmclock */
2693 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2694 &spapr->tb);
2695
2696 kvmppc_spapr_enable_inkernel_multitce();
2697 }
2698 }
2699
2700 static int spapr_kvm_type(const char *vm_type)
2701 {
2702 if (!vm_type) {
2703 return 0;
2704 }
2705
2706 if (!strcmp(vm_type, "HV")) {
2707 return 1;
2708 }
2709
2710 if (!strcmp(vm_type, "PR")) {
2711 return 2;
2712 }
2713
2714 error_report("Unknown kvm-type specified '%s'", vm_type);
2715 exit(1);
2716 }
2717
2718 /*
2719 * Implementation of an interface to adjust firmware path
2720 * for the bootindex property handling.
2721 */
2722 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2723 DeviceState *dev)
2724 {
2725 #define CAST(type, obj, name) \
2726 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2727 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2728 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2729 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2730
2731 if (d) {
2732 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2733 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2734 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2735
2736 if (spapr) {
2737 /*
2738 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2739 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2740 * in the top 16 bits of the 64-bit LUN
2741 */
2742 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2743 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2744 (uint64_t)id << 48);
2745 } else if (virtio) {
2746 /*
2747 * We use SRP luns of the form 01000000 | (target << 8) | lun
2748 * in the top 32 bits of the 64-bit LUN
2749 * Note: the quote above is from SLOF and it is wrong,
2750 * the actual binding is:
2751 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2752 */
2753 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2754 if (d->lun >= 256) {
2755 /* Use the LUN "flat space addressing method" */
2756 id |= 0x4000;
2757 }
2758 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2759 (uint64_t)id << 32);
2760 } else if (usb) {
2761 /*
2762 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2763 * in the top 32 bits of the 64-bit LUN
2764 */
2765 unsigned usb_port = atoi(usb->port->path);
2766 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2767 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2768 (uint64_t)id << 32);
2769 }
2770 }
2771
2772 /*
2773 * SLOF probes the USB devices, and if it recognizes that the device is a
2774 * storage device, it changes its name to "storage" instead of "usb-host",
2775 * and additionally adds a child node for the SCSI LUN, so the correct
2776 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2777 */
2778 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2779 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2780 if (usb_host_dev_is_scsi_storage(usbdev)) {
2781 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2782 }
2783 }
2784
2785 if (phb) {
2786 /* Replace "pci" with "pci@800000020000000" */
2787 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2788 }
2789
2790 if (vsc) {
2791 /* Same logic as virtio above */
2792 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2793 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2794 }
2795
2796 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2797 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2798 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2799 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2800 }
2801
2802 return NULL;
2803 }
2804
2805 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2806 {
2807 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2808
2809 return g_strdup(spapr->kvm_type);
2810 }
2811
2812 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2813 {
2814 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2815
2816 g_free(spapr->kvm_type);
2817 spapr->kvm_type = g_strdup(value);
2818 }
2819
2820 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2821 {
2822 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2823
2824 return spapr->use_hotplug_event_source;
2825 }
2826
2827 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2828 Error **errp)
2829 {
2830 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2831
2832 spapr->use_hotplug_event_source = value;
2833 }
2834
2835 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2836 {
2837 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2838
2839 switch (spapr->resize_hpt) {
2840 case SPAPR_RESIZE_HPT_DEFAULT:
2841 return g_strdup("default");
2842 case SPAPR_RESIZE_HPT_DISABLED:
2843 return g_strdup("disabled");
2844 case SPAPR_RESIZE_HPT_ENABLED:
2845 return g_strdup("enabled");
2846 case SPAPR_RESIZE_HPT_REQUIRED:
2847 return g_strdup("required");
2848 }
2849 g_assert_not_reached();
2850 }
2851
2852 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2853 {
2854 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2855
2856 if (strcmp(value, "default") == 0) {
2857 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2858 } else if (strcmp(value, "disabled") == 0) {
2859 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2860 } else if (strcmp(value, "enabled") == 0) {
2861 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2862 } else if (strcmp(value, "required") == 0) {
2863 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2864 } else {
2865 error_setg(errp, "Bad value for \"resize-hpt\" property");
2866 }
2867 }
2868
2869 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
2870 void *opaque, Error **errp)
2871 {
2872 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2873 }
2874
2875 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
2876 void *opaque, Error **errp)
2877 {
2878 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2879 }
2880
2881 static void spapr_instance_init(Object *obj)
2882 {
2883 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2884
2885 spapr->htab_fd = -1;
2886 spapr->use_hotplug_event_source = true;
2887 object_property_add_str(obj, "kvm-type",
2888 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2889 object_property_set_description(obj, "kvm-type",
2890 "Specifies the KVM virtualization mode (HV, PR)",
2891 NULL);
2892 object_property_add_bool(obj, "modern-hotplug-events",
2893 spapr_get_modern_hotplug_events,
2894 spapr_set_modern_hotplug_events,
2895 NULL);
2896 object_property_set_description(obj, "modern-hotplug-events",
2897 "Use dedicated hotplug event mechanism in"
2898 " place of standard EPOW events when possible"
2899 " (required for memory hot-unplug support)",
2900 NULL);
2901
2902 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2903 "Maximum permitted CPU compatibility mode",
2904 &error_fatal);
2905
2906 object_property_add_str(obj, "resize-hpt",
2907 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2908 object_property_set_description(obj, "resize-hpt",
2909 "Resizing of the Hash Page Table (enabled, disabled, required)",
2910 NULL);
2911 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
2912 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
2913 object_property_set_description(obj, "vsmt",
2914 "Virtual SMT: KVM behaves as if this were"
2915 " the host's SMT mode", &error_abort);
2916 }
2917
2918 static void spapr_machine_finalizefn(Object *obj)
2919 {
2920 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2921
2922 g_free(spapr->kvm_type);
2923 }
2924
2925 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2926 {
2927 cpu_synchronize_state(cs);
2928 ppc_cpu_do_system_reset(cs);
2929 }
2930
2931 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2932 {
2933 CPUState *cs;
2934
2935 CPU_FOREACH(cs) {
2936 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2937 }
2938 }
2939
2940 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2941 uint32_t node, bool dedicated_hp_event_source,
2942 Error **errp)
2943 {
2944 sPAPRDRConnector *drc;
2945 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2946 int i, fdt_offset, fdt_size;
2947 void *fdt;
2948 uint64_t addr = addr_start;
2949 bool hotplugged = spapr_drc_hotplugged(dev);
2950 Error *local_err = NULL;
2951
2952 for (i = 0; i < nr_lmbs; i++) {
2953 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2954 addr / SPAPR_MEMORY_BLOCK_SIZE);
2955 g_assert(drc);
2956
2957 fdt = create_device_tree(&fdt_size);
2958 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2959 SPAPR_MEMORY_BLOCK_SIZE);
2960
2961 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2962 if (local_err) {
2963 while (addr > addr_start) {
2964 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2965 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2966 addr / SPAPR_MEMORY_BLOCK_SIZE);
2967 spapr_drc_detach(drc);
2968 }
2969 g_free(fdt);
2970 error_propagate(errp, local_err);
2971 return;
2972 }
2973 if (!hotplugged) {
2974 spapr_drc_reset(drc);
2975 }
2976 addr += SPAPR_MEMORY_BLOCK_SIZE;
2977 }
2978 /* send hotplug notification to the
2979 * guest only in case of hotplugged memory
2980 */
2981 if (hotplugged) {
2982 if (dedicated_hp_event_source) {
2983 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2984 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2985 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2986 nr_lmbs,
2987 spapr_drc_index(drc));
2988 } else {
2989 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2990 nr_lmbs);
2991 }
2992 }
2993 }
2994
2995 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2996 uint32_t node, Error **errp)
2997 {
2998 Error *local_err = NULL;
2999 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3000 PCDIMMDevice *dimm = PC_DIMM(dev);
3001 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3002 MemoryRegion *mr;
3003 uint64_t align, size, addr;
3004
3005 mr = ddc->get_memory_region(dimm, &local_err);
3006 if (local_err) {
3007 goto out;
3008 }
3009 align = memory_region_get_alignment(mr);
3010 size = memory_region_size(mr);
3011
3012 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
3013 if (local_err) {
3014 goto out;
3015 }
3016
3017 addr = object_property_get_uint(OBJECT(dimm),
3018 PC_DIMM_ADDR_PROP, &local_err);
3019 if (local_err) {
3020 goto out_unplug;
3021 }
3022
3023 spapr_add_lmbs(dev, addr, size, node,
3024 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3025 &local_err);
3026 if (local_err) {
3027 goto out_unplug;
3028 }
3029
3030 return;
3031
3032 out_unplug:
3033 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
3034 out:
3035 error_propagate(errp, local_err);
3036 }
3037
3038 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3039 Error **errp)
3040 {
3041 PCDIMMDevice *dimm = PC_DIMM(dev);
3042 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3043 MemoryRegion *mr;
3044 uint64_t size;
3045 char *mem_dev;
3046
3047 mr = ddc->get_memory_region(dimm, errp);
3048 if (!mr) {
3049 return;
3050 }
3051 size = memory_region_size(mr);
3052
3053 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3054 error_setg(errp, "Hotplugged memory size must be a multiple of "
3055 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
3056 return;
3057 }
3058
3059 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
3060 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
3061 error_setg(errp, "Memory backend has bad page size. "
3062 "Use 'memory-backend-file' with correct mem-path.");
3063 goto out;
3064 }
3065
3066 out:
3067 g_free(mem_dev);
3068 }
3069
3070 struct sPAPRDIMMState {
3071 PCDIMMDevice *dimm;
3072 uint32_t nr_lmbs;
3073 QTAILQ_ENTRY(sPAPRDIMMState) next;
3074 };
3075
3076 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
3077 PCDIMMDevice *dimm)
3078 {
3079 sPAPRDIMMState *dimm_state = NULL;
3080
3081 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3082 if (dimm_state->dimm == dimm) {
3083 break;
3084 }
3085 }
3086 return dimm_state;
3087 }
3088
3089 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
3090 uint32_t nr_lmbs,
3091 PCDIMMDevice *dimm)
3092 {
3093 sPAPRDIMMState *ds = NULL;
3094
3095 /*
3096 * If this request is for a DIMM whose removal had failed earlier
3097 * (due to guest's refusal to remove the LMBs), we would have this
3098 * dimm already in the pending_dimm_unplugs list. In that
3099 * case don't add again.
3100 */
3101 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3102 if (!ds) {
3103 ds = g_malloc0(sizeof(sPAPRDIMMState));
3104 ds->nr_lmbs = nr_lmbs;
3105 ds->dimm = dimm;
3106 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3107 }
3108 return ds;
3109 }
3110
3111 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3112 sPAPRDIMMState *dimm_state)
3113 {
3114 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3115 g_free(dimm_state);
3116 }
3117
3118 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3119 PCDIMMDevice *dimm)
3120 {
3121 sPAPRDRConnector *drc;
3122 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3123 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3124 uint64_t size = memory_region_size(mr);
3125 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3126 uint32_t avail_lmbs = 0;
3127 uint64_t addr_start, addr;
3128 int i;
3129
3130 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3131 &error_abort);
3132
3133 addr = addr_start;
3134 for (i = 0; i < nr_lmbs; i++) {
3135 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3136 addr / SPAPR_MEMORY_BLOCK_SIZE);
3137 g_assert(drc);
3138 if (drc->dev) {
3139 avail_lmbs++;
3140 }
3141 addr += SPAPR_MEMORY_BLOCK_SIZE;
3142 }
3143
3144 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3145 }
3146
3147 /* Callback to be called during DRC release. */
3148 void spapr_lmb_release(DeviceState *dev)
3149 {
3150 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
3151 PCDIMMDevice *dimm = PC_DIMM(dev);
3152 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3153 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3154 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3155
3156 /* This information will get lost if a migration occurs
3157 * during the unplug process. In this case recover it. */
3158 if (ds == NULL) {
3159 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3160 g_assert(ds);
3161 /* The DRC being examined by the caller at least must be counted */
3162 g_assert(ds->nr_lmbs);
3163 }
3164
3165 if (--ds->nr_lmbs) {
3166 return;
3167 }
3168
3169 /*
3170 * Now that all the LMBs have been removed by the guest, call the
3171 * pc-dimm unplug handler to cleanup up the pc-dimm device.
3172 */
3173 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
3174 object_unparent(OBJECT(dev));
3175 spapr_pending_dimm_unplugs_remove(spapr, ds);
3176 }
3177
3178 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3179 DeviceState *dev, Error **errp)
3180 {
3181 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3182 Error *local_err = NULL;
3183 PCDIMMDevice *dimm = PC_DIMM(dev);
3184 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3185 MemoryRegion *mr;
3186 uint32_t nr_lmbs;
3187 uint64_t size, addr_start, addr;
3188 int i;
3189 sPAPRDRConnector *drc;
3190
3191 mr = ddc->get_memory_region(dimm, &local_err);
3192 if (local_err) {
3193 goto out;
3194 }
3195 size = memory_region_size(mr);
3196 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3197
3198 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3199 &local_err);
3200 if (local_err) {
3201 goto out;
3202 }
3203
3204 /*
3205 * An existing pending dimm state for this DIMM means that there is an
3206 * unplug operation in progress, waiting for the spapr_lmb_release
3207 * callback to complete the job (BQL can't cover that far). In this case,
3208 * bail out to avoid detaching DRCs that were already released.
3209 */
3210 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3211 error_setg(&local_err,
3212 "Memory unplug already in progress for device %s",
3213 dev->id);
3214 goto out;
3215 }
3216
3217 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3218
3219 addr = addr_start;
3220 for (i = 0; i < nr_lmbs; i++) {
3221 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3222 addr / SPAPR_MEMORY_BLOCK_SIZE);
3223 g_assert(drc);
3224
3225 spapr_drc_detach(drc);
3226 addr += SPAPR_MEMORY_BLOCK_SIZE;
3227 }
3228
3229 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3230 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3231 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3232 nr_lmbs, spapr_drc_index(drc));
3233 out:
3234 error_propagate(errp, local_err);
3235 }
3236
3237 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3238 sPAPRMachineState *spapr)
3239 {
3240 PowerPCCPU *cpu = POWERPC_CPU(cs);
3241 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3242 int id = spapr_vcpu_id(cpu);
3243 void *fdt;
3244 int offset, fdt_size;
3245 char *nodename;
3246
3247 fdt = create_device_tree(&fdt_size);
3248 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3249 offset = fdt_add_subnode(fdt, 0, nodename);
3250
3251 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3252 g_free(nodename);
3253
3254 *fdt_offset = offset;
3255 return fdt;
3256 }
3257
3258 /* Callback to be called during DRC release. */
3259 void spapr_core_release(DeviceState *dev)
3260 {
3261 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3262 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3263 CPUCore *cc = CPU_CORE(dev);
3264 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3265
3266 if (smc->pre_2_10_has_unused_icps) {
3267 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3268 int i;
3269
3270 for (i = 0; i < cc->nr_threads; i++) {
3271 CPUState *cs = CPU(sc->threads[i]);
3272
3273 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3274 }
3275 }
3276
3277 assert(core_slot);
3278 core_slot->cpu = NULL;
3279 object_unparent(OBJECT(dev));
3280 }
3281
3282 static
3283 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3284 Error **errp)
3285 {
3286 int index;
3287 sPAPRDRConnector *drc;
3288 CPUCore *cc = CPU_CORE(dev);
3289 int smt = kvmppc_smt_threads();
3290
3291 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3292 error_setg(errp, "Unable to find CPU core with core-id: %d",
3293 cc->core_id);
3294 return;
3295 }
3296 if (index == 0) {
3297 error_setg(errp, "Boot CPU core may not be unplugged");
3298 return;
3299 }
3300
3301 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3302 g_assert(drc);
3303
3304 spapr_drc_detach(drc);
3305
3306 spapr_hotplug_req_remove_by_index(drc);
3307 }
3308
3309 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3310 Error **errp)
3311 {
3312 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3313 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3314 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3315 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3316 CPUCore *cc = CPU_CORE(dev);
3317 CPUState *cs = CPU(core->threads[0]);
3318 sPAPRDRConnector *drc;
3319 Error *local_err = NULL;
3320 int smt = kvmppc_smt_threads();
3321 CPUArchId *core_slot;
3322 int index;
3323 bool hotplugged = spapr_drc_hotplugged(dev);
3324
3325 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3326 if (!core_slot) {
3327 error_setg(errp, "Unable to find CPU core with core-id: %d",
3328 cc->core_id);
3329 return;
3330 }
3331 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3332
3333 g_assert(drc || !mc->has_hotpluggable_cpus);
3334
3335 if (drc) {
3336 void *fdt;
3337 int fdt_offset;
3338
3339 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3340
3341 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3342 if (local_err) {
3343 g_free(fdt);
3344 error_propagate(errp, local_err);
3345 return;
3346 }
3347
3348 if (hotplugged) {
3349 /*
3350 * Send hotplug notification interrupt to the guest only
3351 * in case of hotplugged CPUs.
3352 */
3353 spapr_hotplug_req_add_by_index(drc);
3354 } else {
3355 spapr_drc_reset(drc);
3356 }
3357 }
3358
3359 core_slot->cpu = OBJECT(dev);
3360
3361 if (smc->pre_2_10_has_unused_icps) {
3362 int i;
3363
3364 for (i = 0; i < cc->nr_threads; i++) {
3365 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev);
3366
3367 cs = CPU(sc->threads[i]);
3368 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3369 }
3370 }
3371 }
3372
3373 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3374 Error **errp)
3375 {
3376 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3377 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3378 Error *local_err = NULL;
3379 CPUCore *cc = CPU_CORE(dev);
3380 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3381 const char *type = object_get_typename(OBJECT(dev));
3382 CPUArchId *core_slot;
3383 int index;
3384
3385 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3386 error_setg(&local_err, "CPU hotplug not supported for this machine");
3387 goto out;
3388 }
3389
3390 if (strcmp(base_core_type, type)) {
3391 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3392 goto out;
3393 }
3394
3395 if (cc->core_id % smp_threads) {
3396 error_setg(&local_err, "invalid core id %d", cc->core_id);
3397 goto out;
3398 }
3399
3400 /*
3401 * In general we should have homogeneous threads-per-core, but old
3402 * (pre hotplug support) machine types allow the last core to have
3403 * reduced threads as a compatibility hack for when we allowed
3404 * total vcpus not a multiple of threads-per-core.
3405 */
3406 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3407 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3408 cc->nr_threads, smp_threads);
3409 goto out;
3410 }
3411
3412 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3413 if (!core_slot) {
3414 error_setg(&local_err, "core id %d out of range", cc->core_id);
3415 goto out;
3416 }
3417
3418 if (core_slot->cpu) {
3419 error_setg(&local_err, "core %d already populated", cc->core_id);
3420 goto out;
3421 }
3422
3423 numa_cpu_pre_plug(core_slot, dev, &local_err);
3424
3425 out:
3426 error_propagate(errp, local_err);
3427 }
3428
3429 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3430 DeviceState *dev, Error **errp)
3431 {
3432 MachineState *ms = MACHINE(hotplug_dev);
3433 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3434
3435 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3436 int node;
3437
3438 if (!smc->dr_lmb_enabled) {
3439 error_setg(errp, "Memory hotplug not supported for this machine");
3440 return;
3441 }
3442 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3443 if (*errp) {
3444 return;
3445 }
3446 if (node < 0 || node >= MAX_NODES) {
3447 error_setg(errp, "Invaild node %d", node);
3448 return;
3449 }
3450
3451 /*
3452 * Currently PowerPC kernel doesn't allow hot-adding memory to
3453 * memory-less node, but instead will silently add the memory
3454 * to the first node that has some memory. This causes two
3455 * unexpected behaviours for the user.
3456 *
3457 * - Memory gets hotplugged to a different node than what the user
3458 * specified.
3459 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
3460 * to memory-less node, a reboot will set things accordingly
3461 * and the previously hotplugged memory now ends in the right node.
3462 * This appears as if some memory moved from one node to another.
3463 *
3464 * So until kernel starts supporting memory hotplug to memory-less
3465 * nodes, just prevent such attempts upfront in QEMU.
3466 */
3467 if (nb_numa_nodes && !numa_info[node].node_mem) {
3468 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3469 node);
3470 return;
3471 }
3472
3473 spapr_memory_plug(hotplug_dev, dev, node, errp);
3474 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3475 spapr_core_plug(hotplug_dev, dev, errp);
3476 }
3477 }
3478
3479 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3480 DeviceState *dev, Error **errp)
3481 {
3482 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3483 MachineClass *mc = MACHINE_GET_CLASS(sms);
3484
3485 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3486 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3487 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3488 } else {
3489 /* NOTE: this means there is a window after guest reset, prior to
3490 * CAS negotiation, where unplug requests will fail due to the
3491 * capability not being detected yet. This is a bit different than
3492 * the case with PCI unplug, where the events will be queued and
3493 * eventually handled by the guest after boot
3494 */
3495 error_setg(errp, "Memory hot unplug not supported for this guest");
3496 }
3497 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3498 if (!mc->has_hotpluggable_cpus) {
3499 error_setg(errp, "CPU hot unplug not supported on this machine");
3500 return;
3501 }
3502 spapr_core_unplug_request(hotplug_dev, dev, errp);
3503 }
3504 }
3505
3506 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3507 DeviceState *dev, Error **errp)
3508 {
3509 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3510 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3511 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3512 spapr_core_pre_plug(hotplug_dev, dev, errp);
3513 }
3514 }
3515
3516 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3517 DeviceState *dev)
3518 {
3519 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3520 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3521 return HOTPLUG_HANDLER(machine);
3522 }
3523 return NULL;
3524 }
3525
3526 static CpuInstanceProperties
3527 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3528 {
3529 CPUArchId *core_slot;
3530 MachineClass *mc = MACHINE_GET_CLASS(machine);
3531
3532 /* make sure possible_cpu are intialized */
3533 mc->possible_cpu_arch_ids(machine);
3534 /* get CPU core slot containing thread that matches cpu_index */
3535 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3536 assert(core_slot);
3537 return core_slot->props;
3538 }
3539
3540 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3541 {
3542 return idx / smp_cores % nb_numa_nodes;
3543 }
3544
3545 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3546 {
3547 int i;
3548 int spapr_max_cores = max_cpus / smp_threads;
3549 MachineClass *mc = MACHINE_GET_CLASS(machine);
3550
3551 if (!mc->has_hotpluggable_cpus) {
3552 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3553 }
3554 if (machine->possible_cpus) {
3555 assert(machine->possible_cpus->len == spapr_max_cores);
3556 return machine->possible_cpus;
3557 }
3558
3559 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3560 sizeof(CPUArchId) * spapr_max_cores);
3561 machine->possible_cpus->len = spapr_max_cores;
3562 for (i = 0; i < machine->possible_cpus->len; i++) {
3563 int core_id = i * smp_threads;
3564
3565 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3566 machine->possible_cpus->cpus[i].arch_id = core_id;
3567 machine->possible_cpus->cpus[i].props.has_core_id = true;
3568 machine->possible_cpus->cpus[i].props.core_id = core_id;
3569 }
3570 return machine->possible_cpus;
3571 }
3572
3573 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3574 uint64_t *buid, hwaddr *pio,
3575 hwaddr *mmio32, hwaddr *mmio64,
3576 unsigned n_dma, uint32_t *liobns, Error **errp)
3577 {
3578 /*
3579 * New-style PHB window placement.
3580 *
3581 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3582 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3583 * windows.
3584 *
3585 * Some guest kernels can't work with MMIO windows above 1<<46
3586 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3587 *
3588 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3589 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3590 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3591 * 1TiB 64-bit MMIO windows for each PHB.
3592 */
3593 const uint64_t base_buid = 0x800000020000000ULL;
3594 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3595 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3596 int i;
3597
3598 /* Sanity check natural alignments */
3599 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3600 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3601 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3602 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3603 /* Sanity check bounds */
3604 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3605 SPAPR_PCI_MEM32_WIN_SIZE);
3606 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3607 SPAPR_PCI_MEM64_WIN_SIZE);
3608
3609 if (index >= SPAPR_MAX_PHBS) {
3610 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3611 SPAPR_MAX_PHBS - 1);
3612 return;
3613 }
3614
3615 *buid = base_buid + index;
3616 for (i = 0; i < n_dma; ++i) {
3617 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3618 }
3619
3620 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3621 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3622 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3623 }
3624
3625 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3626 {
3627 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3628
3629 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3630 }
3631
3632 static void spapr_ics_resend(XICSFabric *dev)
3633 {
3634 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3635
3636 ics_resend(spapr->ics);
3637 }
3638
3639 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3640 {
3641 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3642
3643 return cpu ? ICP(cpu->intc) : NULL;
3644 }
3645
3646 #define ICS_IRQ_FREE(ics, srcno) \
3647 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
3648
3649 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
3650 {
3651 int first, i;
3652
3653 for (first = 0; first < ics->nr_irqs; first += alignnum) {
3654 if (num > (ics->nr_irqs - first)) {
3655 return -1;
3656 }
3657 for (i = first; i < first + num; ++i) {
3658 if (!ICS_IRQ_FREE(ics, i)) {
3659 break;
3660 }
3661 }
3662 if (i == (first + num)) {
3663 return first;
3664 }
3665 }
3666
3667 return -1;
3668 }
3669
3670 /*
3671 * Allocate the IRQ number and set the IRQ type, LSI or MSI
3672 */
3673 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi)
3674 {
3675 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi);
3676 }
3677
3678 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
3679 Error **errp)
3680 {
3681 ICSState *ics = spapr->ics;
3682 int irq;
3683
3684 if (!ics) {
3685 return -1;
3686 }
3687 if (irq_hint) {
3688 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
3689 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
3690 return -1;
3691 }
3692 irq = irq_hint;
3693 } else {
3694 irq = ics_find_free_block(ics, 1, 1);
3695 if (irq < 0) {
3696 error_setg(errp, "can't allocate IRQ: no IRQ left");
3697 return -1;
3698 }
3699 irq += ics->offset;
3700 }
3701
3702 spapr_irq_set_lsi(spapr, irq, lsi);
3703 trace_spapr_irq_alloc(irq);
3704
3705 return irq;
3706 }
3707
3708 /*
3709 * Allocate block of consecutive IRQs, and return the number of the first IRQ in
3710 * the block. If align==true, aligns the first IRQ number to num.
3711 */
3712 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
3713 bool align, Error **errp)
3714 {
3715 ICSState *ics = spapr->ics;
3716 int i, first = -1;
3717
3718 if (!ics) {
3719 return -1;
3720 }
3721
3722 /*
3723 * MSIMesage::data is used for storing VIRQ so
3724 * it has to be aligned to num to support multiple
3725 * MSI vectors. MSI-X is not affected by this.
3726 * The hint is used for the first IRQ, the rest should
3727 * be allocated continuously.
3728 */
3729 if (align) {
3730 assert((num == 1) || (num == 2) || (num == 4) ||
3731 (num == 8) || (num == 16) || (num == 32));
3732 first = ics_find_free_block(ics, num, num);
3733 } else {
3734 first = ics_find_free_block(ics, num, 1);
3735 }
3736 if (first < 0) {
3737 error_setg(errp, "can't find a free %d-IRQ block", num);
3738 return -1;
3739 }
3740
3741 first += ics->offset;
3742 for (i = first; i < first + num; ++i) {
3743 spapr_irq_set_lsi(spapr, i, lsi);
3744 }
3745
3746 trace_spapr_irq_alloc_block(first, num, lsi, align);
3747
3748 return first;
3749 }
3750
3751 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
3752 {
3753 ICSState *ics = spapr->ics;
3754 int srcno = irq - ics->offset;
3755 int i;
3756
3757 if (ics_valid_irq(ics, irq)) {
3758 trace_spapr_irq_free(0, irq, num);
3759 for (i = srcno; i < srcno + num; ++i) {
3760 if (ICS_IRQ_FREE(ics, i)) {
3761 trace_spapr_irq_free_warn(0, i + ics->offset);
3762 }
3763 memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
3764 }
3765 }
3766 }
3767
3768 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
3769 {
3770 ICSState *ics = spapr->ics;
3771
3772 if (ics_valid_irq(ics, irq)) {
3773 return ics->qirqs[irq - ics->offset];
3774 }
3775
3776 return NULL;
3777 }
3778
3779 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3780 Monitor *mon)
3781 {
3782 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3783 CPUState *cs;
3784
3785 CPU_FOREACH(cs) {
3786 PowerPCCPU *cpu = POWERPC_CPU(cs);
3787
3788 icp_pic_print_info(ICP(cpu->intc), mon);
3789 }
3790
3791 ics_pic_print_info(spapr->ics, mon);
3792 }
3793
3794 int spapr_vcpu_id(PowerPCCPU *cpu)
3795 {
3796 CPUState *cs = CPU(cpu);
3797
3798 if (kvm_enabled()) {
3799 return kvm_arch_vcpu_id(cs);
3800 } else {
3801 return cs->cpu_index;
3802 }
3803 }
3804
3805 PowerPCCPU *spapr_find_cpu(int vcpu_id)
3806 {
3807 CPUState *cs;
3808
3809 CPU_FOREACH(cs) {
3810 PowerPCCPU *cpu = POWERPC_CPU(cs);
3811
3812 if (spapr_vcpu_id(cpu) == vcpu_id) {
3813 return cpu;
3814 }
3815 }
3816
3817 return NULL;
3818 }
3819
3820 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3821 {
3822 MachineClass *mc = MACHINE_CLASS(oc);
3823 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3824 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3825 NMIClass *nc = NMI_CLASS(oc);
3826 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3827 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3828 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3829 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3830
3831 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3832
3833 /*
3834 * We set up the default / latest behaviour here. The class_init
3835 * functions for the specific versioned machine types can override
3836 * these details for backwards compatibility
3837 */
3838 mc->init = spapr_machine_init;
3839 mc->reset = spapr_machine_reset;
3840 mc->block_default_type = IF_SCSI;
3841 mc->max_cpus = 1024;
3842 mc->no_parallel = 1;
3843 mc->default_boot_order = "";
3844 mc->default_ram_size = 512 * M_BYTE;
3845 mc->kvm_type = spapr_kvm_type;
3846 mc->has_dynamic_sysbus = true;
3847 mc->pci_allow_0_address = true;
3848 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3849 hc->pre_plug = spapr_machine_device_pre_plug;
3850 hc->plug = spapr_machine_device_plug;
3851 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3852 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3853 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3854 hc->unplug_request = spapr_machine_device_unplug_request;
3855
3856 smc->dr_lmb_enabled = true;
3857 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
3858 mc->has_hotpluggable_cpus = true;
3859 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3860 fwc->get_dev_path = spapr_get_fw_dev_path;
3861 nc->nmi_monitor_handler = spapr_nmi;
3862 smc->phb_placement = spapr_phb_placement;
3863 vhc->hypercall = emulate_spapr_hypercall;
3864 vhc->hpt_mask = spapr_hpt_mask;
3865 vhc->map_hptes = spapr_map_hptes;
3866 vhc->unmap_hptes = spapr_unmap_hptes;
3867 vhc->store_hpte = spapr_store_hpte;
3868 vhc->get_patbe = spapr_get_patbe;
3869 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
3870 xic->ics_get = spapr_ics_get;
3871 xic->ics_resend = spapr_ics_resend;
3872 xic->icp_get = spapr_icp_get;
3873 ispc->print_info = spapr_pic_print_info;
3874 /* Force NUMA node memory size to be a multiple of
3875 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3876 * in which LMBs are represented and hot-added
3877 */
3878 mc->numa_mem_align_shift = 28;
3879
3880 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
3881 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
3882 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
3883 spapr_caps_add_properties(smc, &error_abort);
3884 }
3885
3886 static const TypeInfo spapr_machine_info = {
3887 .name = TYPE_SPAPR_MACHINE,
3888 .parent = TYPE_MACHINE,
3889 .abstract = true,
3890 .instance_size = sizeof(sPAPRMachineState),
3891 .instance_init = spapr_instance_init,
3892 .instance_finalize = spapr_machine_finalizefn,
3893 .class_size = sizeof(sPAPRMachineClass),
3894 .class_init = spapr_machine_class_init,
3895 .interfaces = (InterfaceInfo[]) {
3896 { TYPE_FW_PATH_PROVIDER },
3897 { TYPE_NMI },
3898 { TYPE_HOTPLUG_HANDLER },
3899 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3900 { TYPE_XICS_FABRIC },
3901 { TYPE_INTERRUPT_STATS_PROVIDER },
3902 { }
3903 },
3904 };
3905
3906 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3907 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3908 void *data) \
3909 { \
3910 MachineClass *mc = MACHINE_CLASS(oc); \
3911 spapr_machine_##suffix##_class_options(mc); \
3912 if (latest) { \
3913 mc->alias = "pseries"; \
3914 mc->is_default = 1; \
3915 } \
3916 } \
3917 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3918 { \
3919 MachineState *machine = MACHINE(obj); \
3920 spapr_machine_##suffix##_instance_options(machine); \
3921 } \
3922 static const TypeInfo spapr_machine_##suffix##_info = { \
3923 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3924 .parent = TYPE_SPAPR_MACHINE, \
3925 .class_init = spapr_machine_##suffix##_class_init, \
3926 .instance_init = spapr_machine_##suffix##_instance_init, \
3927 }; \
3928 static void spapr_machine_register_##suffix(void) \
3929 { \
3930 type_register(&spapr_machine_##suffix##_info); \
3931 } \
3932 type_init(spapr_machine_register_##suffix)
3933
3934 /*
3935 * pseries-2.12
3936 */
3937 static void spapr_machine_2_12_instance_options(MachineState *machine)
3938 {
3939 }
3940
3941 static void spapr_machine_2_12_class_options(MachineClass *mc)
3942 {
3943 /* Defaults for the latest behaviour inherited from the base class */
3944 }
3945
3946 DEFINE_SPAPR_MACHINE(2_12, "2.12", true);
3947
3948 /*
3949 * pseries-2.11
3950 */
3951 #define SPAPR_COMPAT_2_11 \
3952 HW_COMPAT_2_11
3953
3954 static void spapr_machine_2_11_instance_options(MachineState *machine)
3955 {
3956 spapr_machine_2_12_instance_options(machine);
3957 }
3958
3959 static void spapr_machine_2_11_class_options(MachineClass *mc)
3960 {
3961 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3962
3963 spapr_machine_2_12_class_options(mc);
3964 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
3965 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
3966 }
3967
3968 DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
3969
3970 /*
3971 * pseries-2.10
3972 */
3973 #define SPAPR_COMPAT_2_10 \
3974 HW_COMPAT_2_10
3975
3976 static void spapr_machine_2_10_instance_options(MachineState *machine)
3977 {
3978 spapr_machine_2_11_instance_options(machine);
3979 }
3980
3981 static void spapr_machine_2_10_class_options(MachineClass *mc)
3982 {
3983 spapr_machine_2_11_class_options(mc);
3984 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
3985 }
3986
3987 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
3988
3989 /*
3990 * pseries-2.9
3991 */
3992 #define SPAPR_COMPAT_2_9 \
3993 HW_COMPAT_2_9 \
3994 { \
3995 .driver = TYPE_POWERPC_CPU, \
3996 .property = "pre-2.10-migration", \
3997 .value = "on", \
3998 }, \
3999
4000 static void spapr_machine_2_9_instance_options(MachineState *machine)
4001 {
4002 spapr_machine_2_10_instance_options(machine);
4003 }
4004
4005 static void spapr_machine_2_9_class_options(MachineClass *mc)
4006 {
4007 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4008
4009 spapr_machine_2_10_class_options(mc);
4010 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
4011 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4012 smc->pre_2_10_has_unused_icps = true;
4013 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4014 }
4015
4016 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4017
4018 /*
4019 * pseries-2.8
4020 */
4021 #define SPAPR_COMPAT_2_8 \
4022 HW_COMPAT_2_8 \
4023 { \
4024 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4025 .property = "pcie-extended-configuration-space", \
4026 .value = "off", \
4027 },
4028
4029 static void spapr_machine_2_8_instance_options(MachineState *machine)
4030 {
4031 spapr_machine_2_9_instance_options(machine);
4032 }
4033
4034 static void spapr_machine_2_8_class_options(MachineClass *mc)
4035 {
4036 spapr_machine_2_9_class_options(mc);
4037 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
4038 mc->numa_mem_align_shift = 23;
4039 }
4040
4041 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4042
4043 /*
4044 * pseries-2.7
4045 */
4046 #define SPAPR_COMPAT_2_7 \
4047 HW_COMPAT_2_7 \
4048 { \
4049 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4050 .property = "mem_win_size", \
4051 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4052 }, \
4053 { \
4054 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4055 .property = "mem64_win_size", \
4056 .value = "0", \
4057 }, \
4058 { \
4059 .driver = TYPE_POWERPC_CPU, \
4060 .property = "pre-2.8-migration", \
4061 .value = "on", \
4062 }, \
4063 { \
4064 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4065 .property = "pre-2.8-migration", \
4066 .value = "on", \
4067 },
4068
4069 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
4070 uint64_t *buid, hwaddr *pio,
4071 hwaddr *mmio32, hwaddr *mmio64,
4072 unsigned n_dma, uint32_t *liobns, Error **errp)
4073 {
4074 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4075 const uint64_t base_buid = 0x800000020000000ULL;
4076 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
4077 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
4078 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
4079 const uint32_t max_index = 255;
4080 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
4081
4082 uint64_t ram_top = MACHINE(spapr)->ram_size;
4083 hwaddr phb0_base, phb_base;
4084 int i;
4085
4086 /* Do we have hotpluggable memory? */
4087 if (MACHINE(spapr)->maxram_size > ram_top) {
4088 /* Can't just use maxram_size, because there may be an
4089 * alignment gap between normal and hotpluggable memory
4090 * regions */
4091 ram_top = spapr->hotplug_memory.base +
4092 memory_region_size(&spapr->hotplug_memory.mr);
4093 }
4094
4095 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4096
4097 if (index > max_index) {
4098 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4099 max_index);
4100 return;
4101 }
4102
4103 *buid = base_buid + index;
4104 for (i = 0; i < n_dma; ++i) {
4105 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4106 }
4107
4108 phb_base = phb0_base + index * phb_spacing;
4109 *pio = phb_base + pio_offset;
4110 *mmio32 = phb_base + mmio_offset;
4111 /*
4112 * We don't set the 64-bit MMIO window, relying on the PHB's
4113 * fallback behaviour of automatically splitting a large "32-bit"
4114 * window into contiguous 32-bit and 64-bit windows
4115 */
4116 }
4117
4118 static void spapr_machine_2_7_instance_options(MachineState *machine)
4119 {
4120 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
4121
4122 spapr_machine_2_8_instance_options(machine);
4123 spapr->use_hotplug_event_source = false;
4124 }
4125
4126 static void spapr_machine_2_7_class_options(MachineClass *mc)
4127 {
4128 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4129
4130 spapr_machine_2_8_class_options(mc);
4131 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4132 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
4133 smc->phb_placement = phb_placement_2_7;
4134 }
4135
4136 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4137
4138 /*
4139 * pseries-2.6
4140 */
4141 #define SPAPR_COMPAT_2_6 \
4142 HW_COMPAT_2_6 \
4143 { \
4144 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4145 .property = "ddw",\
4146 .value = stringify(off),\
4147 },
4148
4149 static void spapr_machine_2_6_instance_options(MachineState *machine)
4150 {
4151 spapr_machine_2_7_instance_options(machine);
4152 }
4153
4154 static void spapr_machine_2_6_class_options(MachineClass *mc)
4155 {
4156 spapr_machine_2_7_class_options(mc);
4157 mc->has_hotpluggable_cpus = false;
4158 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4159 }
4160
4161 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4162
4163 /*
4164 * pseries-2.5
4165 */
4166 #define SPAPR_COMPAT_2_5 \
4167 HW_COMPAT_2_5 \
4168 { \
4169 .driver = "spapr-vlan", \
4170 .property = "use-rx-buffer-pools", \
4171 .value = "off", \
4172 },
4173
4174 static void spapr_machine_2_5_instance_options(MachineState *machine)
4175 {
4176 spapr_machine_2_6_instance_options(machine);
4177 }
4178
4179 static void spapr_machine_2_5_class_options(MachineClass *mc)
4180 {
4181 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4182
4183 spapr_machine_2_6_class_options(mc);
4184 smc->use_ohci_by_default = true;
4185 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
4186 }
4187
4188 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4189
4190 /*
4191 * pseries-2.4
4192 */
4193 #define SPAPR_COMPAT_2_4 \
4194 HW_COMPAT_2_4
4195
4196 static void spapr_machine_2_4_instance_options(MachineState *machine)
4197 {
4198 spapr_machine_2_5_instance_options(machine);
4199 }
4200
4201 static void spapr_machine_2_4_class_options(MachineClass *mc)
4202 {
4203 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4204
4205 spapr_machine_2_5_class_options(mc);
4206 smc->dr_lmb_enabled = false;
4207 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
4208 }
4209
4210 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4211
4212 /*
4213 * pseries-2.3
4214 */
4215 #define SPAPR_COMPAT_2_3 \
4216 HW_COMPAT_2_3 \
4217 {\
4218 .driver = "spapr-pci-host-bridge",\
4219 .property = "dynamic-reconfiguration",\
4220 .value = "off",\
4221 },
4222
4223 static void spapr_machine_2_3_instance_options(MachineState *machine)
4224 {
4225 spapr_machine_2_4_instance_options(machine);
4226 }
4227
4228 static void spapr_machine_2_3_class_options(MachineClass *mc)
4229 {
4230 spapr_machine_2_4_class_options(mc);
4231 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
4232 }
4233 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4234
4235 /*
4236 * pseries-2.2
4237 */
4238
4239 #define SPAPR_COMPAT_2_2 \
4240 HW_COMPAT_2_2 \
4241 {\
4242 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4243 .property = "mem_win_size",\
4244 .value = "0x20000000",\
4245 },
4246
4247 static void spapr_machine_2_2_instance_options(MachineState *machine)
4248 {
4249 spapr_machine_2_3_instance_options(machine);
4250 machine->suppress_vmdesc = true;
4251 }
4252
4253 static void spapr_machine_2_2_class_options(MachineClass *mc)
4254 {
4255 spapr_machine_2_3_class_options(mc);
4256 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4257 }
4258 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4259
4260 /*
4261 * pseries-2.1
4262 */
4263 #define SPAPR_COMPAT_2_1 \
4264 HW_COMPAT_2_1
4265
4266 static void spapr_machine_2_1_instance_options(MachineState *machine)
4267 {
4268 spapr_machine_2_2_instance_options(machine);
4269 }
4270
4271 static void spapr_machine_2_1_class_options(MachineClass *mc)
4272 {
4273 spapr_machine_2_2_class_options(mc);
4274 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
4275 }
4276 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4277
4278 static void spapr_machine_register_types(void)
4279 {
4280 type_register_static(&spapr_machine_info);
4281 }
4282
4283 type_init(spapr_machine_register_types)
AR7 emulation for QEMU