hw/usb/hcd-dwc2.h

   1 /*
   2  * dwc-hsotg (dwc2) USB host controller state definitions
   3  *
   4  * Based on hw/usb/hcd-ehci.h
   5  *
   6  * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #ifndef HW_USB_DWC2_H
  20 #define HW_USB_DWC2_H
  21
  22 #include "qemu/timer.h"
  23 #include "hw/irq.h"
  24 #include "hw/sysbus.h"
  25 #include "hw/usb.h"
  26 #include "sysemu/dma.h"
  27
  28 #define DWC2_MMIO_SIZE      0x11000
  29
  30 #define DWC2_NB_CHAN        8       /* Number of host channels */
  31 #define DWC2_MAX_XFER_SIZE  65536   /* Max transfer size expected in HCTSIZ */
  32
  33 typedef struct DWC2Packet DWC2Packet;
  34 typedef struct DWC2State DWC2State;
  35 typedef struct DWC2Class DWC2Class;
  36
  37 enum async_state {
  38     DWC2_ASYNC_NONE = 0,
  39     DWC2_ASYNC_INITIALIZED,
  40     DWC2_ASYNC_INFLIGHT,
  41     DWC2_ASYNC_FINISHED,
  42 };
  43
  44 struct DWC2Packet {
  45     USBPacket packet;
  46     uint32_t devadr;
  47     uint32_t epnum;
  48     uint32_t epdir;
  49     uint32_t mps;
  50     uint32_t pid;
  51     uint32_t index;
  52     uint32_t pcnt;
  53     uint32_t len;
  54     int32_t async;
  55     bool small;
  56     bool needs_service;
  57 };
  58
  59 struct DWC2State {
  60     /*< private >*/
  61     SysBusDevice parent_obj;
  62
  63     /*< public >*/
  64     USBBus bus;
  65     qemu_irq irq;
  66     MemoryRegion *dma_mr;
  67     AddressSpace dma_as;
  68     MemoryRegion container;
  69     MemoryRegion hsotg;
  70     MemoryRegion fifos;
  71
  72     union {
  73 #define DWC2_GLBREG_SIZE    0x70
  74         uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)];
  75         struct {
  76             uint32_t gotgctl;       /* 00 */
  77             uint32_t gotgint;       /* 04 */
  78             uint32_t gahbcfg;       /* 08 */
  79             uint32_t gusbcfg;       /* 0c */
  80             uint32_t grstctl;       /* 10 */
  81             uint32_t gintsts;       /* 14 */
  82             uint32_t gintmsk;       /* 18 */
  83             uint32_t grxstsr;       /* 1c */
  84             uint32_t grxstsp;       /* 20 */
  85             uint32_t grxfsiz;       /* 24 */
  86             uint32_t gnptxfsiz;     /* 28 */
  87             uint32_t gnptxsts;      /* 2c */
  88             uint32_t gi2cctl;       /* 30 */
  89             uint32_t gpvndctl;      /* 34 */
  90             uint32_t ggpio;         /* 38 */
  91             uint32_t guid;          /* 3c */
  92             uint32_t gsnpsid;       /* 40 */
  93             uint32_t ghwcfg1;       /* 44 */
  94             uint32_t ghwcfg2;       /* 48 */
  95             uint32_t ghwcfg3;       /* 4c */
  96             uint32_t ghwcfg4;       /* 50 */
  97             uint32_t glpmcfg;       /* 54 */
  98             uint32_t gpwrdn;        /* 58 */
  99             uint32_t gdfifocfg;     /* 5c */
 100             uint32_t gadpctl;       /* 60 */
 101             uint32_t grefclk;       /* 64 */
 102             uint32_t gintmsk2;      /* 68 */
 103             uint32_t gintsts2;      /* 6c */
 104         };
 105     };
 106
 107     union {
 108 #define DWC2_FSZREG_SIZE    0x04
 109         uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)];
 110         struct {
 111             uint32_t hptxfsiz;      /* 100 */
 112         };
 113     };
 114
 115     union {
 116 #define DWC2_HREG0_SIZE     0x44
 117         uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)];
 118         struct {
 119             uint32_t hcfg;          /* 400 */
 120             uint32_t hfir;          /* 404 */
 121             uint32_t hfnum;         /* 408 */
 122             uint32_t rsvd0;         /* 40c */
 123             uint32_t hptxsts;       /* 410 */
 124             uint32_t haint;         /* 414 */
 125             uint32_t haintmsk;      /* 418 */
 126             uint32_t hflbaddr;      /* 41c */
 127             uint32_t rsvd1[8];      /* 420-43c */
 128             uint32_t hprt0;         /* 440 */
 129         };
 130     };
 131
 132 #define DWC2_HREG1_SIZE     (0x20 * DWC2_NB_CHAN)
 133     uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)];
 134
 135 #define hcchar(_ch)     hreg1[((_ch) << 3) + 0] /* 500, 520, ... */
 136 #define hcsplt(_ch)     hreg1[((_ch) << 3) + 1] /* 504, 524, ... */
 137 #define hcint(_ch)      hreg1[((_ch) << 3) + 2] /* 508, 528, ... */
 138 #define hcintmsk(_ch)   hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */
 139 #define hctsiz(_ch)     hreg1[((_ch) << 3) + 4] /* 510, 530, ... */
 140 #define hcdma(_ch)      hreg1[((_ch) << 3) + 5] /* 514, 534, ... */
 141 #define hcdmab(_ch)     hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */
 142
 143     union {
 144 #define DWC2_PCGREG_SIZE    0x08
 145         uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)];
 146         struct {
 147             uint32_t pcgctl;        /* e00 */
 148             uint32_t pcgcctl1;      /* e04 */
 149         };
 150     };
 151
 152     /* TODO - implement FIFO registers for slave mode */
 153 #define DWC2_HFIFO_SIZE     (0x1000 * DWC2_NB_CHAN)
 154
 155     /*
 156      *  Internal state
 157      */
 158     QEMUTimer *eof_timer;
 159     QEMUTimer *frame_timer;
 160     QEMUBH *async_bh;
 161     int64_t sof_time;
 162     int64_t usb_frame_time;
 163     int64_t usb_bit_time;
 164     uint32_t usb_version;
 165     uint16_t frame_number;
 166     uint16_t fi;
 167     uint16_t next_chan;
 168     bool working;
 169     USBPort uport;
 170     DWC2Packet packet[DWC2_NB_CHAN];                   /* one packet per chan */
 171     uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */
 172 };
 173
 174 struct DWC2Class {
 175     /*< private >*/
 176     SysBusDeviceClass parent_class;
 177     ResettablePhases parent_phases;
 178
 179     /*< public >*/
 180 };
 181
 182 #define TYPE_DWC2_USB   "dwc2-usb"
 183 #define DWC2_USB(obj) \
 184     OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB)
 185 #define DWC2_USB_CLASS(klass) \
 186     OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB)
 187 #define DWC2_USB_GET_CLASS(obj) \
 188     OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB)
 189
 190 #endif