target-microblaze/op_helper.c

   1 /*
   2  *  Microblaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <assert.h>
  22 #include "cpu.h"
  23 #include "helper.h"
  24 #include "qemu/host-utils.h"
  25
  26 #define D(x)
  27
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "exec/softmmu_exec.h"
  30
  31 #define MMUSUFFIX _mmu
  32 #define SHIFT 0
  33 #include "exec/softmmu_template.h"
  34 #define SHIFT 1
  35 #include "exec/softmmu_template.h"
  36 #define SHIFT 2
  37 #include "exec/softmmu_template.h"
  38 #define SHIFT 3
  39 #include "exec/softmmu_template.h"
  40
  41 /* Try to fill the TLB and return an exception if error. If retaddr is
  42  * NULL, it means that the function was called in C code (i.e. not
  43  * from generated code or from helper.c)
  44  */
  45 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  46               uintptr_t retaddr)
  47 {
  48     int ret;
  49
  50     ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  51     if (unlikely(ret)) {
  52         if (retaddr) {
  53             /* now we have a real cpu fault */
  54             cpu_restore_state(cs, retaddr);
  55         }
  56         cpu_loop_exit(cs);
  57     }
  58 }
  59 #endif
  60
  61 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
  62 {
  63     int test = ctrl & STREAM_TEST;
  64     int atomic = ctrl & STREAM_ATOMIC;
  65     int control = ctrl & STREAM_CONTROL;
  66     int nonblock = ctrl & STREAM_NONBLOCK;
  67     int exception = ctrl & STREAM_EXCEPTION;
  68
  69     qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
  70              id, data,
  71              test ? "t" : "",
  72              nonblock ? "n" : "",
  73              exception ? "e" : "",
  74              control ? "c" : "",
  75              atomic ? "a" : "");
  76 }
  77
  78 uint32_t helper_get(uint32_t id, uint32_t ctrl)
  79 {
  80     int test = ctrl & STREAM_TEST;
  81     int atomic = ctrl & STREAM_ATOMIC;
  82     int control = ctrl & STREAM_CONTROL;
  83     int nonblock = ctrl & STREAM_NONBLOCK;
  84     int exception = ctrl & STREAM_EXCEPTION;
  85
  86     qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
  87              id,
  88              test ? "t" : "",
  89              nonblock ? "n" : "",
  90              exception ? "e" : "",
  91              control ? "c" : "",
  92              atomic ? "a" : "");
  93     return 0xdead0000 | id;
  94 }
  95
  96 void helper_raise_exception(CPUMBState *env, uint32_t index)
  97 {
  98     CPUState *cs = CPU(mb_env_get_cpu(env));
  99
 100     cs->exception_index = index;
 101     cpu_loop_exit(cs);
 102 }
 103
 104 void helper_debug(CPUMBState *env)
 105 {
 106     int i;
 107
 108     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
 109     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
 110              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
 111              env->debug, env->imm, env->iflags);
 112     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
 113              env->btaken, env->btarget,
 114              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
 115              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
 116              (env->sregs[SR_MSR] & MSR_EIP),
 117              (env->sregs[SR_MSR] & MSR_IE));
 118     for (i = 0; i < 32; i++) {
 119         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
 120         if ((i + 1) % 4 == 0)
 121             qemu_log("\n");
 122     }
 123     qemu_log("\n\n");
 124 }
 125
 126 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
 127 {
 128     uint32_t cout = 0;
 129
 130     if ((b == ~0) && cin)
 131         cout = 1;
 132     else if ((~0 - a) < (b + cin))
 133         cout = 1;
 134     return cout;
 135 }
 136
 137 uint32_t helper_cmp(uint32_t a, uint32_t b)
 138 {
 139     uint32_t t;
 140
 141     t = b + ~a + 1;
 142     if ((b & 0x80000000) ^ (a & 0x80000000))
 143         t = (t & 0x7fffffff) | (b & 0x80000000);
 144     return t;
 145 }
 146
 147 uint32_t helper_cmpu(uint32_t a, uint32_t b)
 148 {
 149     uint32_t t;
 150
 151     t = b + ~a + 1;
 152     if ((b & 0x80000000) ^ (a & 0x80000000))
 153         t = (t & 0x7fffffff) | (a & 0x80000000);
 154     return t;
 155 }
 156
 157 uint32_t helper_clz(uint32_t t0)
 158 {
 159     return clz32(t0);
 160 }
 161
 162 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
 163 {
 164     uint32_t ncf;
 165     ncf = compute_carry(a, b, cf);
 166     return ncf;
 167 }
 168
 169 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
 170 {
 171     if (b == 0) {
 172         env->sregs[SR_MSR] |= MSR_DZ;
 173
 174         if ((env->sregs[SR_MSR] & MSR_EE)
 175             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
 176             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
 177             helper_raise_exception(env, EXCP_HW_EXCP);
 178         }
 179         return 0;
 180     }
 181     env->sregs[SR_MSR] &= ~MSR_DZ;
 182     return 1;
 183 }
 184
 185 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
 186 {
 187     if (!div_prepare(env, a, b)) {
 188         return 0;
 189     }
 190     return (int32_t)a / (int32_t)b;
 191 }
 192
 193 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
 194 {
 195     if (!div_prepare(env, a, b)) {
 196         return 0;
 197     }
 198     return a / b;
 199 }
 200
 201 /* raise FPU exception.  */
 202 static void raise_fpu_exception(CPUMBState *env)
 203 {
 204     env->sregs[SR_ESR] = ESR_EC_FPU;
 205     helper_raise_exception(env, EXCP_HW_EXCP);
 206 }
 207
 208 static void update_fpu_flags(CPUMBState *env, int flags)
 209 {
 210     int raise = 0;
 211
 212     if (flags & float_flag_invalid) {
 213         env->sregs[SR_FSR] |= FSR_IO;
 214         raise = 1;
 215     }
 216     if (flags & float_flag_divbyzero) {
 217         env->sregs[SR_FSR] |= FSR_DZ;
 218         raise = 1;
 219     }
 220     if (flags & float_flag_overflow) {
 221         env->sregs[SR_FSR] |= FSR_OF;
 222         raise = 1;
 223     }
 224     if (flags & float_flag_underflow) {
 225         env->sregs[SR_FSR] |= FSR_UF;
 226         raise = 1;
 227     }
 228     if (raise
 229         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
 230         && (env->sregs[SR_MSR] & MSR_EE)) {
 231         raise_fpu_exception(env);
 232     }
 233 }
 234
 235 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
 236 {
 237     CPU_FloatU fd, fa, fb;
 238     int flags;
 239
 240     set_float_exception_flags(0, &env->fp_status);
 241     fa.l = a;
 242     fb.l = b;
 243     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
 244
 245     flags = get_float_exception_flags(&env->fp_status);
 246     update_fpu_flags(env, flags);
 247     return fd.l;
 248 }
 249
 250 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
 251 {
 252     CPU_FloatU fd, fa, fb;
 253     int flags;
 254
 255     set_float_exception_flags(0, &env->fp_status);
 256     fa.l = a;
 257     fb.l = b;
 258     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
 259     flags = get_float_exception_flags(&env->fp_status);
 260     update_fpu_flags(env, flags);
 261     return fd.l;
 262 }
 263
 264 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
 265 {
 266     CPU_FloatU fd, fa, fb;
 267     int flags;
 268
 269     set_float_exception_flags(0, &env->fp_status);
 270     fa.l = a;
 271     fb.l = b;
 272     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
 273     flags = get_float_exception_flags(&env->fp_status);
 274     update_fpu_flags(env, flags);
 275
 276     return fd.l;
 277 }
 278
 279 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
 280 {
 281     CPU_FloatU fd, fa, fb;
 282     int flags;
 283
 284     set_float_exception_flags(0, &env->fp_status);
 285     fa.l = a;
 286     fb.l = b;
 287     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
 288     flags = get_float_exception_flags(&env->fp_status);
 289     update_fpu_flags(env, flags);
 290
 291     return fd.l;
 292 }
 293
 294 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
 295 {
 296     CPU_FloatU fa, fb;
 297     uint32_t r = 0;
 298
 299     fa.l = a;
 300     fb.l = b;
 301
 302     if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
 303         update_fpu_flags(env, float_flag_invalid);
 304         r = 1;
 305     }
 306
 307     if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
 308         r = 1;
 309     }
 310
 311     return r;
 312 }
 313
 314 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
 315 {
 316     CPU_FloatU fa, fb;
 317     int r;
 318     int flags;
 319
 320     set_float_exception_flags(0, &env->fp_status);
 321     fa.l = a;
 322     fb.l = b;
 323     r = float32_lt(fb.f, fa.f, &env->fp_status);
 324     flags = get_float_exception_flags(&env->fp_status);
 325     update_fpu_flags(env, flags & float_flag_invalid);
 326
 327     return r;
 328 }
 329
 330 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
 331 {
 332     CPU_FloatU fa, fb;
 333     int flags;
 334     int r;
 335
 336     set_float_exception_flags(0, &env->fp_status);
 337     fa.l = a;
 338     fb.l = b;
 339     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 340     flags = get_float_exception_flags(&env->fp_status);
 341     update_fpu_flags(env, flags & float_flag_invalid);
 342
 343     return r;
 344 }
 345
 346 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
 347 {
 348     CPU_FloatU fa, fb;
 349     int flags;
 350     int r;
 351
 352     fa.l = a;
 353     fb.l = b;
 354     set_float_exception_flags(0, &env->fp_status);
 355     r = float32_le(fa.f, fb.f, &env->fp_status);
 356     flags = get_float_exception_flags(&env->fp_status);
 357     update_fpu_flags(env, flags & float_flag_invalid);
 358
 359
 360     return r;
 361 }
 362
 363 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
 364 {
 365     CPU_FloatU fa, fb;
 366     int flags, r;
 367
 368     fa.l = a;
 369     fb.l = b;
 370     set_float_exception_flags(0, &env->fp_status);
 371     r = float32_lt(fa.f, fb.f, &env->fp_status);
 372     flags = get_float_exception_flags(&env->fp_status);
 373     update_fpu_flags(env, flags & float_flag_invalid);
 374     return r;
 375 }
 376
 377 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
 378 {
 379     CPU_FloatU fa, fb;
 380     int flags, r;
 381
 382     fa.l = a;
 383     fb.l = b;
 384     set_float_exception_flags(0, &env->fp_status);
 385     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 386     flags = get_float_exception_flags(&env->fp_status);
 387     update_fpu_flags(env, flags & float_flag_invalid);
 388
 389     return r;
 390 }
 391
 392 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
 393 {
 394     CPU_FloatU fa, fb;
 395     int flags, r;
 396
 397     fa.l = a;
 398     fb.l = b;
 399     set_float_exception_flags(0, &env->fp_status);
 400     r = !float32_lt(fa.f, fb.f, &env->fp_status);
 401     flags = get_float_exception_flags(&env->fp_status);
 402     update_fpu_flags(env, flags & float_flag_invalid);
 403
 404     return r;
 405 }
 406
 407 uint32_t helper_flt(CPUMBState *env, uint32_t a)
 408 {
 409     CPU_FloatU fd, fa;
 410
 411     fa.l = a;
 412     fd.f = int32_to_float32(fa.l, &env->fp_status);
 413     return fd.l;
 414 }
 415
 416 uint32_t helper_fint(CPUMBState *env, uint32_t a)
 417 {
 418     CPU_FloatU fa;
 419     uint32_t r;
 420     int flags;
 421
 422     set_float_exception_flags(0, &env->fp_status);
 423     fa.l = a;
 424     r = float32_to_int32(fa.f, &env->fp_status);
 425     flags = get_float_exception_flags(&env->fp_status);
 426     update_fpu_flags(env, flags);
 427
 428     return r;
 429 }
 430
 431 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
 432 {
 433     CPU_FloatU fd, fa;
 434     int flags;
 435
 436     set_float_exception_flags(0, &env->fp_status);
 437     fa.l = a;
 438     fd.l = float32_sqrt(fa.f, &env->fp_status);
 439     flags = get_float_exception_flags(&env->fp_status);
 440     update_fpu_flags(env, flags);
 441
 442     return fd.l;
 443 }
 444
 445 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
 446 {
 447     unsigned int i;
 448     uint32_t mask = 0xff000000;
 449
 450     for (i = 0; i < 4; i++) {
 451         if ((a & mask) == (b & mask))
 452             return i + 1;
 453         mask >>= 8;
 454     }
 455     return 0;
 456 }
 457
 458 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
 459                      uint32_t mask)
 460 {
 461     if (addr & mask) {
 462             qemu_log_mask(CPU_LOG_INT,
 463                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
 464                           addr, mask, wr, dr);
 465             env->sregs[SR_EAR] = addr;
 466             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
 467                                  | (dr & 31) << 5;
 468             if (mask == 3) {
 469                 env->sregs[SR_ESR] |= 1 << 11;
 470             }
 471             if (!(env->sregs[SR_MSR] & MSR_EE)) {
 472                 return;
 473             }
 474             helper_raise_exception(env, EXCP_HW_EXCP);
 475     }
 476 }
 477
 478 void helper_stackprot(CPUMBState *env, uint32_t addr)
 479 {
 480     if (addr < env->slr || addr > env->shr) {
 481             qemu_log("Stack protector violation at %x %x %x\n",
 482                      addr, env->slr, env->shr);
 483             env->sregs[SR_EAR] = addr;
 484             env->sregs[SR_ESR] = ESR_EC_STACKPROT;
 485             helper_raise_exception(env, EXCP_HW_EXCP);
 486     }
 487 }
 488
 489 #if !defined(CONFIG_USER_ONLY)
 490 /* Writes/reads to the MMU's special regs end up here.  */
 491 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
 492 {
 493     return mmu_read(env, rn);
 494 }
 495
 496 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
 497 {
 498     mmu_write(env, rn, v);
 499 }
 500
 501 void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 502                               bool is_write, bool is_exec, int is_asi,
 503                               unsigned size)
 504 {
 505     MicroBlazeCPU *cpu;
 506     CPUMBState *env;
 507
 508     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
 509              addr, is_write ? 1 : 0, is_exec ? 1 : 0);
 510     if (cs == NULL) {
 511         return;
 512     }
 513     cpu = MICROBLAZE_CPU(cs);
 514     env = &cpu->env;
 515     if (!(env->sregs[SR_MSR] & MSR_EE)) {
 516         return;
 517     }
 518
 519     env->sregs[SR_EAR] = addr;
 520     if (is_exec) {
 521         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
 522             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
 523             helper_raise_exception(env, EXCP_HW_EXCP);
 524         }
 525     } else {
 526         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
 527             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
 528             helper_raise_exception(env, EXCP_HW_EXCP);
 529         }
 530     }
 531 }
 532 #endif