target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "cpu.h"
  21 #include "helper.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_ppc.h"
  24 #include "mmu-hash64.h"
  25
  26 //#define DEBUG_MMU
  27 //#define DEBUG_SLB
  28
  29 #ifdef DEBUG_MMU
  30 #  define LOG_MMU(...) qemu_log(__VA_ARGS__)
  31 #  define LOG_MMU_STATE(env) log_cpu_state((env), 0)
  32 #else
  33 #  define LOG_MMU(...) do { } while (0)
  34 #  define LOG_MMU_STATE(...) do { } while (0)
  35 #endif
  36
  37 #ifdef DEBUG_SLB
  38 #  define LOG_SLB(...) qemu_log(__VA_ARGS__)
  39 #else
  40 #  define LOG_SLB(...) do { } while (0)
  41 #endif
  42
  43 struct mmu_ctx_hash64 {
  44     hwaddr raddr;      /* Real address              */
  45     int prot;                      /* Protection bits           */
  46     int key;                       /* Access key                */
  47 };
  48
  49 /*
  50  * SLB handling
  51  */
  52
  53 static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
  54 {
  55     uint64_t esid_256M, esid_1T;
  56     int n;
  57
  58     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  59
  60     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  61     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  62
  63     for (n = 0; n < env->slb_nr; n++) {
  64         ppc_slb_t *slb = &env->slb[n];
  65
  66         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  67                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  68         /* We check for 1T matches on all MMUs here - if the MMU
  69          * doesn't have 1T segment support, we will have prevented 1T
  70          * entries from being inserted in the slbmte code. */
  71         if (((slb->esid == esid_256M) &&
  72              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  73             || ((slb->esid == esid_1T) &&
  74                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  75             return slb;
  76         }
  77     }
  78
  79     return NULL;
  80 }
  81
  82 void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
  83 {
  84     int i;
  85     uint64_t slbe, slbv;
  86
  87     cpu_synchronize_state(env);
  88
  89     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  90     for (i = 0; i < env->slb_nr; i++) {
  91         slbe = env->slb[i].esid;
  92         slbv = env->slb[i].vsid;
  93         if (slbe == 0 && slbv == 0) {
  94             continue;
  95         }
  96         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
  97                     i, slbe, slbv);
  98     }
  99 }
 100
 101 void helper_slbia(CPUPPCState *env)
 102 {
 103     int n, do_invalidate;
 104
 105     do_invalidate = 0;
 106     /* XXX: Warning: slbia never invalidates the first segment */
 107     for (n = 1; n < env->slb_nr; n++) {
 108         ppc_slb_t *slb = &env->slb[n];
 109
 110         if (slb->esid & SLB_ESID_V) {
 111             slb->esid &= ~SLB_ESID_V;
 112             /* XXX: given the fact that segment size is 256 MB or 1TB,
 113              *      and we still don't have a tlb_flush_mask(env, n, mask)
 114              *      in QEMU, we just invalidate all TLBs
 115              */
 116             do_invalidate = 1;
 117         }
 118     }
 119     if (do_invalidate) {
 120         tlb_flush(env, 1);
 121     }
 122 }
 123
 124 void helper_slbie(CPUPPCState *env, target_ulong addr)
 125 {
 126     ppc_slb_t *slb;
 127
 128     slb = slb_lookup(env, addr);
 129     if (!slb) {
 130         return;
 131     }
 132
 133     if (slb->esid & SLB_ESID_V) {
 134         slb->esid &= ~SLB_ESID_V;
 135
 136         /* XXX: given the fact that segment size is 256 MB or 1TB,
 137          *      and we still don't have a tlb_flush_mask(env, n, mask)
 138          *      in QEMU, we just invalidate all TLBs
 139          */
 140         tlb_flush(env, 1);
 141     }
 142 }
 143
 144 int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 145 {
 146     int slot = rb & 0xfff;
 147     ppc_slb_t *slb = &env->slb[slot];
 148
 149     if (rb & (0x1000 - env->slb_nr)) {
 150         return -1; /* Reserved bits set or slot too high */
 151     }
 152     if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 153         return -1; /* Bad segment size */
 154     }
 155     if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 156         return -1; /* 1T segment on MMU that doesn't support it */
 157     }
 158
 159     /* Mask out the slot number as we store the entry */
 160     slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
 161     slb->vsid = rs;
 162
 163     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 164             " %016" PRIx64 "\n", __func__, slot, rb, rs,
 165             slb->esid, slb->vsid);
 166
 167     return 0;
 168 }
 169
 170 static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
 171                              target_ulong *rt)
 172 {
 173     int slot = rb & 0xfff;
 174     ppc_slb_t *slb = &env->slb[slot];
 175
 176     if (slot >= env->slb_nr) {
 177         return -1;
 178     }
 179
 180     *rt = slb->esid;
 181     return 0;
 182 }
 183
 184 static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
 185                              target_ulong *rt)
 186 {
 187     int slot = rb & 0xfff;
 188     ppc_slb_t *slb = &env->slb[slot];
 189
 190     if (slot >= env->slb_nr) {
 191         return -1;
 192     }
 193
 194     *rt = slb->vsid;
 195     return 0;
 196 }
 197
 198 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 199 {
 200     if (ppc_store_slb(env, rb, rs) < 0) {
 201         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 202                                    POWERPC_EXCP_INVAL);
 203     }
 204 }
 205
 206 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 207 {
 208     target_ulong rt = 0;
 209
 210     if (ppc_load_slb_esid(env, rb, &rt) < 0) {
 211         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 212                                    POWERPC_EXCP_INVAL);
 213     }
 214     return rt;
 215 }
 216
 217 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 218 {
 219     target_ulong rt = 0;
 220
 221     if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
 222         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 223                                    POWERPC_EXCP_INVAL);
 224     }
 225     return rt;
 226 }
 227
 228 /*
 229  * 64-bit hash table MMU handling
 230  */
 231
 232 static int ppc_hash64_pp_check(int key, int pp, bool nx)
 233 {
 234     int access;
 235
 236     /* Compute access rights */
 237     /* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
 238     access = 0;
 239     if (key == 0) {
 240         switch (pp) {
 241         case 0x0:
 242         case 0x1:
 243         case 0x2:
 244             access |= PAGE_WRITE;
 245             /* No break here */
 246         case 0x3:
 247         case 0x6:
 248             access |= PAGE_READ;
 249             break;
 250         }
 251     } else {
 252         switch (pp) {
 253         case 0x0:
 254         case 0x6:
 255             access = 0;
 256             break;
 257         case 0x1:
 258         case 0x3:
 259             access = PAGE_READ;
 260             break;
 261         case 0x2:
 262             access = PAGE_READ | PAGE_WRITE;
 263             break;
 264         }
 265     }
 266     if (!nx) {
 267         access |= PAGE_EXEC;
 268     }
 269
 270     return access;
 271 }
 272
 273 static int ppc_hash64_check_prot(int prot, int rwx)
 274 {
 275     int ret;
 276
 277     if (rwx == 2) {
 278         if (prot & PAGE_EXEC) {
 279             ret = 0;
 280         } else {
 281             ret = -2;
 282         }
 283     } else if (rwx == 1) {
 284         if (prot & PAGE_WRITE) {
 285             ret = 0;
 286         } else {
 287             ret = -2;
 288         }
 289     } else {
 290         if (prot & PAGE_READ) {
 291             ret = 0;
 292         } else {
 293             ret = -2;
 294         }
 295     }
 296
 297     return ret;
 298 }
 299
 300 static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
 301                                        uint64_t *pte1p, int ret, int rw)
 302 {
 303     int store = 0;
 304
 305     /* Update page flags */
 306     if (!(*pte1p & HPTE64_R_R)) {
 307         /* Update accessed flag */
 308         *pte1p |= HPTE64_R_R;
 309         store = 1;
 310     }
 311     if (!(*pte1p & HPTE64_R_C)) {
 312         if (rw == 1 && ret == 0) {
 313             /* Update changed flag */
 314             *pte1p |= HPTE64_R_C;
 315             store = 1;
 316         } else {
 317             /* Force page fault for first write access */
 318             ctx->prot &= ~PAGE_WRITE;
 319         }
 320     }
 321
 322     return store;
 323 }
 324
 325 static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr pteg_off,
 326                                      bool secondary, target_ulong ptem,
 327                                      ppc_hash_pte64_t *pte)
 328 {
 329     hwaddr pte_offset = pteg_off;
 330     target_ulong pte0, pte1;
 331     int i;
 332
 333     for (i = 0; i < HPTES_PER_GROUP; i++) {
 334         pte0 = ppc_hash64_load_hpte0(env, pte_offset);
 335         pte1 = ppc_hash64_load_hpte1(env, pte_offset);
 336
 337         if ((pte0 & HPTE64_V_VALID)
 338             && (secondary == !!(pte0 & HPTE64_V_SECONDARY))
 339             && HPTE64_V_COMPARE(pte0, ptem)) {
 340             pte->pte0 = pte0;
 341             pte->pte1 = pte1;
 342             return pte_offset;
 343         }
 344
 345         pte_offset += HASH_PTE_SIZE_64;
 346     }
 347
 348     return -1;
 349 }
 350
 351 static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
 352                                      ppc_slb_t *slb, target_ulong eaddr,
 353                                      ppc_hash_pte64_t *pte)
 354 {
 355     hwaddr pteg_off, pte_offset;
 356     hwaddr hash;
 357     uint64_t vsid, epnshift, epnmask, epn, ptem;
 358
 359     /* Page size according to the SLB, which we use to generate the
 360      * EPN for hash table lookup..  When we implement more recent MMU
 361      * extensions this might be different from the actual page size
 362      * encoded in the PTE */
 363     epnshift = (slb->vsid & SLB_VSID_L)
 364         ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
 365     epnmask = ~((1ULL << epnshift) - 1);
 366
 367     if (slb->vsid & SLB_VSID_B) {
 368         /* 1TB segment */
 369         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 370         epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
 371         hash = vsid ^ (vsid << 25) ^ (epn >> epnshift);
 372     } else {
 373         /* 256M segment */
 374         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 375         epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
 376         hash = vsid ^ (epn >> epnshift);
 377     }
 378     ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
 379
 380     /* Page address translation */
 381     LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 382             " hash " TARGET_FMT_plx "\n",
 383             env->htab_base, env->htab_mask, hash);
 384
 385     /* Primary PTEG lookup */
 386     LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 387             " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 388             " hash=" TARGET_FMT_plx "\n",
 389             env->htab_base, env->htab_mask, vsid, ptem,  hash);
 390     pteg_off = (hash * HASH_PTEG_SIZE_64) & env->htab_mask;
 391     pte_offset = ppc_hash64_pteg_search(env, pteg_off, 0, ptem, pte);
 392
 393     if (pte_offset == -1) {
 394         /* Secondary PTEG lookup */
 395         LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 396                 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 397                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 398                 env->htab_mask, vsid, ptem, ~hash);
 399
 400         pteg_off = (~hash * HASH_PTEG_SIZE_64) & env->htab_mask;
 401         pte_offset = ppc_hash64_pteg_search(env, pteg_off, 1, ptem, pte);
 402     }
 403
 404     return pte_offset;
 405 }
 406
 407 static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
 408                                 target_ulong eaddr, int rwx)
 409 {
 410     int ret;
 411     ppc_slb_t *slb;
 412     hwaddr pte_offset;
 413     ppc_hash_pte64_t pte;
 414     int target_page_bits;
 415
 416     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 417
 418     /* 1. Handle real mode accesses */
 419     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 420         /* Translation is off */
 421         /* In real mode the top 4 effective address bits are ignored */
 422         ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 423         ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
 424         return 0;
 425     }
 426
 427     /* 2. Translation is on, so look up the SLB */
 428     slb = slb_lookup(env, eaddr);
 429
 430     if (!slb) {
 431         return -5;
 432     }
 433
 434     /* 3. Check for segment level no-execute violation */
 435     if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
 436         return -3;
 437     }
 438
 439     /* 4. Locate the PTE in the hash table */
 440     pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
 441     if (pte_offset == -1) {
 442         return -1;
 443     }
 444     LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
 445
 446     /* 5. Check access permissions */
 447     ctx->key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
 448                   : (slb->vsid & SLB_VSID_KS));
 449
 450
 451     int access, pp;
 452     bool nx;
 453
 454     pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
 455     /* No execute if either noexec or guarded bits set */
 456     nx = (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G);
 457     /* Compute access rights */
 458     access = ppc_hash64_pp_check(ctx->key, pp, nx);
 459     /* Keep the matching PTE informations */
 460     ctx->raddr = pte.pte1;
 461     ctx->prot = access;
 462     ret = ppc_hash64_check_prot(ctx->prot, rwx);
 463
 464     if (ret) {
 465         /* Access right violation */
 466         LOG_MMU("PTE access rejected\n");
 467         return ret;
 468     }
 469
 470     LOG_MMU("PTE access granted !\n");
 471
 472     /* 6. Update PTE referenced and changed bits if necessary */
 473
 474     if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
 475         ppc_hash64_store_hpte1(env, pte_offset, pte.pte1);
 476     }
 477
 478     /* We have a TLB that saves 4K pages, so let's
 479      * split a huge page to 4k chunks */
 480     target_page_bits = (slb->vsid & SLB_VSID_L)
 481         ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
 482     if (target_page_bits != TARGET_PAGE_BITS) {
 483         ctx->raddr |= (eaddr & ((1 << target_page_bits) - 1))
 484                       & TARGET_PAGE_MASK;
 485     }
 486     return ret;
 487 }
 488
 489 hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
 490 {
 491     struct mmu_ctx_hash64 ctx;
 492
 493     if (unlikely(ppc_hash64_translate(env, &ctx, addr, 0) != 0)) {
 494         return -1;
 495     }
 496
 497     return ctx.raddr & TARGET_PAGE_MASK;
 498 }
 499
 500 int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx,
 501                                 int mmu_idx)
 502 {
 503     struct mmu_ctx_hash64 ctx;
 504     int ret = 0;
 505
 506     ret = ppc_hash64_translate(env, &ctx, address, rwx);
 507     if (ret == 0) {
 508         tlb_set_page(env, address & TARGET_PAGE_MASK,
 509                      ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
 510                      mmu_idx, TARGET_PAGE_SIZE);
 511         ret = 0;
 512     } else if (ret < 0) {
 513         LOG_MMU_STATE(env);
 514         if (rwx == 2) {
 515             switch (ret) {
 516             case -1:
 517                 env->exception_index = POWERPC_EXCP_ISI;
 518                 env->error_code = 0x40000000;
 519                 break;
 520             case -2:
 521                 /* Access rights violation */
 522                 env->exception_index = POWERPC_EXCP_ISI;
 523                 env->error_code = 0x08000000;
 524                 break;
 525             case -3:
 526                 /* No execute protection violation */
 527                 env->exception_index = POWERPC_EXCP_ISI;
 528                 env->error_code = 0x10000000;
 529                 break;
 530             case -5:
 531                 /* No match in segment table */
 532                 env->exception_index = POWERPC_EXCP_ISEG;
 533                 env->error_code = 0;
 534                 break;
 535             }
 536         } else {
 537             switch (ret) {
 538             case -1:
 539                 /* No matches in page tables or TLB */
 540                 env->exception_index = POWERPC_EXCP_DSI;
 541                 env->error_code = 0;
 542                 env->spr[SPR_DAR] = address;
 543                 if (rwx == 1) {
 544                     env->spr[SPR_DSISR] = 0x42000000;
 545                 } else {
 546                     env->spr[SPR_DSISR] = 0x40000000;
 547                 }
 548                 break;
 549             case -2:
 550                 /* Access rights violation */
 551                 env->exception_index = POWERPC_EXCP_DSI;
 552                 env->error_code = 0;
 553                 env->spr[SPR_DAR] = address;
 554                 if (rwx == 1) {
 555                     env->spr[SPR_DSISR] = 0x0A000000;
 556                 } else {
 557                     env->spr[SPR_DSISR] = 0x08000000;
 558                 }
 559                 break;
 560             case -5:
 561                 /* No match in segment table */
 562                 env->exception_index = POWERPC_EXCP_DSEG;
 563                 env->error_code = 0;
 564                 env->spr[SPR_DAR] = address;
 565                 break;
 566             }
 567         }
 568 #if 0
 569         printf("%s: set exception to %d %02x\n", __func__,
 570                env->exception, env->error_code);
 571 #endif
 572         ret = 1;
 573     }
 574
 575     return ret;
 576 }