hw/openpic.c

   1 /*
   2  * OpenPIC emulation
   3  *
   4  * Copyright (c) 2004 Jocelyn Mayer
   5  *               2011 Alexander Graf
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 /*
  26  *
  27  * Based on OpenPic implementations:
  28  * - Intel GW80314 I/O companion chip developer's manual
  29  * - Motorola MPC8245 & MPC8540 user manuals.
  30  * - Motorola MCP750 (aka Raven) programmer manual.
  31  * - Motorola Harrier programmer manuel
  32  *
  33  * Serial interrupts, as implemented in Raven chipset are not supported yet.
  34  *
  35  */
  36 #include "hw.h"
  37 #include "ppc_mac.h"
  38 #include "pci/pci.h"
  39 #include "openpic.h"
  40 #include "sysbus.h"
  41 #include "pci/msi.h"
  42
  43 //#define DEBUG_OPENPIC
  44
  45 #ifdef DEBUG_OPENPIC
  46 #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
  47 #else
  48 #define DPRINTF(fmt, ...) do { } while (0)
  49 #endif
  50
  51 #define MAX_CPU     15
  52 #define MAX_SRC     256
  53 #define MAX_TMR     4
  54 #define VECTOR_BITS 8
  55 #define MAX_IPI     4
  56 #define MAX_MSI     8
  57 #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
  58 #define VID         0x03 /* MPIC version ID */
  59
  60 /* OpenPIC capability flags */
  61 #define OPENPIC_FLAG_IDE_CRIT     (1 << 0)
  62
  63 /* OpenPIC address map */
  64 #define OPENPIC_GLB_REG_START        0x0
  65 #define OPENPIC_GLB_REG_SIZE         0x10F0
  66 #define OPENPIC_TMR_REG_START        0x10F0
  67 #define OPENPIC_TMR_REG_SIZE         0x220
  68 #define OPENPIC_MSI_REG_START        0x1600
  69 #define OPENPIC_MSI_REG_SIZE         0x200
  70 #define OPENPIC_SRC_REG_START        0x10000
  71 #define OPENPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
  72 #define OPENPIC_CPU_REG_START        0x20000
  73 #define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
  74
  75 /* Raven */
  76 #define RAVEN_MAX_CPU      2
  77 #define RAVEN_MAX_EXT     48
  78 #define RAVEN_MAX_IRQ     64
  79 #define RAVEN_MAX_TMR      MAX_TMR
  80 #define RAVEN_MAX_IPI      MAX_IPI
  81
  82 /* Interrupt definitions */
  83 #define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
  84 #define RAVEN_ERR_IRQ    (RAVEN_MAX_EXT + 1) /* Error IRQ */
  85 #define RAVEN_TMR_IRQ    (RAVEN_MAX_EXT + 2) /* First timer IRQ */
  86 #define RAVEN_IPI_IRQ    (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
  87 /* First doorbell IRQ */
  88 #define RAVEN_DBL_IRQ    (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
  89
  90 /* FSL_MPIC_20 */
  91 #define FSL_MPIC_20_MAX_CPU      1
  92 #define FSL_MPIC_20_MAX_EXT     12
  93 #define FSL_MPIC_20_MAX_INT     64
  94 #define FSL_MPIC_20_MAX_IRQ     MAX_IRQ
  95
  96 /* Interrupt definitions */
  97 /* IRQs, accessible through the IRQ region */
  98 #define FSL_MPIC_20_EXT_IRQ      0x00
  99 #define FSL_MPIC_20_INT_IRQ      0x10
 100 #define FSL_MPIC_20_MSG_IRQ      0xb0
 101 #define FSL_MPIC_20_MSI_IRQ      0xe0
 102 /* These are available through separate regions, but
 103    for simplicity's sake mapped into the same number space */
 104 #define FSL_MPIC_20_TMR_IRQ      0x100
 105 #define FSL_MPIC_20_IPI_IRQ      0x104
 106
 107 /*
 108  * Block Revision Register1 (BRR1): QEMU does not fully emulate
 109  * any version on MPIC. So to start with, set the IP version to 0.
 110  *
 111  * NOTE: This is Freescale MPIC specific register. Keep it here till
 112  * this code is refactored for different variants of OPENPIC and MPIC.
 113  */
 114 #define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */
 115 #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */
 116 #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
 117
 118 #define FREP_NIRQ_SHIFT   16
 119 #define FREP_NCPU_SHIFT    8
 120 #define FREP_VID_SHIFT     0
 121
 122 #define VID_REVISION_1_2   2
 123 #define VID_REVISION_1_3   3
 124
 125 #define VENI_GENERIC      0x00000000 /* Generic Vendor ID */
 126
 127 #define IDR_EP_SHIFT      31
 128 #define IDR_EP_MASK       (1 << IDR_EP_SHIFT)
 129 #define IDR_CI0_SHIFT     30
 130 #define IDR_CI1_SHIFT     29
 131 #define IDR_P1_SHIFT      1
 132 #define IDR_P0_SHIFT      0
 133
 134 #define MSIIR_OFFSET       0x140
 135 #define MSIIR_SRS_SHIFT    29
 136 #define MSIIR_SRS_MASK     (0x7 << MSIIR_SRS_SHIFT)
 137 #define MSIIR_IBS_SHIFT    24
 138 #define MSIIR_IBS_MASK     (0x1f << MSIIR_IBS_SHIFT)
 139
 140 #define BF_WIDTH(_bits_) \
 141 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
 142
 143 static inline void set_bit(uint32_t *field, int bit)
 144 {
 145     field[bit >> 5] |= 1 << (bit & 0x1F);
 146 }
 147
 148 static inline void reset_bit(uint32_t *field, int bit)
 149 {
 150     field[bit >> 5] &= ~(1 << (bit & 0x1F));
 151 }
 152
 153 static inline int test_bit(uint32_t *field, int bit)
 154 {
 155     return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
 156 }
 157
 158 static int get_current_cpu(void)
 159 {
 160   return cpu_single_env->cpu_index;
 161 }
 162
 163 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
 164                                           int idx);
 165 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
 166                                        uint32_t val, int idx);
 167
 168 typedef struct IRQ_queue_t {
 169     uint32_t queue[BF_WIDTH(MAX_IRQ)];
 170     int next;
 171     int priority;
 172     int pending;    /* nr of pending bits in queue */
 173 } IRQ_queue_t;
 174
 175 typedef struct IRQ_src_t {
 176     uint32_t ipvp;  /* IRQ vector/priority register */
 177     uint32_t ide;   /* IRQ destination register */
 178     int last_cpu;
 179     int pending;    /* TRUE if IRQ is pending */
 180 } IRQ_src_t;
 181
 182 #define IPVP_MASK_SHIFT       31
 183 #define IPVP_MASK_MASK        (1 << IPVP_MASK_SHIFT)
 184 #define IPVP_ACTIVITY_SHIFT   30
 185 #define IPVP_ACTIVITY_MASK    (1 << IPVP_ACTIVITY_SHIFT)
 186 #define IPVP_MODE_SHIFT       29
 187 #define IPVP_MODE_MASK        (1 << IPVP_MODE_SHIFT)
 188 #define IPVP_POLARITY_SHIFT   23
 189 #define IPVP_POLARITY_MASK    (1 << IPVP_POLARITY_SHIFT)
 190 #define IPVP_SENSE_SHIFT      22
 191 #define IPVP_SENSE_MASK       (1 << IPVP_SENSE_SHIFT)
 192
 193 #define IPVP_PRIORITY_MASK     (0x1F << 16)
 194 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
 195 #define IPVP_VECTOR_MASK       ((1 << VECTOR_BITS) - 1)
 196 #define IPVP_VECTOR(_ipvpr_)   ((_ipvpr_) & IPVP_VECTOR_MASK)
 197
 198 typedef struct IRQ_dst_t {
 199     uint32_t pctp; /* CPU current task priority */
 200     uint32_t pcsr; /* CPU sensitivity register */
 201     IRQ_queue_t raised;
 202     IRQ_queue_t servicing;
 203     qemu_irq *irqs;
 204 } IRQ_dst_t;
 205
 206 typedef struct OpenPICState {
 207     SysBusDevice busdev;
 208     MemoryRegion mem;
 209
 210     /* Behavior control */
 211     uint32_t model;
 212     uint32_t flags;
 213     uint32_t nb_irqs;
 214     uint32_t vid;
 215     uint32_t veni; /* Vendor identification register */
 216     uint32_t spve_mask;
 217     uint32_t tifr_reset;
 218     uint32_t ipvp_reset;
 219     uint32_t ide_reset;
 220     uint32_t brr1;
 221
 222     /* Sub-regions */
 223     MemoryRegion sub_io_mem[5];
 224
 225     /* Global registers */
 226     uint32_t frep; /* Feature reporting register */
 227     uint32_t glbc; /* Global configuration register  */
 228     uint32_t pint; /* Processor initialization register */
 229     uint32_t spve; /* Spurious vector register */
 230     uint32_t tifr; /* Timer frequency reporting register */
 231     /* Source registers */
 232     IRQ_src_t src[MAX_IRQ];
 233     /* Local registers per output pin */
 234     IRQ_dst_t dst[MAX_CPU];
 235     uint32_t nb_cpus;
 236     /* Timer registers */
 237     struct {
 238         uint32_t ticc;  /* Global timer current count register */
 239         uint32_t tibc;  /* Global timer base count register */
 240     } timers[MAX_TMR];
 241     /* Shared MSI registers */
 242     struct {
 243         uint32_t msir;   /* Shared Message Signaled Interrupt Register */
 244     } msi[MAX_MSI];
 245     uint32_t max_irq;
 246     uint32_t irq_ipi0;
 247     uint32_t irq_tim0;
 248     uint32_t irq_msi;
 249 } OpenPICState;
 250
 251 static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
 252
 253 static inline void IRQ_setbit(IRQ_queue_t *q, int n_IRQ)
 254 {
 255     q->pending++;
 256     set_bit(q->queue, n_IRQ);
 257 }
 258
 259 static inline void IRQ_resetbit(IRQ_queue_t *q, int n_IRQ)
 260 {
 261     q->pending--;
 262     reset_bit(q->queue, n_IRQ);
 263 }
 264
 265 static inline int IRQ_testbit(IRQ_queue_t *q, int n_IRQ)
 266 {
 267     return test_bit(q->queue, n_IRQ);
 268 }
 269
 270 static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
 271 {
 272     int next, i;
 273     int priority;
 274
 275     next = -1;
 276     priority = -1;
 277
 278     if (!q->pending) {
 279         /* IRQ bitmap is empty */
 280         goto out;
 281     }
 282
 283     for (i = 0; i < opp->max_irq; i++) {
 284         if (IRQ_testbit(q, i)) {
 285             DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
 286                     i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
 287             if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
 288                 next = i;
 289                 priority = IPVP_PRIORITY(opp->src[i].ipvp);
 290             }
 291         }
 292     }
 293
 294 out:
 295     q->next = next;
 296     q->priority = priority;
 297 }
 298
 299 static int IRQ_get_next(OpenPICState *opp, IRQ_queue_t *q)
 300 {
 301     if (q->next == -1) {
 302         /* XXX: optimize */
 303         IRQ_check(opp, q);
 304     }
 305
 306     return q->next;
 307 }
 308
 309 static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ)
 310 {
 311     IRQ_dst_t *dst;
 312     IRQ_src_t *src;
 313     int priority;
 314
 315     dst = &opp->dst[n_CPU];
 316     src = &opp->src[n_IRQ];
 317     priority = IPVP_PRIORITY(src->ipvp);
 318     if (priority <= dst->pctp) {
 319         /* Too low priority */
 320         DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
 321                 __func__, n_IRQ, n_CPU);
 322         return;
 323     }
 324     if (IRQ_testbit(&dst->raised, n_IRQ)) {
 325         /* Interrupt miss */
 326         DPRINTF("%s: IRQ %d was missed on CPU %d\n",
 327                 __func__, n_IRQ, n_CPU);
 328         return;
 329     }
 330     src->ipvp |= IPVP_ACTIVITY_MASK;
 331     IRQ_setbit(&dst->raised, n_IRQ);
 332     if (priority < dst->raised.priority) {
 333         /* An higher priority IRQ is already raised */
 334         DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
 335                 __func__, n_IRQ, dst->raised.next, n_CPU);
 336         return;
 337     }
 338     IRQ_get_next(opp, &dst->raised);
 339     if (IRQ_get_next(opp, &dst->servicing) != -1 &&
 340         priority <= dst->servicing.priority) {
 341         DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
 342                 __func__, n_IRQ, dst->servicing.next, n_CPU);
 343         /* Already servicing a higher priority IRQ */
 344         return;
 345     }
 346     DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
 347     openpic_irq_raise(opp, n_CPU, src);
 348 }
 349
 350 /* update pic state because registers for n_IRQ have changed value */
 351 static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
 352 {
 353     IRQ_src_t *src;
 354     int i;
 355
 356     src = &opp->src[n_IRQ];
 357
 358     if (!src->pending) {
 359         /* no irq pending */
 360         DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
 361         return;
 362     }
 363     if (src->ipvp & IPVP_MASK_MASK) {
 364         /* Interrupt source is disabled */
 365         DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
 366         return;
 367     }
 368     if (IPVP_PRIORITY(src->ipvp) == 0) {
 369         /* Priority set to zero */
 370         DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
 371         return;
 372     }
 373     if (src->ipvp & IPVP_ACTIVITY_MASK) {
 374         /* IRQ already active */
 375         DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
 376         return;
 377     }
 378     if (src->ide == 0x00000000) {
 379         /* No target */
 380         DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
 381         return;
 382     }
 383
 384     if (src->ide == (1 << src->last_cpu)) {
 385         /* Only one CPU is allowed to receive this IRQ */
 386         IRQ_local_pipe(opp, src->last_cpu, n_IRQ);
 387     } else if (!(src->ipvp & IPVP_MODE_MASK)) {
 388         /* Directed delivery mode */
 389         for (i = 0; i < opp->nb_cpus; i++) {
 390             if (src->ide & (1 << i)) {
 391                 IRQ_local_pipe(opp, i, n_IRQ);
 392             }
 393         }
 394     } else {
 395         /* Distributed delivery mode */
 396         for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
 397             if (i == opp->nb_cpus)
 398                 i = 0;
 399             if (src->ide & (1 << i)) {
 400                 IRQ_local_pipe(opp, i, n_IRQ);
 401                 src->last_cpu = i;
 402                 break;
 403             }
 404         }
 405     }
 406 }
 407
 408 static void openpic_set_irq(void *opaque, int n_IRQ, int level)
 409 {
 410     OpenPICState *opp = opaque;
 411     IRQ_src_t *src;
 412
 413     src = &opp->src[n_IRQ];
 414     DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
 415             n_IRQ, level, src->ipvp);
 416     if (src->ipvp & IPVP_SENSE_MASK) {
 417         /* level-sensitive irq */
 418         src->pending = level;
 419         if (!level) {
 420             src->ipvp &= ~IPVP_ACTIVITY_MASK;
 421         }
 422     } else {
 423         /* edge-sensitive irq */
 424         if (level)
 425             src->pending = 1;
 426     }
 427     openpic_update_irq(opp, n_IRQ);
 428 }
 429
 430 static void openpic_reset(DeviceState *d)
 431 {
 432     OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d));
 433     int i;
 434
 435     opp->glbc = 0x80000000;
 436     /* Initialise controller registers */
 437     opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) |
 438                 ((opp->nb_cpus -1) << FREP_NCPU_SHIFT) |
 439                 (opp->vid << FREP_VID_SHIFT);
 440
 441     opp->pint = 0x00000000;
 442     opp->spve = -1 & opp->spve_mask;
 443     opp->tifr = opp->tifr_reset;
 444     /* Initialise IRQ sources */
 445     for (i = 0; i < opp->max_irq; i++) {
 446         opp->src[i].ipvp = opp->ipvp_reset;
 447         opp->src[i].ide  = opp->ide_reset;
 448     }
 449     /* Initialise IRQ destinations */
 450     for (i = 0; i < MAX_CPU; i++) {
 451         opp->dst[i].pctp      = 0x0000000F;
 452         opp->dst[i].pcsr      = 0x00000000;
 453         memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
 454         opp->dst[i].raised.next = -1;
 455         memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
 456         opp->dst[i].servicing.next = -1;
 457     }
 458     /* Initialise timers */
 459     for (i = 0; i < MAX_TMR; i++) {
 460         opp->timers[i].ticc = 0x00000000;
 461         opp->timers[i].tibc = 0x80000000;
 462     }
 463     /* Go out of RESET state */
 464     opp->glbc = 0x00000000;
 465 }
 466
 467 static inline uint32_t read_IRQreg_ide(OpenPICState *opp, int n_IRQ)
 468 {
 469     return opp->src[n_IRQ].ide;
 470 }
 471
 472 static inline uint32_t read_IRQreg_ipvp(OpenPICState *opp, int n_IRQ)
 473 {
 474     return opp->src[n_IRQ].ipvp;
 475 }
 476
 477 static inline void write_IRQreg_ide(OpenPICState *opp, int n_IRQ, uint32_t val)
 478 {
 479     uint32_t tmp;
 480
 481     tmp = val & 0xC0000000;
 482     tmp |= val & ((1ULL << MAX_CPU) - 1);
 483     opp->src[n_IRQ].ide = tmp;
 484     DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
 485 }
 486
 487 static inline void write_IRQreg_ipvp(OpenPICState *opp, int n_IRQ, uint32_t val)
 488 {
 489     /* NOTE: not fully accurate for special IRQs, but simple and sufficient */
 490     /* ACTIVITY bit is read-only */
 491     opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & 0x40000000)
 492                          | (val & 0x800F00FF);
 493     openpic_update_irq(opp, n_IRQ);
 494     DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
 495             opp->src[n_IRQ].ipvp);
 496 }
 497
 498 static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
 499                               unsigned len)
 500 {
 501     OpenPICState *opp = opaque;
 502     IRQ_dst_t *dst;
 503     int idx;
 504
 505     DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
 506     if (addr & 0xF)
 507         return;
 508     switch (addr) {
 509     case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
 510         break;
 511     case 0x40:
 512     case 0x50:
 513     case 0x60:
 514     case 0x70:
 515     case 0x80:
 516     case 0x90:
 517     case 0xA0:
 518     case 0xB0:
 519         openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
 520         break;
 521     case 0x1000: /* FREP */
 522         break;
 523     case 0x1020: /* GLBC */
 524         if (val & 0x80000000) {
 525             openpic_reset(&opp->busdev.qdev);
 526         }
 527         break;
 528     case 0x1080: /* VENI */
 529         break;
 530     case 0x1090: /* PINT */
 531         for (idx = 0; idx < opp->nb_cpus; idx++) {
 532             if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
 533                 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
 534                 dst = &opp->dst[idx];
 535                 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
 536             } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) {
 537                 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
 538                 dst = &opp->dst[idx];
 539                 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
 540             }
 541         }
 542         opp->pint = val;
 543         break;
 544     case 0x10A0: /* IPI_IPVP */
 545     case 0x10B0:
 546     case 0x10C0:
 547     case 0x10D0:
 548         {
 549             int idx;
 550             idx = (addr - 0x10A0) >> 4;
 551             write_IRQreg_ipvp(opp, opp->irq_ipi0 + idx, val);
 552         }
 553         break;
 554     case 0x10E0: /* SPVE */
 555         opp->spve = val & opp->spve_mask;
 556         break;
 557     default:
 558         break;
 559     }
 560 }
 561
 562 static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
 563 {
 564     OpenPICState *opp = opaque;
 565     uint32_t retval;
 566
 567     DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
 568     retval = 0xFFFFFFFF;
 569     if (addr & 0xF)
 570         return retval;
 571     switch (addr) {
 572     case 0x1000: /* FREP */
 573         retval = opp->frep;
 574         break;
 575     case 0x1020: /* GLBC */
 576         retval = opp->glbc;
 577         break;
 578     case 0x1080: /* VENI */
 579         retval = opp->veni;
 580         break;
 581     case 0x1090: /* PINT */
 582         retval = 0x00000000;
 583         break;
 584     case 0x00: /* Block Revision Register1 (BRR1) */
 585     case 0x40:
 586     case 0x50:
 587     case 0x60:
 588     case 0x70:
 589     case 0x80:
 590     case 0x90:
 591     case 0xA0:
 592     case 0xB0:
 593         retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
 594         break;
 595     case 0x10A0: /* IPI_IPVP */
 596     case 0x10B0:
 597     case 0x10C0:
 598     case 0x10D0:
 599         {
 600             int idx;
 601             idx = (addr - 0x10A0) >> 4;
 602             retval = read_IRQreg_ipvp(opp, opp->irq_ipi0 + idx);
 603         }
 604         break;
 605     case 0x10E0: /* SPVE */
 606         retval = opp->spve;
 607         break;
 608     default:
 609         break;
 610     }
 611     DPRINTF("%s: => %08x\n", __func__, retval);
 612
 613     return retval;
 614 }
 615
 616 static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
 617                                 unsigned len)
 618 {
 619     OpenPICState *opp = opaque;
 620     int idx;
 621
 622     DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
 623     if (addr & 0xF)
 624         return;
 625     idx = (addr >> 6) & 0x3;
 626     addr = addr & 0x30;
 627
 628     if (addr == 0x0) {
 629         /* TIFR (TFRR) */
 630         opp->tifr = val;
 631         return;
 632     }
 633     switch (addr & 0x30) {
 634     case 0x00: /* TICC (GTCCR) */
 635         break;
 636     case 0x10: /* TIBC (GTBCR) */
 637         if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
 638             (val & 0x80000000) == 0 &&
 639             (opp->timers[idx].tibc & 0x80000000) != 0)
 640             opp->timers[idx].ticc &= ~0x80000000;
 641         opp->timers[idx].tibc = val;
 642         break;
 643     case 0x20: /* TIVP (GTIVPR) */
 644         write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val);
 645         break;
 646     case 0x30: /* TIDE (GTIDR) */
 647         write_IRQreg_ide(opp, opp->irq_tim0 + idx, val);
 648         break;
 649     }
 650 }
 651
 652 static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
 653 {
 654     OpenPICState *opp = opaque;
 655     uint32_t retval = -1;
 656     int idx;
 657
 658     DPRINTF("%s: addr %08x\n", __func__, addr);
 659     if (addr & 0xF) {
 660         goto out;
 661     }
 662     idx = (addr >> 6) & 0x3;
 663     if (addr == 0x0) {
 664         /* TIFR (TFRR) */
 665         retval = opp->tifr;
 666         goto out;
 667     }
 668     switch (addr & 0x30) {
 669     case 0x00: /* TICC (GTCCR) */
 670         retval = opp->timers[idx].ticc;
 671         break;
 672     case 0x10: /* TIBC (GTBCR) */
 673         retval = opp->timers[idx].tibc;
 674         break;
 675     case 0x20: /* TIPV (TIPV) */
 676         retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx);
 677         break;
 678     case 0x30: /* TIDE (TIDR) */
 679         retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx);
 680         break;
 681     }
 682
 683 out:
 684     DPRINTF("%s: => %08x\n", __func__, retval);
 685
 686     return retval;
 687 }
 688
 689 static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
 690                               unsigned len)
 691 {
 692     OpenPICState *opp = opaque;
 693     int idx;
 694
 695     DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
 696     if (addr & 0xF)
 697         return;
 698     addr = addr & 0xFFF0;
 699     idx = addr >> 5;
 700     if (addr & 0x10) {
 701         /* EXDE / IFEDE / IEEDE */
 702         write_IRQreg_ide(opp, idx, val);
 703     } else {
 704         /* EXVP / IFEVP / IEEVP */
 705         write_IRQreg_ipvp(opp, idx, val);
 706     }
 707 }
 708
 709 static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
 710 {
 711     OpenPICState *opp = opaque;
 712     uint32_t retval;
 713     int idx;
 714
 715     DPRINTF("%s: addr %08x\n", __func__, addr);
 716     retval = 0xFFFFFFFF;
 717     if (addr & 0xF)
 718         return retval;
 719     addr = addr & 0xFFF0;
 720     idx = addr >> 5;
 721     if (addr & 0x10) {
 722         /* EXDE / IFEDE / IEEDE */
 723         retval = read_IRQreg_ide(opp, idx);
 724     } else {
 725         /* EXVP / IFEVP / IEEVP */
 726         retval = read_IRQreg_ipvp(opp, idx);
 727     }
 728     DPRINTF("%s: => %08x\n", __func__, retval);
 729
 730     return retval;
 731 }
 732
 733 static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val,
 734                               unsigned size)
 735 {
 736     OpenPICState *opp = opaque;
 737     int idx = opp->irq_msi;
 738     int srs, ibs;
 739
 740     DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
 741     if (addr & 0xF) {
 742         return;
 743     }
 744
 745     switch (addr) {
 746     case MSIIR_OFFSET:
 747         srs = val >> MSIIR_SRS_SHIFT;
 748         idx += srs;
 749         ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
 750         opp->msi[srs].msir |= 1 << ibs;
 751         openpic_set_irq(opp, idx, 1);
 752         break;
 753     default:
 754         /* most registers are read-only, thus ignored */
 755         break;
 756     }
 757 }
 758
 759 static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
 760 {
 761     OpenPICState *opp = opaque;
 762     uint64_t r = 0;
 763     int i, srs;
 764
 765     DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
 766     if (addr & 0xF) {
 767         return -1;
 768     }
 769
 770     srs = addr >> 4;
 771
 772     switch (addr) {
 773     case 0x00:
 774     case 0x10:
 775     case 0x20:
 776     case 0x30:
 777     case 0x40:
 778     case 0x50:
 779     case 0x60:
 780     case 0x70: /* MSIRs */
 781         r = opp->msi[srs].msir;
 782         /* Clear on read */
 783         opp->msi[srs].msir = 0;
 784         break;
 785     case 0x120: /* MSISR */
 786         for (i = 0; i < MAX_MSI; i++) {
 787             r |= (opp->msi[i].msir ? 1 : 0) << i;
 788         }
 789         break;
 790     }
 791
 792     return r;
 793 }
 794
 795 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
 796                                        uint32_t val, int idx)
 797 {
 798     OpenPICState *opp = opaque;
 799     IRQ_src_t *src;
 800     IRQ_dst_t *dst;
 801     int s_IRQ, n_IRQ;
 802
 803     DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
 804             addr, val);
 805     if (addr & 0xF)
 806         return;
 807     dst = &opp->dst[idx];
 808     addr &= 0xFF0;
 809     switch (addr) {
 810     case 0x40: /* IPIDR */
 811     case 0x50:
 812     case 0x60:
 813     case 0x70:
 814         idx = (addr - 0x40) >> 4;
 815         /* we use IDE as mask which CPUs to deliver the IPI to still. */
 816         write_IRQreg_ide(opp, opp->irq_ipi0 + idx,
 817                          opp->src[opp->irq_ipi0 + idx].ide | val);
 818         openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
 819         openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
 820         break;
 821     case 0x80: /* PCTP */
 822         dst->pctp = val & 0x0000000F;
 823         break;
 824     case 0x90: /* WHOAMI */
 825         /* Read-only register */
 826         break;
 827     case 0xA0: /* PIAC */
 828         /* Read-only register */
 829         break;
 830     case 0xB0: /* PEOI */
 831         DPRINTF("PEOI\n");
 832         s_IRQ = IRQ_get_next(opp, &dst->servicing);
 833         IRQ_resetbit(&dst->servicing, s_IRQ);
 834         dst->servicing.next = -1;
 835         /* Set up next servicing IRQ */
 836         s_IRQ = IRQ_get_next(opp, &dst->servicing);
 837         /* Check queued interrupts. */
 838         n_IRQ = IRQ_get_next(opp, &dst->raised);
 839         src = &opp->src[n_IRQ];
 840         if (n_IRQ != -1 &&
 841             (s_IRQ == -1 ||
 842              IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) {
 843             DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
 844                     idx, n_IRQ);
 845             openpic_irq_raise(opp, idx, src);
 846         }
 847         break;
 848     default:
 849         break;
 850     }
 851 }
 852
 853 static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
 854                               unsigned len)
 855 {
 856     openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
 857 }
 858
 859 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
 860                                           int idx)
 861 {
 862     OpenPICState *opp = opaque;
 863     IRQ_src_t *src;
 864     IRQ_dst_t *dst;
 865     uint32_t retval;
 866     int n_IRQ;
 867
 868     DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr);
 869     retval = 0xFFFFFFFF;
 870     if (addr & 0xF)
 871         return retval;
 872     dst = &opp->dst[idx];
 873     addr &= 0xFF0;
 874     switch (addr) {
 875     case 0x00: /* Block Revision Register1 (BRR1) */
 876         retval = opp->brr1;
 877         break;
 878     case 0x80: /* PCTP */
 879         retval = dst->pctp;
 880         break;
 881     case 0x90: /* WHOAMI */
 882         retval = idx;
 883         break;
 884     case 0xA0: /* PIAC */
 885         DPRINTF("Lower OpenPIC INT output\n");
 886         qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
 887         n_IRQ = IRQ_get_next(opp, &dst->raised);
 888         DPRINTF("PIAC: irq=%d\n", n_IRQ);
 889         if (n_IRQ == -1) {
 890             /* No more interrupt pending */
 891             retval = IPVP_VECTOR(opp->spve);
 892         } else {
 893             src = &opp->src[n_IRQ];
 894             if (!(src->ipvp & IPVP_ACTIVITY_MASK) ||
 895                 !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
 896                 /* - Spurious level-sensitive IRQ
 897                  * - Priorities has been changed
 898                  *   and the pending IRQ isn't allowed anymore
 899                  */
 900                 src->ipvp &= ~IPVP_ACTIVITY_MASK;
 901                 retval = IPVP_VECTOR(opp->spve);
 902             } else {
 903                 /* IRQ enter servicing state */
 904                 IRQ_setbit(&dst->servicing, n_IRQ);
 905                 retval = IPVP_VECTOR(src->ipvp);
 906             }
 907             IRQ_resetbit(&dst->raised, n_IRQ);
 908             dst->raised.next = -1;
 909             if (!(src->ipvp & IPVP_SENSE_MASK)) {
 910                 /* edge-sensitive IRQ */
 911                 src->ipvp &= ~IPVP_ACTIVITY_MASK;
 912                 src->pending = 0;
 913             }
 914
 915             if ((n_IRQ >= opp->irq_ipi0) &&  (n_IRQ < (opp->irq_ipi0 + MAX_IPI))) {
 916                 src->ide &= ~(1 << idx);
 917                 if (src->ide && !(src->ipvp & IPVP_SENSE_MASK)) {
 918                     /* trigger on CPUs that didn't know about it yet */
 919                     openpic_set_irq(opp, n_IRQ, 1);
 920                     openpic_set_irq(opp, n_IRQ, 0);
 921                     /* if all CPUs knew about it, set active bit again */
 922                     src->ipvp |= IPVP_ACTIVITY_MASK;
 923                 }
 924             }
 925         }
 926         break;
 927     case 0xB0: /* PEOI */
 928         retval = 0;
 929         break;
 930     default:
 931         break;
 932     }
 933     DPRINTF("%s: => %08x\n", __func__, retval);
 934
 935     return retval;
 936 }
 937
 938 static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
 939 {
 940     return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
 941 }
 942
 943 static const MemoryRegionOps openpic_glb_ops_le = {
 944     .write = openpic_gbl_write,
 945     .read  = openpic_gbl_read,
 946     .endianness = DEVICE_LITTLE_ENDIAN,
 947     .impl = {
 948         .min_access_size = 4,
 949         .max_access_size = 4,
 950     },
 951 };
 952
 953 static const MemoryRegionOps openpic_glb_ops_be = {
 954     .write = openpic_gbl_write,
 955     .read  = openpic_gbl_read,
 956     .endianness = DEVICE_BIG_ENDIAN,
 957     .impl = {
 958         .min_access_size = 4,
 959         .max_access_size = 4,
 960     },
 961 };
 962
 963 static const MemoryRegionOps openpic_tmr_ops_le = {
 964     .write = openpic_tmr_write,
 965     .read  = openpic_tmr_read,
 966     .endianness = DEVICE_LITTLE_ENDIAN,
 967     .impl = {
 968         .min_access_size = 4,
 969         .max_access_size = 4,
 970     },
 971 };
 972
 973 static const MemoryRegionOps openpic_tmr_ops_be = {
 974     .write = openpic_tmr_write,
 975     .read  = openpic_tmr_read,
 976     .endianness = DEVICE_BIG_ENDIAN,
 977     .impl = {
 978         .min_access_size = 4,
 979         .max_access_size = 4,
 980     },
 981 };
 982
 983 static const MemoryRegionOps openpic_cpu_ops_le = {
 984     .write = openpic_cpu_write,
 985     .read  = openpic_cpu_read,
 986     .endianness = DEVICE_LITTLE_ENDIAN,
 987     .impl = {
 988         .min_access_size = 4,
 989         .max_access_size = 4,
 990     },
 991 };
 992
 993 static const MemoryRegionOps openpic_cpu_ops_be = {
 994     .write = openpic_cpu_write,
 995     .read  = openpic_cpu_read,
 996     .endianness = DEVICE_BIG_ENDIAN,
 997     .impl = {
 998         .min_access_size = 4,
 999         .max_access_size = 4,
1000     },
1001 };
1002
1003 static const MemoryRegionOps openpic_src_ops_le = {
1004     .write = openpic_src_write,
1005     .read  = openpic_src_read,
1006     .endianness = DEVICE_LITTLE_ENDIAN,
1007     .impl = {
1008         .min_access_size = 4,
1009         .max_access_size = 4,
1010     },
1011 };
1012
1013 static const MemoryRegionOps openpic_src_ops_be = {
1014     .write = openpic_src_write,
1015     .read  = openpic_src_read,
1016     .endianness = DEVICE_BIG_ENDIAN,
1017     .impl = {
1018         .min_access_size = 4,
1019         .max_access_size = 4,
1020     },
1021 };
1022
1023 static const MemoryRegionOps openpic_msi_ops_le = {
1024     .read = openpic_msi_read,
1025     .write = openpic_msi_write,
1026     .endianness = DEVICE_LITTLE_ENDIAN,
1027     .impl = {
1028         .min_access_size = 4,
1029         .max_access_size = 4,
1030     },
1031 };
1032
1033 static const MemoryRegionOps openpic_msi_ops_be = {
1034     .read = openpic_msi_read,
1035     .write = openpic_msi_write,
1036     .endianness = DEVICE_BIG_ENDIAN,
1037     .impl = {
1038         .min_access_size = 4,
1039         .max_access_size = 4,
1040     },
1041 };
1042
1043 static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
1044 {
1045     unsigned int i;
1046
1047     for (i = 0; i < BF_WIDTH(MAX_IRQ); i++)
1048         qemu_put_be32s(f, &q->queue[i]);
1049
1050     qemu_put_sbe32s(f, &q->next);
1051     qemu_put_sbe32s(f, &q->priority);
1052 }
1053
1054 static void openpic_save(QEMUFile* f, void *opaque)
1055 {
1056     OpenPICState *opp = (OpenPICState *)opaque;
1057     unsigned int i;
1058
1059     qemu_put_be32s(f, &opp->glbc);
1060     qemu_put_be32s(f, &opp->veni);
1061     qemu_put_be32s(f, &opp->pint);
1062     qemu_put_be32s(f, &opp->spve);
1063     qemu_put_be32s(f, &opp->tifr);
1064
1065     for (i = 0; i < opp->max_irq; i++) {
1066         qemu_put_be32s(f, &opp->src[i].ipvp);
1067         qemu_put_be32s(f, &opp->src[i].ide);
1068         qemu_put_sbe32s(f, &opp->src[i].last_cpu);
1069         qemu_put_sbe32s(f, &opp->src[i].pending);
1070     }
1071
1072     qemu_put_be32s(f, &opp->nb_cpus);
1073
1074     for (i = 0; i < opp->nb_cpus; i++) {
1075         qemu_put_be32s(f, &opp->dst[i].pctp);
1076         qemu_put_be32s(f, &opp->dst[i].pcsr);
1077         openpic_save_IRQ_queue(f, &opp->dst[i].raised);
1078         openpic_save_IRQ_queue(f, &opp->dst[i].servicing);
1079     }
1080
1081     for (i = 0; i < MAX_TMR; i++) {
1082         qemu_put_be32s(f, &opp->timers[i].ticc);
1083         qemu_put_be32s(f, &opp->timers[i].tibc);
1084     }
1085 }
1086
1087 static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
1088 {
1089     unsigned int i;
1090
1091     for (i = 0; i < BF_WIDTH(MAX_IRQ); i++)
1092         qemu_get_be32s(f, &q->queue[i]);
1093
1094     qemu_get_sbe32s(f, &q->next);
1095     qemu_get_sbe32s(f, &q->priority);
1096 }
1097
1098 static int openpic_load(QEMUFile* f, void *opaque, int version_id)
1099 {
1100     OpenPICState *opp = (OpenPICState *)opaque;
1101     unsigned int i;
1102
1103     if (version_id != 1)
1104         return -EINVAL;
1105
1106     qemu_get_be32s(f, &opp->glbc);
1107     qemu_get_be32s(f, &opp->veni);
1108     qemu_get_be32s(f, &opp->pint);
1109     qemu_get_be32s(f, &opp->spve);
1110     qemu_get_be32s(f, &opp->tifr);
1111
1112     for (i = 0; i < opp->max_irq; i++) {
1113         qemu_get_be32s(f, &opp->src[i].ipvp);
1114         qemu_get_be32s(f, &opp->src[i].ide);
1115         qemu_get_sbe32s(f, &opp->src[i].last_cpu);
1116         qemu_get_sbe32s(f, &opp->src[i].pending);
1117     }
1118
1119     qemu_get_be32s(f, &opp->nb_cpus);
1120
1121     for (i = 0; i < opp->nb_cpus; i++) {
1122         qemu_get_be32s(f, &opp->dst[i].pctp);
1123         qemu_get_be32s(f, &opp->dst[i].pcsr);
1124         openpic_load_IRQ_queue(f, &opp->dst[i].raised);
1125         openpic_load_IRQ_queue(f, &opp->dst[i].servicing);
1126     }
1127
1128     for (i = 0; i < MAX_TMR; i++) {
1129         qemu_get_be32s(f, &opp->timers[i].ticc);
1130         qemu_get_be32s(f, &opp->timers[i].tibc);
1131     }
1132
1133     return 0;
1134 }
1135
1136 static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
1137 {
1138     int n_ci = IDR_CI0_SHIFT - n_CPU;
1139
1140     if ((opp->flags & OPENPIC_FLAG_IDE_CRIT) && (src->ide & (1 << n_ci))) {
1141         qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
1142     } else {
1143         qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
1144     }
1145 }
1146
1147 struct memreg {
1148     const char             *name;
1149     MemoryRegionOps const  *ops;
1150     bool                   map;
1151     hwaddr      start_addr;
1152     ram_addr_t              size;
1153 };
1154
1155 static int openpic_init(SysBusDevice *dev)
1156 {
1157     OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev);
1158     int i, j;
1159     struct memreg list_le[] = {
1160         {"glb", &openpic_glb_ops_le, true,
1161                 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
1162         {"tmr", &openpic_tmr_ops_le, true,
1163                 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
1164         {"msi", &openpic_msi_ops_le, true,
1165                 OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
1166         {"src", &openpic_src_ops_le, true,
1167                 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
1168         {"cpu", &openpic_cpu_ops_le, true,
1169                 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
1170     };
1171     struct memreg list_be[] = {
1172         {"glb", &openpic_glb_ops_be, true,
1173                 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
1174         {"tmr", &openpic_tmr_ops_be, true,
1175                 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
1176         {"msi", &openpic_msi_ops_be, true,
1177                 OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
1178         {"src", &openpic_src_ops_be, true,
1179                 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
1180         {"cpu", &openpic_cpu_ops_be, true,
1181                 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
1182     };
1183     struct memreg *list;
1184
1185     switch (opp->model) {
1186     case OPENPIC_MODEL_FSL_MPIC_20:
1187     default:
1188         opp->flags |= OPENPIC_FLAG_IDE_CRIT;
1189         opp->nb_irqs = 80;
1190         opp->vid = VID_REVISION_1_2;
1191         opp->veni = VENI_GENERIC;
1192         opp->spve_mask = 0xFFFF;
1193         opp->tifr_reset = 0x00000000;
1194         opp->ipvp_reset = 0x80000000;
1195         opp->ide_reset = 0x00000001;
1196         opp->max_irq = FSL_MPIC_20_MAX_IRQ;
1197         opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ;
1198         opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
1199         opp->irq_msi = FSL_MPIC_20_MSI_IRQ;
1200         opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
1201         msi_supported = true;
1202         list = list_be;
1203         break;
1204     case OPENPIC_MODEL_RAVEN:
1205         opp->nb_irqs = RAVEN_MAX_EXT;
1206         opp->vid = VID_REVISION_1_3;
1207         opp->veni = VENI_GENERIC;
1208         opp->spve_mask = 0xFF;
1209         opp->tifr_reset = 0x003F7A00;
1210         opp->ipvp_reset = 0xA0000000;
1211         opp->ide_reset = 0x00000000;
1212         opp->max_irq = RAVEN_MAX_IRQ;
1213         opp->irq_ipi0 = RAVEN_IPI_IRQ;
1214         opp->irq_tim0 = RAVEN_TMR_IRQ;
1215         opp->brr1 = -1;
1216         list = list_le;
1217         /* Don't map MSI region */
1218         list[2].map = false;
1219
1220         /* Only UP supported today */
1221         if (opp->nb_cpus != 1) {
1222             return -EINVAL;
1223         }
1224         break;
1225     }
1226
1227     memory_region_init(&opp->mem, "openpic", 0x40000);
1228
1229     for (i = 0; i < ARRAY_SIZE(list_le); i++) {
1230         if (!list[i].map) {
1231             continue;
1232         }
1233
1234         memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,
1235                               list[i].name, list[i].size);
1236
1237         memory_region_add_subregion(&opp->mem, list[i].start_addr,
1238                                     &opp->sub_io_mem[i]);
1239     }
1240
1241     for (i = 0; i < opp->nb_cpus; i++) {
1242         opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB);
1243         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
1244             sysbus_init_irq(dev, &opp->dst[i].irqs[j]);
1245         }
1246     }
1247
1248     register_savevm(&opp->busdev.qdev, "openpic", 0, 2,
1249                     openpic_save, openpic_load, opp);
1250
1251     sysbus_init_mmio(dev, &opp->mem);
1252     qdev_init_gpio_in(&dev->qdev, openpic_set_irq, opp->max_irq);
1253
1254     return 0;
1255 }
1256
1257 static Property openpic_properties[] = {
1258     DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20),
1259     DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1),
1260     DEFINE_PROP_END_OF_LIST(),
1261 };
1262
1263 static void openpic_class_init(ObjectClass *klass, void *data)
1264 {
1265     DeviceClass *dc = DEVICE_CLASS(klass);
1266     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1267
1268     k->init = openpic_init;
1269     dc->props = openpic_properties;
1270     dc->reset = openpic_reset;
1271 }
1272
1273 static TypeInfo openpic_info = {
1274     .name          = "openpic",
1275     .parent        = TYPE_SYS_BUS_DEVICE,
1276     .instance_size = sizeof(OpenPICState),
1277     .class_init    = openpic_class_init,
1278 };
1279
1280 static void openpic_register_types(void)
1281 {
1282     type_register_static(&openpic_info);
1283 }
1284
1285 type_init(openpic_register_types)