2 * I/O instructions for S/390
4 * Copyright 2012, 2015 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
12 #include "qemu/osdep.h"
16 #include "hw/s390x/ioinst.h"
18 #include "hw/s390x/s390-pci-bus.h"
20 int ioinst_disassemble_sch_ident(uint32_t value
, int *m
, int *cssid
, int *ssid
,
23 if (!IOINST_SCHID_ONE(value
)) {
26 if (!IOINST_SCHID_M(value
)) {
27 if (IOINST_SCHID_CSSID(value
)) {
33 *cssid
= IOINST_SCHID_CSSID(value
);
36 *ssid
= IOINST_SCHID_SSID(value
);
37 *schid
= IOINST_SCHID_NR(value
);
41 void ioinst_handle_xsch(S390CPU
*cpu
, uint64_t reg1
, uintptr_t ra
)
43 int cssid
, ssid
, schid
, m
;
46 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
47 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, 4, ra
);
50 trace_ioinst_sch_id("xsch", cssid
, ssid
, schid
);
51 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
52 if (!sch
|| !css_subch_visible(sch
)) {
56 setcc(cpu
, css_do_xsch(sch
));
59 void ioinst_handle_csch(S390CPU
*cpu
, uint64_t reg1
, uintptr_t ra
)
61 int cssid
, ssid
, schid
, m
;
64 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
65 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, 4, ra
);
68 trace_ioinst_sch_id("csch", cssid
, ssid
, schid
);
69 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
70 if (!sch
|| !css_subch_visible(sch
)) {
74 setcc(cpu
, css_do_csch(sch
));
77 void ioinst_handle_hsch(S390CPU
*cpu
, uint64_t reg1
, uintptr_t ra
)
79 int cssid
, ssid
, schid
, m
;
82 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
83 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, 4, ra
);
86 trace_ioinst_sch_id("hsch", cssid
, ssid
, schid
);
87 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
88 if (!sch
|| !css_subch_visible(sch
)) {
92 setcc(cpu
, css_do_hsch(sch
));
95 static int ioinst_schib_valid(SCHIB
*schib
)
97 if ((be16_to_cpu(schib
->pmcw
.flags
) & PMCW_FLAGS_MASK_INVALID
) ||
98 (be32_to_cpu(schib
->pmcw
.chars
) & PMCW_CHARS_MASK_INVALID
)) {
101 /* Disallow extended measurements for now. */
102 if (be32_to_cpu(schib
->pmcw
.chars
) & PMCW_CHARS_MASK_XMWME
) {
108 void ioinst_handle_msch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
, uintptr_t ra
)
110 int cssid
, ssid
, schid
, m
;
114 CPUS390XState
*env
= &cpu
->env
;
117 addr
= decode_basedisp_s(env
, ipb
, &ar
);
119 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
122 if (s390_cpu_virt_mem_read(cpu
, addr
, ar
, &schib
, sizeof(schib
))) {
123 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
126 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
) ||
127 !ioinst_schib_valid(&schib
)) {
128 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
131 trace_ioinst_sch_id("msch", cssid
, ssid
, schid
);
132 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
133 if (!sch
|| !css_subch_visible(sch
)) {
137 setcc(cpu
, css_do_msch(sch
, &schib
));
140 static void copy_orb_from_guest(ORB
*dest
, const ORB
*src
)
142 dest
->intparm
= be32_to_cpu(src
->intparm
);
143 dest
->ctrl0
= be16_to_cpu(src
->ctrl0
);
144 dest
->lpm
= src
->lpm
;
145 dest
->ctrl1
= src
->ctrl1
;
146 dest
->cpa
= be32_to_cpu(src
->cpa
);
149 static int ioinst_orb_valid(ORB
*orb
)
151 if ((orb
->ctrl0
& ORB_CTRL0_MASK_INVALID
) ||
152 (orb
->ctrl1
& ORB_CTRL1_MASK_INVALID
)) {
155 /* We don't support MIDA. */
156 if (orb
->ctrl1
& ORB_CTRL1_MASK_MIDAW
) {
159 if ((orb
->cpa
& HIGH_ORDER_BIT
) != 0) {
165 void ioinst_handle_ssch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
, uintptr_t ra
)
167 int cssid
, ssid
, schid
, m
;
171 CPUS390XState
*env
= &cpu
->env
;
174 addr
= decode_basedisp_s(env
, ipb
, &ar
);
176 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
179 if (s390_cpu_virt_mem_read(cpu
, addr
, ar
, &orig_orb
, sizeof(orb
))) {
180 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
183 copy_orb_from_guest(&orb
, &orig_orb
);
184 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
) ||
185 !ioinst_orb_valid(&orb
)) {
186 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
189 trace_ioinst_sch_id("ssch", cssid
, ssid
, schid
);
190 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
191 if (!sch
|| !css_subch_visible(sch
)) {
195 setcc(cpu
, css_do_ssch(sch
, &orb
));
198 void ioinst_handle_stcrw(S390CPU
*cpu
, uint32_t ipb
, uintptr_t ra
)
203 CPUS390XState
*env
= &cpu
->env
;
206 addr
= decode_basedisp_s(env
, ipb
, &ar
);
208 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
212 cc
= css_do_stcrw(&crw
);
213 /* 0 - crw stored, 1 - zeroes stored */
215 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &crw
, sizeof(crw
)) == 0) {
219 /* Write failed: requeue CRW since STCRW is suppressing */
220 css_undo_stcrw(&crw
);
222 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
226 void ioinst_handle_stsch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
,
229 int cssid
, ssid
, schid
, m
;
234 CPUS390XState
*env
= &cpu
->env
;
237 addr
= decode_basedisp_s(env
, ipb
, &ar
);
239 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
243 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
245 * As operand exceptions have a lower priority than access exceptions,
246 * we check whether the memory area is writeable (injecting the
247 * access execption if it is not) first.
249 if (!s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, sizeof(schib
))) {
250 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
252 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
256 trace_ioinst_sch_id("stsch", cssid
, ssid
, schid
);
257 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
259 if (css_subch_visible(sch
)) {
260 css_do_stsch(sch
, &schib
);
263 /* Indicate no more subchannels in this css/ss */
267 if (css_schid_final(m
, cssid
, ssid
, schid
)) {
268 cc
= 3; /* No more subchannels in this css/ss */
270 /* Store an empty schib. */
271 memset(&schib
, 0, sizeof(schib
));
276 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &schib
,
277 sizeof(schib
)) != 0) {
278 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
282 /* Access exceptions have a higher priority than cc3 */
283 if (s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, sizeof(schib
)) != 0) {
284 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
291 int ioinst_handle_tsch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
, uintptr_t ra
)
293 CPUS390XState
*env
= &cpu
->env
;
294 int cssid
, ssid
, schid
, m
;
301 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
302 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
305 trace_ioinst_sch_id("tsch", cssid
, ssid
, schid
);
306 addr
= decode_basedisp_s(env
, ipb
, &ar
);
308 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
312 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
313 if (sch
&& css_subch_visible(sch
)) {
314 cc
= css_do_tsch_get_irb(sch
, &irb
, &irb_len
);
318 /* 0 - status pending, 1 - not status pending, 3 - not operational */
320 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &irb
, irb_len
) != 0) {
321 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
324 css_do_tsch_update_subch(sch
);
326 irb_len
= sizeof(irb
) - sizeof(irb
.emw
);
327 /* Access exceptions have a higher priority than cc3 */
328 if (s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, irb_len
) != 0) {
329 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
338 typedef struct ChscReq
{
344 } QEMU_PACKED ChscReq
;
346 typedef struct ChscResp
{
351 } QEMU_PACKED ChscResp
;
353 #define CHSC_MIN_RESP_LEN 0x0008
355 #define CHSC_SCPD 0x0002
356 #define CHSC_SCSC 0x0010
357 #define CHSC_SDA 0x0031
358 #define CHSC_SEI 0x000e
360 #define CHSC_SCPD_0_M 0x20000000
361 #define CHSC_SCPD_0_C 0x10000000
362 #define CHSC_SCPD_0_FMT 0x0f000000
363 #define CHSC_SCPD_0_CSSID 0x00ff0000
364 #define CHSC_SCPD_0_RFMT 0x00000f00
365 #define CHSC_SCPD_0_RES 0xc000f000
366 #define CHSC_SCPD_1_RES 0xffffff00
367 #define CHSC_SCPD_01_CHPID 0x000000ff
368 static void ioinst_handle_chsc_scpd(ChscReq
*req
, ChscResp
*res
)
370 uint16_t len
= be16_to_cpu(req
->len
);
371 uint32_t param0
= be32_to_cpu(req
->param0
);
372 uint32_t param1
= be32_to_cpu(req
->param1
);
376 uint8_t f_chpid
, l_chpid
;
380 rfmt
= (param0
& CHSC_SCPD_0_RFMT
) >> 8;
381 if ((rfmt
== 0) || (rfmt
== 1)) {
382 rfmt
= !!(param0
& CHSC_SCPD_0_C
);
384 if ((len
!= 0x0010) || (param0
& CHSC_SCPD_0_RES
) ||
385 (param1
& CHSC_SCPD_1_RES
) || req
->param2
) {
389 if (param0
& CHSC_SCPD_0_FMT
) {
393 cssid
= (param0
& CHSC_SCPD_0_CSSID
) >> 16;
394 m
= param0
& CHSC_SCPD_0_M
;
396 if (!m
|| !css_present(cssid
)) {
401 f_chpid
= param0
& CHSC_SCPD_01_CHPID
;
402 l_chpid
= param1
& CHSC_SCPD_01_CHPID
;
403 if (l_chpid
< f_chpid
) {
407 /* css_collect_chp_desc() is endian-aware */
408 desc_size
= css_collect_chp_desc(m
, cssid
, f_chpid
, l_chpid
, rfmt
,
410 res
->code
= cpu_to_be16(0x0001);
411 res
->len
= cpu_to_be16(8 + desc_size
);
412 res
->param
= cpu_to_be32(rfmt
);
416 res
->code
= cpu_to_be16(resp_code
);
417 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
418 res
->param
= cpu_to_be32(rfmt
);
421 #define CHSC_SCSC_0_M 0x20000000
422 #define CHSC_SCSC_0_FMT 0x000f0000
423 #define CHSC_SCSC_0_CSSID 0x0000ff00
424 #define CHSC_SCSC_0_RES 0xdff000ff
425 static void ioinst_handle_chsc_scsc(ChscReq
*req
, ChscResp
*res
)
427 uint16_t len
= be16_to_cpu(req
->len
);
428 uint32_t param0
= be32_to_cpu(req
->param0
);
431 uint32_t general_chars
[510];
432 uint32_t chsc_chars
[508];
439 if (param0
& CHSC_SCSC_0_FMT
) {
443 cssid
= (param0
& CHSC_SCSC_0_CSSID
) >> 8;
445 if (!(param0
& CHSC_SCSC_0_M
) || !css_present(cssid
)) {
450 if ((param0
& CHSC_SCSC_0_RES
) || req
->param1
|| req
->param2
) {
454 res
->code
= cpu_to_be16(0x0001);
455 res
->len
= cpu_to_be16(4080);
458 memset(general_chars
, 0, sizeof(general_chars
));
459 memset(chsc_chars
, 0, sizeof(chsc_chars
));
461 general_chars
[0] = cpu_to_be32(0x03000000);
462 general_chars
[1] = cpu_to_be32(0x00079000);
463 general_chars
[3] = cpu_to_be32(0x00080000);
465 chsc_chars
[0] = cpu_to_be32(0x40000000);
466 chsc_chars
[3] = cpu_to_be32(0x00040000);
468 memcpy(res
->data
, general_chars
, sizeof(general_chars
));
469 memcpy(res
->data
+ sizeof(general_chars
), chsc_chars
, sizeof(chsc_chars
));
473 res
->code
= cpu_to_be16(resp_code
);
474 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
478 #define CHSC_SDA_0_FMT 0x0f000000
479 #define CHSC_SDA_0_OC 0x0000ffff
480 #define CHSC_SDA_0_RES 0xf0ff0000
481 #define CHSC_SDA_OC_MCSSE 0x0
482 #define CHSC_SDA_OC_MSS 0x2
483 static void ioinst_handle_chsc_sda(ChscReq
*req
, ChscResp
*res
)
485 uint16_t resp_code
= 0x0001;
486 uint16_t len
= be16_to_cpu(req
->len
);
487 uint32_t param0
= be32_to_cpu(req
->param0
);
491 if ((len
!= 0x0400) || (param0
& CHSC_SDA_0_RES
)) {
496 if (param0
& CHSC_SDA_0_FMT
) {
501 oc
= param0
& CHSC_SDA_0_OC
;
503 case CHSC_SDA_OC_MCSSE
:
504 ret
= css_enable_mcsse();
505 if (ret
== -EINVAL
) {
510 case CHSC_SDA_OC_MSS
:
511 ret
= css_enable_mss();
512 if (ret
== -EINVAL
) {
523 res
->code
= cpu_to_be16(resp_code
);
524 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
528 static int chsc_sei_nt0_get_event(void *res
)
534 static int chsc_sei_nt0_have_event(void)
540 static int chsc_sei_nt2_get_event(void *res
)
542 if (s390_has_feat(S390_FEAT_ZPCI
)) {
543 return pci_chsc_sei_nt2_get_event(res
);
548 static int chsc_sei_nt2_have_event(void)
550 if (s390_has_feat(S390_FEAT_ZPCI
)) {
551 return pci_chsc_sei_nt2_have_event();
556 #define CHSC_SEI_NT0 (1ULL << 63)
557 #define CHSC_SEI_NT2 (1ULL << 61)
558 static void ioinst_handle_chsc_sei(ChscReq
*req
, ChscResp
*res
)
560 uint64_t selection_mask
= ldq_p(&req
->param1
);
561 uint8_t *res_flags
= (uint8_t *)res
->data
;
565 /* regarding architecture nt0 can not be masked */
566 have_event
= !chsc_sei_nt0_get_event(res
);
567 have_more
= chsc_sei_nt0_have_event();
569 if (selection_mask
& CHSC_SEI_NT2
) {
571 have_event
= !chsc_sei_nt2_get_event(res
);
575 have_more
= chsc_sei_nt2_have_event();
580 res
->code
= cpu_to_be16(0x0001);
582 (*res_flags
) |= 0x80;
584 (*res_flags
) &= ~0x80;
585 css_clear_sei_pending();
588 res
->code
= cpu_to_be16(0x0005);
589 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
593 static void ioinst_handle_chsc_unimplemented(ChscResp
*res
)
595 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
596 res
->code
= cpu_to_be16(0x0004);
600 void ioinst_handle_chsc(S390CPU
*cpu
, uint32_t ipb
, uintptr_t ra
)
608 CPUS390XState
*env
= &cpu
->env
;
609 uint8_t buf
[TARGET_PAGE_SIZE
];
611 trace_ioinst("chsc");
612 reg
= (ipb
>> 20) & 0x00f;
613 addr
= env
->regs
[reg
];
616 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
620 * Reading sizeof(ChscReq) bytes is currently enough for all of our
621 * present CHSC sub-handlers ... if we ever need more, we should take
622 * care of req->len here first.
624 if (s390_cpu_virt_mem_read(cpu
, addr
, reg
, buf
, sizeof(ChscReq
))) {
625 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
628 req
= (ChscReq
*)buf
;
629 len
= be16_to_cpu(req
->len
);
630 /* Length field valid? */
631 if ((len
< 16) || (len
> 4088) || (len
& 7)) {
632 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
635 memset((char *)req
+ len
, 0, TARGET_PAGE_SIZE
- len
);
636 res
= (void *)((char *)req
+ len
);
637 command
= be16_to_cpu(req
->command
);
638 trace_ioinst_chsc_cmd(command
, len
);
641 ioinst_handle_chsc_scsc(req
, res
);
644 ioinst_handle_chsc_scpd(req
, res
);
647 ioinst_handle_chsc_sda(req
, res
);
650 ioinst_handle_chsc_sei(req
, res
);
653 ioinst_handle_chsc_unimplemented(res
);
657 if (!s390_cpu_virt_mem_write(cpu
, addr
+ len
, reg
, res
,
658 be16_to_cpu(res
->len
))) {
659 setcc(cpu
, 0); /* Command execution complete */
661 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
665 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
666 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
667 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
668 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
670 void ioinst_handle_schm(S390CPU
*cpu
, uint64_t reg1
, uint64_t reg2
,
671 uint32_t ipb
, uintptr_t ra
)
676 CPUS390XState
*env
= &cpu
->env
;
678 trace_ioinst("schm");
680 if (SCHM_REG1_RES(reg1
)) {
681 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
685 mbk
= SCHM_REG1_MBK(reg1
);
686 update
= SCHM_REG1_UPD(reg1
);
687 dct
= SCHM_REG1_DCT(reg1
);
689 if (update
&& (reg2
& 0x000000000000001f)) {
690 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
694 css_do_schm(mbk
, update
, dct
, update
? reg2
: 0);
697 void ioinst_handle_rsch(S390CPU
*cpu
, uint64_t reg1
, uintptr_t ra
)
699 int cssid
, ssid
, schid
, m
;
702 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
703 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, 4, ra
);
706 trace_ioinst_sch_id("rsch", cssid
, ssid
, schid
);
707 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
708 if (!sch
|| !css_subch_visible(sch
)) {
712 setcc(cpu
, css_do_rsch(sch
));
715 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
716 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
717 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
718 void ioinst_handle_rchp(S390CPU
*cpu
, uint64_t reg1
, uintptr_t ra
)
724 CPUS390XState
*env
= &cpu
->env
;
726 if (RCHP_REG1_RES(reg1
)) {
727 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
731 cssid
= RCHP_REG1_CSSID(reg1
);
732 chpid
= RCHP_REG1_CHPID(reg1
);
734 trace_ioinst_chp_id("rchp", cssid
, chpid
);
736 ret
= css_do_rchp(cssid
, chpid
);
749 /* Invalid channel subsystem. */
750 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
756 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
757 void ioinst_handle_sal(S390CPU
*cpu
, uint64_t reg1
, uintptr_t ra
)
759 /* We do not provide address limit checking, so let's suppress it. */
760 if (SAL_REG1_INVALID(reg1
) || reg1
& 0x000000000000ffff) {
761 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, 4, ra
);