hw/xen/xen_pt_msi.c

   1 /*
   2  * Copyright (c) 2007, Intel Corporation.
   3  *
   4  * This work is licensed under the terms of the GNU GPL, version 2.  See
   5  * the COPYING file in the top-level directory.
   6  *
   7  * Jiang Yunhong <yunhong.jiang@intel.com>
   8  *
   9  * This file implements direct PCI assignment to a HVM guest
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include <sys/mman.h>
  14
  15 #include "hw/xen/xen_backend.h"
  16 #include "xen_pt.h"
  17 #include "hw/i386/apic-msidef.h"
  18
  19
  20 #define XEN_PT_AUTO_ASSIGN -1
  21
  22 /* shift count for gflags */
  23 #define XEN_PT_GFLAGS_SHIFT_DEST_ID        0
  24 #define XEN_PT_GFLAGS_SHIFT_RH             8
  25 #define XEN_PT_GFLAGS_SHIFT_DM             9
  26 #define XEN_PT_GFLAGSSHIFT_DELIV_MODE     12
  27 #define XEN_PT_GFLAGSSHIFT_TRG_MODE       15
  28
  29 #define latch(fld) latch[PCI_MSIX_ENTRY_##fld / sizeof(uint32_t)]
  30
  31 /*
  32  * Helpers
  33  */
  34
  35 static inline uint8_t msi_vector(uint32_t data)
  36 {
  37     return (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
  38 }
  39
  40 static inline uint8_t msi_dest_id(uint32_t addr)
  41 {
  42     return (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
  43 }
  44
  45 static inline uint32_t msi_ext_dest_id(uint32_t addr_hi)
  46 {
  47     return addr_hi & 0xffffff00;
  48 }
  49
  50 static uint32_t msi_gflags(uint32_t data, uint64_t addr)
  51 {
  52     uint32_t result = 0;
  53     int rh, dm, dest_id, deliv_mode, trig_mode;
  54
  55     rh = (addr >> MSI_ADDR_REDIRECTION_SHIFT) & 0x1;
  56     dm = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
  57     dest_id = msi_dest_id(addr);
  58     deliv_mode = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
  59     trig_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
  60
  61     result = dest_id | (rh << XEN_PT_GFLAGS_SHIFT_RH)
  62         | (dm << XEN_PT_GFLAGS_SHIFT_DM)
  63         | (deliv_mode << XEN_PT_GFLAGSSHIFT_DELIV_MODE)
  64         | (trig_mode << XEN_PT_GFLAGSSHIFT_TRG_MODE);
  65
  66     return result;
  67 }
  68
  69 static inline uint64_t msi_addr64(XenPTMSI *msi)
  70 {
  71     return (uint64_t)msi->addr_hi << 32 | msi->addr_lo;
  72 }
  73
  74 static int msi_msix_enable(XenPCIPassthroughState *s,
  75                            uint32_t address,
  76                            uint16_t flag,
  77                            bool enable)
  78 {
  79     uint16_t val = 0;
  80     int rc;
  81
  82     if (!address) {
  83         return -1;
  84     }
  85
  86     rc = xen_host_pci_get_word(&s->real_device, address, &val);
  87     if (rc) {
  88         XEN_PT_ERR(&s->dev, "Failed to read MSI/MSI-X register (0x%x), rc:%d\n",
  89                    address, rc);
  90         return rc;
  91     }
  92     if (enable) {
  93         val |= flag;
  94     } else {
  95         val &= ~flag;
  96     }
  97     rc = xen_host_pci_set_word(&s->real_device, address, val);
  98     if (rc) {
  99         XEN_PT_ERR(&s->dev, "Failed to write MSI/MSI-X register (0x%x), rc:%d\n",
 100                    address, rc);
 101     }
 102     return rc;
 103 }
 104
 105 static int msi_msix_setup(XenPCIPassthroughState *s,
 106                           uint64_t addr,
 107                           uint32_t data,
 108                           int *ppirq,
 109                           bool is_msix,
 110                           int msix_entry,
 111                           bool is_not_mapped)
 112 {
 113     uint8_t gvec = msi_vector(data);
 114     int rc = 0;
 115
 116     assert((!is_msix && msix_entry == 0) || is_msix);
 117
 118     if (gvec == 0) {
 119         /* if gvec is 0, the guest is asking for a particular pirq that
 120          * is passed as dest_id */
 121         *ppirq = msi_ext_dest_id(addr >> 32) | msi_dest_id(addr);
 122         if (!*ppirq) {
 123             /* this probably identifies an misconfiguration of the guest,
 124              * try the emulated path */
 125             *ppirq = XEN_PT_UNASSIGNED_PIRQ;
 126         } else {
 127             XEN_PT_LOG(&s->dev, "requested pirq %d for MSI%s"
 128                        " (vec: %#x, entry: %#x)\n",
 129                        *ppirq, is_msix ? "-X" : "", gvec, msix_entry);
 130         }
 131     }
 132
 133     if (is_not_mapped) {
 134         uint64_t table_base = 0;
 135
 136         if (is_msix) {
 137             table_base = s->msix->table_base;
 138         }
 139
 140         rc = xc_physdev_map_pirq_msi(xen_xc, xen_domid, XEN_PT_AUTO_ASSIGN,
 141                                      ppirq, PCI_DEVFN(s->real_device.dev,
 142                                                       s->real_device.func),
 143                                      s->real_device.bus,
 144                                      msix_entry, table_base);
 145         if (rc) {
 146             XEN_PT_ERR(&s->dev,
 147                        "Mapping of MSI%s (err: %i, vec: %#x, entry %#x)\n",
 148                        is_msix ? "-X" : "", errno, gvec, msix_entry);
 149             return rc;
 150         }
 151     }
 152
 153     return 0;
 154 }
 155 static int msi_msix_update(XenPCIPassthroughState *s,
 156                            uint64_t addr,
 157                            uint32_t data,
 158                            int pirq,
 159                            bool is_msix,
 160                            int msix_entry,
 161                            int *old_pirq)
 162 {
 163     PCIDevice *d = &s->dev;
 164     uint8_t gvec = msi_vector(data);
 165     uint32_t gflags = msi_gflags(data, addr);
 166     int rc = 0;
 167     uint64_t table_addr = 0;
 168
 169     XEN_PT_LOG(d, "Updating MSI%s with pirq %d gvec %#x gflags %#x"
 170                " (entry: %#x)\n",
 171                is_msix ? "-X" : "", pirq, gvec, gflags, msix_entry);
 172
 173     if (is_msix) {
 174         table_addr = s->msix->mmio_base_addr;
 175     }
 176
 177     rc = xc_domain_update_msi_irq(xen_xc, xen_domid, gvec,
 178                                   pirq, gflags, table_addr);
 179
 180     if (rc) {
 181         XEN_PT_ERR(d, "Updating of MSI%s failed. (err: %d)\n",
 182                    is_msix ? "-X" : "", errno);
 183
 184         if (xc_physdev_unmap_pirq(xen_xc, xen_domid, *old_pirq)) {
 185             XEN_PT_ERR(d, "Unmapping of MSI%s pirq %d failed. (err: %d)\n",
 186                        is_msix ? "-X" : "", *old_pirq, errno);
 187         }
 188         *old_pirq = XEN_PT_UNASSIGNED_PIRQ;
 189     }
 190     return rc;
 191 }
 192
 193 static int msi_msix_disable(XenPCIPassthroughState *s,
 194                             uint64_t addr,
 195                             uint32_t data,
 196                             int pirq,
 197                             bool is_msix,
 198                             bool is_binded)
 199 {
 200     PCIDevice *d = &s->dev;
 201     uint8_t gvec = msi_vector(data);
 202     uint32_t gflags = msi_gflags(data, addr);
 203     int rc = 0;
 204
 205     if (pirq == XEN_PT_UNASSIGNED_PIRQ) {
 206         return 0;
 207     }
 208
 209     if (is_binded) {
 210         XEN_PT_LOG(d, "Unbind MSI%s with pirq %d, gvec %#x\n",
 211                    is_msix ? "-X" : "", pirq, gvec);
 212         rc = xc_domain_unbind_msi_irq(xen_xc, xen_domid, gvec, pirq, gflags);
 213         if (rc) {
 214             XEN_PT_ERR(d, "Unbinding of MSI%s failed. (err: %d, pirq: %d, gvec: %#x)\n",
 215                        is_msix ? "-X" : "", errno, pirq, gvec);
 216             return rc;
 217         }
 218     }
 219
 220     XEN_PT_LOG(d, "Unmap MSI%s pirq %d\n", is_msix ? "-X" : "", pirq);
 221     rc = xc_physdev_unmap_pirq(xen_xc, xen_domid, pirq);
 222     if (rc) {
 223         XEN_PT_ERR(d, "Unmapping of MSI%s pirq %d failed. (err: %i)\n",
 224                    is_msix ? "-X" : "", pirq, errno);
 225         return rc;
 226     }
 227
 228     return 0;
 229 }
 230
 231 /*
 232  * MSI virtualization functions
 233  */
 234
 235 static int xen_pt_msi_set_enable(XenPCIPassthroughState *s, bool enable)
 236 {
 237     XEN_PT_LOG(&s->dev, "%s MSI.\n", enable ? "enabling" : "disabling");
 238
 239     if (!s->msi) {
 240         return -1;
 241     }
 242
 243     return msi_msix_enable(s, s->msi->ctrl_offset, PCI_MSI_FLAGS_ENABLE,
 244                            enable);
 245 }
 246
 247 /* setup physical msi, but don't enable it */
 248 int xen_pt_msi_setup(XenPCIPassthroughState *s)
 249 {
 250     int pirq = XEN_PT_UNASSIGNED_PIRQ;
 251     int rc = 0;
 252     XenPTMSI *msi = s->msi;
 253
 254     if (msi->initialized) {
 255         XEN_PT_ERR(&s->dev,
 256                    "Setup physical MSI when it has been properly initialized.\n");
 257         return -1;
 258     }
 259
 260     rc = msi_msix_setup(s, msi_addr64(msi), msi->data, &pirq, false, 0, true);
 261     if (rc) {
 262         return rc;
 263     }
 264
 265     if (pirq < 0) {
 266         XEN_PT_ERR(&s->dev, "Invalid pirq number: %d.\n", pirq);
 267         return -1;
 268     }
 269
 270     msi->pirq = pirq;
 271     XEN_PT_LOG(&s->dev, "MSI mapped with pirq %d.\n", pirq);
 272
 273     return 0;
 274 }
 275
 276 int xen_pt_msi_update(XenPCIPassthroughState *s)
 277 {
 278     XenPTMSI *msi = s->msi;
 279     return msi_msix_update(s, msi_addr64(msi), msi->data, msi->pirq,
 280                            false, 0, &msi->pirq);
 281 }
 282
 283 void xen_pt_msi_disable(XenPCIPassthroughState *s)
 284 {
 285     XenPTMSI *msi = s->msi;
 286
 287     if (!msi) {
 288         return;
 289     }
 290
 291     (void)xen_pt_msi_set_enable(s, false);
 292
 293     msi_msix_disable(s, msi_addr64(msi), msi->data, msi->pirq, false,
 294                      msi->initialized);
 295
 296     /* clear msi info */
 297     msi->flags &= ~PCI_MSI_FLAGS_ENABLE;
 298     msi->initialized = false;
 299     msi->mapped = false;
 300     msi->pirq = XEN_PT_UNASSIGNED_PIRQ;
 301 }
 302
 303 /*
 304  * MSI-X virtualization functions
 305  */
 306
 307 static int msix_set_enable(XenPCIPassthroughState *s, bool enabled)
 308 {
 309     XEN_PT_LOG(&s->dev, "%s MSI-X.\n", enabled ? "enabling" : "disabling");
 310
 311     if (!s->msix) {
 312         return -1;
 313     }
 314
 315     return msi_msix_enable(s, s->msix->ctrl_offset, PCI_MSIX_FLAGS_ENABLE,
 316                            enabled);
 317 }
 318
 319 static int xen_pt_msix_update_one(XenPCIPassthroughState *s, int entry_nr,
 320                                   uint32_t vec_ctrl)
 321 {
 322     XenPTMSIXEntry *entry = NULL;
 323     int pirq;
 324     int rc;
 325
 326     if (entry_nr < 0 || entry_nr >= s->msix->total_entries) {
 327         return -EINVAL;
 328     }
 329
 330     entry = &s->msix->msix_entry[entry_nr];
 331
 332     if (!entry->updated) {
 333         return 0;
 334     }
 335
 336     pirq = entry->pirq;
 337
 338     /*
 339      * Update the entry addr and data to the latest values only when the
 340      * entry is masked or they are all masked, as required by the spec.
 341      * Addr and data changes while the MSI-X entry is unmasked get deferred
 342      * until the next masked -> unmasked transition.
 343      */
 344     if (pirq == XEN_PT_UNASSIGNED_PIRQ || s->msix->maskall ||
 345         (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)) {
 346         entry->addr = entry->latch(LOWER_ADDR) |
 347                       ((uint64_t)entry->latch(UPPER_ADDR) << 32);
 348         entry->data = entry->latch(DATA);
 349     }
 350
 351     rc = msi_msix_setup(s, entry->addr, entry->data, &pirq, true, entry_nr,
 352                         entry->pirq == XEN_PT_UNASSIGNED_PIRQ);
 353     if (rc) {
 354         return rc;
 355     }
 356     if (entry->pirq == XEN_PT_UNASSIGNED_PIRQ) {
 357         entry->pirq = pirq;
 358     }
 359
 360     rc = msi_msix_update(s, entry->addr, entry->data, pirq, true,
 361                          entry_nr, &entry->pirq);
 362
 363     if (!rc) {
 364         entry->updated = false;
 365     }
 366
 367     return rc;
 368 }
 369
 370 int xen_pt_msix_update(XenPCIPassthroughState *s)
 371 {
 372     XenPTMSIX *msix = s->msix;
 373     int i;
 374
 375     for (i = 0; i < msix->total_entries; i++) {
 376         xen_pt_msix_update_one(s, i, msix->msix_entry[i].latch(VECTOR_CTRL));
 377     }
 378
 379     return 0;
 380 }
 381
 382 void xen_pt_msix_disable(XenPCIPassthroughState *s)
 383 {
 384     int i = 0;
 385
 386     msix_set_enable(s, false);
 387
 388     for (i = 0; i < s->msix->total_entries; i++) {
 389         XenPTMSIXEntry *entry = &s->msix->msix_entry[i];
 390
 391         msi_msix_disable(s, entry->addr, entry->data, entry->pirq, true, true);
 392
 393         /* clear MSI-X info */
 394         entry->pirq = XEN_PT_UNASSIGNED_PIRQ;
 395         entry->updated = false;
 396     }
 397 }
 398
 399 int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index)
 400 {
 401     XenPTMSIXEntry *entry;
 402     int i, ret;
 403
 404     if (!(s->msix && s->msix->bar_index == bar_index)) {
 405         return 0;
 406     }
 407
 408     for (i = 0; i < s->msix->total_entries; i++) {
 409         entry = &s->msix->msix_entry[i];
 410         if (entry->pirq != XEN_PT_UNASSIGNED_PIRQ) {
 411             ret = xc_domain_unbind_pt_irq(xen_xc, xen_domid, entry->pirq,
 412                                           PT_IRQ_TYPE_MSI, 0, 0, 0, 0);
 413             if (ret) {
 414                 XEN_PT_ERR(&s->dev, "unbind MSI-X entry %d failed (err: %d)\n",
 415                            entry->pirq, errno);
 416             }
 417             entry->updated = true;
 418         }
 419     }
 420     return xen_pt_msix_update(s);
 421 }
 422
 423 static uint32_t get_entry_value(XenPTMSIXEntry *e, int offset)
 424 {
 425     assert(!(offset % sizeof(*e->latch)));
 426     return e->latch[offset / sizeof(*e->latch)];
 427 }
 428
 429 static void set_entry_value(XenPTMSIXEntry *e, int offset, uint32_t val)
 430 {
 431     assert(!(offset % sizeof(*e->latch)));
 432     e->latch[offset / sizeof(*e->latch)] = val;
 433 }
 434
 435 static void pci_msix_write(void *opaque, hwaddr addr,
 436                            uint64_t val, unsigned size)
 437 {
 438     XenPCIPassthroughState *s = opaque;
 439     XenPTMSIX *msix = s->msix;
 440     XenPTMSIXEntry *entry;
 441     unsigned int entry_nr, offset;
 442
 443     entry_nr = addr / PCI_MSIX_ENTRY_SIZE;
 444     if (entry_nr >= msix->total_entries) {
 445         return;
 446     }
 447     entry = &msix->msix_entry[entry_nr];
 448     offset = addr % PCI_MSIX_ENTRY_SIZE;
 449
 450     if (offset != PCI_MSIX_ENTRY_VECTOR_CTRL) {
 451         if (get_entry_value(entry, offset) == val
 452             && entry->pirq != XEN_PT_UNASSIGNED_PIRQ) {
 453             return;
 454         }
 455
 456         entry->updated = true;
 457     } else if (msix->enabled && entry->updated &&
 458                !(val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) {
 459         const volatile uint32_t *vec_ctrl;
 460
 461         /*
 462          * If Xen intercepts the mask bit access, entry->vec_ctrl may not be
 463          * up-to-date. Read from hardware directly.
 464          */
 465         vec_ctrl = s->msix->phys_iomem_base + entry_nr * PCI_MSIX_ENTRY_SIZE
 466             + PCI_MSIX_ENTRY_VECTOR_CTRL;
 467         xen_pt_msix_update_one(s, entry_nr, *vec_ctrl);
 468     }
 469
 470     set_entry_value(entry, offset, val);
 471 }
 472
 473 static uint64_t pci_msix_read(void *opaque, hwaddr addr,
 474                               unsigned size)
 475 {
 476     XenPCIPassthroughState *s = opaque;
 477     XenPTMSIX *msix = s->msix;
 478     int entry_nr, offset;
 479
 480     entry_nr = addr / PCI_MSIX_ENTRY_SIZE;
 481     if (entry_nr < 0) {
 482         XEN_PT_ERR(&s->dev, "asked MSI-X entry '%i' invalid!\n", entry_nr);
 483         return 0;
 484     }
 485
 486     offset = addr % PCI_MSIX_ENTRY_SIZE;
 487
 488     if (addr < msix->total_entries * PCI_MSIX_ENTRY_SIZE) {
 489         return get_entry_value(&msix->msix_entry[entry_nr], offset);
 490     } else {
 491         /* Pending Bit Array (PBA) */
 492         return *(uint32_t *)(msix->phys_iomem_base + addr);
 493     }
 494 }
 495
 496 static bool pci_msix_accepts(void *opaque, hwaddr addr,
 497                              unsigned size, bool is_write)
 498 {
 499     return !(addr & (size - 1));
 500 }
 501
 502 static const MemoryRegionOps pci_msix_ops = {
 503     .read = pci_msix_read,
 504     .write = pci_msix_write,
 505     .endianness = DEVICE_NATIVE_ENDIAN,
 506     .valid = {
 507         .min_access_size = 4,
 508         .max_access_size = 4,
 509         .unaligned = false,
 510         .accepts = pci_msix_accepts
 511     },
 512     .impl = {
 513         .min_access_size = 4,
 514         .max_access_size = 4,
 515         .unaligned = false
 516     }
 517 };
 518
 519 int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base)
 520 {
 521     uint8_t id = 0;
 522     uint16_t control = 0;
 523     uint32_t table_off = 0;
 524     int i, total_entries, bar_index;
 525     XenHostPCIDevice *hd = &s->real_device;
 526     PCIDevice *d = &s->dev;
 527     int fd = -1;
 528     XenPTMSIX *msix = NULL;
 529     int rc = 0;
 530
 531     rc = xen_host_pci_get_byte(hd, base + PCI_CAP_LIST_ID, &id);
 532     if (rc) {
 533         return rc;
 534     }
 535
 536     if (id != PCI_CAP_ID_MSIX) {
 537         XEN_PT_ERR(d, "Invalid id %#x base %#x\n", id, base);
 538         return -1;
 539     }
 540
 541     xen_host_pci_get_word(hd, base + PCI_MSIX_FLAGS, &control);
 542     total_entries = control & PCI_MSIX_FLAGS_QSIZE;
 543     total_entries += 1;
 544
 545     s->msix = g_malloc0(sizeof (XenPTMSIX)
 546                         + total_entries * sizeof (XenPTMSIXEntry));
 547     msix = s->msix;
 548
 549     msix->total_entries = total_entries;
 550     for (i = 0; i < total_entries; i++) {
 551         msix->msix_entry[i].pirq = XEN_PT_UNASSIGNED_PIRQ;
 552     }
 553
 554     memory_region_init_io(&msix->mmio, OBJECT(s), &pci_msix_ops,
 555                           s, "xen-pci-pt-msix",
 556                           (total_entries * PCI_MSIX_ENTRY_SIZE
 557                            + XC_PAGE_SIZE - 1)
 558                           & XC_PAGE_MASK);
 559
 560     xen_host_pci_get_long(hd, base + PCI_MSIX_TABLE, &table_off);
 561     bar_index = msix->bar_index = table_off & PCI_MSIX_FLAGS_BIRMASK;
 562     table_off = table_off & ~PCI_MSIX_FLAGS_BIRMASK;
 563     msix->table_base = s->real_device.io_regions[bar_index].base_addr;
 564     XEN_PT_LOG(d, "get MSI-X table BAR base 0x%"PRIx64"\n", msix->table_base);
 565
 566     fd = open("/dev/mem", O_RDWR);
 567     if (fd == -1) {
 568         rc = -errno;
 569         XEN_PT_ERR(d, "Can't open /dev/mem: %s\n", strerror(errno));
 570         goto error_out;
 571     }
 572     XEN_PT_LOG(d, "table_off = %#x, total_entries = %d\n",
 573                table_off, total_entries);
 574     msix->table_offset_adjust = table_off & 0x0fff;
 575     msix->phys_iomem_base =
 576         mmap(NULL,
 577              total_entries * PCI_MSIX_ENTRY_SIZE + msix->table_offset_adjust,
 578              PROT_READ,
 579              MAP_SHARED | MAP_LOCKED,
 580              fd,
 581              msix->table_base + table_off - msix->table_offset_adjust);
 582     close(fd);
 583     if (msix->phys_iomem_base == MAP_FAILED) {
 584         rc = -errno;
 585         XEN_PT_ERR(d, "Can't map physical MSI-X table: %s\n", strerror(errno));
 586         goto error_out;
 587     }
 588     msix->phys_iomem_base = (char *)msix->phys_iomem_base
 589         + msix->table_offset_adjust;
 590
 591     XEN_PT_LOG(d, "mapping physical MSI-X table to %p\n",
 592                msix->phys_iomem_base);
 593
 594     memory_region_add_subregion_overlap(&s->bar[bar_index], table_off,
 595                                         &msix->mmio,
 596                                         2); /* Priority: pci default + 1 */
 597
 598     return 0;
 599
 600 error_out:
 601     g_free(s->msix);
 602     s->msix = NULL;
 603     return rc;
 604 }
 605
 606 void xen_pt_msix_unmap(XenPCIPassthroughState *s)
 607 {
 608     XenPTMSIX *msix = s->msix;
 609
 610     if (!msix) {
 611         return;
 612     }
 613
 614     /* unmap the MSI-X memory mapped register area */
 615     if (msix->phys_iomem_base) {
 616         XEN_PT_LOG(&s->dev, "unmapping physical MSI-X table from %p\n",
 617                    msix->phys_iomem_base);
 618         munmap(msix->phys_iomem_base, msix->total_entries * PCI_MSIX_ENTRY_SIZE
 619                + msix->table_offset_adjust);
 620     }
 621
 622     memory_region_del_subregion(&s->bar[msix->bar_index], &msix->mmio);
 623 }
 624
 625 void xen_pt_msix_delete(XenPCIPassthroughState *s)
 626 {
 627     XenPTMSIX *msix = s->msix;
 628
 629     if (!msix) {
 630         return;
 631     }
 632
 633     object_unparent(OBJECT(&msix->mmio));
 634
 635     g_free(s->msix);
 636     s->msix = NULL;
 637 }