tests/tcg/xtensa/fpu.h

   1 #if XCHAL_HAVE_DFP || XCHAL_HAVE_FP_DIV
   2 #define DFPU 1
   3 #else
   4 #define DFPU 0
   5 #endif
   6
   7 #define FCR_RM_NEAREST 0
   8 #define FCR_RM_TRUNC   1
   9 #define FCR_RM_CEIL    2
  10 #define FCR_RM_FLOOR   3
  11
  12 #define FSR__ 0x00000000
  13 #define FSR_I 0x00000080
  14 #define FSR_U 0x00000100
  15 #define FSR_O 0x00000200
  16 #define FSR_Z 0x00000400
  17 #define FSR_V 0x00000800
  18
  19 #define FSR_UI (FSR_U | FSR_I)
  20 #define FSR_OI (FSR_O | FSR_I)
  21
  22 #define F32_0           0x00000000
  23 #define F32_0_5         0x3f000000
  24 #define F32_1           0x3f800000
  25 #define F32_MAX         0x7f7fffff
  26 #define F32_PINF        0x7f800000
  27 #define F32_NINF        0xff800000
  28
  29 #define F32_DNAN        0x7fc00000
  30 #define F32_SNAN(v)     (0x7f800000 | (v))
  31 #define F32_QNAN(v)     (0x7fc00000 | (v))
  32
  33 #define F32_MINUS       0x80000000
  34
  35 #define F64_0           0x0000000000000000
  36 #define F64_MIN_NORM    0x0010000000000000
  37 #define F64_1           0x3ff0000000000000
  38 #define F64_MAX_2       0x7fe0000000000000
  39 #define F64_MAX         0x7fefffffffffffff
  40 #define F64_PINF        0x7ff0000000000000
  41 #define F64_NINF        0xfff0000000000000
  42
  43 #define F64_DNAN        0x7ff8000000000000
  44 #define F64_SNAN(v)     (0x7ff0000000000000 | (v))
  45 #define F64_QNAN(v)     (0x7ff8000000000000 | (v))
  46
  47 #define F64_MINUS       0x8000000000000000
  48
  49 .macro test_op1_rm op, fr0, fr1, v0, r, sr
  50     movi    a2, 0
  51     wur     a2, fsr
  52     movfp   \fr0, \v0
  53     \op     \fr1, \fr0
  54     check_res \fr1, \r, \sr
  55 .endm
  56
  57 .macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr
  58     movi    a2, 0
  59     wur     a2, fsr
  60     movfp   \fr0, \v0
  61     movfp   \fr1, \v1
  62     \op     \fr2, \fr0, \fr1
  63     check_res \fr2, \r, \sr
  64 .endm
  65
  66 .macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r, sr
  67     movi    a2, 0
  68     wur     a2, fsr
  69     movfp   \fr0, \v0
  70     movfp   \fr1, \v1
  71     movfp   \fr2, \v2
  72     \op     \fr0, \fr1, \fr2
  73     check_res \fr3, \r, \sr
  74 .endm
  75
  76 .macro test_op1_ex op, fr0, fr1, v0, rm, r, sr
  77     movi    a2, \rm
  78     wur     a2, fcr
  79     test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
  80     movi    a2, (\rm) | 0x7c
  81     wur     a2, fcr
  82     test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
  83 .endm
  84
  85 .macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r, sr
  86     movi    a2, \rm
  87     wur     a2, fcr
  88     test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr
  89     movi    a2, (\rm) | 0x7c
  90     wur     a2, fcr
  91     test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr
  92 .endm
  93
  94 .macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r, sr
  95     movi    a2, \rm
  96     wur     a2, fcr
  97     test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr
  98     movi    a2, (\rm) | 0x7c
  99     wur     a2, fcr
 100     test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr
 101 .endm
 102
 103 .macro test_op1 op, fr0, fr1, v0, r0, r1, r2, r3, sr0, sr1, sr2, sr3
 104     test_op1_ex \op, \fr0, \fr1, \v0, 0, \r0, \sr0
 105     test_op1_ex \op, \fr0, \fr1, \v0, 1, \r1, \sr1
 106     test_op1_ex \op, \fr0, \fr1, \v0, 2, \r2, \sr2
 107     test_op1_ex \op, \fr0, \fr1, \v0, 3, \r3, \sr3
 108 .endm
 109
 110 .macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3, sr0, sr1, sr2, sr3
 111     test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0, \sr0
 112     test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1, \sr1
 113     test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2, \sr2
 114     test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3, \sr3
 115 .endm
 116
 117 .macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3, sr0, sr1, sr2, sr3
 118     test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0, \sr0
 119     test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1, \sr1
 120     test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2, \sr2
 121     test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3, \sr3
 122 .endm
 123
 124 .macro test_op2_cpe op
 125     set_vector  kernel, 2f
 126     movi    a2, 0
 127     wsr     a2, cpenable
 128 1:
 129     \op     f2, f0, f1
 130     test_fail
 131 2:
 132     rsr     a2, excvaddr
 133     movi    a3, 1b
 134     assert  eq, a2, a3
 135     rsr     a2, exccause
 136     movi    a3, 32
 137     assert  eq, a2, a3
 138
 139     set_vector  kernel, 0
 140     movi    a2, 1
 141     wsr     a2, cpenable
 142 .endm