target/mips: Declare generic FPU / Coprocessor functions in translate.h
[qemu/ar7.git] / hw / mips / boston.c
blob467fbc1c8be7b15e039a526bd42fe85d09a8fb92
1 /*
2 * MIPS Boston development board emulation.
4 * Copyright (c) 2016 Imagination Technologies
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
23 #include "exec/address-spaces.h"
24 #include "hw/boards.h"
25 #include "hw/char/serial.h"
26 #include "hw/ide/pci.h"
27 #include "hw/ide/ahci.h"
28 #include "hw/loader.h"
29 #include "hw/loader-fit.h"
30 #include "hw/mips/cps.h"
31 #include "hw/pci-host/xilinx-pcie.h"
32 #include "hw/qdev-clock.h"
33 #include "hw/qdev-properties.h"
34 #include "qapi/error.h"
35 #include "qemu/error-report.h"
36 #include "qemu/log.h"
37 #include "chardev/char.h"
38 #include "sysemu/device_tree.h"
39 #include "sysemu/sysemu.h"
40 #include "sysemu/qtest.h"
41 #include "sysemu/runstate.h"
43 #include <libfdt.h>
44 #include "qom/object.h"
46 #define TYPE_BOSTON "mips-boston"
47 typedef struct BostonState BostonState;
48 DECLARE_INSTANCE_CHECKER(BostonState, BOSTON,
49 TYPE_BOSTON)
51 struct BostonState {
52 SysBusDevice parent_obj;
54 MachineState *mach;
55 MIPSCPSState cps;
56 SerialMM *uart;
57 Clock *cpuclk;
59 CharBackend lcd_display;
60 char lcd_content[8];
61 bool lcd_inited;
63 hwaddr kernel_entry;
64 hwaddr fdt_base;
67 enum boston_plat_reg {
68 PLAT_FPGA_BUILD = 0x00,
69 PLAT_CORE_CL = 0x04,
70 PLAT_WRAPPER_CL = 0x08,
71 PLAT_SYSCLK_STATUS = 0x0c,
72 PLAT_SOFTRST_CTL = 0x10,
73 #define PLAT_SOFTRST_CTL_SYSRESET (1 << 4)
74 PLAT_DDR3_STATUS = 0x14,
75 #define PLAT_DDR3_STATUS_LOCKED (1 << 0)
76 #define PLAT_DDR3_STATUS_CALIBRATED (1 << 2)
77 PLAT_PCIE_STATUS = 0x18,
78 #define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0)
79 #define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8)
80 #define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16)
81 PLAT_FLASH_CTL = 0x1c,
82 PLAT_SPARE0 = 0x20,
83 PLAT_SPARE1 = 0x24,
84 PLAT_SPARE2 = 0x28,
85 PLAT_SPARE3 = 0x2c,
86 PLAT_MMCM_DIV = 0x30,
87 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0
88 #define PLAT_MMCM_DIV_INPUT_SHIFT 8
89 #define PLAT_MMCM_DIV_MUL_SHIFT 16
90 #define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24
91 PLAT_BUILD_CFG = 0x34,
92 #define PLAT_BUILD_CFG_IOCU_EN (1 << 0)
93 #define PLAT_BUILD_CFG_PCIE0_EN (1 << 1)
94 #define PLAT_BUILD_CFG_PCIE1_EN (1 << 2)
95 #define PLAT_BUILD_CFG_PCIE2_EN (1 << 3)
96 PLAT_DDR_CFG = 0x38,
97 #define PLAT_DDR_CFG_SIZE (0xf << 0)
98 #define PLAT_DDR_CFG_MHZ (0xfff << 4)
99 PLAT_NOC_PCIE0_ADDR = 0x3c,
100 PLAT_NOC_PCIE1_ADDR = 0x40,
101 PLAT_NOC_PCIE2_ADDR = 0x44,
102 PLAT_SYS_CTL = 0x48,
105 static void boston_lcd_event(void *opaque, QEMUChrEvent event)
107 BostonState *s = opaque;
108 if (event == CHR_EVENT_OPENED && !s->lcd_inited) {
109 qemu_chr_fe_printf(&s->lcd_display, " ");
110 s->lcd_inited = true;
114 static uint64_t boston_lcd_read(void *opaque, hwaddr addr,
115 unsigned size)
117 BostonState *s = opaque;
118 uint64_t val = 0;
120 switch (size) {
121 case 8:
122 val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56;
123 val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48;
124 val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40;
125 val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32;
126 /* fall through */
127 case 4:
128 val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24;
129 val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16;
130 /* fall through */
131 case 2:
132 val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8;
133 /* fall through */
134 case 1:
135 val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7];
136 break;
139 return val;
142 static void boston_lcd_write(void *opaque, hwaddr addr,
143 uint64_t val, unsigned size)
145 BostonState *s = opaque;
147 switch (size) {
148 case 8:
149 s->lcd_content[(addr + 7) & 0x7] = val >> 56;
150 s->lcd_content[(addr + 6) & 0x7] = val >> 48;
151 s->lcd_content[(addr + 5) & 0x7] = val >> 40;
152 s->lcd_content[(addr + 4) & 0x7] = val >> 32;
153 /* fall through */
154 case 4:
155 s->lcd_content[(addr + 3) & 0x7] = val >> 24;
156 s->lcd_content[(addr + 2) & 0x7] = val >> 16;
157 /* fall through */
158 case 2:
159 s->lcd_content[(addr + 1) & 0x7] = val >> 8;
160 /* fall through */
161 case 1:
162 s->lcd_content[(addr + 0) & 0x7] = val;
163 break;
166 qemu_chr_fe_printf(&s->lcd_display,
167 "\r%-8.8s", s->lcd_content);
170 static const MemoryRegionOps boston_lcd_ops = {
171 .read = boston_lcd_read,
172 .write = boston_lcd_write,
173 .endianness = DEVICE_NATIVE_ENDIAN,
176 static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
177 unsigned size)
179 BostonState *s = opaque;
180 uint32_t gic_freq, val;
182 if (size != 4) {
183 qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size);
184 return 0;
187 switch (addr & 0xffff) {
188 case PLAT_FPGA_BUILD:
189 case PLAT_CORE_CL:
190 case PLAT_WRAPPER_CL:
191 return 0;
192 case PLAT_DDR3_STATUS:
193 return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED;
194 case PLAT_MMCM_DIV:
195 gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000;
196 val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT;
197 val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT;
198 val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT;
199 val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT;
200 return val;
201 case PLAT_BUILD_CFG:
202 val = PLAT_BUILD_CFG_PCIE0_EN;
203 val |= PLAT_BUILD_CFG_PCIE1_EN;
204 val |= PLAT_BUILD_CFG_PCIE2_EN;
205 return val;
206 case PLAT_DDR_CFG:
207 val = s->mach->ram_size / GiB;
208 assert(!(val & ~PLAT_DDR_CFG_SIZE));
209 val |= PLAT_DDR_CFG_MHZ;
210 return val;
211 default:
212 qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n",
213 addr & 0xffff);
214 return 0;
218 static void boston_platreg_write(void *opaque, hwaddr addr,
219 uint64_t val, unsigned size)
221 if (size != 4) {
222 qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size);
223 return;
226 switch (addr & 0xffff) {
227 case PLAT_FPGA_BUILD:
228 case PLAT_CORE_CL:
229 case PLAT_WRAPPER_CL:
230 case PLAT_DDR3_STATUS:
231 case PLAT_PCIE_STATUS:
232 case PLAT_MMCM_DIV:
233 case PLAT_BUILD_CFG:
234 case PLAT_DDR_CFG:
235 /* read only */
236 break;
237 case PLAT_SOFTRST_CTL:
238 if (val & PLAT_SOFTRST_CTL_SYSRESET) {
239 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
241 break;
242 default:
243 qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx
244 " = 0x%" PRIx64 "\n", addr & 0xffff, val);
245 break;
249 static const MemoryRegionOps boston_platreg_ops = {
250 .read = boston_platreg_read,
251 .write = boston_platreg_write,
252 .endianness = DEVICE_NATIVE_ENDIAN,
255 static void mips_boston_instance_init(Object *obj)
257 BostonState *s = BOSTON(obj);
259 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
260 clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */
263 static const TypeInfo boston_device = {
264 .name = TYPE_BOSTON,
265 .parent = TYPE_SYS_BUS_DEVICE,
266 .instance_size = sizeof(BostonState),
267 .instance_init = mips_boston_instance_init,
270 static void boston_register_types(void)
272 type_register_static(&boston_device);
274 type_init(boston_register_types)
276 static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
277 bool is_64b)
279 const uint32_t cm_base = 0x16100000;
280 const uint32_t gic_base = 0x16120000;
281 const uint32_t cpc_base = 0x16200000;
283 /* Move CM GCRs */
284 if (is_64b) {
285 stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */
286 stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */
287 } else {
288 stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */
289 stl_p(p++, 0x00084100); /* sll $8, $8, 4 */
291 stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */
292 stl_p(p++, 0x01094025); /* or $8, $9 */
293 stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */
294 if (is_64b) {
295 stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */
296 } else {
297 stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */
299 stl_p(p++, 0x012a4025); /* or $8, $10 */
301 /* Move & enable GIC GCRs */
302 stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */
303 stl_p(p++, 0x35290001); /* ori $9, 0x1 */
304 if (is_64b) {
305 stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */
306 } else {
307 stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */
310 /* Move & enable CPC GCRs */
311 stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */
312 stl_p(p++, 0x35290001); /* ori $9, 0x1 */
313 if (is_64b) {
314 stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */
315 } else {
316 stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */
320 * Setup argument registers to follow the UHI boot protocol:
322 * a0/$4 = -2
323 * a1/$5 = virtual address of FDT
324 * a2/$6 = 0
325 * a3/$7 = 0
327 stl_p(p++, 0x2404fffe); /* li $4, -2 */
328 /* lui $5, hi(fdt_addr) */
329 stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff));
330 if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */
331 stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff));
333 stl_p(p++, 0x34060000); /* li $6, 0 */
334 stl_p(p++, 0x34070000); /* li $7, 0 */
336 /* Load kernel entry address & jump to it */
337 /* lui $25, hi(kernel_entry) */
338 stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff));
339 /* ori $25, lo(kernel_entry) */
340 stl_p(p++, 0x37390000 | (kernel_entry & 0xffff));
341 stl_p(p++, 0x03200009); /* jr $25 */
344 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
345 const void *match_data, hwaddr *load_addr)
347 BostonState *s = BOSTON(opaque);
348 MachineState *machine = s->mach;
349 const char *cmdline;
350 int err;
351 size_t ram_low_sz, ram_high_sz;
352 size_t fdt_sz = fdt_totalsize(fdt_orig) * 2;
353 g_autofree void *fdt = g_malloc0(fdt_sz);
355 err = fdt_open_into(fdt_orig, fdt, fdt_sz);
356 if (err) {
357 fprintf(stderr, "unable to open FDT\n");
358 return NULL;
361 cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0])
362 ? machine->kernel_cmdline : " ";
363 err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
364 if (err < 0) {
365 fprintf(stderr, "couldn't set /chosen/bootargs\n");
366 return NULL;
369 ram_low_sz = MIN(256 * MiB, machine->ram_size);
370 ram_high_sz = machine->ram_size - ram_low_sz;
371 qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
372 1, 0x00000000, 1, ram_low_sz,
373 1, 0x90000000, 1, ram_high_sz);
375 fdt = g_realloc(fdt, fdt_totalsize(fdt));
376 qemu_fdt_dumpdtb(fdt, fdt_sz);
378 s->fdt_base = *load_addr;
380 return g_steal_pointer(&fdt);
383 static const void *boston_kernel_filter(void *opaque, const void *kernel,
384 hwaddr *load_addr, hwaddr *entry_addr)
386 BostonState *s = BOSTON(opaque);
388 s->kernel_entry = *entry_addr;
390 return kernel;
393 static const struct fit_loader_match boston_matches[] = {
394 { "img,boston" },
395 { NULL },
398 static const struct fit_loader boston_fit_loader = {
399 .matches = boston_matches,
400 .addr_to_phys = cpu_mips_kseg0_to_phys,
401 .fdt_filter = boston_fdt_filter,
402 .kernel_filter = boston_kernel_filter,
405 static inline XilinxPCIEHost *
406 xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
407 hwaddr cfg_base, uint64_t cfg_size,
408 hwaddr mmio_base, uint64_t mmio_size,
409 qemu_irq irq, bool link_up)
411 DeviceState *dev;
412 MemoryRegion *cfg, *mmio;
414 dev = qdev_new(TYPE_XILINX_PCIE_HOST);
416 qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
417 qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
418 qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
419 qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
420 qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
421 qdev_prop_set_bit(dev, "link_up", link_up);
423 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
425 cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
426 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
428 mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
429 memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
431 qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
433 return XILINX_PCIE_HOST(dev);
436 static void boston_mach_init(MachineState *machine)
438 DeviceState *dev;
439 BostonState *s;
440 MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg;
441 MemoryRegion *sys_mem = get_system_memory();
442 XilinxPCIEHost *pcie2;
443 PCIDevice *ahci;
444 DriveInfo *hd[6];
445 Chardev *chr;
446 int fw_size, fit_err;
448 if ((machine->ram_size % GiB) ||
449 (machine->ram_size > (2 * GiB))) {
450 error_report("Memory size must be 1GB or 2GB");
451 exit(1);
454 dev = qdev_new(TYPE_BOSTON);
455 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
457 s = BOSTON(dev);
458 s->mach = machine;
460 if (!cpu_type_supports_cps_smp(machine->cpu_type)) {
461 error_report("Boston requires CPUs which support CPS");
462 exit(1);
465 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
466 object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
467 &error_fatal);
468 object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus,
469 &error_fatal);
470 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in",
471 qdev_get_clock_out(dev, "cpu-refclk"));
472 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
474 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
476 flash = g_new(MemoryRegion, 1);
477 memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
478 &error_fatal);
479 memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
481 memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
483 ddr_low_alias = g_new(MemoryRegion, 1);
484 memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
485 machine->ram, 0,
486 MIN(machine->ram_size, (256 * MiB)));
487 memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
489 xilinx_pcie_init(sys_mem, 0,
490 0x10000000, 32 * MiB,
491 0x40000000, 1 * GiB,
492 get_cps_irq(&s->cps, 2), false);
494 xilinx_pcie_init(sys_mem, 1,
495 0x12000000, 32 * MiB,
496 0x20000000, 512 * MiB,
497 get_cps_irq(&s->cps, 1), false);
499 pcie2 = xilinx_pcie_init(sys_mem, 2,
500 0x14000000, 32 * MiB,
501 0x16000000, 1 * MiB,
502 get_cps_irq(&s->cps, 0), true);
504 platreg = g_new(MemoryRegion, 1);
505 memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
506 "boston-platregs", 0x1000);
507 memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
509 s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
510 get_cps_irq(&s->cps, 3), 10000000,
511 serial_hd(0), DEVICE_NATIVE_ENDIAN);
513 lcd = g_new(MemoryRegion, 1);
514 memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
515 memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
517 chr = qemu_chr_new("lcd", "vc:320x240", NULL);
518 qemu_chr_fe_init(&s->lcd_display, chr, NULL);
519 qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL,
520 boston_lcd_event, NULL, s, NULL, true);
522 ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus,
523 PCI_DEVFN(0, 0),
524 true, TYPE_ICH9_AHCI);
525 g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci));
526 ide_drive_get(hd, ahci_get_num_ports(ahci));
527 ahci_ide_create_devs(ahci, hd);
529 if (machine->firmware) {
530 fw_size = load_image_targphys(machine->firmware,
531 0x1fc00000, 4 * MiB);
532 if (fw_size == -1) {
533 error_report("unable to load firmware image '%s'",
534 machine->firmware);
535 exit(1);
537 } else if (machine->kernel_filename) {
538 fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s);
539 if (fit_err) {
540 error_report("unable to load FIT image");
541 exit(1);
544 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
545 s->kernel_entry, s->fdt_base,
546 cpu_type_is_64bit(machine->cpu_type));
547 } else if (!qtest_enabled()) {
548 error_report("Please provide either a -kernel or -bios argument");
549 exit(1);
553 static void boston_mach_class_init(MachineClass *mc)
555 mc->desc = "MIPS Boston";
556 mc->init = boston_mach_init;
557 mc->block_default_type = IF_IDE;
558 mc->default_ram_size = 1 * GiB;
559 mc->default_ram_id = "boston.ddr";
560 mc->max_cpus = 16;
561 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
564 DEFINE_MACHINE("boston", boston_mach_class_init)