hw/lm32/lm32_boards.c

   1 /*
   2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/units.h"
  22 #include "qemu/cutils.h"
  23 #include "qemu/error-report.h"
  24 #include "cpu.h"
  25 #include "hw/sysbus.h"
  26 #include "hw/irq.h"
  27 #include "hw/block/flash.h"
  28 #include "hw/boards.h"
  29 #include "hw/loader.h"
  30 #include "elf.h"
  31 #include "lm32_hwsetup.h"
  32 #include "lm32.h"
  33 #include "exec/address-spaces.h"
  34 #include "sysemu/reset.h"
  35 #include "sysemu/sysemu.h"
  36
  37 typedef struct {
  38     LM32CPU *cpu;
  39     hwaddr bootstrap_pc;
  40     hwaddr flash_base;
  41     hwaddr hwsetup_base;
  42     hwaddr initrd_base;
  43     size_t initrd_size;
  44     hwaddr cmdline_base;
  45 } ResetInfo;
  46
  47 static void cpu_irq_handler(void *opaque, int irq, int level)
  48 {
  49     LM32CPU *cpu = opaque;
  50     CPUState *cs = CPU(cpu);
  51
  52     if (level) {
  53         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  54     } else {
  55         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  56     }
  57 }
  58
  59 static void main_cpu_reset(void *opaque)
  60 {
  61     ResetInfo *reset_info = opaque;
  62     CPULM32State *env = &reset_info->cpu->env;
  63
  64     cpu_reset(CPU(reset_info->cpu));
  65
  66     /* init defaults */
  67     env->pc = (uint32_t)reset_info->bootstrap_pc;
  68     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
  69     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
  70     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
  71     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
  72         reset_info->initrd_size);
  73     env->eba = reset_info->flash_base;
  74     env->deba = reset_info->flash_base;
  75 }
  76
  77 static void lm32_evr_init(MachineState *machine)
  78 {
  79     MachineClass *mc = MACHINE_GET_CLASS(machine);
  80     const char *kernel_filename = machine->kernel_filename;
  81     LM32CPU *cpu;
  82     CPULM32State *env;
  83     DriveInfo *dinfo;
  84     MemoryRegion *address_space_mem =  get_system_memory();
  85     qemu_irq irq[32];
  86     ResetInfo *reset_info;
  87     int i;
  88
  89     if (machine->ram_size != mc->default_ram_size) {
  90         char *sz = size_to_str(mc->default_ram_size);
  91         error_report("Invalid RAM size, should be %s", sz);
  92         g_free(sz);
  93         exit(EXIT_FAILURE);
  94     }
  95
  96     /* memory map */
  97     hwaddr flash_base  = 0x04000000;
  98     size_t flash_sector_size       = 256 * KiB;
  99     size_t flash_size              = 32 * MiB;
 100     hwaddr ram_base    = 0x08000000;
 101     hwaddr timer0_base = 0x80002000;
 102     hwaddr uart0_base  = 0x80006000;
 103     hwaddr timer1_base = 0x8000a000;
 104     int uart0_irq                  = 0;
 105     int timer0_irq                 = 1;
 106     int timer1_irq                 = 3;
 107
 108     reset_info = g_malloc0(sizeof(ResetInfo));
 109
 110     cpu = LM32_CPU(cpu_create(machine->cpu_type));
 111
 112     env = &cpu->env;
 113     reset_info->cpu = cpu;
 114
 115     reset_info->flash_base = flash_base;
 116
 117     memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
 118
 119     dinfo = drive_get(IF_PFLASH, 0, 0);
 120     /* Spansion S29NS128P */
 121     pflash_cfi02_register(flash_base, "lm32_evr.flash", flash_size,
 122                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 123                           flash_sector_size,
 124                           1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 125
 126     /* create irq lines */
 127     env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
 128     for (i = 0; i < 32; i++) {
 129         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 130     }
 131
 132     lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
 133     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 134     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 135
 136     /* make sure juart isn't the first chardev */
 137     env->juart_state = lm32_juart_init(serial_hd(1));
 138
 139     reset_info->bootstrap_pc = flash_base;
 140
 141     if (kernel_filename) {
 142         uint64_t entry;
 143         int kernel_size;
 144
 145         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 146                                &entry, NULL, NULL, NULL,
 147                                1, EM_LATTICEMICO32, 0, 0);
 148         reset_info->bootstrap_pc = entry;
 149
 150         if (kernel_size < 0) {
 151             kernel_size = load_image_targphys(kernel_filename, ram_base,
 152                                               machine->ram_size);
 153             reset_info->bootstrap_pc = ram_base;
 154         }
 155
 156         if (kernel_size < 0) {
 157             error_report("could not load kernel '%s'", kernel_filename);
 158             exit(1);
 159         }
 160     }
 161
 162     qemu_register_reset(main_cpu_reset, reset_info);
 163 }
 164
 165 static void lm32_uclinux_init(MachineState *machine)
 166 {
 167     MachineClass *mc = MACHINE_GET_CLASS(machine);
 168     const char *kernel_filename = machine->kernel_filename;
 169     const char *kernel_cmdline = machine->kernel_cmdline;
 170     const char *initrd_filename = machine->initrd_filename;
 171     LM32CPU *cpu;
 172     CPULM32State *env;
 173     DriveInfo *dinfo;
 174     MemoryRegion *address_space_mem =  get_system_memory();
 175     qemu_irq irq[32];
 176     HWSetup *hw;
 177     ResetInfo *reset_info;
 178     int i;
 179
 180     if (machine->ram_size != mc->default_ram_size) {
 181         char *sz = size_to_str(mc->default_ram_size);
 182         error_report("Invalid RAM size, should be %s", sz);
 183         g_free(sz);
 184         exit(EXIT_FAILURE);
 185     }
 186
 187     /* memory map */
 188     hwaddr flash_base   = 0x04000000;
 189     size_t flash_sector_size        = 256 * KiB;
 190     size_t flash_size               = 32 * MiB;
 191     hwaddr ram_base     = 0x08000000;
 192     hwaddr uart0_base   = 0x80000000;
 193     hwaddr timer0_base  = 0x80002000;
 194     hwaddr timer1_base  = 0x80010000;
 195     hwaddr timer2_base  = 0x80012000;
 196     int uart0_irq                   = 0;
 197     int timer0_irq                  = 1;
 198     int timer1_irq                  = 20;
 199     int timer2_irq                  = 21;
 200     hwaddr hwsetup_base = 0x0bffe000;
 201     hwaddr cmdline_base = 0x0bfff000;
 202     hwaddr initrd_base  = 0x08400000;
 203     size_t initrd_max               = 0x01000000;
 204
 205     reset_info = g_malloc0(sizeof(ResetInfo));
 206
 207     cpu = LM32_CPU(cpu_create(machine->cpu_type));
 208
 209     env = &cpu->env;
 210     reset_info->cpu = cpu;
 211
 212     reset_info->flash_base = flash_base;
 213
 214     memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
 215
 216     dinfo = drive_get(IF_PFLASH, 0, 0);
 217     /* Spansion S29NS128P */
 218     pflash_cfi02_register(flash_base, "lm32_uclinux.flash", flash_size,
 219                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 220                           flash_sector_size,
 221                           1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 222
 223     /* create irq lines */
 224     env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
 225     for (i = 0; i < 32; i++) {
 226         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 227     }
 228
 229     lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0));
 230     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 231     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 232     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
 233
 234     /* make sure juart isn't the first chardev */
 235     env->juart_state = lm32_juart_init(serial_hd(1));
 236
 237     reset_info->bootstrap_pc = flash_base;
 238
 239     if (kernel_filename) {
 240         uint64_t entry;
 241         int kernel_size;
 242
 243         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 244                                &entry, NULL, NULL, NULL,
 245                                1, EM_LATTICEMICO32, 0, 0);
 246         reset_info->bootstrap_pc = entry;
 247
 248         if (kernel_size < 0) {
 249             kernel_size = load_image_targphys(kernel_filename, ram_base,
 250                                               machine->ram_size);
 251             reset_info->bootstrap_pc = ram_base;
 252         }
 253
 254         if (kernel_size < 0) {
 255             error_report("could not load kernel '%s'", kernel_filename);
 256             exit(1);
 257         }
 258     }
 259
 260     /* generate a rom with the hardware description */
 261     hw = hwsetup_init();
 262     hwsetup_add_cpu(hw, "LM32", 75000000);
 263     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
 264     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, machine->ram_size);
 265     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
 266     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
 267     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
 268     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
 269     hwsetup_add_trailer(hw);
 270     hwsetup_create_rom(hw, hwsetup_base);
 271     hwsetup_free(hw);
 272
 273     reset_info->hwsetup_base = hwsetup_base;
 274
 275     if (kernel_cmdline && strlen(kernel_cmdline)) {
 276         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 277                 kernel_cmdline);
 278         reset_info->cmdline_base = cmdline_base;
 279     }
 280
 281     if (initrd_filename) {
 282         size_t initrd_size;
 283         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 284                 initrd_max);
 285         reset_info->initrd_base = initrd_base;
 286         reset_info->initrd_size = initrd_size;
 287     }
 288
 289     qemu_register_reset(main_cpu_reset, reset_info);
 290 }
 291
 292 static void lm32_evr_class_init(ObjectClass *oc, void *data)
 293 {
 294     MachineClass *mc = MACHINE_CLASS(oc);
 295
 296     mc->desc = "LatticeMico32 EVR32 eval system";
 297     mc->init = lm32_evr_init;
 298     mc->is_default = true;
 299     mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
 300     mc->default_ram_size = 64 * MiB;
 301     mc->default_ram_id = "lm32_evr.sdram";
 302 }
 303
 304 static const TypeInfo lm32_evr_type = {
 305     .name = MACHINE_TYPE_NAME("lm32-evr"),
 306     .parent = TYPE_MACHINE,
 307     .class_init = lm32_evr_class_init,
 308 };
 309
 310 static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
 311 {
 312     MachineClass *mc = MACHINE_CLASS(oc);
 313
 314     mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
 315     mc->init = lm32_uclinux_init;
 316     mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full");
 317     mc->default_ram_size = 64 * MiB;
 318     mc->default_ram_id = "lm32_uclinux.sdram";
 319 }
 320
 321 static const TypeInfo lm32_uclinux_type = {
 322     .name = MACHINE_TYPE_NAME("lm32-uclinux"),
 323     .parent = TYPE_MACHINE,
 324     .class_init = lm32_uclinux_class_init,
 325 };
 326
 327 static void lm32_machine_init(void)
 328 {
 329     type_register_static(&lm32_evr_type);
 330     type_register_static(&lm32_uclinux_type);
 331 }
 332
 333 type_init(lm32_machine_init)