2 * QEMU ETRAX System Emulator
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
29 #include "hw/sysbus.h"
30 #include "chardev/char-fe.h"
32 #include "qemu/module.h"
33 #include "qom/object.h"
37 #define RW_TR_CTRL (0x00 / 4)
38 #define RW_TR_DMA_EN (0x04 / 4)
39 #define RW_REC_CTRL (0x08 / 4)
40 #define RW_DOUT (0x1c / 4)
41 #define RS_STAT_DIN (0x20 / 4)
42 #define R_STAT_DIN (0x24 / 4)
43 #define RW_INTR_MASK (0x2c / 4)
44 #define RW_ACK_INTR (0x30 / 4)
45 #define R_INTR (0x34 / 4)
46 #define R_MASKED_INTR (0x38 / 4)
47 #define R_MAX (0x3c / 4)
50 #define STAT_TR_IDLE 22
51 #define STAT_TR_RDY 24
53 #define TYPE_ETRAX_FS_SERIAL "etraxfs,serial"
54 typedef struct ETRAXSerial ETRAXSerial
;
55 DECLARE_INSTANCE_CHECKER(ETRAXSerial
, ETRAX_SERIAL
,
59 SysBusDevice parent_obj
;
68 unsigned int rx_fifo_pos
;
69 unsigned int rx_fifo_len
;
71 /* Control registers. */
75 static void ser_update_irq(ETRAXSerial
*s
)
81 s
->regs
[R_INTR
] &= ~8;
84 s
->regs
[R_MASKED_INTR
] = s
->regs
[R_INTR
] & s
->regs
[RW_INTR_MASK
];
85 qemu_set_irq(s
->irq
, !!s
->regs
[R_MASKED_INTR
]);
89 ser_read(void *opaque
, hwaddr addr
, unsigned int size
)
91 ETRAXSerial
*s
= opaque
;
98 r
= s
->rx_fifo
[(s
->rx_fifo_pos
- s
->rx_fifo_len
) & 15];
102 r
|= 1 << STAT_TR_RDY
;
103 r
|= 1 << STAT_TR_IDLE
;
106 r
= s
->rx_fifo
[(s
->rx_fifo_pos
- s
->rx_fifo_len
) & 15];
107 if (s
->rx_fifo_len
) {
111 r
|= 1 << STAT_TR_RDY
;
112 r
|= 1 << STAT_TR_IDLE
;
116 D(qemu_log("%s " TARGET_FMT_plx
"=%x\n", __func__
, addr
, r
));
123 ser_write(void *opaque
, hwaddr addr
,
124 uint64_t val64
, unsigned int size
)
126 ETRAXSerial
*s
= opaque
;
127 uint32_t value
= val64
;
128 unsigned char ch
= val64
;
130 D(qemu_log("%s " TARGET_FMT_plx
"=%x\n", __func__
, addr
, value
));
135 /* XXX this blocks entire thread. Rewrite to use
136 * qemu_chr_fe_write and background I/O callbacks */
137 qemu_chr_fe_write_all(&s
->chr
, &ch
, 1);
138 s
->regs
[R_INTR
] |= 3;
140 s
->regs
[addr
] = value
;
146 D(qemu_log("fixedup value=%x r_intr=%x\n",
147 value
, s
->regs
[R_INTR
]));
149 s
->regs
[addr
] = value
;
150 s
->regs
[R_INTR
] &= ~value
;
151 D(printf("r_intr=%x\n", s
->regs
[R_INTR
]));
154 s
->regs
[addr
] = value
;
160 static const MemoryRegionOps ser_ops
= {
163 .endianness
= DEVICE_NATIVE_ENDIAN
,
165 .min_access_size
= 4,
170 static Property etraxfs_ser_properties
[] = {
171 DEFINE_PROP_CHR("chardev", ETRAXSerial
, chr
),
172 DEFINE_PROP_END_OF_LIST(),
175 static void serial_receive(void *opaque
, const uint8_t *buf
, int size
)
177 ETRAXSerial
*s
= opaque
;
181 if (s
->rx_fifo_len
>= 16) {
182 D(qemu_log("WARNING: UART dropped char.\n"));
186 for (i
= 0; i
< size
; i
++) {
187 s
->rx_fifo
[s
->rx_fifo_pos
] = buf
[i
];
189 s
->rx_fifo_pos
&= 15;
196 static int serial_can_receive(void *opaque
)
198 ETRAXSerial
*s
= opaque
;
200 /* Is the receiver enabled? */
201 if (!(s
->regs
[RW_REC_CTRL
] & (1 << 3))) {
205 return sizeof(s
->rx_fifo
) - s
->rx_fifo_len
;
208 static void serial_event(void *opaque
, QEMUChrEvent event
)
213 static void etraxfs_ser_reset(DeviceState
*d
)
215 ETRAXSerial
*s
= ETRAX_SERIAL(d
);
217 /* transmitter begins ready and idle. */
218 s
->regs
[RS_STAT_DIN
] |= (1 << STAT_TR_RDY
);
219 s
->regs
[RS_STAT_DIN
] |= (1 << STAT_TR_IDLE
);
221 s
->regs
[RW_REC_CTRL
] = 0x10000;
225 static void etraxfs_ser_init(Object
*obj
)
227 ETRAXSerial
*s
= ETRAX_SERIAL(obj
);
228 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
230 sysbus_init_irq(dev
, &s
->irq
);
231 memory_region_init_io(&s
->mmio
, obj
, &ser_ops
, s
,
232 "etraxfs-serial", R_MAX
* 4);
233 sysbus_init_mmio(dev
, &s
->mmio
);
236 static void etraxfs_ser_realize(DeviceState
*dev
, Error
**errp
)
238 ETRAXSerial
*s
= ETRAX_SERIAL(dev
);
240 qemu_chr_fe_set_handlers(&s
->chr
,
241 serial_can_receive
, serial_receive
,
242 serial_event
, NULL
, s
, NULL
, true);
245 static void etraxfs_ser_class_init(ObjectClass
*klass
, void *data
)
247 DeviceClass
*dc
= DEVICE_CLASS(klass
);
249 dc
->reset
= etraxfs_ser_reset
;
250 device_class_set_props(dc
, etraxfs_ser_properties
);
251 dc
->realize
= etraxfs_ser_realize
;
254 static const TypeInfo etraxfs_ser_info
= {
255 .name
= TYPE_ETRAX_FS_SERIAL
,
256 .parent
= TYPE_SYS_BUS_DEVICE
,
257 .instance_size
= sizeof(ETRAXSerial
),
258 .instance_init
= etraxfs_ser_init
,
259 .class_init
= etraxfs_ser_class_init
,
262 static void etraxfs_serial_register_types(void)
264 type_register_static(&etraxfs_ser_info
);
267 type_init(etraxfs_serial_register_types
)