2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
24 #include "exec/cpu_ldst.h"
25 #include "sysemu/kvm.h"
27 /*****************************************************************************/
28 /* Exceptions processing helpers */
30 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
33 do_raise_exception_err(env
, exception
, error_code
, 0);
36 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
38 do_raise_exception(env
, exception
, GETPC());
41 void helper_raise_exception_debug(CPUMIPSState
*env
)
43 do_raise_exception(env
, EXCP_DEBUG
, 0);
46 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
48 do_raise_exception(env
, exception
, 0);
51 #if defined(CONFIG_USER_ONLY)
52 #define HELPER_LD(name, insn, type) \
53 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
54 int mem_idx, uintptr_t retaddr) \
56 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
59 #define HELPER_LD(name, insn, type) \
60 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
61 int mem_idx, uintptr_t retaddr) \
65 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
66 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
68 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
72 HELPER_LD(lw
, ldl
, int32_t)
73 #if defined(TARGET_MIPS64)
74 HELPER_LD(ld
, ldq
, int64_t)
78 #if defined(CONFIG_USER_ONLY)
79 #define HELPER_ST(name, insn, type) \
80 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
81 type val, int mem_idx, uintptr_t retaddr) \
83 cpu_##insn##_data_ra(env, addr, val, retaddr); \
86 #define HELPER_ST(name, insn, type) \
87 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
88 type val, int mem_idx, uintptr_t retaddr) \
92 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
93 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
95 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
99 HELPER_ST(sb
, stb
, uint8_t)
100 HELPER_ST(sw
, stl
, uint32_t)
101 #if defined(TARGET_MIPS64)
102 HELPER_ST(sd
, stq
, uint64_t)
106 target_ulong
helper_clo (target_ulong arg1
)
111 target_ulong
helper_clz (target_ulong arg1
)
116 #if defined(TARGET_MIPS64)
117 target_ulong
helper_dclo (target_ulong arg1
)
122 target_ulong
helper_dclz (target_ulong arg1
)
126 #endif /* TARGET_MIPS64 */
128 /* 64 bits arithmetic for 32 bits hosts */
129 static inline uint64_t get_HILO(CPUMIPSState
*env
)
131 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
134 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
136 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
137 return env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
140 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
142 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
143 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
147 /* Multiplication variants of the vr54xx. */
148 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
151 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
152 (int64_t)(int32_t)arg2
));
155 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
158 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
159 (uint64_t)(uint32_t)arg2
);
162 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
165 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
166 (int64_t)(int32_t)arg2
);
169 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
172 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
173 (int64_t)(int32_t)arg2
);
176 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
179 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
180 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
183 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
186 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
187 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
190 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
193 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
194 (int64_t)(int32_t)arg2
);
197 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
200 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
201 (int64_t)(int32_t)arg2
);
204 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
207 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
208 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
211 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
214 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
215 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
218 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
221 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
224 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
227 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
228 (uint64_t)(uint32_t)arg2
);
231 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
234 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
235 (int64_t)(int32_t)arg2
);
238 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
241 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
242 (uint64_t)(uint32_t)arg2
);
245 static inline target_ulong
bitswap(target_ulong v
)
247 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
248 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
249 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
250 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
251 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
252 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
257 target_ulong
helper_dbitswap(target_ulong rt
)
263 target_ulong
helper_bitswap(target_ulong rt
)
265 return (int32_t)bitswap(rt
);
268 #ifndef CONFIG_USER_ONLY
270 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
271 target_ulong address
,
272 int rw
, uintptr_t retaddr
)
275 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
277 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
279 if (lladdr
== -1LL) {
280 cpu_loop_exit_restore(cs
, retaddr
);
286 #define HELPER_LD_ATOMIC(name, insn, almask) \
287 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
289 if (arg & almask) { \
290 env->CP0_BadVAddr = arg; \
291 do_raise_exception(env, EXCP_AdEL, GETPC()); \
293 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
294 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
297 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
299 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
301 #undef HELPER_LD_ATOMIC
303 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
304 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
305 target_ulong arg2, int mem_idx) \
309 if (arg2 & almask) { \
310 env->CP0_BadVAddr = arg2; \
311 do_raise_exception(env, EXCP_AdES, GETPC()); \
313 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
314 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
315 if (tmp == env->llval) { \
316 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
322 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
324 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
326 #undef HELPER_ST_ATOMIC
329 #ifdef TARGET_WORDS_BIGENDIAN
330 #define GET_LMASK(v) ((v) & 3)
331 #define GET_OFFSET(addr, offset) (addr + (offset))
333 #define GET_LMASK(v) (((v) & 3) ^ 3)
334 #define GET_OFFSET(addr, offset) (addr - (offset))
337 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
340 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
342 if (GET_LMASK(arg2
) <= 2) {
343 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
,
347 if (GET_LMASK(arg2
) <= 1) {
348 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
,
352 if (GET_LMASK(arg2
) == 0) {
353 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
,
358 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
361 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
363 if (GET_LMASK(arg2
) >= 1) {
364 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
368 if (GET_LMASK(arg2
) >= 2) {
369 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
373 if (GET_LMASK(arg2
) == 3) {
374 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
379 #if defined(TARGET_MIPS64)
380 /* "half" load and stores. We must do the memory access inline,
381 or fault handling won't work. */
383 #ifdef TARGET_WORDS_BIGENDIAN
384 #define GET_LMASK64(v) ((v) & 7)
386 #define GET_LMASK64(v) (((v) & 7) ^ 7)
389 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
392 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
394 if (GET_LMASK64(arg2
) <= 6) {
395 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
,
399 if (GET_LMASK64(arg2
) <= 5) {
400 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
,
404 if (GET_LMASK64(arg2
) <= 4) {
405 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
,
409 if (GET_LMASK64(arg2
) <= 3) {
410 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
,
414 if (GET_LMASK64(arg2
) <= 2) {
415 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
,
419 if (GET_LMASK64(arg2
) <= 1) {
420 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
,
424 if (GET_LMASK64(arg2
) <= 0) {
425 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
,
430 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
433 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
435 if (GET_LMASK64(arg2
) >= 1) {
436 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
440 if (GET_LMASK64(arg2
) >= 2) {
441 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
445 if (GET_LMASK64(arg2
) >= 3) {
446 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
450 if (GET_LMASK64(arg2
) >= 4) {
451 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
,
455 if (GET_LMASK64(arg2
) >= 5) {
456 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
,
460 if (GET_LMASK64(arg2
) >= 6) {
461 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
,
465 if (GET_LMASK64(arg2
) == 7) {
466 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
,
470 #endif /* TARGET_MIPS64 */
472 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
474 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
477 target_ulong base_reglist
= reglist
& 0xf;
478 target_ulong do_r31
= reglist
& 0x10;
480 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
483 for (i
= 0; i
< base_reglist
; i
++) {
484 env
->active_tc
.gpr
[multiple_regs
[i
]] =
485 (target_long
)do_lw(env
, addr
, mem_idx
, GETPC());
491 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
,
496 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
499 target_ulong base_reglist
= reglist
& 0xf;
500 target_ulong do_r31
= reglist
& 0x10;
502 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
505 for (i
= 0; i
< base_reglist
; i
++) {
506 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
513 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
517 #if defined(TARGET_MIPS64)
518 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
521 target_ulong base_reglist
= reglist
& 0xf;
522 target_ulong do_r31
= reglist
& 0x10;
524 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
527 for (i
= 0; i
< base_reglist
; i
++) {
528 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
,
535 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
, GETPC());
539 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
542 target_ulong base_reglist
= reglist
& 0xf;
543 target_ulong do_r31
= reglist
& 0x10;
545 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
548 for (i
= 0; i
< base_reglist
; i
++) {
549 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
556 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
561 #ifndef CONFIG_USER_ONLY
563 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
565 CPUState
*cpu
= CPU(c
);
566 CPUMIPSState
*env
= &c
->env
;
568 /* If the VPE is halted but otherwise active, it means it's waiting for
570 return cpu
->halted
&& mips_vpe_active(env
);
573 static bool mips_vp_is_wfi(MIPSCPU
*c
)
575 CPUState
*cpu
= CPU(c
);
576 CPUMIPSState
*env
= &c
->env
;
578 return cpu
->halted
&& mips_vp_active(env
);
581 static inline void mips_vpe_wake(MIPSCPU
*c
)
583 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
584 because there might be other conditions that state that c should
586 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
589 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
591 CPUState
*cs
= CPU(cpu
);
593 /* The VPE was shut off, really go to bed.
594 Reset any old _WAKE requests. */
596 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
599 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
601 CPUMIPSState
*c
= &cpu
->env
;
603 /* FIXME: TC reschedule. */
604 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
609 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
611 CPUMIPSState
*c
= &cpu
->env
;
613 /* FIXME: TC reschedule. */
614 if (!mips_vpe_active(c
)) {
621 * @env: CPU from which mapping is performed.
622 * @tc: Should point to an int with the value of the global TC index.
624 * This function will transform @tc into a local index within the
625 * returned #CPUMIPSState.
627 /* FIXME: This code assumes that all VPEs have the same number of TCs,
628 which depends on runtime setup. Can probably be fixed by
629 walking the list of CPUMIPSStates. */
630 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
638 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
639 /* Not allowed to address other CPUs. */
640 *tc
= env
->current_tc
;
644 cs
= CPU(mips_env_get_cpu(env
));
645 vpe_idx
= tc_idx
/ cs
->nr_threads
;
646 *tc
= tc_idx
% cs
->nr_threads
;
647 other_cs
= qemu_get_cpu(vpe_idx
);
648 if (other_cs
== NULL
) {
651 cpu
= MIPS_CPU(other_cs
);
655 /* The per VPE CP0_Status register shares some fields with the per TC
656 CP0_TCStatus registers. These fields are wired to the same registers,
657 so changes to either of them should be reflected on both registers.
659 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
661 These helper call synchronizes the regs for a given cpu. */
663 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
664 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
667 /* Called for updates to CP0_TCStatus. */
668 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
672 uint32_t tcu
, tmx
, tasid
, tksu
;
673 uint32_t mask
= ((1U << CP0St_CU3
)
680 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
681 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
683 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
685 status
= tcu
<< CP0St_CU0
;
686 status
|= tmx
<< CP0St_MX
;
687 status
|= tksu
<< CP0St_KSU
;
689 cpu
->CP0_Status
&= ~mask
;
690 cpu
->CP0_Status
|= status
;
692 /* Sync the TASID with EntryHi. */
693 cpu
->CP0_EntryHi
&= ~0xff;
694 cpu
->CP0_EntryHi
|= tasid
;
699 /* Called for updates to CP0_EntryHi. */
700 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
703 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
707 if (tc
== cpu
->current_tc
) {
708 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
710 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
718 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
720 return env
->mvp
->CP0_MVPControl
;
723 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
725 return env
->mvp
->CP0_MVPConf0
;
728 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
730 return env
->mvp
->CP0_MVPConf1
;
733 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
735 return (int32_t)cpu_mips_get_random(env
);
738 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
740 return env
->active_tc
.CP0_TCStatus
;
743 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
745 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
746 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
748 if (other_tc
== other
->current_tc
)
749 return other
->active_tc
.CP0_TCStatus
;
751 return other
->tcs
[other_tc
].CP0_TCStatus
;
754 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
756 return env
->active_tc
.CP0_TCBind
;
759 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
761 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
762 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
764 if (other_tc
== other
->current_tc
)
765 return other
->active_tc
.CP0_TCBind
;
767 return other
->tcs
[other_tc
].CP0_TCBind
;
770 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
772 return env
->active_tc
.PC
;
775 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
777 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
778 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
780 if (other_tc
== other
->current_tc
)
781 return other
->active_tc
.PC
;
783 return other
->tcs
[other_tc
].PC
;
786 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
788 return env
->active_tc
.CP0_TCHalt
;
791 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
793 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
794 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
796 if (other_tc
== other
->current_tc
)
797 return other
->active_tc
.CP0_TCHalt
;
799 return other
->tcs
[other_tc
].CP0_TCHalt
;
802 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
804 return env
->active_tc
.CP0_TCContext
;
807 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
809 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
810 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
812 if (other_tc
== other
->current_tc
)
813 return other
->active_tc
.CP0_TCContext
;
815 return other
->tcs
[other_tc
].CP0_TCContext
;
818 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
820 return env
->active_tc
.CP0_TCSchedule
;
823 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
825 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
826 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
828 if (other_tc
== other
->current_tc
)
829 return other
->active_tc
.CP0_TCSchedule
;
831 return other
->tcs
[other_tc
].CP0_TCSchedule
;
834 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
836 return env
->active_tc
.CP0_TCScheFBack
;
839 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
841 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
842 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
844 if (other_tc
== other
->current_tc
)
845 return other
->active_tc
.CP0_TCScheFBack
;
847 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
850 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
852 return (int32_t)cpu_mips_get_count(env
);
855 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
857 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
858 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
860 return other
->CP0_EntryHi
;
863 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
865 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
867 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
869 if (other_tc
== other
->current_tc
) {
870 tccause
= other
->CP0_Cause
;
872 tccause
= other
->CP0_Cause
;
878 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
880 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
881 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
883 return other
->CP0_Status
;
886 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
888 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
891 target_ulong
helper_mfc0_maar(CPUMIPSState
*env
)
893 return (int32_t) env
->CP0_MAAR
[env
->CP0_MAARI
];
896 target_ulong
helper_mfhc0_maar(CPUMIPSState
*env
)
898 return env
->CP0_MAAR
[env
->CP0_MAARI
] >> 32;
901 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
903 return (int32_t)env
->CP0_WatchLo
[sel
];
906 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
908 return env
->CP0_WatchHi
[sel
];
911 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
913 target_ulong t0
= env
->CP0_Debug
;
914 if (env
->hflags
& MIPS_HFLAG_DM
)
920 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
922 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
924 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
926 if (other_tc
== other
->current_tc
)
927 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
929 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
931 /* XXX: Might be wrong, check with EJTAG spec. */
932 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
933 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
936 #if defined(TARGET_MIPS64)
937 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
939 return env
->active_tc
.PC
;
942 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
944 return env
->active_tc
.CP0_TCHalt
;
947 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
949 return env
->active_tc
.CP0_TCContext
;
952 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
954 return env
->active_tc
.CP0_TCSchedule
;
957 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
959 return env
->active_tc
.CP0_TCScheFBack
;
962 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
964 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
967 target_ulong
helper_dmfc0_maar(CPUMIPSState
*env
)
969 return env
->CP0_MAAR
[env
->CP0_MAARI
];
972 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
974 return env
->CP0_WatchLo
[sel
];
976 #endif /* TARGET_MIPS64 */
978 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
980 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
981 uint32_t tlb_index
= arg1
& 0x7fffffff;
982 if (tlb_index
< env
->tlb
->nb_tlb
) {
983 if (env
->insn_flags
& ISA_MIPS32R6
) {
984 index_p
|= arg1
& 0x80000000;
986 env
->CP0_Index
= index_p
| tlb_index
;
990 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
995 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
996 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
998 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
999 mask
|= (1 << CP0MVPCo_STLB
);
1000 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
1002 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1004 env
->mvp
->CP0_MVPControl
= newval
;
1007 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1012 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1013 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1014 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1016 /* Yield scheduler intercept not implemented. */
1017 /* Gating storage scheduler intercept not implemented. */
1019 // TODO: Enable/disable TCs.
1021 env
->CP0_VPEControl
= newval
;
1024 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1026 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1027 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1031 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1032 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1033 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1035 /* TODO: Enable/disable TCs. */
1037 other
->CP0_VPEControl
= newval
;
1040 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1042 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1043 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1044 /* FIXME: Mask away return zero on read bits. */
1045 return other
->CP0_VPEControl
;
1048 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1050 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1051 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1053 return other
->CP0_VPEConf0
;
1056 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1061 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1062 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1063 mask
|= (0xff << CP0VPEC0_XTC
);
1064 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1066 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1068 // TODO: TC exclusive handling due to ERL/EXL.
1070 env
->CP0_VPEConf0
= newval
;
1073 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1075 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1076 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1080 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1081 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1083 /* TODO: TC exclusive handling due to ERL/EXL. */
1084 other
->CP0_VPEConf0
= newval
;
1087 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1092 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1093 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1094 (0xff << CP0VPEC1_NCP1
);
1095 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1097 /* UDI not implemented. */
1098 /* CP2 not implemented. */
1100 // TODO: Handle FPU (CP1) binding.
1102 env
->CP0_VPEConf1
= newval
;
1105 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1107 /* Yield qualifier inputs not implemented. */
1108 env
->CP0_YQMask
= 0x00000000;
1111 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1113 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1116 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1118 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1120 /* 1k pages not implemented */
1121 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1122 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1123 | (rxi
<< (CP0EnLo_XI
- 30));
1126 #if defined(TARGET_MIPS64)
1127 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1129 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1131 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1132 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1136 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1138 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1141 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1143 env
->active_tc
.CP0_TCStatus
= newval
;
1144 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1147 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1149 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1150 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1152 if (other_tc
== other
->current_tc
)
1153 other
->active_tc
.CP0_TCStatus
= arg1
;
1155 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1156 sync_c0_tcstatus(other
, other_tc
, arg1
);
1159 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1161 uint32_t mask
= (1 << CP0TCBd_TBE
);
1164 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1165 mask
|= (1 << CP0TCBd_CurVPE
);
1166 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1167 env
->active_tc
.CP0_TCBind
= newval
;
1170 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1172 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1173 uint32_t mask
= (1 << CP0TCBd_TBE
);
1175 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1177 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1178 mask
|= (1 << CP0TCBd_CurVPE
);
1179 if (other_tc
== other
->current_tc
) {
1180 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1181 other
->active_tc
.CP0_TCBind
= newval
;
1183 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1184 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1188 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1190 env
->active_tc
.PC
= arg1
;
1191 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1193 /* MIPS16 not implemented. */
1196 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1198 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1199 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1201 if (other_tc
== other
->current_tc
) {
1202 other
->active_tc
.PC
= arg1
;
1203 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1204 other
->lladdr
= 0ULL;
1205 /* MIPS16 not implemented. */
1207 other
->tcs
[other_tc
].PC
= arg1
;
1208 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1209 other
->lladdr
= 0ULL;
1210 /* MIPS16 not implemented. */
1214 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1216 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1218 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1220 // TODO: Halt TC / Restart (if allocated+active) TC.
1221 if (env
->active_tc
.CP0_TCHalt
& 1) {
1222 mips_tc_sleep(cpu
, env
->current_tc
);
1224 mips_tc_wake(cpu
, env
->current_tc
);
1228 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1230 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1231 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1232 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1234 // TODO: Halt TC / Restart (if allocated+active) TC.
1236 if (other_tc
== other
->current_tc
)
1237 other
->active_tc
.CP0_TCHalt
= arg1
;
1239 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1242 mips_tc_sleep(other_cpu
, other_tc
);
1244 mips_tc_wake(other_cpu
, other_tc
);
1248 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1250 env
->active_tc
.CP0_TCContext
= arg1
;
1253 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1255 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1256 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1258 if (other_tc
== other
->current_tc
)
1259 other
->active_tc
.CP0_TCContext
= arg1
;
1261 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1264 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1266 env
->active_tc
.CP0_TCSchedule
= arg1
;
1269 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1271 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1272 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1274 if (other_tc
== other
->current_tc
)
1275 other
->active_tc
.CP0_TCSchedule
= arg1
;
1277 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1280 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1282 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1285 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1287 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1288 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1290 if (other_tc
== other
->current_tc
)
1291 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1293 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1296 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1298 /* 1k pages not implemented */
1299 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1300 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1301 | (rxi
<< (CP0EnLo_XI
- 30));
1304 #if defined(TARGET_MIPS64)
1305 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1307 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1308 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1312 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1314 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1317 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1319 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1320 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1321 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1322 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1323 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1324 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1328 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1330 /* SmartMIPS not implemented */
1331 /* 1k pages not implemented */
1332 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1333 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1334 compute_hflags(env
);
1335 restore_pamask(env
);
1338 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1340 if (env
->insn_flags
& ISA_MIPS32R6
) {
1341 if (arg1
< env
->tlb
->nb_tlb
) {
1342 env
->CP0_Wired
= arg1
;
1345 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1349 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1351 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1354 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1356 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1359 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1361 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1364 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1366 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1369 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1371 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1374 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1376 uint32_t mask
= 0x0000000F;
1378 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1379 (env
->insn_flags
& ISA_MIPS32R6
)) {
1382 if (env
->insn_flags
& ISA_MIPS32R6
) {
1385 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1388 if (arg1
& (1 << 29)) {
1389 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1391 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1395 env
->CP0_HWREna
= arg1
& mask
;
1398 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1400 cpu_mips_store_count(env
, arg1
);
1403 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1405 target_ulong old
, val
, mask
;
1406 mask
= (TARGET_PAGE_MASK
<< 1) | 0xFF;
1407 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1408 mask
|= 1 << CP0EnHi_EHINV
;
1411 /* 1k pages not implemented */
1412 #if defined(TARGET_MIPS64)
1413 if (env
->insn_flags
& ISA_MIPS32R6
) {
1414 int entryhi_r
= extract64(arg1
, 62, 2);
1415 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1416 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1417 if ((entryhi_r
== 2) ||
1418 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1419 /* skip EntryHi.R field if new value is reserved */
1420 mask
&= ~(0x3ull
<< 62);
1423 mask
&= env
->SEGMask
;
1425 old
= env
->CP0_EntryHi
;
1426 val
= (arg1
& mask
) | (old
& ~mask
);
1427 env
->CP0_EntryHi
= val
;
1428 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1429 sync_c0_entryhi(env
, env
->current_tc
);
1431 /* If the ASID changes, flush qemu's TLB. */
1432 if ((old
& 0xFF) != (val
& 0xFF))
1433 cpu_mips_tlb_flush(env
, 1);
1436 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1438 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1439 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1441 other
->CP0_EntryHi
= arg1
;
1442 sync_c0_entryhi(other
, other_tc
);
1445 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1447 cpu_mips_store_compare(env
, arg1
);
1450 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1452 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1455 old
= env
->CP0_Status
;
1456 cpu_mips_store_status(env
, arg1
);
1457 val
= env
->CP0_Status
;
1459 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1460 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1461 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1462 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1464 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1465 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1466 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1467 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1469 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1475 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1477 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1478 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1479 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1481 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1482 sync_c0_status(env
, other
, other_tc
);
1485 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1487 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1490 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1492 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1493 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1496 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1498 cpu_mips_store_cause(env
, arg1
);
1501 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1503 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1504 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1506 cpu_mips_store_cause(other
, arg1
);
1509 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1511 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1512 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1514 return other
->CP0_EPC
;
1517 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1519 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1520 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1522 return other
->CP0_EBase
;
1525 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1527 env
->CP0_EBase
= (env
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1530 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1532 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1533 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1534 other
->CP0_EBase
= (other
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1537 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1539 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1540 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1543 case 0: return other
->CP0_Config0
;
1544 case 1: return other
->CP0_Config1
;
1545 case 2: return other
->CP0_Config2
;
1546 case 3: return other
->CP0_Config3
;
1547 /* 4 and 5 are reserved. */
1548 case 6: return other
->CP0_Config6
;
1549 case 7: return other
->CP0_Config7
;
1556 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1558 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1561 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1563 /* tertiary/secondary caches not implemented */
1564 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1567 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1569 if (env
->insn_flags
& ASE_MICROMIPS
) {
1570 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1571 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1575 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1577 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1578 (arg1
& env
->CP0_Config4_rw_bitmask
);
1581 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1583 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1584 (arg1
& env
->CP0_Config5_rw_bitmask
);
1585 compute_hflags(env
);
1588 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1590 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1591 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1592 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1595 #define MTC0_MAAR_MASK(env) \
1596 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1598 void helper_mtc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1600 env
->CP0_MAAR
[env
->CP0_MAARI
] = arg1
& MTC0_MAAR_MASK(env
);
1603 void helper_mthc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1605 env
->CP0_MAAR
[env
->CP0_MAARI
] =
1606 (((uint64_t) arg1
<< 32) & MTC0_MAAR_MASK(env
)) |
1607 (env
->CP0_MAAR
[env
->CP0_MAARI
] & 0x00000000ffffffffULL
);
1610 void helper_mtc0_maari(CPUMIPSState
*env
, target_ulong arg1
)
1612 int index
= arg1
& 0x3f;
1613 if (index
== 0x3f) {
1614 /* Software may write all ones to INDEX to determine the
1615 maximum value supported. */
1616 env
->CP0_MAARI
= MIPS_MAAR_MAX
- 1;
1617 } else if (index
< MIPS_MAAR_MAX
) {
1618 env
->CP0_MAARI
= index
;
1620 /* Other than the all ones, if the
1621 value written is not supported, then INDEX is unchanged
1622 from its previous value. */
1625 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1627 /* Watch exceptions for instructions, data loads, data stores
1629 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1632 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1634 env
->CP0_WatchHi
[sel
] = (arg1
& 0x40FF0FF8);
1635 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1638 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1640 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1641 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1644 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1646 env
->CP0_Framemask
= arg1
; /* XXX */
1649 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1651 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1652 if (arg1
& (1 << CP0DB_DM
))
1653 env
->hflags
|= MIPS_HFLAG_DM
;
1655 env
->hflags
&= ~MIPS_HFLAG_DM
;
1658 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1660 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1661 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1662 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1664 /* XXX: Might be wrong, check with EJTAG spec. */
1665 if (other_tc
== other
->current_tc
)
1666 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1668 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1669 other
->CP0_Debug
= (other
->CP0_Debug
&
1670 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1671 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1674 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1676 env
->CP0_Performance0
= arg1
& 0x000007ff;
1679 void helper_mtc0_errctl(CPUMIPSState
*env
, target_ulong arg1
)
1681 int32_t wst
= arg1
& (1 << CP0EC_WST
);
1682 int32_t spr
= arg1
& (1 << CP0EC_SPR
);
1683 int32_t itc
= env
->itc_tag
? (arg1
& (1 << CP0EC_ITC
)) : 0;
1685 env
->CP0_ErrCtl
= wst
| spr
| itc
;
1687 if (itc
&& !wst
&& !spr
) {
1688 env
->hflags
|= MIPS_HFLAG_ITC_CACHE
;
1690 env
->hflags
&= ~MIPS_HFLAG_ITC_CACHE
;
1694 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1696 if (env
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
1697 /* If CACHE instruction is configured for ITC tags then make all
1698 CP0.TagLo bits writable. The actual write to ITC Configuration
1699 Tag will take care of the read-only bits. */
1700 env
->CP0_TagLo
= arg1
;
1702 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1706 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1708 env
->CP0_DataLo
= arg1
; /* XXX */
1711 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1713 env
->CP0_TagHi
= arg1
; /* XXX */
1716 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1718 env
->CP0_DataHi
= arg1
; /* XXX */
1721 /* MIPS MT functions */
1722 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1724 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1725 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1727 if (other_tc
== other
->current_tc
)
1728 return other
->active_tc
.gpr
[sel
];
1730 return other
->tcs
[other_tc
].gpr
[sel
];
1733 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1735 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1736 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1738 if (other_tc
== other
->current_tc
)
1739 return other
->active_tc
.LO
[sel
];
1741 return other
->tcs
[other_tc
].LO
[sel
];
1744 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1746 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1747 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1749 if (other_tc
== other
->current_tc
)
1750 return other
->active_tc
.HI
[sel
];
1752 return other
->tcs
[other_tc
].HI
[sel
];
1755 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1757 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1758 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1760 if (other_tc
== other
->current_tc
)
1761 return other
->active_tc
.ACX
[sel
];
1763 return other
->tcs
[other_tc
].ACX
[sel
];
1766 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1768 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1769 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1771 if (other_tc
== other
->current_tc
)
1772 return other
->active_tc
.DSPControl
;
1774 return other
->tcs
[other_tc
].DSPControl
;
1777 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1779 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1780 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1782 if (other_tc
== other
->current_tc
)
1783 other
->active_tc
.gpr
[sel
] = arg1
;
1785 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1788 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1790 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1791 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1793 if (other_tc
== other
->current_tc
)
1794 other
->active_tc
.LO
[sel
] = arg1
;
1796 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1799 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1801 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1802 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1804 if (other_tc
== other
->current_tc
)
1805 other
->active_tc
.HI
[sel
] = arg1
;
1807 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1810 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1812 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1813 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1815 if (other_tc
== other
->current_tc
)
1816 other
->active_tc
.ACX
[sel
] = arg1
;
1818 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1821 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
1823 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1824 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1826 if (other_tc
== other
->current_tc
)
1827 other
->active_tc
.DSPControl
= arg1
;
1829 other
->tcs
[other_tc
].DSPControl
= arg1
;
1832 /* MIPS MT functions */
1833 target_ulong
helper_dmt(void)
1839 target_ulong
helper_emt(void)
1845 target_ulong
helper_dvpe(CPUMIPSState
*env
)
1847 CPUState
*other_cs
= first_cpu
;
1848 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1850 CPU_FOREACH(other_cs
) {
1851 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1852 /* Turn off all VPEs except the one executing the dvpe. */
1853 if (&other_cpu
->env
!= env
) {
1854 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1855 mips_vpe_sleep(other_cpu
);
1861 target_ulong
helper_evpe(CPUMIPSState
*env
)
1863 CPUState
*other_cs
= first_cpu
;
1864 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1866 CPU_FOREACH(other_cs
) {
1867 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1869 if (&other_cpu
->env
!= env
1870 /* If the VPE is WFI, don't disturb its sleep. */
1871 && !mips_vpe_is_wfi(other_cpu
)) {
1872 /* Enable the VPE. */
1873 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1874 mips_vpe_wake(other_cpu
); /* And wake it up. */
1879 #endif /* !CONFIG_USER_ONLY */
1881 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1883 // arg1 = rt, arg2 = rs
1884 // TODO: store to TC register
1887 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
1889 target_long arg1
= arg
;
1892 /* No scheduling policy implemented. */
1894 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1895 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1896 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1897 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1898 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1901 } else if (arg1
== 0) {
1902 if (0 /* TODO: TC underflow */) {
1903 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1904 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1906 // TODO: Deallocate TC
1908 } else if (arg1
> 0) {
1909 /* Yield qualifier inputs not implemented. */
1910 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1911 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1912 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1914 return env
->CP0_YQMask
;
1917 /* R6 Multi-threading */
1918 #ifndef CONFIG_USER_ONLY
1919 target_ulong
helper_dvp(CPUMIPSState
*env
)
1921 CPUState
*other_cs
= first_cpu
;
1922 target_ulong prev
= env
->CP0_VPControl
;
1924 if (!((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
1925 CPU_FOREACH(other_cs
) {
1926 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1927 /* Turn off all VPs except the one executing the dvp. */
1928 if (&other_cpu
->env
!= env
) {
1929 mips_vpe_sleep(other_cpu
);
1932 env
->CP0_VPControl
|= (1 << CP0VPCtl_DIS
);
1937 target_ulong
helper_evp(CPUMIPSState
*env
)
1939 CPUState
*other_cs
= first_cpu
;
1940 target_ulong prev
= env
->CP0_VPControl
;
1942 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
1943 CPU_FOREACH(other_cs
) {
1944 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1945 if ((&other_cpu
->env
!= env
) && !mips_vp_is_wfi(other_cpu
)) {
1946 /* If the VP is WFI, don't disturb its sleep.
1947 * Otherwise, wake it up. */
1948 mips_vpe_wake(other_cpu
);
1951 env
->CP0_VPControl
&= ~(1 << CP0VPCtl_DIS
);
1955 #endif /* !CONFIG_USER_ONLY */
1957 #ifndef CONFIG_USER_ONLY
1958 /* TLB management */
1959 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
1961 /* Discard entries from env->tlb[first] onwards. */
1962 while (env
->tlb
->tlb_in_use
> first
) {
1963 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1967 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
1969 #if defined(TARGET_MIPS64)
1970 return extract64(entrylo
, 6, 54);
1972 return extract64(entrylo
, 6, 24) | /* PFN */
1973 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
1977 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
1981 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1982 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1983 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
1988 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1989 #if defined(TARGET_MIPS64)
1990 tlb
->VPN
&= env
->SEGMask
;
1992 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
1993 tlb
->PageMask
= env
->CP0_PageMask
;
1994 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1995 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
1996 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
1997 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
1998 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
1999 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
2000 tlb
->PFN
[0] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) << 12;
2001 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
2002 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
2003 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
2004 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
2005 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
2006 tlb
->PFN
[1] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) << 12;
2009 void r4k_helper_tlbinv(CPUMIPSState
*env
)
2013 uint8_t ASID
= env
->CP0_EntryHi
& 0xFF;
2015 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2016 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2017 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
2021 cpu_mips_tlb_flush(env
, 1);
2024 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
2028 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2029 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
2031 cpu_mips_tlb_flush(env
, 1);
2034 void r4k_helper_tlbwi(CPUMIPSState
*env
)
2040 bool G
, V0
, D0
, V1
, D1
;
2042 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2043 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2044 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2045 #if defined(TARGET_MIPS64)
2046 VPN
&= env
->SEGMask
;
2048 ASID
= env
->CP0_EntryHi
& 0xff;
2049 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2050 V0
= (env
->CP0_EntryLo0
& 2) != 0;
2051 D0
= (env
->CP0_EntryLo0
& 4) != 0;
2052 V1
= (env
->CP0_EntryLo1
& 2) != 0;
2053 D1
= (env
->CP0_EntryLo1
& 4) != 0;
2055 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2056 permissions on the current entry. */
2057 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
2058 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
2059 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
)) {
2060 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2063 r4k_invalidate_tlb(env
, idx
, 0);
2064 r4k_fill_tlb(env
, idx
);
2067 void r4k_helper_tlbwr(CPUMIPSState
*env
)
2069 int r
= cpu_mips_get_random(env
);
2071 r4k_invalidate_tlb(env
, r
, 1);
2072 r4k_fill_tlb(env
, r
);
2075 void r4k_helper_tlbp(CPUMIPSState
*env
)
2084 ASID
= env
->CP0_EntryHi
& 0xFF;
2085 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
2086 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2087 /* 1k pages are not supported. */
2088 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2089 tag
= env
->CP0_EntryHi
& ~mask
;
2090 VPN
= tlb
->VPN
& ~mask
;
2091 #if defined(TARGET_MIPS64)
2092 tag
&= env
->SEGMask
;
2094 /* Check ASID, virtual page number & size */
2095 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
2101 if (i
== env
->tlb
->nb_tlb
) {
2102 /* No match. Discard any shadow entries, if any of them match. */
2103 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
2104 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2105 /* 1k pages are not supported. */
2106 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2107 tag
= env
->CP0_EntryHi
& ~mask
;
2108 VPN
= tlb
->VPN
& ~mask
;
2109 #if defined(TARGET_MIPS64)
2110 tag
&= env
->SEGMask
;
2112 /* Check ASID, virtual page number & size */
2113 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2114 r4k_mips_tlb_flush_extra (env
, i
);
2119 env
->CP0_Index
|= 0x80000000;
2123 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
2125 #if defined(TARGET_MIPS64)
2126 return tlb_pfn
<< 6;
2128 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
2129 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2133 void r4k_helper_tlbr(CPUMIPSState
*env
)
2139 ASID
= env
->CP0_EntryHi
& 0xFF;
2140 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2141 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2143 /* If this will change the current ASID, flush qemu's TLB. */
2144 if (ASID
!= tlb
->ASID
)
2145 cpu_mips_tlb_flush (env
, 1);
2147 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2150 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2151 env
->CP0_PageMask
= 0;
2152 env
->CP0_EntryLo0
= 0;
2153 env
->CP0_EntryLo1
= 0;
2155 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2156 env
->CP0_PageMask
= tlb
->PageMask
;
2157 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2158 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2159 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2160 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2161 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2162 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2163 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2164 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2168 void helper_tlbwi(CPUMIPSState
*env
)
2170 env
->tlb
->helper_tlbwi(env
);
2173 void helper_tlbwr(CPUMIPSState
*env
)
2175 env
->tlb
->helper_tlbwr(env
);
2178 void helper_tlbp(CPUMIPSState
*env
)
2180 env
->tlb
->helper_tlbp(env
);
2183 void helper_tlbr(CPUMIPSState
*env
)
2185 env
->tlb
->helper_tlbr(env
);
2188 void helper_tlbinv(CPUMIPSState
*env
)
2190 env
->tlb
->helper_tlbinv(env
);
2193 void helper_tlbinvf(CPUMIPSState
*env
)
2195 env
->tlb
->helper_tlbinvf(env
);
2199 target_ulong
helper_di(CPUMIPSState
*env
)
2201 target_ulong t0
= env
->CP0_Status
;
2203 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2207 target_ulong
helper_ei(CPUMIPSState
*env
)
2209 target_ulong t0
= env
->CP0_Status
;
2211 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2215 static void debug_pre_eret(CPUMIPSState
*env
)
2217 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2218 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2219 env
->active_tc
.PC
, env
->CP0_EPC
);
2220 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2221 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2222 if (env
->hflags
& MIPS_HFLAG_DM
)
2223 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2228 static void debug_post_eret(CPUMIPSState
*env
)
2230 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2232 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2233 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2234 env
->active_tc
.PC
, env
->CP0_EPC
);
2235 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2236 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2237 if (env
->hflags
& MIPS_HFLAG_DM
)
2238 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2239 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
2240 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2241 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2242 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2244 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2250 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2252 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2254 env
->hflags
|= MIPS_HFLAG_M16
;
2256 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2260 static inline void exception_return(CPUMIPSState
*env
)
2262 debug_pre_eret(env
);
2263 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2264 set_pc(env
, env
->CP0_ErrorEPC
);
2265 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2267 set_pc(env
, env
->CP0_EPC
);
2268 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2270 compute_hflags(env
);
2271 debug_post_eret(env
);
2274 void helper_eret(CPUMIPSState
*env
)
2276 exception_return(env
);
2280 void helper_eretnc(CPUMIPSState
*env
)
2282 exception_return(env
);
2285 void helper_deret(CPUMIPSState
*env
)
2287 debug_pre_eret(env
);
2288 set_pc(env
, env
->CP0_DEPC
);
2290 env
->hflags
&= ~MIPS_HFLAG_DM
;
2291 compute_hflags(env
);
2292 debug_post_eret(env
);
2294 #endif /* !CONFIG_USER_ONLY */
2296 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
2298 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
2301 do_raise_exception(env
, EXCP_RI
, pc
);
2304 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2306 check_hwrena(env
, 0, GETPC());
2307 return env
->CP0_EBase
& 0x3ff;
2310 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2312 check_hwrena(env
, 1, GETPC());
2313 return env
->SYNCI_Step
;
2316 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2318 check_hwrena(env
, 2, GETPC());
2319 #ifdef CONFIG_USER_ONLY
2320 return env
->CP0_Count
;
2322 return (int32_t)cpu_mips_get_count(env
);
2326 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2328 check_hwrena(env
, 3, GETPC());
2332 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
2334 check_hwrena(env
, 4, GETPC());
2335 return env
->CP0_Performance0
;
2338 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
2340 check_hwrena(env
, 5, GETPC());
2341 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
2344 void helper_pmon(CPUMIPSState
*env
, int function
)
2348 case 2: /* TODO: char inbyte(int waitflag); */
2349 if (env
->active_tc
.gpr
[4] == 0)
2350 env
->active_tc
.gpr
[2] = -1;
2352 case 11: /* TODO: char inbyte (void); */
2353 env
->active_tc
.gpr
[2] = -1;
2357 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2363 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2370 void helper_wait(CPUMIPSState
*env
)
2372 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2375 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2376 /* Last instruction in the block, PC was updated before
2377 - no need to recover PC and icount */
2378 raise_exception(env
, EXCP_HLT
);
2381 #if !defined(CONFIG_USER_ONLY)
2383 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2384 int access_type
, int is_user
,
2387 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2388 CPUMIPSState
*env
= &cpu
->env
;
2392 env
->CP0_BadVAddr
= addr
;
2394 if (access_type
== MMU_DATA_STORE
) {
2398 if (access_type
== MMU_INST_FETCH
) {
2399 error_code
|= EXCP_INST_NOTAVAIL
;
2403 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2406 void tlb_fill(CPUState
*cs
, target_ulong addr
, int is_write
, int mmu_idx
,
2411 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, is_write
, mmu_idx
);
2413 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2414 CPUMIPSState
*env
= &cpu
->env
;
2416 do_raise_exception_err(env
, cs
->exception_index
,
2417 env
->error_code
, retaddr
);
2421 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2422 bool is_write
, bool is_exec
, int unused
,
2425 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2426 CPUMIPSState
*env
= &cpu
->env
;
2429 * Raising an exception with KVM enabled will crash because it won't be from
2430 * the main execution loop so the longjmp won't have a matching setjmp.
2431 * Until we can trigger a bus error exception through KVM lets just ignore
2434 if (kvm_enabled()) {
2439 raise_exception(env
, EXCP_IBE
);
2441 raise_exception(env
, EXCP_DBE
);
2444 #endif /* !CONFIG_USER_ONLY */
2446 /* Complex FPU operations which may need stack space. */
2448 #define FLOAT_TWO32 make_float32(1 << 30)
2449 #define FLOAT_TWO64 make_float64(1ULL << 62)
2451 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2452 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2454 /* convert MIPS rounding mode in FCR31 to IEEE library */
2455 unsigned int ieee_rm
[] = {
2456 float_round_nearest_even
,
2457 float_round_to_zero
,
2462 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2464 target_ulong arg1
= 0;
2468 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2471 /* UFR Support - Read Status FR */
2472 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2473 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2475 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2477 do_raise_exception(env
, EXCP_RI
, GETPC());
2482 /* FRE Support - read Config5.FRE bit */
2483 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2484 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2485 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2487 helper_raise_exception(env
, EXCP_RI
);
2492 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2495 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2498 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2501 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2508 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2512 /* UFR Alias - Reset Status FR */
2513 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2516 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2517 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2518 compute_hflags(env
);
2520 do_raise_exception(env
, EXCP_RI
, GETPC());
2524 /* UNFR Alias - Set Status FR */
2525 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2528 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2529 env
->CP0_Status
|= (1 << CP0St_FR
);
2530 compute_hflags(env
);
2532 do_raise_exception(env
, EXCP_RI
, GETPC());
2536 /* FRE Support - clear Config5.FRE bit */
2537 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2540 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2541 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2542 compute_hflags(env
);
2544 helper_raise_exception(env
, EXCP_RI
);
2548 /* FRE Support - set Config5.FRE bit */
2549 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2552 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2553 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2554 compute_hflags(env
);
2556 helper_raise_exception(env
, EXCP_RI
);
2560 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2563 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2564 ((arg1
& 0x1) << 23);
2567 if (arg1
& 0x007c0000)
2569 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2572 if (arg1
& 0x007c0000)
2574 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2575 ((arg1
& 0x4) << 22);
2578 if (env
->insn_flags
& ISA_MIPS32R6
) {
2579 uint32_t mask
= 0xfefc0000;
2580 env
->active_fpu
.fcr31
= (arg1
& ~mask
) |
2581 (env
->active_fpu
.fcr31
& mask
);
2582 } else if (!(arg1
& 0x007c0000)) {
2583 env
->active_fpu
.fcr31
= arg1
;
2589 /* set rounding mode */
2590 restore_rounding_mode(env
);
2591 /* set flush-to-zero mode */
2592 restore_flush_mode(env
);
2593 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2594 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2595 do_raise_exception(env
, EXCP_FPE
, GETPC());
2598 int ieee_ex_to_mips(int xcpt
)
2602 if (xcpt
& float_flag_invalid
) {
2605 if (xcpt
& float_flag_overflow
) {
2608 if (xcpt
& float_flag_underflow
) {
2609 ret
|= FP_UNDERFLOW
;
2611 if (xcpt
& float_flag_divbyzero
) {
2614 if (xcpt
& float_flag_inexact
) {
2621 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2623 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2625 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2628 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2630 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2631 do_raise_exception(env
, EXCP_FPE
, pc
);
2633 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2639 Single precition routines have a "s" suffix, double precision a
2640 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2641 paired single lower "pl", paired single upper "pu". */
2643 /* unary operations, modifying fp status */
2644 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2646 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2647 update_fcr31(env
, GETPC());
2651 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2653 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2654 update_fcr31(env
, GETPC());
2658 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2662 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2663 fdt2
= float64_maybe_silence_nan(fdt2
, &env
->active_fpu
.fp_status
);
2664 update_fcr31(env
, GETPC());
2668 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2672 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2673 update_fcr31(env
, GETPC());
2677 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2681 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2682 update_fcr31(env
, GETPC());
2686 uint64_t helper_float_cvt_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2690 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2691 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2692 & (float_flag_invalid
| float_flag_overflow
)) {
2693 dt2
= FP_TO_INT64_OVERFLOW
;
2695 update_fcr31(env
, GETPC());
2699 uint64_t helper_float_cvt_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2703 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2704 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2705 & (float_flag_invalid
| float_flag_overflow
)) {
2706 dt2
= FP_TO_INT64_OVERFLOW
;
2708 update_fcr31(env
, GETPC());
2712 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2717 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2718 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2719 update_fcr31(env
, GETPC());
2720 return ((uint64_t)fsth2
<< 32) | fst2
;
2723 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2729 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2730 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2731 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2732 wt2
= FP_TO_INT32_OVERFLOW
;
2735 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2736 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2737 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2738 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2739 wth2
= FP_TO_INT32_OVERFLOW
;
2742 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
2743 update_fcr31(env
, GETPC());
2745 return ((uint64_t)wth2
<< 32) | wt2
;
2748 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
2752 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2753 fst2
= float32_maybe_silence_nan(fst2
, &env
->active_fpu
.fp_status
);
2754 update_fcr31(env
, GETPC());
2758 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
2762 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2763 update_fcr31(env
, GETPC());
2767 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
2771 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2772 update_fcr31(env
, GETPC());
2776 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
2781 update_fcr31(env
, GETPC());
2785 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
2790 update_fcr31(env
, GETPC());
2794 uint32_t helper_float_cvt_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2798 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2799 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2800 & (float_flag_invalid
| float_flag_overflow
)) {
2801 wt2
= FP_TO_INT32_OVERFLOW
;
2803 update_fcr31(env
, GETPC());
2807 uint32_t helper_float_cvt_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2811 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2812 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2813 & (float_flag_invalid
| float_flag_overflow
)) {
2814 wt2
= FP_TO_INT32_OVERFLOW
;
2816 update_fcr31(env
, GETPC());
2820 uint64_t helper_float_round_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2824 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2825 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2826 restore_rounding_mode(env
);
2827 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2828 & (float_flag_invalid
| float_flag_overflow
)) {
2829 dt2
= FP_TO_INT64_OVERFLOW
;
2831 update_fcr31(env
, GETPC());
2835 uint64_t helper_float_round_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2839 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2840 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2841 restore_rounding_mode(env
);
2842 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2843 & (float_flag_invalid
| float_flag_overflow
)) {
2844 dt2
= FP_TO_INT64_OVERFLOW
;
2846 update_fcr31(env
, GETPC());
2850 uint32_t helper_float_round_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2854 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2855 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2856 restore_rounding_mode(env
);
2857 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2858 & (float_flag_invalid
| float_flag_overflow
)) {
2859 wt2
= FP_TO_INT32_OVERFLOW
;
2861 update_fcr31(env
, GETPC());
2865 uint32_t helper_float_round_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2869 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2870 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2871 restore_rounding_mode(env
);
2872 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2873 & (float_flag_invalid
| float_flag_overflow
)) {
2874 wt2
= FP_TO_INT32_OVERFLOW
;
2876 update_fcr31(env
, GETPC());
2880 uint64_t helper_float_trunc_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2884 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2885 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2886 & (float_flag_invalid
| float_flag_overflow
)) {
2887 dt2
= FP_TO_INT64_OVERFLOW
;
2889 update_fcr31(env
, GETPC());
2893 uint64_t helper_float_trunc_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2897 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2898 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2899 & (float_flag_invalid
| float_flag_overflow
)) {
2900 dt2
= FP_TO_INT64_OVERFLOW
;
2902 update_fcr31(env
, GETPC());
2906 uint32_t helper_float_trunc_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2910 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2911 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2912 & (float_flag_invalid
| float_flag_overflow
)) {
2913 wt2
= FP_TO_INT32_OVERFLOW
;
2915 update_fcr31(env
, GETPC());
2919 uint32_t helper_float_trunc_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2923 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2924 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2925 & (float_flag_invalid
| float_flag_overflow
)) {
2926 wt2
= FP_TO_INT32_OVERFLOW
;
2928 update_fcr31(env
, GETPC());
2932 uint64_t helper_float_ceil_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2936 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2937 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2938 restore_rounding_mode(env
);
2939 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2940 & (float_flag_invalid
| float_flag_overflow
)) {
2941 dt2
= FP_TO_INT64_OVERFLOW
;
2943 update_fcr31(env
, GETPC());
2947 uint64_t helper_float_ceil_l_s(CPUMIPSState
*env
, uint32_t fst0
)
2951 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2952 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2953 restore_rounding_mode(env
);
2954 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2955 & (float_flag_invalid
| float_flag_overflow
)) {
2956 dt2
= FP_TO_INT64_OVERFLOW
;
2958 update_fcr31(env
, GETPC());
2962 uint32_t helper_float_ceil_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
2966 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2967 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2968 restore_rounding_mode(env
);
2969 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2970 & (float_flag_invalid
| float_flag_overflow
)) {
2971 wt2
= FP_TO_INT32_OVERFLOW
;
2973 update_fcr31(env
, GETPC());
2977 uint32_t helper_float_ceil_w_s(CPUMIPSState
*env
, uint32_t fst0
)
2981 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2982 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2983 restore_rounding_mode(env
);
2984 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2985 & (float_flag_invalid
| float_flag_overflow
)) {
2986 wt2
= FP_TO_INT32_OVERFLOW
;
2988 update_fcr31(env
, GETPC());
2992 uint64_t helper_float_floor_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
2996 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2997 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2998 restore_rounding_mode(env
);
2999 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3000 & (float_flag_invalid
| float_flag_overflow
)) {
3001 dt2
= FP_TO_INT64_OVERFLOW
;
3003 update_fcr31(env
, GETPC());
3007 uint64_t helper_float_floor_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3011 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3012 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3013 restore_rounding_mode(env
);
3014 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3015 & (float_flag_invalid
| float_flag_overflow
)) {
3016 dt2
= FP_TO_INT64_OVERFLOW
;
3018 update_fcr31(env
, GETPC());
3022 uint32_t helper_float_floor_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3026 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3027 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3028 restore_rounding_mode(env
);
3029 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3030 & (float_flag_invalid
| float_flag_overflow
)) {
3031 wt2
= FP_TO_INT32_OVERFLOW
;
3033 update_fcr31(env
, GETPC());
3037 uint32_t helper_float_floor_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3041 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3042 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3043 restore_rounding_mode(env
);
3044 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3045 & (float_flag_invalid
| float_flag_overflow
)) {
3046 wt2
= FP_TO_INT32_OVERFLOW
;
3048 update_fcr31(env
, GETPC());
3052 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3056 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3057 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3058 & float_flag_invalid
) {
3059 if (float64_is_any_nan(fdt0
)) {
3063 update_fcr31(env
, GETPC());
3067 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3071 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3072 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3073 & float_flag_invalid
) {
3074 if (float32_is_any_nan(fst0
)) {
3078 update_fcr31(env
, GETPC());
3082 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3086 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3087 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3088 & float_flag_invalid
) {
3089 if (float64_is_any_nan(fdt0
)) {
3093 update_fcr31(env
, GETPC());
3097 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3101 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3102 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3103 & float_flag_invalid
) {
3104 if (float32_is_any_nan(fst0
)) {
3108 update_fcr31(env
, GETPC());
3112 uint64_t helper_float_round_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3116 set_float_rounding_mode(float_round_nearest_even
,
3117 &env
->active_fpu
.fp_status
);
3118 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3119 restore_rounding_mode(env
);
3120 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3121 & float_flag_invalid
) {
3122 if (float64_is_any_nan(fdt0
)) {
3126 update_fcr31(env
, GETPC());
3130 uint64_t helper_float_round_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3134 set_float_rounding_mode(float_round_nearest_even
,
3135 &env
->active_fpu
.fp_status
);
3136 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3137 restore_rounding_mode(env
);
3138 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3139 & float_flag_invalid
) {
3140 if (float32_is_any_nan(fst0
)) {
3144 update_fcr31(env
, GETPC());
3148 uint32_t helper_float_round_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3152 set_float_rounding_mode(float_round_nearest_even
,
3153 &env
->active_fpu
.fp_status
);
3154 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3155 restore_rounding_mode(env
);
3156 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3157 & float_flag_invalid
) {
3158 if (float64_is_any_nan(fdt0
)) {
3162 update_fcr31(env
, GETPC());
3166 uint32_t helper_float_round_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3170 set_float_rounding_mode(float_round_nearest_even
,
3171 &env
->active_fpu
.fp_status
);
3172 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3173 restore_rounding_mode(env
);
3174 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3175 & float_flag_invalid
) {
3176 if (float32_is_any_nan(fst0
)) {
3180 update_fcr31(env
, GETPC());
3184 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3188 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3189 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3190 & float_flag_invalid
) {
3191 if (float64_is_any_nan(fdt0
)) {
3195 update_fcr31(env
, GETPC());
3199 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3203 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3204 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3205 & float_flag_invalid
) {
3206 if (float32_is_any_nan(fst0
)) {
3210 update_fcr31(env
, GETPC());
3214 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3218 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
3219 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3220 & float_flag_invalid
) {
3221 if (float64_is_any_nan(fdt0
)) {
3225 update_fcr31(env
, GETPC());
3229 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3233 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
3234 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3235 & float_flag_invalid
) {
3236 if (float32_is_any_nan(fst0
)) {
3240 update_fcr31(env
, GETPC());
3244 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3248 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3249 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3250 restore_rounding_mode(env
);
3251 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3252 & float_flag_invalid
) {
3253 if (float64_is_any_nan(fdt0
)) {
3257 update_fcr31(env
, GETPC());
3261 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3265 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3266 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3267 restore_rounding_mode(env
);
3268 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3269 & float_flag_invalid
) {
3270 if (float32_is_any_nan(fst0
)) {
3274 update_fcr31(env
, GETPC());
3278 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3282 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3283 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3284 restore_rounding_mode(env
);
3285 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3286 & float_flag_invalid
) {
3287 if (float64_is_any_nan(fdt0
)) {
3291 update_fcr31(env
, GETPC());
3295 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3299 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
3300 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3301 restore_rounding_mode(env
);
3302 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3303 & float_flag_invalid
) {
3304 if (float32_is_any_nan(fst0
)) {
3308 update_fcr31(env
, GETPC());
3312 uint64_t helper_float_floor_2008_l_d(CPUMIPSState
*env
, uint64_t fdt0
)
3316 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3317 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3318 restore_rounding_mode(env
);
3319 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3320 & float_flag_invalid
) {
3321 if (float64_is_any_nan(fdt0
)) {
3325 update_fcr31(env
, GETPC());
3329 uint64_t helper_float_floor_2008_l_s(CPUMIPSState
*env
, uint32_t fst0
)
3333 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3334 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3335 restore_rounding_mode(env
);
3336 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3337 & float_flag_invalid
) {
3338 if (float32_is_any_nan(fst0
)) {
3342 update_fcr31(env
, GETPC());
3346 uint32_t helper_float_floor_2008_w_d(CPUMIPSState
*env
, uint64_t fdt0
)
3350 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3351 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3352 restore_rounding_mode(env
);
3353 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3354 & float_flag_invalid
) {
3355 if (float64_is_any_nan(fdt0
)) {
3359 update_fcr31(env
, GETPC());
3363 uint32_t helper_float_floor_2008_w_s(CPUMIPSState
*env
, uint32_t fst0
)
3367 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3368 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3369 restore_rounding_mode(env
);
3370 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3371 & float_flag_invalid
) {
3372 if (float32_is_any_nan(fst0
)) {
3376 update_fcr31(env
, GETPC());
3380 /* unary operations, not modifying fp status */
3381 #define FLOAT_UNOP(name) \
3382 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3384 return float64_ ## name(fdt0); \
3386 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3388 return float32_ ## name(fst0); \
3390 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3395 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3396 wth0 = float32_ ## name(fdt0 >> 32); \
3397 return ((uint64_t)wth0 << 32) | wt0; \
3403 /* MIPS specific unary operations */
3404 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
3408 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3409 update_fcr31(env
, GETPC());
3413 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
3417 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3418 update_fcr31(env
, GETPC());
3422 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
3426 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3427 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3428 update_fcr31(env
, GETPC());
3432 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
3436 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3437 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3438 update_fcr31(env
, GETPC());
3442 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3446 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3447 update_fcr31(env
, GETPC());
3451 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
3455 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3456 update_fcr31(env
, GETPC());
3460 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3465 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3466 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3467 update_fcr31(env
, GETPC());
3468 return ((uint64_t)fsth2
<< 32) | fst2
;
3471 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3475 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3476 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3477 update_fcr31(env
, GETPC());
3481 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3485 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3486 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3487 update_fcr31(env
, GETPC());
3491 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3496 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3497 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3498 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3499 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3500 update_fcr31(env
, GETPC());
3501 return ((uint64_t)fsth2
<< 32) | fst2
;
3504 #define FLOAT_RINT(name, bits) \
3505 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3506 uint ## bits ## _t fs) \
3508 uint ## bits ## _t fdret; \
3510 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3511 update_fcr31(env, GETPC()); \
3515 FLOAT_RINT(rint_s
, 32)
3516 FLOAT_RINT(rint_d
, 64)
3519 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3520 #define FLOAT_CLASS_QUIET_NAN 0x002
3521 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3522 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3523 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3524 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3525 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3526 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3527 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3528 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3530 #define FLOAT_CLASS(name, bits) \
3531 uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3532 float_status *status) \
3534 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3535 return FLOAT_CLASS_SIGNALING_NAN; \
3536 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3537 return FLOAT_CLASS_QUIET_NAN; \
3538 } else if (float ## bits ## _is_neg(arg)) { \
3539 if (float ## bits ## _is_infinity(arg)) { \
3540 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3541 } else if (float ## bits ## _is_zero(arg)) { \
3542 return FLOAT_CLASS_NEGATIVE_ZERO; \
3543 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3544 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3546 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3549 if (float ## bits ## _is_infinity(arg)) { \
3550 return FLOAT_CLASS_POSITIVE_INFINITY; \
3551 } else if (float ## bits ## _is_zero(arg)) { \
3552 return FLOAT_CLASS_POSITIVE_ZERO; \
3553 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3554 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3556 return FLOAT_CLASS_POSITIVE_NORMAL; \
3561 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3562 uint ## bits ## _t arg) \
3564 return float_ ## name(arg, &env->active_fpu.fp_status); \
3567 FLOAT_CLASS(class_s
, 32)
3568 FLOAT_CLASS(class_d
, 64)
3571 /* binary operations */
3572 #define FLOAT_BINOP(name) \
3573 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3574 uint64_t fdt0, uint64_t fdt1) \
3578 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3579 update_fcr31(env, GETPC()); \
3583 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3584 uint32_t fst0, uint32_t fst1) \
3588 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3589 update_fcr31(env, GETPC()); \
3593 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3597 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3598 uint32_t fsth0 = fdt0 >> 32; \
3599 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3600 uint32_t fsth1 = fdt1 >> 32; \
3604 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3605 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3606 update_fcr31(env, GETPC()); \
3607 return ((uint64_t)wth2 << 32) | wt2; \
3616 /* MIPS specific binary operations */
3617 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3619 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3620 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3621 update_fcr31(env
, GETPC());
3625 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3627 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3628 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3629 update_fcr31(env
, GETPC());
3633 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3635 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3636 uint32_t fsth0
= fdt0
>> 32;
3637 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3638 uint32_t fsth2
= fdt2
>> 32;
3640 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3641 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3642 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3643 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3644 update_fcr31(env
, GETPC());
3645 return ((uint64_t)fsth2
<< 32) | fst2
;
3648 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3650 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3651 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3652 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3653 update_fcr31(env
, GETPC());
3657 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3659 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3660 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3661 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3662 update_fcr31(env
, GETPC());
3666 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3668 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3669 uint32_t fsth0
= fdt0
>> 32;
3670 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3671 uint32_t fsth2
= fdt2
>> 32;
3673 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3674 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3675 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3676 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3677 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3678 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3679 update_fcr31(env
, GETPC());
3680 return ((uint64_t)fsth2
<< 32) | fst2
;
3683 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3685 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3686 uint32_t fsth0
= fdt0
>> 32;
3687 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3688 uint32_t fsth1
= fdt1
>> 32;
3692 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3693 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3694 update_fcr31(env
, GETPC());
3695 return ((uint64_t)fsth2
<< 32) | fst2
;
3698 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3700 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3701 uint32_t fsth0
= fdt0
>> 32;
3702 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3703 uint32_t fsth1
= fdt1
>> 32;
3707 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3708 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3709 update_fcr31(env
, GETPC());
3710 return ((uint64_t)fsth2
<< 32) | fst2
;
3713 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3714 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3715 uint ## bits ## _t fs, \
3716 uint ## bits ## _t ft) \
3718 uint ## bits ## _t fdret; \
3720 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3721 &env->active_fpu.fp_status); \
3722 update_fcr31(env, GETPC()); \
3726 FLOAT_MINMAX(max_s
, 32, maxnum
)
3727 FLOAT_MINMAX(max_d
, 64, maxnum
)
3728 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
3729 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
3731 FLOAT_MINMAX(min_s
, 32, minnum
)
3732 FLOAT_MINMAX(min_d
, 64, minnum
)
3733 FLOAT_MINMAX(mina_s
, 32, minnummag
)
3734 FLOAT_MINMAX(mina_d
, 64, minnummag
)
3737 /* ternary operations */
3738 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3740 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3741 if ((flags) & float_muladd_negate_c) { \
3742 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3744 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3746 if ((flags) & float_muladd_negate_result) { \
3747 a = prefix##_chs(a); \
3751 /* FMA based operations */
3752 #define FLOAT_FMA(name, type) \
3753 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3754 uint64_t fdt0, uint64_t fdt1, \
3757 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3758 update_fcr31(env, GETPC()); \
3762 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3763 uint32_t fst0, uint32_t fst1, \
3766 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3767 update_fcr31(env, GETPC()); \
3771 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3772 uint64_t fdt0, uint64_t fdt1, \
3775 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3776 uint32_t fsth0 = fdt0 >> 32; \
3777 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3778 uint32_t fsth1 = fdt1 >> 32; \
3779 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3780 uint32_t fsth2 = fdt2 >> 32; \
3782 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3783 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3784 update_fcr31(env, GETPC()); \
3785 return ((uint64_t)fsth0 << 32) | fst0; \
3788 FLOAT_FMA(msub
, float_muladd_negate_c
)
3789 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
3790 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
3793 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3794 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3795 uint ## bits ## _t fs, \
3796 uint ## bits ## _t ft, \
3797 uint ## bits ## _t fd) \
3799 uint ## bits ## _t fdret; \
3801 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3802 &env->active_fpu.fp_status); \
3803 update_fcr31(env, GETPC()); \
3807 FLOAT_FMADDSUB(maddf_s
, 32, 0)
3808 FLOAT_FMADDSUB(maddf_d
, 64, 0)
3809 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
3810 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
3811 #undef FLOAT_FMADDSUB
3813 /* compare operations */
3814 #define FOP_COND_D(op, cond) \
3815 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3816 uint64_t fdt1, int cc) \
3820 update_fcr31(env, GETPC()); \
3822 SET_FP_COND(cc, env->active_fpu); \
3824 CLEAR_FP_COND(cc, env->active_fpu); \
3826 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3827 uint64_t fdt1, int cc) \
3830 fdt0 = float64_abs(fdt0); \
3831 fdt1 = float64_abs(fdt1); \
3833 update_fcr31(env, GETPC()); \
3835 SET_FP_COND(cc, env->active_fpu); \
3837 CLEAR_FP_COND(cc, env->active_fpu); \
3840 /* NOTE: the comma operator will make "cond" to eval to false,
3841 * but float64_unordered_quiet() is still called. */
3842 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3843 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3844 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3845 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3846 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3847 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3848 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3849 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3850 /* NOTE: the comma operator will make "cond" to eval to false,
3851 * but float64_unordered() is still called. */
3852 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3853 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3854 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3855 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3856 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3857 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3858 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3859 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3861 #define FOP_COND_S(op, cond) \
3862 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3863 uint32_t fst1, int cc) \
3867 update_fcr31(env, GETPC()); \
3869 SET_FP_COND(cc, env->active_fpu); \
3871 CLEAR_FP_COND(cc, env->active_fpu); \
3873 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3874 uint32_t fst1, int cc) \
3877 fst0 = float32_abs(fst0); \
3878 fst1 = float32_abs(fst1); \
3880 update_fcr31(env, GETPC()); \
3882 SET_FP_COND(cc, env->active_fpu); \
3884 CLEAR_FP_COND(cc, env->active_fpu); \
3887 /* NOTE: the comma operator will make "cond" to eval to false,
3888 * but float32_unordered_quiet() is still called. */
3889 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3890 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3891 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3892 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3893 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3894 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3895 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3896 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3897 /* NOTE: the comma operator will make "cond" to eval to false,
3898 * but float32_unordered() is still called. */
3899 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3900 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3901 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3902 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3903 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3904 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3905 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3906 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3908 #define FOP_COND_PS(op, condl, condh) \
3909 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3910 uint64_t fdt1, int cc) \
3912 uint32_t fst0, fsth0, fst1, fsth1; \
3914 fst0 = fdt0 & 0XFFFFFFFF; \
3915 fsth0 = fdt0 >> 32; \
3916 fst1 = fdt1 & 0XFFFFFFFF; \
3917 fsth1 = fdt1 >> 32; \
3920 update_fcr31(env, GETPC()); \
3922 SET_FP_COND(cc, env->active_fpu); \
3924 CLEAR_FP_COND(cc, env->active_fpu); \
3926 SET_FP_COND(cc + 1, env->active_fpu); \
3928 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3930 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3931 uint64_t fdt1, int cc) \
3933 uint32_t fst0, fsth0, fst1, fsth1; \
3935 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3936 fsth0 = float32_abs(fdt0 >> 32); \
3937 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3938 fsth1 = float32_abs(fdt1 >> 32); \
3941 update_fcr31(env, GETPC()); \
3943 SET_FP_COND(cc, env->active_fpu); \
3945 CLEAR_FP_COND(cc, env->active_fpu); \
3947 SET_FP_COND(cc + 1, env->active_fpu); \
3949 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3952 /* NOTE: the comma operator will make "cond" to eval to false,
3953 * but float32_unordered_quiet() is still called. */
3954 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3955 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3956 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3957 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3958 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3959 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3960 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3961 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3962 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3963 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3964 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3965 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3966 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3967 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3968 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3969 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3970 /* NOTE: the comma operator will make "cond" to eval to false,
3971 * but float32_unordered() is still called. */
3972 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3973 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3974 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3975 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3976 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3977 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3978 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3979 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3980 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3981 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3982 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3983 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3984 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3985 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3986 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3987 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3989 /* R6 compare operations */
3990 #define FOP_CONDN_D(op, cond) \
3991 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3996 update_fcr31(env, GETPC()); \
4004 /* NOTE: the comma operator will make "cond" to eval to false,
4005 * but float64_unordered_quiet() is still called. */
4006 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4007 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4008 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4009 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4010 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4011 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4012 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4013 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4014 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4015 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4016 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4017 /* NOTE: the comma operator will make "cond" to eval to false,
4018 * but float64_unordered() is still called. */
4019 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
4020 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
4021 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4022 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4023 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4024 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4025 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4026 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4027 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4028 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4029 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4030 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4031 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4032 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4033 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4034 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4035 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4036 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4037 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4038 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4039 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4040 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4041 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4042 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
4043 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
4045 #define FOP_CONDN_S(op, cond) \
4046 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4051 update_fcr31(env, GETPC()); \
4059 /* NOTE: the comma operator will make "cond" to eval to false,
4060 * but float32_unordered_quiet() is still called. */
4061 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4062 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4063 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4064 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4065 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4066 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4067 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4068 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4069 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4070 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4071 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4072 /* NOTE: the comma operator will make "cond" to eval to false,
4073 * but float32_unordered() is still called. */
4074 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
4075 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
4076 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4077 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4078 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4079 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4080 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4081 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4082 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4083 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4084 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4085 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4086 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4087 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4088 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4089 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4090 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4091 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4092 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4093 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4094 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4095 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4096 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4097 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
4098 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
4101 /* Data format min and max values */
4102 #define DF_BITS(df) (1 << ((df) + 3))
4104 /* Element-by-element access macros */
4105 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4107 #if !defined(CONFIG_USER_ONLY)
4108 #define MEMOP_IDX(DF) \
4109 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4110 cpu_mmu_index(env, false));
4112 #define MEMOP_IDX(DF)
4115 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
4116 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4117 target_ulong addr) \
4119 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4123 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4124 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
4126 memcpy(pwd, &wx, sizeof(wr_t)); \
4129 #if !defined(CONFIG_USER_ONLY)
4130 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETRA())
4131 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETRA())
4132 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETRA())
4133 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETRA())
4135 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
4136 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
4137 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
4138 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
4141 #define MSA_PAGESPAN(x) \
4142 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4144 static inline void ensure_writable_pages(CPUMIPSState
*env
,
4149 #if !defined(CONFIG_USER_ONLY)
4150 target_ulong page_addr
;
4151 if (unlikely(MSA_PAGESPAN(addr
))) {
4153 probe_write(env
, addr
, mmu_idx
, retaddr
);
4155 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4156 probe_write(env
, page_addr
, mmu_idx
, retaddr
);
4161 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
4162 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
4163 target_ulong addr) \
4165 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
4166 int mmu_idx = cpu_mmu_index(env, false); \
4169 ensure_writable_pages(env, addr, mmu_idx, GETRA()); \
4170 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
4171 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
4175 #if !defined(CONFIG_USER_ONLY)
4176 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETRA())
4177 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETRA())
4178 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETRA())
4179 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETRA())
4181 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
4182 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
4183 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
4184 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)
4187 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
4189 #ifndef CONFIG_USER_ONLY
4190 target_ulong index
= addr
& 0x1fffffff;
4192 /* Index Store Tag */
4193 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
4194 8, MEMTXATTRS_UNSPECIFIED
);
4195 } else if (op
== 5) {
4196 /* Index Load Tag */
4197 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
4198 8, MEMTXATTRS_UNSPECIFIED
);