include/hw/ppc/xive.h

   1 /*
   2  * QEMU PowerPC XIVE interrupt controller model
   3  *
   4  *
   5  * The POWER9 processor comes with a new interrupt controller, called
   6  * XIVE as "eXternal Interrupt Virtualization Engine".
   7  *
   8  * = Overall architecture
   9  *
  10  *
  11  *              XIVE Interrupt Controller
  12  *              +------------------------------------+      IPIs
  13  *              | +---------+ +---------+ +--------+ |    +-------+
  14  *              | |VC       | |CQ       | |PC      |----> | CORES |
  15  *              | |     esb | |         | |        |----> |       |
  16  *              | |     eas | |  Bridge | |   tctx |----> |       |
  17  *              | |SC   end | |         | |    nvt | |    |       |
  18  *  +------+    | +---------+ +----+----+ +--------+ |    +-+-+-+-+
  19  *  | RAM  |    +------------------|-----------------+      | | |
  20  *  |      |                       |                        | | |
  21  *  |      |                       |                        | | |
  22  *  |      |  +--------------------v------------------------v-v-v--+    other
  23  *  |      <--+                     Power Bus                      +--> chips
  24  *  |  esb |  +---------+-----------------------+------------------+
  25  *  |  eas |            |                       |
  26  *  |  end |         +--|------+                |
  27  *  |  nvt |       +----+----+ |           +----+----+
  28  *  +------+       |SC       | |           |SC       |
  29  *                 |         | |           |         |
  30  *                 | PQ-bits | |           | PQ-bits |
  31  *                 | local   |-+           |  in VC  |
  32  *                 +---------+             +---------+
  33  *                    PCIe                 NX,NPU,CAPI
  34  *
  35  *                   SC: Source Controller (aka. IVSE)
  36  *                   VC: Virtualization Controller (aka. IVRE)
  37  *                   PC: Presentation Controller (aka. IVPE)
  38  *                   CQ: Common Queue (Bridge)
  39  *
  40  *              PQ-bits: 2 bits source state machine (P:pending Q:queued)
  41  *                  esb: Event State Buffer (Array of PQ bits in an IVSE)
  42  *                  eas: Event Assignment Structure
  43  *                  end: Event Notification Descriptor
  44  *                  nvt: Notification Virtual Target
  45  *                 tctx: Thread interrupt Context
  46  *
  47  *
  48  * The XIVE IC is composed of three sub-engines :
  49  *
  50  * - Interrupt Virtualization Source Engine (IVSE), or Source
  51  *   Controller (SC). These are found in PCI PHBs, in the PSI host
  52  *   bridge controller, but also inside the main controller for the
  53  *   core IPIs and other sub-chips (NX, CAP, NPU) of the
  54  *   chip/processor. They are configured to feed the IVRE with events.
  55  *
  56  * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
  57  *   Controller (VC). Its job is to match an event source with an
  58  *   Event Notification Descriptor (END).
  59  *
  60  * - Interrupt Virtualization Presentation Engine (IVPE) or
  61  *   Presentation Controller (PC). It maintains the interrupt context
  62  *   state of each thread and handles the delivery of the external
  63  *   exception to the thread.
  64  *
  65  * In XIVE 1.0, the sub-engines used to be referred as:
  66  *
  67  *   SC     Source Controller
  68  *   VC     Virtualization Controller
  69  *   PC     Presentation Controller
  70  *   CQ     Common Queue (PowerBUS Bridge)
  71  *
  72  *
  73  * = XIVE internal tables
  74  *
  75  * Each of the sub-engines uses a set of tables to redirect exceptions
  76  * from event sources to CPU threads.
  77  *
  78  *                                           +-------+
  79  *   User or OS                              |  EQ   |
  80  *       or                          +------>|entries|
  81  *   Hypervisor                      |       |  ..   |
  82  *     Memory                        |       +-------+
  83  *                                   |           ^
  84  *                                   |           |
  85  *              +-------------------------------------------------+
  86  *                                   |           |
  87  *   Hypervisor      +------+    +---+--+    +---+--+   +------+
  88  *     Memory        | ESB  |    | EAT  |    | ENDT |   | NVTT |
  89  *    (skiboot)      +----+-+    +----+-+    +----+-+   +------+
  90  *                     ^  |        ^  |        ^  |       ^
  91  *                     |  |        |  |        |  |       |
  92  *              +-------------------------------------------------+
  93  *                     |  |        |  |        |  |       |
  94  *                     |  |        |  |        |  |       |
  95  *                +----|--|--------|--|--------|--|-+   +-|-----+    +------+
  96  *                |    |  |        |  |        |  | |   | | tctx|    |Thread|
  97  *   IPI or   --> |    +  v        +  v        +  v |---| +  .. |----->     |
  98  *  HW events --> |                                 |   |       |    |      |
  99  *    IVSE        |             IVRE                |   | IVPE  |    +------+
 100  *                +---------------------------------+   +-------+
 101  *
 102  *
 103  *
 104  * The IVSE have a 2-bits state machine, P for pending and Q for queued,
 105  * for each source that allows events to be triggered. They are stored in
 106  * an Event State Buffer (ESB) array and can be controlled by MMIOs.
 107  *
 108  * If the event is let through, the IVRE looks up in the Event Assignment
 109  * Structure (EAS) table for an Event Notification Descriptor (END)
 110  * configured for the source. Each Event Notification Descriptor defines
 111  * a notification path to a CPU and an in-memory Event Queue, in which
 112  * will be enqueued an EQ data for the OS to pull.
 113  *
 114  * The IVPE determines if a Notification Virtual Target (NVT) can
 115  * handle the event by scanning the thread contexts of the VCPUs
 116  * dispatched on the processor HW threads. It maintains the state of
 117  * the thread interrupt context (TCTX) of each thread in a NVT table.
 118  *
 119  * = Acronyms
 120  *
 121  *          Description                     In XIVE 1.0, used to be referred as
 122  *
 123  *   EAS    Event Assignment Structure      IVE   Interrupt Virt. Entry
 124  *   EAT    Event Assignment Table          IVT   Interrupt Virt. Table
 125  *   ENDT   Event Notif. Descriptor Table   EQDT  Event Queue Desc. Table
 126  *   EQ     Event Queue                     same
 127  *   ESB    Event State Buffer              SBE   State Bit Entry
 128  *   NVT    Notif. Virtual Target           VPD   Virtual Processor Desc.
 129  *   NVTT   Notif. Virtual Target Table     VPDT  Virtual Processor Desc. Table
 130  *   TCTX   Thread interrupt Context
 131  *
 132  *
 133  * Copyright (c) 2017-2018, IBM Corporation.
 134  *
 135  * This code is licensed under the GPL version 2 or later. See the
 136  * COPYING file in the top-level directory.
 137  *
 138  */
 139
 140 #ifndef PPC_XIVE_H
 141 #define PPC_XIVE_H
 142
 143 #include "hw/qdev-core.h"
 144 #include "hw/sysbus.h"
 145 #include "hw/ppc/xive_regs.h"
 146
 147 /*
 148  * XIVE Fabric (Interface between Source and Router)
 149  */
 150
 151 typedef struct XiveNotifier {
 152     Object parent;
 153 } XiveNotifier;
 154
 155 #define TYPE_XIVE_NOTIFIER "xive-notifier"
 156 #define XIVE_NOTIFIER(obj)                                     \
 157     OBJECT_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
 158 #define XIVE_NOTIFIER_CLASS(klass)                                     \
 159     OBJECT_CLASS_CHECK(XiveNotifierClass, (klass), TYPE_XIVE_NOTIFIER)
 160 #define XIVE_NOTIFIER_GET_CLASS(obj)                                   \
 161     OBJECT_GET_CLASS(XiveNotifierClass, (obj), TYPE_XIVE_NOTIFIER)
 162
 163 typedef struct XiveNotifierClass {
 164     InterfaceClass parent;
 165     void (*notify)(XiveNotifier *xn, uint32_t lisn);
 166 } XiveNotifierClass;
 167
 168 /*
 169  * XIVE Interrupt Source
 170  */
 171
 172 #define TYPE_XIVE_SOURCE "xive-source"
 173 #define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE)
 174
 175 /*
 176  * XIVE Interrupt Source characteristics, which define how the ESB are
 177  * controlled.
 178  */
 179 #define XIVE_SRC_H_INT_ESB     0x1 /* ESB managed with hcall H_INT_ESB */
 180 #define XIVE_SRC_STORE_EOI     0x2 /* Store EOI supported */
 181
 182 typedef struct XiveSource {
 183     DeviceState parent;
 184
 185     /* IRQs */
 186     uint32_t        nr_irqs;
 187     unsigned long   *lsi_map;
 188
 189     /* PQ bits and LSI assertion bit */
 190     uint8_t         *status;
 191
 192     /* ESB memory region */
 193     uint64_t        esb_flags;
 194     uint32_t        esb_shift;
 195     MemoryRegion    esb_mmio;
 196
 197     XiveNotifier    *xive;
 198 } XiveSource;
 199
 200 /*
 201  * ESB MMIO setting. Can be one page, for both source triggering and
 202  * source management, or two different pages. See below for magic
 203  * values.
 204  */
 205 #define XIVE_ESB_4K          12 /* PSI HB only */
 206 #define XIVE_ESB_4K_2PAGE    13
 207 #define XIVE_ESB_64K         16
 208 #define XIVE_ESB_64K_2PAGE   17
 209
 210 static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
 211 {
 212     return xsrc->esb_shift == XIVE_ESB_64K_2PAGE ||
 213         xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
 214 }
 215
 216 /* The trigger page is always the first/even page */
 217 static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno)
 218 {
 219     assert(srcno < xsrc->nr_irqs);
 220     return (1ull << xsrc->esb_shift) * srcno;
 221 }
 222
 223 /* In a two pages ESB MMIO setting, the odd page is for management */
 224 static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno)
 225 {
 226     hwaddr addr = xive_source_esb_page(xsrc, srcno);
 227
 228     if (xive_source_esb_has_2page(xsrc)) {
 229         addr += (1 << (xsrc->esb_shift - 1));
 230     }
 231
 232     return addr;
 233 }
 234
 235 /*
 236  * Each interrupt source has a 2-bit state machine which can be
 237  * controlled by MMIO. P indicates that an interrupt is pending (has
 238  * been sent to a queue and is waiting for an EOI). Q indicates that
 239  * the interrupt has been triggered while pending.
 240  *
 241  * This acts as a coalescing mechanism in order to guarantee that a
 242  * given interrupt only occurs at most once in a queue.
 243  *
 244  * When doing an EOI, the Q bit will indicate if the interrupt
 245  * needs to be re-triggered.
 246  */
 247 #define XIVE_STATUS_ASSERTED  0x4  /* Extra bit for LSI */
 248 #define XIVE_ESB_VAL_P        0x2
 249 #define XIVE_ESB_VAL_Q        0x1
 250
 251 #define XIVE_ESB_RESET        0x0
 252 #define XIVE_ESB_PENDING      XIVE_ESB_VAL_P
 253 #define XIVE_ESB_QUEUED       (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
 254 #define XIVE_ESB_OFF          XIVE_ESB_VAL_Q
 255
 256 /*
 257  * "magic" Event State Buffer (ESB) MMIO offsets.
 258  *
 259  * The following offsets into the ESB MMIO allow to read or manipulate
 260  * the PQ bits. They must be used with an 8-byte load instruction.
 261  * They all return the previous state of the interrupt (atomically).
 262  *
 263  * Additionally, some ESB pages support doing an EOI via a store and
 264  * some ESBs support doing a trigger via a separate trigger page.
 265  */
 266 #define XIVE_ESB_STORE_EOI      0x400 /* Store */
 267 #define XIVE_ESB_LOAD_EOI       0x000 /* Load */
 268 #define XIVE_ESB_GET            0x800 /* Load */
 269 #define XIVE_ESB_SET_PQ_00      0xc00 /* Load */
 270 #define XIVE_ESB_SET_PQ_01      0xd00 /* Load */
 271 #define XIVE_ESB_SET_PQ_10      0xe00 /* Load */
 272 #define XIVE_ESB_SET_PQ_11      0xf00 /* Load */
 273
 274 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno);
 275 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
 276
 277 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
 278                                 Monitor *mon);
 279
 280 static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
 281 {
 282     assert(srcno < xsrc->nr_irqs);
 283     return test_bit(srcno, xsrc->lsi_map);
 284 }
 285
 286 static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno,
 287                                        bool lsi)
 288 {
 289     assert(srcno < xsrc->nr_irqs);
 290     if (lsi) {
 291         bitmap_set(xsrc->lsi_map, srcno, 1);
 292     }
 293 }
 294
 295 void xive_source_set_irq(void *opaque, int srcno, int val);
 296
 297 /*
 298  * XIVE Router
 299  */
 300
 301 typedef struct XiveRouter {
 302     SysBusDevice    parent;
 303 } XiveRouter;
 304
 305 #define TYPE_XIVE_ROUTER "xive-router"
 306 #define XIVE_ROUTER(obj)                                \
 307     OBJECT_CHECK(XiveRouter, (obj), TYPE_XIVE_ROUTER)
 308 #define XIVE_ROUTER_CLASS(klass)                                        \
 309     OBJECT_CLASS_CHECK(XiveRouterClass, (klass), TYPE_XIVE_ROUTER)
 310 #define XIVE_ROUTER_GET_CLASS(obj)                              \
 311     OBJECT_GET_CLASS(XiveRouterClass, (obj), TYPE_XIVE_ROUTER)
 312
 313 typedef struct XiveRouterClass {
 314     SysBusDeviceClass parent;
 315
 316     /* XIVE table accessors */
 317     int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
 318                    XiveEAS *eas);
 319     int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
 320                    XiveEND *end);
 321     int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
 322                      XiveEND *end, uint8_t word_number);
 323     int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 324                    XiveNVT *nvt);
 325     int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 326                      XiveNVT *nvt, uint8_t word_number);
 327 } XiveRouterClass;
 328
 329 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
 330
 331 int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
 332                         XiveEAS *eas);
 333 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
 334                         XiveEND *end);
 335 int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
 336                           XiveEND *end, uint8_t word_number);
 337 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 338                         XiveNVT *nvt);
 339 int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 340                           XiveNVT *nvt, uint8_t word_number);
 341
 342
 343 /*
 344  * XIVE END ESBs
 345  */
 346
 347 #define TYPE_XIVE_END_SOURCE "xive-end-source"
 348 #define XIVE_END_SOURCE(obj) \
 349     OBJECT_CHECK(XiveENDSource, (obj), TYPE_XIVE_END_SOURCE)
 350
 351 typedef struct XiveENDSource {
 352     DeviceState parent;
 353
 354     uint32_t        nr_ends;
 355     uint8_t         block_id;
 356
 357     /* ESB memory region */
 358     uint32_t        esb_shift;
 359     MemoryRegion    esb_mmio;
 360
 361     XiveRouter      *xrtr;
 362 } XiveENDSource;
 363
 364 /*
 365  * For legacy compatibility, the exceptions define up to 256 different
 366  * priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
 367  * and the least favored level 0xFF.
 368  */
 369 #define XIVE_PRIORITY_MAX  7
 370
 371 void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
 372 void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
 373
 374 /*
 375  * XIVE Thread interrupt Management (TM) context
 376  */
 377
 378 #define TYPE_XIVE_TCTX "xive-tctx"
 379 #define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
 380
 381 /*
 382  * XIVE Thread interrupt Management register rings :
 383  *
 384  *   QW-0  User       event-based exception state
 385  *   QW-1  O/S        OS context for priority management, interrupt acks
 386  *   QW-2  Pool       hypervisor pool context for virtual processors dispatched
 387  *   QW-3  Physical   physical thread context and security context
 388  */
 389 #define XIVE_TM_RING_COUNT      4
 390 #define XIVE_TM_RING_SIZE       0x10
 391
 392 typedef struct XiveTCTX {
 393     DeviceState parent_obj;
 394
 395     CPUState    *cs;
 396     qemu_irq    output;
 397
 398     uint8_t     regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
 399 } XiveTCTX;
 400
 401 /*
 402  * XIVE Thread Interrupt Management Aera (TIMA)
 403  *
 404  * This region gives access to the registers of the thread interrupt
 405  * management context. It is four page wide, each page providing a
 406  * different view of the registers. The page with the lower offset is
 407  * the most privileged and gives access to the entire context.
 408  */
 409 #define XIVE_TM_HW_PAGE         0x0
 410 #define XIVE_TM_HV_PAGE         0x1
 411 #define XIVE_TM_OS_PAGE         0x2
 412 #define XIVE_TM_USER_PAGE       0x3
 413
 414 extern const MemoryRegionOps xive_tm_ops;
 415
 416 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
 417 Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
 418
 419 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx)
 420 {
 421     return (nvt_blk << 19) | nvt_idx;
 422 }
 423
 424 #endif /* PPC_XIVE_H */