hw/ppc/spapr_irq.c

   1 /*
   2  * QEMU PowerPC sPAPR IRQ interface
   3  *
   4  * Copyright (c) 2018, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/error-report.h"
  13 #include "qapi/error.h"
  14 #include "hw/ppc/spapr.h"
  15 #include "hw/ppc/spapr_xive.h"
  16 #include "hw/ppc/xics.h"
  17 #include "sysemu/kvm.h"
  18
  19 #include "trace.h"
  20
  21 void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
  22 {
  23     spapr->irq_map_nr = nr_msis;
  24     spapr->irq_map = bitmap_new(spapr->irq_map_nr);
  25 }
  26
  27 int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
  28                         Error **errp)
  29 {
  30     int irq;
  31
  32     /*
  33      * The 'align_mask' parameter of bitmap_find_next_zero_area()
  34      * should be one less than a power of 2; 0 means no
  35      * alignment. Adapt the 'align' value of the former allocator
  36      * to fit the requirements of bitmap_find_next_zero_area()
  37      */
  38     align -= 1;
  39
  40     irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
  41                                      align);
  42     if (irq == spapr->irq_map_nr) {
  43         error_setg(errp, "can't find a free %d-IRQ block", num);
  44         return -1;
  45     }
  46
  47     bitmap_set(spapr->irq_map, irq, num);
  48
  49     return irq + SPAPR_IRQ_MSI;
  50 }
  51
  52 void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
  53 {
  54     bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
  55 }
  56
  57 void spapr_irq_msi_reset(sPAPRMachineState *spapr)
  58 {
  59     bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
  60 }
  61
  62
  63 /*
  64  * XICS IRQ backend.
  65  */
  66
  67 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
  68                                   const char *type_ics,
  69                                   int nr_irqs, Error **errp)
  70 {
  71     Error *local_err = NULL;
  72     Object *obj;
  73
  74     obj = object_new(type_ics);
  75     object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
  76     object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
  77                                    &error_abort);
  78     object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
  79     if (local_err) {
  80         goto error;
  81     }
  82     object_property_set_bool(obj, true, "realized", &local_err);
  83     if (local_err) {
  84         goto error;
  85     }
  86
  87     return ICS_BASE(obj);
  88
  89 error:
  90     error_propagate(errp, local_err);
  91     return NULL;
  92 }
  93
  94 static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
  95 {
  96     MachineState *machine = MACHINE(spapr);
  97     int nr_irqs = spapr->irq->nr_irqs;
  98     Error *local_err = NULL;
  99
 100     if (kvm_enabled()) {
 101         if (machine_kernel_irqchip_allowed(machine) &&
 102             !xics_kvm_init(spapr, &local_err)) {
 103             spapr->icp_type = TYPE_KVM_ICP;
 104             spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
 105                                           &local_err);
 106         }
 107         if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
 108             error_prepend(&local_err,
 109                           "kernel_irqchip requested but unavailable: ");
 110             goto error;
 111         }
 112         error_free(local_err);
 113         local_err = NULL;
 114     }
 115
 116     if (!spapr->ics) {
 117         xics_spapr_init(spapr);
 118         spapr->icp_type = TYPE_ICP;
 119         spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
 120                                       &local_err);
 121     }
 122
 123 error:
 124     error_propagate(errp, local_err);
 125 }
 126
 127 #define ICS_IRQ_FREE(ics, srcno)   \
 128     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
 129
 130 static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
 131                                 Error **errp)
 132 {
 133     ICSState *ics = spapr->ics;
 134
 135     assert(ics);
 136
 137     if (!ics_valid_irq(ics, irq)) {
 138         error_setg(errp, "IRQ %d is invalid", irq);
 139         return -1;
 140     }
 141
 142     if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
 143         error_setg(errp, "IRQ %d is not free", irq);
 144         return -1;
 145     }
 146
 147     ics_set_irq_type(ics, irq - ics->offset, lsi);
 148     return 0;
 149 }
 150
 151 static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
 152 {
 153     ICSState *ics = spapr->ics;
 154     uint32_t srcno = irq - ics->offset;
 155     int i;
 156
 157     if (ics_valid_irq(ics, irq)) {
 158         trace_spapr_irq_free(0, irq, num);
 159         for (i = srcno; i < srcno + num; ++i) {
 160             if (ICS_IRQ_FREE(ics, i)) {
 161                 trace_spapr_irq_free_warn(0, i);
 162             }
 163             memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
 164         }
 165     }
 166 }
 167
 168 static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
 169 {
 170     ICSState *ics = spapr->ics;
 171     uint32_t srcno = irq - ics->offset;
 172
 173     if (ics_valid_irq(ics, irq)) {
 174         return spapr->qirqs[srcno];
 175     }
 176
 177     return NULL;
 178 }
 179
 180 static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
 181 {
 182     CPUState *cs;
 183
 184     CPU_FOREACH(cs) {
 185         PowerPCCPU *cpu = POWERPC_CPU(cs);
 186
 187         icp_pic_print_info(cpu->icp, mon);
 188     }
 189
 190     ics_pic_print_info(spapr->ics, mon);
 191 }
 192
 193 static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
 194                                            PowerPCCPU *cpu, Error **errp)
 195 {
 196     Error *local_err = NULL;
 197     Object *obj;
 198
 199     obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
 200                      &local_err);
 201     if (local_err) {
 202         error_propagate(errp, local_err);
 203         return;
 204     }
 205
 206     cpu->icp = ICP(obj);
 207 }
 208
 209 static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
 210 {
 211     if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
 212         CPUState *cs;
 213         CPU_FOREACH(cs) {
 214             PowerPCCPU *cpu = POWERPC_CPU(cs);
 215             icp_resend(cpu->icp);
 216         }
 217     }
 218     return 0;
 219 }
 220
 221 static void spapr_irq_set_irq_xics(void *opaque, int srcno, int val)
 222 {
 223     sPAPRMachineState *spapr = opaque;
 224     MachineState *machine = MACHINE(opaque);
 225
 226     if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
 227         ics_kvm_set_irq(spapr->ics, srcno, val);
 228     } else {
 229         ics_simple_set_irq(spapr->ics, srcno, val);
 230     }
 231 }
 232
 233 #define SPAPR_IRQ_XICS_NR_IRQS     0x1000
 234 #define SPAPR_IRQ_XICS_NR_MSIS     \
 235     (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
 236
 237 sPAPRIrq spapr_irq_xics = {
 238     .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
 239     .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
 240     .ov5         = SPAPR_OV5_XIVE_LEGACY,
 241
 242     .init        = spapr_irq_init_xics,
 243     .claim       = spapr_irq_claim_xics,
 244     .free        = spapr_irq_free_xics,
 245     .qirq        = spapr_qirq_xics,
 246     .print_info  = spapr_irq_print_info_xics,
 247     .dt_populate = spapr_dt_xics,
 248     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
 249     .post_load   = spapr_irq_post_load_xics,
 250     .set_irq     = spapr_irq_set_irq_xics,
 251 };
 252
 253 /*
 254  * XIVE IRQ backend.
 255  */
 256 static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
 257 {
 258     MachineState *machine = MACHINE(spapr);
 259     uint32_t nr_servers = spapr_max_server_number(spapr);
 260     DeviceState *dev;
 261     int i;
 262
 263     /* KVM XIVE device not yet available */
 264     if (kvm_enabled()) {
 265         if (machine_kernel_irqchip_required(machine)) {
 266             error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
 267             return;
 268         }
 269     }
 270
 271     dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
 272     qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs);
 273     /*
 274      * 8 XIVE END structures per CPU. One for each available priority
 275      */
 276     qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
 277     qdev_init_nofail(dev);
 278
 279     spapr->xive = SPAPR_XIVE(dev);
 280
 281     /* Enable the CPU IPIs */
 282     for (i = 0; i < nr_servers; ++i) {
 283         spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
 284     }
 285
 286     spapr_xive_hcall_init(spapr);
 287 }
 288
 289 static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
 290                                 Error **errp)
 291 {
 292     if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
 293         error_setg(errp, "IRQ %d is invalid", irq);
 294         return -1;
 295     }
 296     return 0;
 297 }
 298
 299 static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
 300 {
 301     int i;
 302
 303     for (i = irq; i < irq + num; ++i) {
 304         spapr_xive_irq_free(spapr->xive, i);
 305     }
 306 }
 307
 308 static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
 309 {
 310     sPAPRXive *xive = spapr->xive;
 311
 312     if (irq >= xive->nr_irqs) {
 313         return NULL;
 314     }
 315
 316     /* The sPAPR machine/device should have claimed the IRQ before */
 317     assert(xive_eas_is_valid(&xive->eat[irq]));
 318
 319     return spapr->qirqs[irq];
 320 }
 321
 322 static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
 323                                       Monitor *mon)
 324 {
 325     CPUState *cs;
 326
 327     CPU_FOREACH(cs) {
 328         PowerPCCPU *cpu = POWERPC_CPU(cs);
 329
 330         xive_tctx_pic_print_info(cpu->tctx, mon);
 331     }
 332
 333     spapr_xive_pic_print_info(spapr->xive, mon);
 334 }
 335
 336 static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
 337                                            PowerPCCPU *cpu, Error **errp)
 338 {
 339     Error *local_err = NULL;
 340     Object *obj;
 341
 342     obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
 343     if (local_err) {
 344         error_propagate(errp, local_err);
 345         return;
 346     }
 347
 348     cpu->tctx = XIVE_TCTX(obj);
 349
 350     /*
 351      * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
 352      * don't beneficiate from the reset of the XIVE IRQ backend
 353      */
 354     spapr_xive_set_tctx_os_cam(cpu->tctx);
 355 }
 356
 357 static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
 358 {
 359     return 0;
 360 }
 361
 362 static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
 363 {
 364     CPUState *cs;
 365
 366     CPU_FOREACH(cs) {
 367         PowerPCCPU *cpu = POWERPC_CPU(cs);
 368
 369         /* (TCG) Set the OS CAM line of the thread interrupt context. */
 370         spapr_xive_set_tctx_os_cam(cpu->tctx);
 371     }
 372 }
 373
 374 static void spapr_irq_set_irq_xive(void *opaque, int srcno, int val)
 375 {
 376     sPAPRMachineState *spapr = opaque;
 377
 378     xive_source_set_irq(&spapr->xive->source, srcno, val);
 379 }
 380
 381 /*
 382  * XIVE uses the full IRQ number space. Set it to 8K to be compatible
 383  * with XICS.
 384  */
 385
 386 #define SPAPR_IRQ_XIVE_NR_IRQS     0x2000
 387 #define SPAPR_IRQ_XIVE_NR_MSIS     (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
 388
 389 sPAPRIrq spapr_irq_xive = {
 390     .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
 391     .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
 392     .ov5         = SPAPR_OV5_XIVE_EXPLOIT,
 393
 394     .init        = spapr_irq_init_xive,
 395     .claim       = spapr_irq_claim_xive,
 396     .free        = spapr_irq_free_xive,
 397     .qirq        = spapr_qirq_xive,
 398     .print_info  = spapr_irq_print_info_xive,
 399     .dt_populate = spapr_dt_xive,
 400     .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
 401     .post_load   = spapr_irq_post_load_xive,
 402     .reset       = spapr_irq_reset_xive,
 403     .set_irq     = spapr_irq_set_irq_xive,
 404 };
 405
 406 /*
 407  * sPAPR IRQ frontend routines for devices
 408  */
 409 void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
 410 {
 411     /* Initialize the MSI IRQ allocator. */
 412     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
 413         spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
 414     }
 415
 416     spapr->irq->init(spapr, errp);
 417
 418     spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr,
 419                                       spapr->irq->nr_irqs);
 420 }
 421
 422 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
 423 {
 424     return spapr->irq->claim(spapr, irq, lsi, errp);
 425 }
 426
 427 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
 428 {
 429     spapr->irq->free(spapr, irq, num);
 430 }
 431
 432 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
 433 {
 434     return spapr->irq->qirq(spapr, irq);
 435 }
 436
 437 int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
 438 {
 439     return spapr->irq->post_load(spapr, version_id);
 440 }
 441
 442 void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp)
 443 {
 444     if (spapr->irq->reset) {
 445         spapr->irq->reset(spapr, errp);
 446     }
 447 }
 448
 449 /*
 450  * XICS legacy routines - to deprecate one day
 451  */
 452
 453 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
 454 {
 455     int first, i;
 456
 457     for (first = 0; first < ics->nr_irqs; first += alignnum) {
 458         if (num > (ics->nr_irqs - first)) {
 459             return -1;
 460         }
 461         for (i = first; i < first + num; ++i) {
 462             if (!ICS_IRQ_FREE(ics, i)) {
 463                 break;
 464             }
 465         }
 466         if (i == (first + num)) {
 467             return first;
 468         }
 469     }
 470
 471     return -1;
 472 }
 473
 474 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
 475 {
 476     ICSState *ics = spapr->ics;
 477     int first = -1;
 478
 479     assert(ics);
 480
 481     /*
 482      * MSIMesage::data is used for storing VIRQ so
 483      * it has to be aligned to num to support multiple
 484      * MSI vectors. MSI-X is not affected by this.
 485      * The hint is used for the first IRQ, the rest should
 486      * be allocated continuously.
 487      */
 488     if (align) {
 489         assert((num == 1) || (num == 2) || (num == 4) ||
 490                (num == 8) || (num == 16) || (num == 32));
 491         first = ics_find_free_block(ics, num, num);
 492     } else {
 493         first = ics_find_free_block(ics, num, 1);
 494     }
 495
 496     if (first < 0) {
 497         error_setg(errp, "can't find a free %d-IRQ block", num);
 498         return -1;
 499     }
 500
 501     return first + ics->offset;
 502 }
 503
 504 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS     0x400
 505
 506 sPAPRIrq spapr_irq_xics_legacy = {
 507     .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
 508     .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
 509     .ov5         = SPAPR_OV5_XIVE_LEGACY,
 510
 511     .init        = spapr_irq_init_xics,
 512     .claim       = spapr_irq_claim_xics,
 513     .free        = spapr_irq_free_xics,
 514     .qirq        = spapr_qirq_xics,
 515     .print_info  = spapr_irq_print_info_xics,
 516     .dt_populate = spapr_dt_xics,
 517     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
 518     .post_load   = spapr_irq_post_load_xics,
 519     .set_irq     = spapr_irq_set_irq_xics,
 520 };