2 * QEMU model of the Milkymist programmable FPU.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Specification available at:
21 * http://milkymist.walle.cc/socdoc/pfpu.pdf
25 #include "qemu/osdep.h"
27 #include "hw/sysbus.h"
28 #include "migration/vmstate.h"
31 #include "qemu/module.h"
32 #include "qemu/error-report.h"
34 #include "qom/object.h"
36 /* #define TRACE_EXEC */
61 CTL_START_BUSY
= (1<<0),
108 #define GPR_BEGIN 0x100
109 #define GPR_END 0x17f
110 #define MICROCODE_BEGIN 0x200
111 #define MICROCODE_END 0x3ff
112 #define MICROCODE_WORDS 2048
114 #define REINTERPRET_CAST(type, val) (*((type *)&(val)))
117 static const char *opcode_to_str
[] = {
118 "NOP", "FADD", "FSUB", "FMUL", "FABS", "F2I", "I2F", "VECTOUT",
119 "SIN", "COS", "ABOVE", "EQUAL", "COPY", "IF", "TSIGN", "QUAKE",
123 #define TYPE_MILKYMIST_PFPU "milkymist-pfpu"
124 OBJECT_DECLARE_SIMPLE_TYPE(MilkymistPFPUState
, MILKYMIST_PFPU
)
126 struct MilkymistPFPUState
{
127 SysBusDevice parent_obj
;
129 MemoryRegion regs_region
;
133 uint32_t regs
[R_MAX
];
134 uint32_t gp_regs
[128];
135 uint32_t microcode
[MICROCODE_WORDS
];
137 int output_queue_pos
;
138 uint32_t output_queue
[MAX_LATENCY
];
141 static inline uint32_t
142 get_dma_address(uint32_t base
, uint32_t x
, uint32_t y
)
144 return base
+ 8 * (128 * y
+ x
);
148 output_queue_insert(MilkymistPFPUState
*s
, uint32_t val
, int pos
)
150 s
->output_queue
[(s
->output_queue_pos
+ pos
) % MAX_LATENCY
] = val
;
153 static inline uint32_t
154 output_queue_remove(MilkymistPFPUState
*s
)
156 return s
->output_queue
[s
->output_queue_pos
];
160 output_queue_advance(MilkymistPFPUState
*s
)
162 s
->output_queue
[s
->output_queue_pos
] = 0;
163 s
->output_queue_pos
= (s
->output_queue_pos
+ 1) % MAX_LATENCY
;
166 static int pfpu_decode_insn(MilkymistPFPUState
*s
)
168 uint32_t pc
= s
->regs
[R_PC
];
169 uint32_t insn
= s
->microcode
[pc
];
170 uint32_t reg_a
= (insn
>> 18) & 0x7f;
171 uint32_t reg_b
= (insn
>> 11) & 0x7f;
172 uint32_t op
= (insn
>> 7) & 0xf;
173 uint32_t reg_d
= insn
& 0x7f;
182 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
183 float b
= REINTERPRET_CAST(float, s
->gp_regs
[reg_b
]);
185 r
= REINTERPRET_CAST(uint32_t, t
);
186 latency
= LATENCY_FADD
;
187 D_EXEC(qemu_log("ADD a=%f b=%f t=%f, r=%08x\n", a
, b
, t
, r
));
191 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
192 float b
= REINTERPRET_CAST(float, s
->gp_regs
[reg_b
]);
194 r
= REINTERPRET_CAST(uint32_t, t
);
195 latency
= LATENCY_FSUB
;
196 D_EXEC(qemu_log("SUB a=%f b=%f t=%f, r=%08x\n", a
, b
, t
, r
));
200 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
201 float b
= REINTERPRET_CAST(float, s
->gp_regs
[reg_b
]);
203 r
= REINTERPRET_CAST(uint32_t, t
);
204 latency
= LATENCY_FMUL
;
205 D_EXEC(qemu_log("MUL a=%f b=%f t=%f, r=%08x\n", a
, b
, t
, r
));
209 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
211 r
= REINTERPRET_CAST(uint32_t, t
);
212 latency
= LATENCY_FABS
;
213 D_EXEC(qemu_log("ABS a=%f t=%f, r=%08x\n", a
, t
, r
));
217 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
219 r
= REINTERPRET_CAST(uint32_t, t
);
220 latency
= LATENCY_F2I
;
221 D_EXEC(qemu_log("F2I a=%f t=%d, r=%08x\n", a
, t
, r
));
225 int32_t a
= REINTERPRET_CAST(int32_t, s
->gp_regs
[reg_a
]);
227 r
= REINTERPRET_CAST(uint32_t, t
);
228 latency
= LATENCY_I2F
;
229 D_EXEC(qemu_log("I2F a=%08x t=%f, r=%08x\n", a
, t
, r
));
233 uint32_t a
= cpu_to_be32(s
->gp_regs
[reg_a
]);
234 uint32_t b
= cpu_to_be32(s
->gp_regs
[reg_b
]);
236 get_dma_address(s
->regs
[R_MESHBASE
],
237 s
->gp_regs
[GPR_X
], s
->gp_regs
[GPR_Y
]);
238 cpu_physical_memory_write(dma_ptr
, &a
, 4);
239 cpu_physical_memory_write(dma_ptr
+ 4, &b
, 4);
240 s
->regs
[R_LASTDMA
] = dma_ptr
+ 4;
241 D_EXEC(qemu_log("VECTOUT a=%08x b=%08x dma=%08x\n", a
, b
, dma_ptr
));
242 trace_milkymist_pfpu_vectout(a
, b
, dma_ptr
);
246 int32_t a
= REINTERPRET_CAST(int32_t, s
->gp_regs
[reg_a
]);
247 float t
= sinf(a
* (1.0f
/ (M_PI
* 4096.0f
)));
248 r
= REINTERPRET_CAST(uint32_t, t
);
249 latency
= LATENCY_SIN
;
250 D_EXEC(qemu_log("SIN a=%d t=%f, r=%08x\n", a
, t
, r
));
254 int32_t a
= REINTERPRET_CAST(int32_t, s
->gp_regs
[reg_a
]);
255 float t
= cosf(a
* (1.0f
/ (M_PI
* 4096.0f
)));
256 r
= REINTERPRET_CAST(uint32_t, t
);
257 latency
= LATENCY_COS
;
258 D_EXEC(qemu_log("COS a=%d t=%f, r=%08x\n", a
, t
, r
));
262 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
263 float b
= REINTERPRET_CAST(float, s
->gp_regs
[reg_b
]);
264 float t
= (a
> b
) ? 1.0f
: 0.0f
;
265 r
= REINTERPRET_CAST(uint32_t, t
);
266 latency
= LATENCY_ABOVE
;
267 D_EXEC(qemu_log("ABOVE a=%f b=%f t=%f, r=%08x\n", a
, b
, t
, r
));
271 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
272 float b
= REINTERPRET_CAST(float, s
->gp_regs
[reg_b
]);
273 float t
= (a
== b
) ? 1.0f
: 0.0f
;
274 r
= REINTERPRET_CAST(uint32_t, t
);
275 latency
= LATENCY_EQUAL
;
276 D_EXEC(qemu_log("EQUAL a=%f b=%f t=%f, r=%08x\n", a
, b
, t
, r
));
280 r
= s
->gp_regs
[reg_a
];
281 latency
= LATENCY_COPY
;
282 D_EXEC(qemu_log("COPY"));
286 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
287 float b
= REINTERPRET_CAST(float, s
->gp_regs
[reg_b
]);
288 uint32_t f
= s
->gp_regs
[GPR_FLAGS
];
289 float t
= (f
!= 0) ? a
: b
;
290 r
= REINTERPRET_CAST(uint32_t, t
);
291 latency
= LATENCY_IF
;
292 D_EXEC(qemu_log("IF f=%u a=%f b=%f t=%f, r=%08x\n", f
, a
, b
, t
, r
));
296 float a
= REINTERPRET_CAST(float, s
->gp_regs
[reg_a
]);
297 float b
= REINTERPRET_CAST(float, s
->gp_regs
[reg_b
]);
298 float t
= (b
< 0) ? -a
: a
;
299 r
= REINTERPRET_CAST(uint32_t, t
);
300 latency
= LATENCY_TSIGN
;
301 D_EXEC(qemu_log("TSIGN a=%f b=%f t=%f, r=%08x\n", a
, b
, t
, r
));
305 uint32_t a
= s
->gp_regs
[reg_a
];
306 r
= 0x5f3759df - (a
>> 1);
307 latency
= LATENCY_QUAKE
;
308 D_EXEC(qemu_log("QUAKE a=%d r=%08x\n", a
, r
));
312 error_report("milkymist_pfpu: unknown opcode %d", op
);
317 D_EXEC(qemu_log("%04d %8s R%03d, R%03d <L=%d, E=%04d>\n",
318 s
->regs
[R_PC
], opcode_to_str
[op
], reg_a
, reg_b
, latency
,
319 s
->regs
[R_PC
] + latency
));
321 D_EXEC(qemu_log("%04d %8s R%03d, R%03d <L=%d, E=%04d> -> R%03d\n",
322 s
->regs
[R_PC
], opcode_to_str
[op
], reg_a
, reg_b
, latency
,
323 s
->regs
[R_PC
] + latency
, reg_d
));
326 if (op
== OP_VECTOUT
) {
330 /* store output for this cycle */
332 uint32_t val
= output_queue_remove(s
);
333 D_EXEC(qemu_log("R%03d <- 0x%08x\n", reg_d
, val
));
334 s
->gp_regs
[reg_d
] = val
;
337 output_queue_advance(s
);
339 /* store op output */
341 output_queue_insert(s
, r
, latency
-1);
350 static void pfpu_start(MilkymistPFPUState
*s
)
355 for (y
= 0; y
<= s
->regs
[R_VMESHLAST
]; y
++) {
356 for (x
= 0; x
<= s
->regs
[R_HMESHLAST
]; x
++) {
357 D_EXEC(qemu_log("\nprocessing x=%d y=%d\n", x
, y
));
359 /* set current position */
360 s
->gp_regs
[GPR_X
] = x
;
361 s
->gp_regs
[GPR_Y
] = y
;
363 /* run microcode on this position */
365 while (pfpu_decode_insn(s
)) {
366 /* decode at most MICROCODE_WORDS instructions */
367 if (++i
>= MICROCODE_WORDS
) {
368 error_report("milkymist_pfpu: too many instructions "
369 "executed in microcode. No VECTOUT?");
374 /* reset pc for next run */
379 s
->regs
[R_VERTICES
] = x
* y
;
381 trace_milkymist_pfpu_pulse_irq();
382 qemu_irq_pulse(s
->irq
);
385 static inline int get_microcode_address(MilkymistPFPUState
*s
, uint32_t addr
)
387 return (512 * s
->regs
[R_CODEPAGE
]) + addr
- MICROCODE_BEGIN
;
390 static uint64_t pfpu_read(void *opaque
, hwaddr addr
,
393 MilkymistPFPUState
*s
= opaque
;
412 case GPR_BEGIN
... GPR_END
:
413 r
= s
->gp_regs
[addr
- GPR_BEGIN
];
415 case MICROCODE_BEGIN
... MICROCODE_END
:
416 r
= s
->microcode
[get_microcode_address(s
, addr
)];
420 error_report("milkymist_pfpu: read access to unknown register 0x"
421 TARGET_FMT_plx
, addr
<< 2);
425 trace_milkymist_pfpu_memory_read(addr
<< 2, r
);
430 static void pfpu_write(void *opaque
, hwaddr addr
, uint64_t value
,
433 MilkymistPFPUState
*s
= opaque
;
435 trace_milkymist_pfpu_memory_write(addr
, value
);
440 if (value
& CTL_START_BUSY
) {
455 s
->regs
[addr
] = value
;
457 case GPR_BEGIN
... GPR_END
:
458 s
->gp_regs
[addr
- GPR_BEGIN
] = value
;
460 case MICROCODE_BEGIN
... MICROCODE_END
:
461 s
->microcode
[get_microcode_address(s
, addr
)] = value
;
465 error_report("milkymist_pfpu: write access to unknown register 0x"
466 TARGET_FMT_plx
, addr
<< 2);
471 static const MemoryRegionOps pfpu_mmio_ops
= {
475 .min_access_size
= 4,
476 .max_access_size
= 4,
478 .endianness
= DEVICE_NATIVE_ENDIAN
,
481 static void milkymist_pfpu_reset(DeviceState
*d
)
483 MilkymistPFPUState
*s
= MILKYMIST_PFPU(d
);
486 for (i
= 0; i
< R_MAX
; i
++) {
489 for (i
= 0; i
< 128; i
++) {
492 for (i
= 0; i
< MICROCODE_WORDS
; i
++) {
495 s
->output_queue_pos
= 0;
496 for (i
= 0; i
< MAX_LATENCY
; i
++) {
497 s
->output_queue
[i
] = 0;
501 static void milkymist_pfpu_realize(DeviceState
*dev
, Error
**errp
)
503 MilkymistPFPUState
*s
= MILKYMIST_PFPU(dev
);
504 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
506 sysbus_init_irq(sbd
, &s
->irq
);
508 memory_region_init_io(&s
->regs_region
, OBJECT(dev
), &pfpu_mmio_ops
, s
,
509 "milkymist-pfpu", MICROCODE_END
* 4);
510 sysbus_init_mmio(sbd
, &s
->regs_region
);
513 static const VMStateDescription vmstate_milkymist_pfpu
= {
514 .name
= "milkymist-pfpu",
516 .minimum_version_id
= 1,
517 .fields
= (VMStateField
[]) {
518 VMSTATE_UINT32_ARRAY(regs
, MilkymistPFPUState
, R_MAX
),
519 VMSTATE_UINT32_ARRAY(gp_regs
, MilkymistPFPUState
, 128),
520 VMSTATE_UINT32_ARRAY(microcode
, MilkymistPFPUState
, MICROCODE_WORDS
),
521 VMSTATE_INT32(output_queue_pos
, MilkymistPFPUState
),
522 VMSTATE_UINT32_ARRAY(output_queue
, MilkymistPFPUState
, MAX_LATENCY
),
523 VMSTATE_END_OF_LIST()
527 static void milkymist_pfpu_class_init(ObjectClass
*klass
, void *data
)
529 DeviceClass
*dc
= DEVICE_CLASS(klass
);
531 dc
->realize
= milkymist_pfpu_realize
;
532 dc
->reset
= milkymist_pfpu_reset
;
533 dc
->vmsd
= &vmstate_milkymist_pfpu
;
536 static const TypeInfo milkymist_pfpu_info
= {
537 .name
= TYPE_MILKYMIST_PFPU
,
538 .parent
= TYPE_SYS_BUS_DEVICE
,
539 .instance_size
= sizeof(MilkymistPFPUState
),
540 .class_init
= milkymist_pfpu_class_init
,
543 static void milkymist_pfpu_register_types(void)
545 type_register_static(&milkymist_pfpu_info
);
548 type_init(milkymist_pfpu_register_types
)